Use the RTC only as the main timer.
This is a major change to how the main tick interrupt is handled on the mc1322x platforms. Instead of using two timer resources, TMR0 and RTC, this patch unifies all the timers to use the RTC. This is enabled by implementing etimers as scheduled rtimers. The main advantage (aside from freeing TMR0 for general use) is have the Contiki timebase come from the same source that will be used for sleeping and wakeup.
This commit is contained in:
Mariano Alvira
parent
ad55ccdec4
commit
fb8bbf37cf
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@ -10,7 +10,7 @@ CONTIKI_CPU=$(CONTIKI)/cpu/mc1322x
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CONTIKI_CPU_DIRS = . lib src board dev ../arm/common/dbg-io
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MC1322X = debug-uart.c rtimer-arch.c watchdog.c contiki-crm.c contiki-maca.c contiki-misc.c leds-arch.c leds.c contiki-uart.c slip-uart1.c init.c config.c
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MC1322X = debug-uart.c rtimer-arch.c watchdog.c contiki-maca.c contiki-misc.c leds-arch.c leds.c contiki-uart.c slip-uart1.c init.c config.c
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DBG_IO = dbg-printf.c dbg-snprintf.c dbg-sprintf.c strformat.c
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@ -36,87 +36,46 @@
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#include <sys/clock.h>
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#include <sys/cc.h>
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#include <sys/etimer.h>
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#include "dev/leds.h"
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#include <sys/rtimer.h>
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#include "contiki-conf.h"
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#include "mc1322x.h"
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#include "contiki-conf.h"
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#define MAX_TICKS (~((clock_time_t)0) / 2)
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static volatile clock_time_t current_clock = 0;
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volatile unsigned long seconds = 0;
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#define TCF 15
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#define TCF1 4
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#define TCF2 5
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static struct rtimer rt_clock;
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/* the typical clock things like incrementing current_clock and etimer checks */
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/* are performed as a periodically scheduled rtimer */
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void
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clock_init()
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rt_do_clock(struct rtimer *t, void *ptr)
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{
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/* timer setup */
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/* CTRL */
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#define COUNT_MODE 1 /* use rising edge of primary source */
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#define PRIME_SRC 0xf /* Perip. clock with 128 prescale (for 24Mhz = 187500Hz)*/
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#define SEC_SRC 0 /* don't need this */
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#define ONCE 0 /* keep counting */
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#define LEN 1 /* count until compare then reload with value in LOAD */
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#define DIR 0 /* count up */
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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rtimer_set(t, RTIMER_TIME(t) + (rtc_freq/CLOCK_CONF_SECOND) , 1,
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(rtimer_callback_t)rt_do_clock, ptr);
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*TMR_ENBL = 0; /* tmrs reset to enabled */
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*TMR0_SCTRL = 0;
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*TMR0_CSCTRL =0x0040;
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*TMR0_LOAD = 0; /* reload to zero */
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*TMR0_COMP_UP = 1875; /* trigger a reload at the end */
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*TMR0_CMPLD1 = 1875; /* compare 1 triggered reload level, 10HZ maybe? */
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*TMR0_CNTR = 0; /* reset count register */
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*TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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*TMR_ENBL = 0xf; /* enable all the timers --- why not? */
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enable_irq(TMR);
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/* Do startup scan of the ADC */
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#if CLOCK_CONF_SAMPLEADC
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adc_reading[8]=0;
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adc_init();
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while (adc_reading[8]==0) adc_service();
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#endif
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}
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void tmr0_isr(void) {
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if(bit_is_set(*TMR(0,CSCTRL),TCF1)) {
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current_clock++;
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if((current_clock % CLOCK_CONF_SECOND) == 0) {
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seconds++;
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#if BLINK_SECONDS
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leds_toggle(LEDS_GREEN);
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#endif
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/* ADC can be serviced every tick or every second */
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#if CLOCK_CONF_SAMPLEADC > 1
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adc_service();
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#endif
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}
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#if CLOCK_CONF_SAMPLEADC == 1
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adc_service();
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#endif
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if(etimer_pending() &&
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(etimer_next_expiration_time() - current_clock - 1) > MAX_TICKS) {
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etimer_request_poll();
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}
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}
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/* clear the compare flags */
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clear_bit(*TMR(0,SCTRL),TCF);
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clear_bit(*TMR(0,CSCTRL),TCF1);
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clear_bit(*TMR(0,CSCTRL),TCF2);
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return;
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} else {
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/* this timer didn't create an interrupt condition */
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return;
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}
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/* RTC MUST have been already setup by mc1322x init */
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void
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clock_init(void)
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{
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rtimer_set(&rt_clock, RTIMER_NOW() + rtc_freq/CLOCK_CONF_SECOND, 1, (rtimer_callback_t)rt_do_clock, NULL);
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}
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clock_time_t
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@ -1,121 +0,0 @@
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/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org) and Contiki.
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki OS.
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*
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*
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*/
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#include "mc1322x.h"
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#define CRM_DEBUG 1
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#if CRM_DEBUG
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#define PRINTF(...) printf(__VA_ARGS__)
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#else
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#define PRINTF(...)
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#endif
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uint32_t cal_rtc_secs; /* calibrated 2khz rtc seconds */
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void sleep(uint32_t opts, uint32_t mode)
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{
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/* the maca must be off before going to sleep */
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/* otherwise the mcu will reboot on wakeup */
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// maca_off();
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*CRM_SLEEP_CNTL = opts;
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*CRM_SLEEP_CNTL = (opts | mode);
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/* wait for the sleep cycle to complete */
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while(!bit_is_set(*CRM_STATUS,0)) { continue; }
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and powers down */
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set_bit(*CRM_STATUS,0);
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/* now we are asleep */
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/* and waiting for something to wake us up */
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/* you did tell us how to wake up right? */
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/* waking up */
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while(!bit_is_set(*CRM_STATUS,0)) { continue; }
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes the wakeup */
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set_bit(*CRM_STATUS,0);
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/* you may also need to do other recovery */
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/* such as interrupt handling */
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/* peripheral init */
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/* and turning the radio back on */
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}
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/* turn on the 32kHz crystal */
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/* once you start the 32xHz crystal it can only be stopped with a reset (hard or soft) */
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void enable_32khz_xtal(void)
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{
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static volatile uint32_t rtc_count;
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PRINTF("enabling 32kHz crystal\n\r");
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/* first, disable the ring osc */
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ring_osc_off();
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/* enable the 32kHZ crystal */
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xtal32_on();
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/* set the XTAL32_EXISTS bit */
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/* the datasheet says to do this after you've check that RTC_COUNT is changing */
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/* the datasheet is not correct */
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xtal32_exists();
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/* now check that the crystal starts */
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/* this blocks until it starts */
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/* it would be better to timeout and return an error */
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rtc_count = *CRM_RTC_COUNT;
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PRINTF("waiting for xtal\n\r");
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while(*CRM_RTC_COUNT == rtc_count) {
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continue;
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}
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/* RTC has started up */
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PRINTF("32kHZ xtal started\n\r");
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}
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void cal_ring_osc(void)
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{
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uint32_t cal_factor;
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PRINTF("performing ring osc cal\n\r");
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PRINTF("crm_status: 0x%0x\n\r",*CRM_STATUS);
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PRINTF("sys_cntl: 0x%0x\n\r",*CRM_SYS_CNTL);
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*CRM_CAL_CNTL = (1<<16) | (20000);
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while((*CRM_STATUS & (1<<9)) == 0);
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PRINTF("ring osc cal complete\n\r");
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PRINTF("cal_count: 0x%0x\n\r",*CRM_CAL_COUNT);
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cal_factor = (REF_OSC*1000) / *CRM_CAL_COUNT;
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cal_rtc_secs = (NOMINAL_RING_OSC_SEC * cal_factor)/100;
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PRINTF("cal factor: %d\n\r", cal_factor);
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PRINTF("hib_wake_secs: %d\n\r", cal_rtc_secs);
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set_bit(*CRM_STATUS,9);
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}
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@ -55,4 +55,8 @@ typedef unsigned short uip_stats_t;
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typedef uint32_t clock_time_t;
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/* Core rtimer.h defaults to 16 bit timer unless RTIMER_CLOCK_LT is defined */
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typedef unsigned long rtimer_clock_t;
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#define RTIMER_CLOCK_LT(a,b) ((signed long)((a)-(b)) < 0)
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#endif
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@ -102,6 +102,7 @@ void buck_setup(void) {
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CRM->VREG_CNTLbits.VREG_1P5V_SEL = 3;
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CRM->VREG_CNTLbits.VREG_1P5V_EN = 3;
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CRM->VREG_CNTLbits.VREG_1P8V_EN = 1;
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while(CRM->STATUSbits.VREG_1P5V_RDY == 0) { continue; }
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while(CRM->STATUSbits.VREG_1P8V_RDY == 0) { continue; }
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@ -149,6 +150,7 @@ void rtc_setup(void) {
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PRINTF("RTC calibrated to %d Hz\r\n", rtc_freq);
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} else {
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PRINTF("32kHz xtal started\n\r");
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rtc_freq = 32768;
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}
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}
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@ -167,13 +169,11 @@ void mc1322x_init(void) {
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PRINTF("mc1322x init\n\r");
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adc_init();
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clock_init();
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ctimer_init();
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process_init();
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process_start(&etimer_process, NULL);
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process_start(&contiki_maca_process, NULL);
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buck_setup();
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rtc_setup();
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/* start with a default config */
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@ -196,6 +196,11 @@ void mc1322x_init(void) {
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set_demodulator_type(mc1322x_config.flags.demod);
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set_prm_mode(mc1322x_config.flags.autoack);
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/* must be done AFTER maca_init */
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/* the radio calibration appears to clobber the RTC trim caps */
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rtc_setup();
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rtimer_init();
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clock_init();
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}
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@ -72,7 +72,7 @@ void rtc_init_osc(int use_32khz)
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continue;
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/* RTC has started up */
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rtc_freq = 32000;
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rtc_freq = 32768;
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}
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else
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{
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@ -168,7 +168,7 @@ void rtc_calibrate(void)
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uint32_t count;
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if (__use_32khz) {
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rtc_freq = 32000;
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rtc_freq = 32768;
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return;
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}
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@ -57,18 +57,41 @@
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#define PRINTF(...)
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#endif
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void rtc_isr(void) {
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PRINTF("rtc_wu_irq\n\r");
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PRINTF("now is %u\n", rtimer_arch_now());
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disable_rtc_wu();
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disable_rtc_wu_irq();
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static uint32_t last_rtc;
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void
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rtc_isr(void)
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{
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/* see note in table 5-13 of the reference manual: it takes at least two RTC clocks for the EVT bit to clear */
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if ((CRM->RTC_COUNT - last_rtc) <= 2) {
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CRM->STATUS = ~0; /* Clear all events */
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// CRM->STATUSbits.RTC_WU_EVT = 1;
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return;
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}
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last_rtc = CRM->RTC_COUNT;
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/* Clear all events (for paranoia) */
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/* clear RTC event flag (for paranoia)*/
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// CRM->STATUSbits.RTC_WU_EVT = 1;
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CRM->STATUS = ~0;
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rtimer_run_next();
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clear_rtc_wu_evt();
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}
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void
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rtimer_arch_init(void)
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{
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last_rtc = CRM->RTC_COUNT;
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/* enable timeout interrupts */
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/* RTC WU is the periodic RTC timer */
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/* TIMER WU is the wakeup timers (clocked from the RTC source) */
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/* it does not appear you can have both enabled at the same time */
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CRM->WU_CNTLbits.RTC_WU_EN = 1;
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CRM->WU_CNTLbits.RTC_WU_IEN = 1;
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enable_irq(CRM);
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}
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void
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@ -76,23 +99,52 @@ rtimer_arch_schedule(rtimer_clock_t t)
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{
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volatile uint32_t now;
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now = rtimer_arch_now();
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PRINTF("rtimer_arch_schedule time %u; now is %u\n", t,now);
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PRINTF("rtimer_arch_schedule time %u; now is %u\n", t, now);
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#if 1
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/* If specified time is always in the future, counter can wrap without harm */
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*CRM_RTC_TIMEOUT = t - now;
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#else
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/* Immediate interrupt if specified time is before current time. This may also
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happen on counter overflow. */
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if(now>t) {
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*CRM_RTC_TIMEOUT = 1;
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if(now > t) {
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CRM->RTC_TIMEOUT = 1;
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} else {
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*CRM_RTC_TIMEOUT = t - now;
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CRM->RTC_TIMEOUT = t - now;
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}
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#endif
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clear_rtc_wu_evt();
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enable_rtc_wu();
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enable_rtc_wu_irq();
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PRINTF("rtimer_arch_schedule CRM_RTC_TIMEOUT is %u\n", *CRM_RTC_TIMEOUT);
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}
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void
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rtimer_arch_sleep(rtimer_clock_t howlong)
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{
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CRM->WU_CNTLbits.TIMER_WU_EN = 1;
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CRM->WU_CNTLbits.RTC_WU_EN = 0;
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CRM->WU_TIMEOUT = howlong;
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/* the maca must be off before going to sleep */
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/* otherwise the mcu will reboot on wakeup */
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maca_off();
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CRM->SLEEP_CNTLbits.DOZE = 0;
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CRM->SLEEP_CNTLbits.RAM_RET = 3;
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CRM->SLEEP_CNTLbits.MCU_RET = 1;
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CRM->SLEEP_CNTLbits.DIG_PAD_EN = 1;
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CRM->SLEEP_CNTLbits.HIB = 1;
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/* wait for the sleep cycle to complete */
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while((*CRM_STATUS & 0x1) == 0) { continue; }
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and powers down */
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*CRM_STATUS = 1;
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/* asleep */
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/* wait for the awake cycle to complete */
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while((*CRM_STATUS & 0x1) == 0) { continue; }
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes wakeup */
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*CRM_STATUS = 1;
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CRM->WU_CNTLbits.TIMER_WU_EN = 0;
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CRM->WU_CNTLbits.RTC_WU_EN = 1;
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/* reschedule clock ticks */
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clock_init();
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clock_adjust_ticks((CRM->WU_COUNT*CLOCK_CONF_SECOND)/rtc_freq);
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}
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|
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@ -47,15 +47,15 @@
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#include "sys/rtimer.h"
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|
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/* mc1322x */
|
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#include "crm.h"
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#include "utils.h"
|
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#include "mc1322x.h"
|
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|
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#if USE_32KHZ_XTAL
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#define RTIMER_ARCH_SECOND 32768
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#else
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#define RTIMER_ARCH_SECOND 18778 /* close --- should get calibrated */
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#define RTIMER_ARCH_SECOND 2000
|
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#endif
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#define rtimer_arch_now() (*CRM_RTC_COUNT)
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#define rtimer_arch_now() (CRM->RTC_COUNT)
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#endif /* __RTIMER_ARCH_H__ */
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||||
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|||
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|
@ -106,10 +106,6 @@
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|||
#define PLATFORM_HAS_LEDS 1
|
||||
#define PLATFORM_HAS_BUTTON 1
|
||||
|
||||
/* Core rtimer.h defaults to 16 bit timer unless RTIMER_CLOCK_LT is defined */
|
||||
typedef unsigned long rtimer_clock_t;
|
||||
#define RTIMER_CLOCK_LT(a,b) ((signed long)((a)-(b)) < 0)
|
||||
|
||||
#define RIMEADDR_CONF_SIZE 8
|
||||
|
||||
#if WITH_UIP6
|
||||
|
|
|
|||
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Reference in a new issue