af27d2d252
Because the CC2538 has a multi-byte SPI RX FIFO, flushing the buffer requires more than just a single read. This adds a loop that empties the entire RX buffer on a FLUSH(). Different SPI chips needs different SPI settings. This commit adds a function that allows chip drivers to configure the SPI peripheral before using it. The frame pin the driver was using as a chip select does not work as most devices expect it to. It toggles after every byte, and most chips interpret that as end of message. To make drivers more reliable, each chip driver should setup a GPIO and assert it as needed.
141 lines
5.2 KiB
C
141 lines
5.2 KiB
C
/*
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* Copyright (c) 2013, University of Michigan.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-spi
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* @{
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*
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* \file
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* Implementation of the cc2538 SPI peripheral
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*/
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#include "contiki.h"
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#include "reg.h"
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#include "spi-arch.h"
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#include "dev/ioc.h"
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#include "dev/sys-ctrl.h"
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#include "dev/spi.h"
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#include "dev/ssi.h"
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#include "dev/gpio.h"
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#define SPI_CLK_PORT_BASE GPIO_PORT_TO_BASE(SPI_CLK_PORT)
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#define SPI_CLK_PIN_MASK GPIO_PIN_MASK(SPI_CLK_PIN)
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#define SPI_MOSI_PORT_BASE GPIO_PORT_TO_BASE(SPI_MOSI_PORT)
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#define SPI_MOSI_PIN_MASK GPIO_PIN_MASK(SPI_MOSI_PIN)
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#define SPI_MISO_PORT_BASE GPIO_PORT_TO_BASE(SPI_MISO_PORT)
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#define SPI_MISO_PIN_MASK GPIO_PIN_MASK(SPI_MISO_PIN)
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/**
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* \brief Initialize the SPI bus.
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*
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* This SPI init() function uses the following #defines to set the pins:
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* SPI_CLK_PORT SPI_CLK_PIN
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* SPI_MOSI_PORT SPI_MOSI_PIN
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* SPI_MISO_PORT SPI_MISO_PIN
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*
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* This sets the mode to Motorola SPI with the following format options:
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* Clock phase: 1; data captured on second (rising) edge
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* Clock polarity: 1; clock is high when idle
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* Data size: 8 bits
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*/
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void
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spi_init(void)
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{
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spi_enable();
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/* Start by disabling the peripheral before configuring it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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/* Set the IO clock as the SSI clock */
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REG(SSI0_BASE + SSI_CC) = 1;
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/* Set the mux correctly to connect the SSI pins to the correct GPIO pins */
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ioc_set_sel(SPI_CLK_PORT, SPI_CLK_PIN, IOC_PXX_SEL_SSI0_CLKOUT);
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ioc_set_sel(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_PXX_SEL_SSI0_TXD);
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REG(IOC_SSIRXD_SSI0) = (SPI_MISO_PORT * 8) + SPI_MISO_PIN;
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/* Put all the SSI gpios into peripheral mode */
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GPIO_PERIPHERAL_CONTROL(SPI_CLK_PORT_BASE, SPI_CLK_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(SPI_MOSI_PORT_BASE, SPI_MOSI_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(SPI_MISO_PORT_BASE, SPI_MISO_PIN_MASK);
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/* Disable any pull ups or the like */
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ioc_set_over(SPI_CLK_PORT, SPI_CLK_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(SPI_MISO_PORT, SPI_MISO_PIN, IOC_OVERRIDE_DIS);
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/* Configure the clock */
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REG(SSI0_BASE + SSI_CPSR) = 2;
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/* Configure the default SPI options.
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* mode: Motorola frame format
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* clock: High when idle
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* data: Valid on rising edges of the clock
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* bits: 8 byte data
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*/
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REG(SSI0_BASE + SSI_CR0) = SSI_CR0_SPH | SSI_CR0_SPO | (0x07);
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/* Enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_cs_init(uint8_t port, uint8_t pin)
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{
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GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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ioc_set_over(port, pin, IOC_OVERRIDE_DIS);
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GPIO_SET_OUTPUT(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_enable(void)
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{
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/* Enable the clock for the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) |= 1;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_disable(void)
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{
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/* Gate the clock for the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) &= ~1;
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}
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/*---------------------------------------------------------------------------*/
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void spi_set_mode(uint32_t frame_format, uint32_t clock_polarity, uint32_t clock_phase, uint32_t data_size)
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{
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/* Disable the SSI peripheral to configure it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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/* Configure the SSI options */
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REG(SSI0_BASE + SSI_CR0) = clock_phase | clock_polarity | frame_format | (data_size - 1);
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/* Re-enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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}
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/** @} */
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