919b6919a5
The previous chip detection was inspired by the old IP65 driver code. For some reason it didn't work as expected. The new code is simpler and based on this statement in the chip datasheet: "The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C96."
426 lines
9.7 KiB
ArmAsm
426 lines
9.7 KiB
ArmAsm
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; Copyright (c) 2003-2007, Adam Dunkels, Josef Soucek and Oliver Schmidt
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; 3. Neither the name of the Institute nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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; SUCH DAMAGE.
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;
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; This file is part of the Contiki operating system.
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;
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; Author: Adam Dunkels <adam@sics.se>, Josef Soucek <josef.soucek@ide64.org>,
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; Oliver Schmidt <ol.sc@web.de>
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;
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;---------------------------------------------------------------------
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.macpack module
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module_header _lan91c96
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; Driver signature
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.byte $65, $74, $68 ; "eth"
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.byte $01 ; Ethernet driver API version number
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; Ethernet address
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mac: .byte $00, $80, $0F ; OUI of Standard Microsystems
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.byte $11, $11, $11
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; Buffer attributes
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bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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; Jump table.
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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.if DYN_DRV
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.zeropage
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sp: .res 2 ; Stack pointer (Do not trash !)
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reg: .res 2 ; Address of register base
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ptr: .res 2 ; Indirect addressing pointer
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len: .res 2 ; Frame length
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.else
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.include "zeropage.inc"
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reg := ptr1 ; Address of register base
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ptr := ptr2 ; Indirect addressing pointer
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len := ptr3 ; Frame length
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.endif
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;---------------------------------------------------------------------
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.rodata
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fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup05-fixup04, fixup06-fixup05, fixup07-fixup06
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.byte fixup08-fixup07, fixup09-fixup08, fixup10-fixup09
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.byte fixup11-fixup10, fixup12-fixup11, fixup13-fixup12
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.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
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.byte fixup26-fixup25, fixup27-fixup26, fixup28-fixup27
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.byte fixup29-fixup28, fixup30-fixup29, fixup31-fixup30
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.byte fixup32-fixup31, fixup33-fixup32, fixup34-fixup33
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.byte fixup35-fixup34, fixup36-fixup35, fixup37-fixup36
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.byte fixup38-fixup37, fixup39-fixup38, fixup40-fixup39
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fixups = * - fixup
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;---------------------------------------------------------------------
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ethbsr := $FF0E ; Bank select register R/W (2B)
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; Register bank 0
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ethtcr := $FF00 ; Transmition control register R/W (2B)
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ethephsr := $FF02 ; EPH status register R/O (2B)
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ethrcr := $FF04 ; Receive control register R/W (2B)
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ethecr := $FF06 ; Counter register R/O (2B)
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ethmir := $FF08 ; Memory information register R/O (2B)
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ethmcr := $FF0A ; Memory Config. reg. +0 R/W +1 R/O (2B)
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; Register bank 1
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ethcr := $FF00 ; Configuration register R/W (2B)
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ethbar := $FF02 ; Base address register R/W (2B)
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ethiar := $FF04 ; Individual address register R/W (6B)
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ethgpr := $FF0A ; General address register R/W (2B)
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ethctr := $FF0C ; Control register R/W (2B)
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; Register bank 2
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ethmmucr := $FF00 ; MMU command register W/O (1B)
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ethautotx := $FF01 ; AUTO TX start register R/W (1B)
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ethpnr := $FF02 ; Packet number register R/W (1B)
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etharr := $FF03 ; Allocation result register R/O (1B)
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ethfifo := $FF04 ; FIFO ports register R/O (2B)
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ethptr := $FF06 ; Pointer register R/W (2B)
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ethdata := $FF08 ; Data register R/W (4B)
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ethist := $FF0C ; Interrupt status register R/O (1B)
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ethack := $FF0C ; Interrupt acknowledge register W/O (1B)
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ethmsk := $FF0D ; Interrupt mask register R/W (1B)
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; Register bank 3
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ethmt := $FF00 ; Multicast table R/W (8B)
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ethmgmt := $FF08 ; Management interface R/W (2B)
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ethrev := $FF0A ; Revision register R/W (2B)
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ethercv := $FF0C ; Early RCV register R/W (2B)
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.data
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;---------------------------------------------------------------------
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init:
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; Save address of register base
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sta reg
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stx reg+1
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; Start with first fixup location
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lda #<(fixup01+1)
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ldx #>(fixup01+1)
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sta ptr
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stx ptr+1
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ldx #$FF
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ldy #$00
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; Fixup address at location
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: lda reg
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ora (ptr),y
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sta (ptr),y
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iny
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lda reg+1
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sta (ptr),y
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dey
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; Advance to next fixup location
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inx
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cpx #fixups
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bcs :+
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lda ptr
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clc
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adc fixup,x
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sta ptr
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bcc :-
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inc ptr+1
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bcs :- ; Always
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; Check bank select register upper byte to always read as $33
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: ldy #$00
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fixup01:sty ethbsr+1
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fixup02:lda ethbsr+1
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cmp #$33
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beq :+
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sec
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rts
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; Reset ETH card
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: ; Bank 0
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fixup03:sty ethbsr
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lda #%10000000 ; Software reset
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fixup04:sta ethrcr+1
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fixup05:sty ethrcr
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fixup06:sty ethrcr+1
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; Delay
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: cmp ($FF,x) ; 6 cycles
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cmp ($FF,x) ; 6 cycles
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iny ; 2 cycles
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bne :- ; 3 cycles
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; 17 * 256 = 4352 -> 4,4 ms
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; Enable transmit and receive
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lda #%10000001 ; Enable transmit TXENA, PAD_EN
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ldx #%00000011 ; Enable receive, strip CRC ???
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fixup07:sta ethtcr
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fixup08:stx ethrcr+1
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lda #$01 ; Bank 1
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fixup09:sta ethbsr
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fixup10:lda ethcr+1
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ora #%00010000 ; No wait (IOCHRDY)
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fixup11:sta ethcr+1
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lda #%00001001 ; Auto release
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fixup12:sta ethctr+1
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; Set MAC address
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ldy #$00
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: lda mac,y
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fixup13:sta ethiar,y
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iny
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cpy #$06
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bcc :-
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; Set interrupt mask
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lda #$02 ; Bank 2
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fixup14:sta ethbsr
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lda #%00000000 ; No interrupts
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fixup15:sta ethmsk
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tax
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clc
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rts
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;---------------------------------------------------------------------
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poll:
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fixup16:lda ethist
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and #%00000001 ; RCV INT
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beq :+
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; Process the incoming packet
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; ---------------------------
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lda #$00
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ldx #%11100000 ; RCV, AUTO INCR., READ
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fixup17:sta ethptr
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fixup18:stx ethptr+1
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; Last word contains 'last data byte' and $60 or 'fill byte' and $40
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fixup19:lda ethdata ; Status word
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fixup20:lda ethdata ; Need high byte only
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; Move ODDFRM bit into carry:
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; - Even packet length -> carry clear -> subtract 6 bytes
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; - Odd packet length -> carry set -> subtract 5 bytes
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lsr
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lsr
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lsr
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lsr
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lsr
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; The packet contains 3 extra words
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fixup21:lda ethdata ; Total number of bytes
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sbc #$05 ; Actually 5 or 6 depending on carry
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sta len
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fixup22:lda ethdata
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sbc #$00
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sta len+1
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; Is bufsize < len ?
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lda bufsize
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cmp len
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lda bufsize+1
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sbc len+1
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bcs :++
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; Yes, skip packet
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; Remove and release RX packet from the FIFO
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lda #%10000000
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fixup23:sta ethmmucr
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; No packet available
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lda #$00
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: tax
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sec
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rts
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; Read bytes into buffer
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: jsr adjustptr
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:
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fixup24:lda ethdata
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sta (ptr),y
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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; Remove and release RX packet from the FIFO
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lda #%10000000
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fixup25:sta ethmmucr
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; Return packet length
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lda len
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ldx len+1
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clc
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rts
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;---------------------------------------------------------------------
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send:
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; Save packet length
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sta len
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stx len+1
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; Allocate memory for TX
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txa
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ora #%00100000
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fixup26:sta ethmmucr
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; 8 retries
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ldy #$08
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; Wait for allocation ready
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:
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fixup27:lda ethist
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and #%00001000 ; ALLOC INT
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bne :+
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; Shouldn't we do something here to actively free memory,
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; maybe removing and releasing an RX packet from the FIFO ???
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; And try again
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dey
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bne :-
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sec
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rts
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; Acknowledge interrupt, is it necessary ???
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: lda #%00001000
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fixup28:sta ethack
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; Set packet address
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fixup29:lda etharr
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fixup30:sta ethpnr
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lda #$00
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ldx #%01000000 ; AUTO INCR.
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fixup31:sta ethptr
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fixup32:stx ethptr+1
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; Status written by CSMA
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lda #$00
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fixup33:sta ethdata
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fixup34:sta ethdata
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; Check packet length parity:
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; - Even packet length -> carry set -> add 6 bytes
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; - Odd packet length -> carry clear -> add 5 bytes
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lda len
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eor #$01
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lsr
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; The packet contains 3 extra words
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lda len
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adc #$05 ; Actually 5 or 6 depending on carry
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fixup35:sta ethdata
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lda len+1
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adc #$00
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fixup36:sta ethdata
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; Send the packet
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; ---------------
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; Write bytes from buffer
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jsr adjustptr
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: lda (ptr),y
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fixup37:sta ethdata
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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; Odd packet length ?
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lda len
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lsr
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bcc :+
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; Yes
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lda #%00100000 ; ODD
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bne :++ ; Always
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; No
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: lda #$00
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fixup38:sta ethdata ; Fill byte
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:
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fixup39:sta ethdata ; Control byte
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; Add packet to FIFO
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lda #%11000000 ; ENQUEUE PACKET - transmit packet
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fixup40:sta ethmmucr
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clc
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rts
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;---------------------------------------------------------------------
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exit:
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rts
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;---------------------------------------------------------------------
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adjustptr:
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lda len
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ldx len+1
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eor #$FF ; Two's complement part 1
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tay
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iny ; Two's complement part 2
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sty reg
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sec
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lda bufaddr
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sbc reg
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sta ptr
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lda bufaddr+1
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sbc #$00
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sta ptr+1
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rts
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;---------------------------------------------------------------------
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