Fixed hardware detection.
The previous chip detection was inspired by the old IP65 driver code. For some reason it didn't work as expected. The new code is simpler and based on this statement in the chip datasheet: "The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C96."
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1 changed files with 18 additions and 19 deletions
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@ -67,7 +67,7 @@ len: .res 2 ; Frame length
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.else
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.include "zeropage.inc"
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reg := ptr1 ; Address of register base
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reg := ptr1 ; Address of register base
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ptr := ptr2 ; Indirect addressing pointer
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len := ptr3 ; Frame length
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@ -168,16 +168,24 @@ init:
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inc ptr+1
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bcs :- ; Always
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; Check bank select register upper byte to always read as $33
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: ldy #$00
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fixup01:sty ethbsr+1
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fixup02:lda ethbsr+1
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cmp #$33
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beq :+
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sec
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rts
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; Reset ETH card
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: lda #$00 ; Bank 0
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fixup01:sta ethbsr
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: ; Bank 0
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fixup03:sty ethbsr
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lda #%10000000 ; Software reset
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fixup02:sta ethrcr+1
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fixup04:sta ethrcr+1
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ldy #$00
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fixup03:sty ethrcr
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fixup04:sty ethrcr+1
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fixup05:sty ethrcr
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fixup06:sty ethrcr+1
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; Delay
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: cmp ($FF,x) ; 6 cycles
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@ -189,21 +197,12 @@ fixup04:sty ethrcr+1
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; Enable transmit and receive
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lda #%10000001 ; Enable transmit TXENA, PAD_EN
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ldx #%00000011 ; Enable receive, strip CRC ???
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fixup05:sta ethtcr
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fixup06:stx ethrcr+1
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fixup07:sta ethtcr
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fixup08:stx ethrcr+1
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lda #$01 ; Bank 1
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fixup07:sta ethbsr
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fixup09:sta ethbsr
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; Check ISA mode base address register for reset values
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lda #$18^67 ; I/O base $300 + ROM $CC000
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fixup08:eor ethbar
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fixup09:eor ethbar+1
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beq :+
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sec
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rts
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:
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fixup10:lda ethcr+1
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ora #%00010000 ; No wait (IOCHRDY)
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fixup11:sta ethcr+1
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