08abd8807d
Some platforms are missing timer channels, this is now left to the (missing) preprocessor definitions on those platforms, no platform-specific defines needed anymore. Also fix usage of timer counter register 3 (hardcoded) in cpu/avr/dev/clock.c -- this code isn't used on many platforms as it requires a very special quartz clock frequency but this now also uses the platform timer specification.
136 lines
4.9 KiB
C
136 lines
4.9 KiB
C
/*
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* Copyright (c) 2007, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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*/
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#ifndef RTIMER_ARCH_H_
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#define RTIMER_ARCH_H_
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#include <avr/interrupt.h>
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/* Nominal ARCH_SECOND is F_CPU/prescaler, e.g. 8000000/1024 = 7812
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* Other prescaler values (1, 8, 64, 256) will give greater precision
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* with shorter maximum intervals.
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* Setting RTIMER_ARCH_PRESCALER to 0 will leave Timers alone.
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* rtimer_arch_now() will then return 0, likely hanging the cpu if used.
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* Timer1 is used if Timer3 is not available.
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*
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* Note the rtimer tick to clock tick conversion will be nominally correct only
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* when the same oscillator is used for both clocks.
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* When an external 32768 watch crystal is used for clock ticks my raven CPU
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* oscillator is 1% slow, 32768 counts on crystal = ~7738 rtimer ticks.
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* For more accuracy define F_CPU to 0x800000 and optionally phase lock CPU
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* clock to 32768 crystal. This gives RTIMER_ARCH_SECOND = 8192.
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*/
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#ifndef RTIMER_ARCH_PRESCALER
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#define RTIMER_ARCH_PRESCALER 1024UL
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#endif
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#if RTIMER_ARCH_PRESCALER
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#define RTIMER_ARCH_SECOND (F_CPU/RTIMER_ARCH_PRESCALER)
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#else
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#define RTIMER_ARCH_SECOND 0
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#endif
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#ifndef PLAT_TIMER
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/* By default use timer 3 if available. Fall back to timer1 if not. */
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#ifdef TCNT3
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#define PLAT_TIMER 3
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#else
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#define PLAT_TIMER 1
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#endif /* TCNT3 */
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#endif /* !PLAT_TIMER */
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#define _R_CONC_(_x,_y,_z) _x##_y##_z
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#define _C_R_CONC_(_X,_Y,_Z) _R_CONC_(_X,_Y,_Z)
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#define PLAT_ICF _C_R_CONC_(ICF,PLAT_TIMER,)
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#define PLAT_ICIE _C_R_CONC_(ICIE,PLAT_TIMER,)
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#define PLAT_OCFA _C_R_CONC_(OCF,PLAT_TIMER,A)
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#define PLAT_OCFB _C_R_CONC_(OCF,PLAT_TIMER,B)
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#define PLAT_OCFC _C_R_CONC_(OCF,PLAT_TIMER,C)
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#define PLAT_OCIEA _C_R_CONC_(OCIE,PLAT_TIMER,A)
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#define PLAT_OCIEB _C_R_CONC_(OCIE,PLAT_TIMER,B)
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#define PLAT_OCIEC _C_R_CONC_(OCIE,PLAT_TIMER,C)
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#define PLAT_OCRA _C_R_CONC_(OCR,PLAT_TIMER,A)
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#define PLAT_TCCRA _C_R_CONC_(TCCR,PLAT_TIMER,A)
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#define PLAT_TCCRB _C_R_CONC_(TCCR,PLAT_TIMER,B)
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#define PLAT_TCCRC _C_R_CONC_(TCCR,PLAT_TIMER,C)
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#define PLAT_TCNT _C_R_CONC_(TCNT,PLAT_TIMER,)
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#define PLAT_TIFR _C_R_CONC_(TIFR,PLAT_TIMER,)
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#define PLAT_TIMSK _C_R_CONC_(TIMSK,PLAT_TIMER,)
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#define PLAT_TOIE _C_R_CONC_(TOIE,PLAT_TIMER,)
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#define PLAT_TOV _C_R_CONC_(TOV,PLAT_TIMER,)
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#define PLAT_VECT _C_R_CONC_(TIMER,PLAT_TIMER,_COMPA_vect)
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/*
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* Unavailable timer channels on some platforms
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* A hack originally found for some architectures.
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* Since OCIEnC isn't used we simple define it to OCIEnB which allows
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* the code to compile. Same for OCFnC and TCCRnC. Note that the TCCRnX
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* registers are only (all) set to 0 in the code. The OCIEnC and OCFnC
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* are shifts which are always set to the same value as OCIEnB and
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* OCFnB, respectively.
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*/
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#if PLAT_TIMER == 3
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#ifndef OCIE3C
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#define PLAT_OCIEC PLAT_OCIEB
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#endif
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#ifndef OCF3C
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#define PLAT_OCFC PLAT_OCFB
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#endif
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#ifndef TCCR3C
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#define PLAT_TCCRC PLAT_TCCRB
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#endif
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#endif /* PLAT_TIMER == 3 */
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#if PLAT_TIMER == 1
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#ifndef OCIE1C
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#define PLAT_OCIEC PLAT_OCIEB
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#endif
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#ifndef OCF1C
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#define PLAT_OCFC PLAT_OCFB
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#endif
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#ifndef TCCR1C
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#define PLAT_TCCRC PLAT_TCCRB
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#endif
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#endif /* PLAT_TIMER == 3 */
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#if RTIMER_ARCH_PRESCALER
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#define rtimer_arch_now() (PLAT_TCNT)
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#else
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#define rtimer_arch_now() (0)
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#endif
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/* some platforms don't have OCIEXC, we rely on the processor
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* definition to #define OCIEXC OCIEXB in that case. This won't hurt
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* since OCIEXC isn't used anyway.
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*/
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void rtimer_arch_sleep(rtimer_clock_t howlong);
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#endif /* RTIMER_ARCH_H_ */
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