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Fixes for platform timer code 

Some platforms are missing timer channels, this is now left to the
(missing) preprocessor definitions on those platforms, no
platform-specific defines needed anymore.
Also fix usage of timer counter register 3 (hardcoded) in
cpu/avr/dev/clock.c -- this code isn't used on many platforms as it
requires a very special quartz clock frequency but this now also uses
the platform timer specification.
ico
Ralf Schlatterbeck 2014-06-26 18:00:30 +02:00
parent b6be226e69
commit 08abd8807d
3 changed files with 36 additions and 23 deletions
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4
cpu/avr/dev/clock.c
View File

@ -371,13 +371,13 @@ volatile static uint8_t osccalhigh,osccallow;
if (seconds < 60) { //give a minute to stabilize
if(++lockcount >= 8192UL*128/RTIMER_ARCH_SECOND) {
lockcount=0;
rtimer_phase = TCNT3 & 0x0fff;
rtimer_phase = PLAT_TCNT & 0x0fff;
if (seconds < 2) OSCCAL=100;
if (last_phase > rtimer_phase) osccalhigh=++OSCCAL; else osccallow=--OSCCAL;
last_phase = rtimer_phase;
}
} else {
uint8_t error = (TCNT3 - last_phase) & 0x3f;
uint8_t error = (PLAT_TCNT - last_phase) & 0x3f;
if (error == 0) {
} else if (error<32) {
OSCCAL=osccallow-1;

21
cpu/avr/rtimer-arch.c
View File

@ -50,27 +50,6 @@
#include "sys/rtimer.h"
#include "rtimer-arch.h"
#if defined(__AVR_ATmega1284P__)
//Has no 'C', so we just set it to B. The code doesn't really use C so this
//is safe to do but lets it compile. Probably should enable the warning if
//it is ever used on other platforms.
//#warning no OCIE3C in timer3 architecture, hopefully it won't be needed!
#define OCIE3C OCIE3B
#define OCF3C OCF3B
#define PLAT_TCCRC PLAT_TCCRB
#endif
#if defined(__AVR_ATmega1281__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega128RFA1__)
#endif
#if defined(__AVR_ATmega328P__) || defined(__AVR_ATmega644__)
//Has no 'C', so we just set it to B. The code doesn't really use C so this
//is safe to do but lets it compile.
#define OCIE1C OCIE1B
#define OCF1C OCF1B
#define PLAT_TCCRC PLAT_TCCRB
#endif
/* Track flow through rtimer interrupts*/
#if DEBUGFLOWSIZE&&0
extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];

34
cpu/avr/rtimer-arch.h
View File

@ -88,6 +88,40 @@
#define PLAT_TOIE _C_R_CONC_(TOIE,PLAT_TIMER,)
#define PLAT_TOV _C_R_CONC_(TOV,PLAT_TIMER,)
#define PLAT_VECT _C_R_CONC_(TIMER,PLAT_TIMER,_COMPA_vect)
/*
* Unavailable timer channels on some platforms
* A hack originally found for some architectures.
* Since OCIEnC isn't used we simple define it to OCIEnB which allows
* the code to compile. Same for OCFnC and TCCRnC. Note that the TCCRnX
* registers are only (all) set to 0 in the code. The OCIEnC and OCFnC
* are shifts which are always set to the same value as OCIEnB and
* OCFnB, respectively.
*/
#if PLAT_TIMER == 3
#ifndef OCIE3C
#define PLAT_OCIEC PLAT_OCIEB
#endif
#ifndef OCF3C
#define PLAT_OCFC PLAT_OCFB
#endif
#ifndef TCCR3C
#define PLAT_TCCRC PLAT_TCCRB
#endif
#endif /* PLAT_TIMER == 3 */
#if PLAT_TIMER == 1
#ifndef OCIE1C
#define PLAT_OCIEC PLAT_OCIEB
#endif
#ifndef OCF1C
#define PLAT_OCFC PLAT_OCFB
#endif
#ifndef TCCR1C
#define PLAT_TCCRC PLAT_TCCRB
#endif
#endif /* PLAT_TIMER == 3 */
#if RTIMER_ARCH_PRESCALER
#define rtimer_arch_now() (PLAT_TCNT)
#else