Commit graph

8 commits

Author SHA1 Message Date
Simon Duquennoy
722b3258d1 Cleanup of the Contiki network layer configuration. Now using CONTIKI_WITH_IPV6, CONTIKI_WITH_IPV4, and CONTIKI_WITH_RIME in makefiles, and UIP_CONF_IPV6, UIP_CONF_IPV4, UIP_CONF_RIME in c code. Now only the stacks that are used are compiled (via makefile MODULES). Make IPv6 the default network stack. 2014-12-01 20:13:09 +01:00
Atis Elsts
68b65e6c47 Fix CPU clock calibration in msp430f2xxx based platforms (e.g. Zolertia Z1).
The following problems were present in the existing DCO calibration algorithm:

Problem #1. In function msp430_quick_synch_dco(), the "for(i=0; i < 1000; i++) { .. }" loop is optimized away by the compiler, as i is not volatile. Making i volatile would improve the results, but would not be sufficient: see the next point.

Problem #2. According to MSP430F2617 Device Erratasheet, bug BCL12 precludes a naive implementations of "fast" calibration altogether. The bug is present on all MCU revisions up to date.

The description of the bug:
"After switching RSELx bits (located in register BCSCTL1) from a value of >13 to a value of <12 OR from a value of <12 to a value of >13, the resulting clock delivered by the DCO can stop before the new clock frequency is applied. This dead time is approximately 20 us. In some instances, the DCO may completely stop, requiring a power cycle.

Furthermore, if all of the RSELx bits in the BSCTL1 register are set, modifying the DCOCTL register to change the DCOx or the MODx bits could also result in DCO dead time or DCO hang up."

In Contiki code for msp430f2xxx @ 8MHz, the RSEL search currently typically goes from 15 down to 11, thus violating the rules.

Step-by-step RSEL change is proposed as the best possible workaround:
"[..] more reliable method can be implemented by changing the RSEL bits step by step in order to guarantee safe function without any dead time of the DCO."

Problem #3. The old Contiki code started from the highest possible calibration values: RSEL=15, DCOx=7. According to MSP430F2617
datasheet, this means that the DCO frequency is set to 26 MHz. For one, Vcc under 3V is not supported for this frequency, so this means that battery-powered nodes have a big problem. The minimal operating voltages are:
- 1.8V for RSEL <= 13
- 2.2V for RSEL = 14
- 3.0V for RSEL = 15
So the correct way is to always start calibration from RSEL <= 13, unless explicityly pre-calibred values are present.

Problem #4. Timer B should be turned off after the calibration, following the "Principles for Low-Power Applications" in MSP430 user's Guide.

The patch fixes these issues by performing step-by-step calibration and turning off Timer B afterwards. As opposed to MSP430F1xxx calibration, this algorithm does not change the ACLK divider beforehand; attempts to make calibration more precise would lead to looping in some cases, as the calibration step granularity at larger frequencies is quite big.

Additionally, the patch improves DCOSYNCH_CONF_ENABLED behavior, allowing the resynchronization to correct for more than one step.
2014-03-25 11:47:13 +01:00
Antonio Lignan
2cf4e30b11 Baudrate now is configured taking into account the MCU frequency, instead of using fixed values for 8MHz freq 2013-01-29 12:23:23 +01:00
Adam Dunkels
944537fccf Removed all old RCS tags in the Contiki source tree. Those RCS tags are not used any more, as we are now using git to manage the Contiki source tree 2012-10-26 15:54:49 +02:00
Niclas Finne
418a5772e6 Removed leds debug output 2012-06-07 10:35:22 +02:00
Niclas Finne
684c3edfa6 Cross compiler interrupt service routine compatibility definitions for MSP430 based platforms based on isr_compat.h by Steve Underwood. 2012-03-07 23:04:52 +01:00
Niclas Finne
f3db12c19d MSP430 setup for f2xxx based on Z1 2012-01-09 14:56:03 +01:00
Niclas Finne
cdfa8708e3 * Added f2xxx for two series (for example z1)
* f1xxx is baseline and always included
* Cleaned up the names of uart and spi (no x in names)
* Updated SPI configuration for WiSMote
2012-01-09 14:54:57 +01:00