* Added f2xxx for two series (for example z1)
* f1xxx is baseline and always included * Cleaned up the names of uart and spi (no x in names) * Updated SPI configuration for WiSMote
This commit is contained in:
parent
1a761ec3eb
commit
cdfa8708e3
15 changed files with 289 additions and 204 deletions
|
@ -12,11 +12,15 @@ CONTIKI_CPU=$(CONTIKI)/cpu/msp430
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### Define the source files we have in the MSP430 port
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ifneq (,$(findstring msp430x5,$(MCU)))
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CONTIKI_CPU_DIRS = ${addprefix f5xxx/,. dev} . dev
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CONTIKI_CPU_FAM_DIR = f5xxx
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else
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CONTIKI_CPU_DIRS = ${addprefix f1xxx/,. dev} . dev
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ifneq (,$(findstring msp430x2,$(MCU)))
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CONTIKI_CPU_FAM_DIR = f2xxx
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endif
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endif
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CONTIKI_CPU_DIRS = $(CONTIKI_CPU_FAM_DIR) f1xxx . dev
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MSP430 = msp430.c flash.c clock.c leds.c leds-arch.c \
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watchdog.c lpm.c mtarch.c rtimer-arch.c
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UIPDRIVERS = me.c me_tabs.c slip.c crc16.c
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@ -182,7 +182,7 @@ void
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clock_delay(unsigned int i)
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{
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while(i--) {
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asm("nop");
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_NOP();
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}
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}
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/*---------------------------------------------------------------------------*/
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@ -92,11 +92,7 @@ handle_rxdma_timer(void *ptr)
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uint8_t
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uart1_active(void)
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{
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#if CONTIKI_TARGET_WISMOTE
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return rx_in_progress | transmitting;
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#else
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return ((~ UTCTL1) & TXEPT) | rx_in_progress | transmitting;
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#endif
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}
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/*---------------------------------------------------------------------------*/
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void
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@ -126,21 +122,16 @@ uart1_writeb(unsigned char c)
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/* Loop until the transmission buffer is available. */
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/*while((IFG2 & UTXIFG1) == 0);*/
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UCA1TXBUF = ringbuf_get(&txbuf);
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TXBUF1 = ringbuf_get(&txbuf);
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}
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#else /* TX_WITH_INTERRUPT */
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#if CONTIKI_TARGET_WISMOTE
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while(!(UCA1IFG & UCTXIFG)); // USCI_A1 TX buffer ready?
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UCA1TXBUF = c;
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#else
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/* Loop until the transmission buffer is available. */
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while((IFG2 & UTXIFG1) == 0);
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/* Transmit the data. */
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TXBUF1 = c;
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#endif
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#endif /* TX_WITH_INTERRUPT */
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}
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/*---------------------------------------------------------------------------*/
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@ -151,35 +142,6 @@ uart1_writeb(unsigned char c)
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void
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uart1_init(unsigned long ubr)
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{
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#if CONTIKI_TARGET_WISMOTE
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P4DIR |= BIT5;
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P4OUT |= BIT5 ;
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P5SEL |= BIT6|BIT7; // P5.6,7 = USCI_A1 TXD/RXD
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P4SEL |= BIT7;
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P4DIR |= BIT7;
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UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
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UCA1CTL1 |= UCSSEL_2; // SMCLK
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UCA1BR0 = 139;//69; // Baudrate 57600 (see User's Guide)
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UCA1BR1 = 0; //
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UCA1MCTL |= UCBRS_2 + UCBRF_0; // Modulation UCBRFx=0
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UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
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UCA1IE |= UCRXIE;
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UCA1IFG &= ~UCRXIFG;
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//UCA1IFG &= ~UCTXIFG;
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// UCA1TCTL1 |= URXSE;
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rx_in_progress = 0;
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transmitting = 0;
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#if TX_WITH_INTERRUPT
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ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
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UCA1IE |= UCTXIE;
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//UCA1IFG &= ~UCTXIFG;
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#endif /* TX_WITH_INTERRUPT */
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#else
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/* RS232 */
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P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
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P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
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@ -271,53 +233,8 @@ uart1_init(unsigned long ubr)
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msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
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#endif /* RX_WITH_DMA */
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#endif
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}
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/*---------------------------------------------------------------------------*/
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#if CONTIKI_TARGET_WISMOTE
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#ifdef __IAR_SYSTEMS_ICC__
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#pragma vector=USCI_A1_VECTOR
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__interrupt void
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#else
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interrupt(USCI_A1_VECTOR)
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#endif
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uart1_rx_interrupt(void)
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{
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uint8_t c;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if(UCRXIFG & UCA1IFG) {
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rx_in_progress = 0;
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// Check status register for receive errors.
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if(UCA1STAT & UCRXERR) {
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c = UCA1RXBUF; // Clear error flags by forcing a dummy read.
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} else {
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c = UCA1RXBUF;
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if(uart1_input_handler != NULL) {
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if(uart1_input_handler(c)) {
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LPM4_EXIT;
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}
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}
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}
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UCA1IFG &= ~UCRXIFG;
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}
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#if TX_WITH_INTERRUPT
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if(UCTXIFG & UCA1IFG) {
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if(ringbuf_elements(&txbuf) == 0) {
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transmitting = 0;
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} else {
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UCA1TXBUF = ringbuf_get(&txbuf);
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}
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UCA1IFG &= ~UCTXIFG;
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}
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#endif
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//UCA1IFG &= 0x00;
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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#else
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#if !RX_WITH_DMA
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#ifdef __IAR_SYSTEMS_ICC__
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#pragma vector=UART1RX_VECTOR
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@ -375,5 +292,4 @@ uart1_tx_interrupt(void)
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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#endif /* TX_WITH_INTERRUPT */
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#endif
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/*---------------------------------------------------------------------------*/
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@ -25,8 +25,6 @@
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)$Id: spix.c,v 1.1 2010/08/24 16:23:20 joxe Exp $
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*/
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#include "contiki.h"
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@ -43,12 +41,7 @@ unsigned char spi_busy = 0;
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void
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spi_init(void)
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{
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//static unsigned char spi_inited = 0;
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//if (spi_inited)
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//return;
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// Initalize ports for communication with SPI units.
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// Initialize ports for communication with SPI units.
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UCB0CTL1 |= UCSWRST; //reset usci
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UCB0CTL1 |= UCSSEL_2; //smclk while usci is reset
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@ -179,7 +179,7 @@ void
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clock_delay(unsigned int i)
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{
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while(i--) {
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asm("nop");
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_NOP();
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}
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}
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/*---------------------------------------------------------------------------*/
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126
cpu/msp430/f5xxx/uart0.c
Normal file
126
cpu/msp430/f5xxx/uart0.c
Normal file
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@ -0,0 +1,126 @@
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/*
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* Copyright (c) 2011, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Yet another machine dependent MSP430X UART0 code.
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* IF2, etc. can not be used here... need to abstract to some macros
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* later.
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*/
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#include "contiki.h"
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#include <stdlib.h>
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#include "sys/energest.h"
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#include "dev/uart0.h"
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#include "dev/watchdog.h"
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static int (*uart0_input_handler)(unsigned char c);
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static volatile uint8_t transmitting;
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/*---------------------------------------------------------------------------*/
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uint8_t
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uart0_active(void)
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{
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return (UCA0STAT & UCBUSY) | transmitting;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart0_set_input(int (*input)(unsigned char c))
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{
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uart0_input_handler = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart0_writeb(unsigned char c)
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{
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watchdog_periodic();
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/* Loop until the transmission buffer is available. */
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while((UCA0STAT & UCBUSY));
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/* Transmit the data. */
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UCA0TXBUF = c;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Initalize the RS232 port.
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*
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*/
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void
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uart0_init(unsigned long ubr)
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{
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/* RS232 */
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UCA0CTL1 |= UCSWRST; /* Hold peripheral in reset state */
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UCA0CTL1 |= UCSSEL_2; /* CLK = SMCLK */
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ubr = (MSP430_CPU_SPEED / ubr);
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UCA0BR0 = ubr & 0xff;
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UCA0BR1 = (ubr >> 8) & 0xff;
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UCA0MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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P3DIR &= ~0x20; /* P3.5 = USCI_A0 RXD as input */
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P3DIR |= 0x10; /* P3.4 = USCI_A0 TXD as output */
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P3SEL |= 0x30; /* P3.4,5 = USCI_A0 TXD/RXD */
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/*UCA0CTL1 &= ~UCSWRST;*/ /* Initialize USCI state machine */
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transmitting = 0;
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/* XXX Clear pending interrupts before enable */
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UCA0IE &= ~UCRXIFG;
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UCA0IE &= ~UCTXIFG;
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UCA0CTL1 &= ~UCSWRST; /* Initialize USCI state machine **before** enabling interrupts */
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UCA0IE |= UCRXIE; /* Enable UCA0 RX interrupt */
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}
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/*---------------------------------------------------------------------------*/
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#ifdef __IAR_SYSTEMS_ICC__
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#pragma vector=USCI_A0_VECTOR
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__interrupt void
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#else
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interrupt(USCI_A0_VECTOR)
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#endif
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uart0_rx_interrupt(void)
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{
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uint8_t c;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if (UCA0IV == 2) {
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if(UCA0STAT & UCRXERR) {
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c = UCA0RXBUF; /* Clear error flags by forcing a dummy read. */
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} else {
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c = UCA0RXBUF;
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if(uart0_input_handler != NULL) {
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if(uart0_input_handler(c)) {
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LPM4_EXIT;
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}
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}
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}
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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/*---------------------------------------------------------------------------*/
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131
cpu/msp430/f5xxx/uart1.c
Normal file
131
cpu/msp430/f5xxx/uart1.c
Normal file
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@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2011, Swedish Institute of Computer Science
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* All rights reserved.
|
||||
*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
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/*
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* Yet another machine dependent MSP430X UART0 code.
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* IF2, etc. can not be used here... need to abstract to some macros
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* later.
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*/
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#include "contiki.h"
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#include <stdlib.h>
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#include "sys/energest.h"
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#include "dev/uart1.h"
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#include "dev/watchdog.h"
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static int (*uart1_input_handler)(unsigned char c);
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static volatile uint8_t transmitting;
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/*---------------------------------------------------------------------------*/
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uint8_t
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uart1_active(void)
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{
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return (UCA1STAT & UCBUSY) | transmitting;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart1_set_input(int (*input)(unsigned char c))
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{
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uart1_input_handler = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart1_writeb(unsigned char c)
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{
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watchdog_periodic();
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/* Loop until the transmission buffer is available. */
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while((UCA1STAT & UCBUSY));
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/* Transmit the data. */
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UCA1TXBUF = c;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Initalize the RS232 port.
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*
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*/
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void
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uart1_init(unsigned long ubr)
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{
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/* RS232 */
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UCA1CTL1 |= UCSWRST; /* Hold peripheral in reset state */
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UCA1CTL1 |= UCSSEL_2; /* CLK = SMCLK */
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ubr = (MSP430_CPU_SPEED / ubr);
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UCA1BR0 = ubr & 0xff;
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UCA1BR1 = (ubr >> 8) & 0xff;
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/* UCA1MCTL |= UCBRS_2 + UCBRF_0; // Modulation UCBRFx=0 */
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UCA1MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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P4DIR |= BIT5;
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P4OUT |= BIT5 ;
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P5SEL |= BIT6|BIT7; // P5.6,7 = USCI_A1 TXD/RXD
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P4SEL |= BIT7;
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P4DIR |= BIT7;
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/*UCA1CTL1 &= ~UCSWRST;*/ /* Initialize USCI state machine */
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transmitting = 0;
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/* XXX Clear pending interrupts before enable */
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UCA1IE &= ~UCRXIFG;
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UCA1IE &= ~UCTXIFG;
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UCA1CTL1 &= ~UCSWRST; /* Initialize USCI state machine **before** enabling interrupts */
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UCA1IE |= UCRXIE; /* Enable UCA1 RX interrupt */
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}
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/*---------------------------------------------------------------------------*/
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#ifdef __IAR_SYSTEMS_ICC__
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#pragma vector=USCI_A1_VECTOR
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__interrupt void
|
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#else
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interrupt(USCI_A1_VECTOR)
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#endif
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uart1_rx_interrupt(void)
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{
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uint8_t c;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if (UCA1IV == 2) {
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if(UCA1STAT & UCRXERR) {
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c = UCA1RXBUF; /* Clear error flags by forcing a dummy read. */
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} else {
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c = UCA1RXBUF;
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if(uart1_input_handler != NULL) {
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if(uart1_input_handler(c)) {
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LPM4_EXIT;
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}
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}
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}
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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/*---------------------------------------------------------------------------*/
|
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@ -7,7 +7,7 @@ CONTIKI_TARGET_SOURCEFILES += contiki-wismote-platform.c \
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sky-sensors.c uip-ipchksum.c \
|
||||
checkpoint-arch.c uart1.c slip_uart1.c uart1-putchar.c
|
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|
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ARCH=spix.c i2c.c node-id.c sensors.c cfs-coffee.c sht15.c \
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ARCH=spi.c i2c.c node-id.c sensors.c cfs-coffee.c sht15.c \
|
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cc2520.c cc2520-arch.c cc2520-arch-sfd.c \
|
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sky-sensors.c uip-ipchksum.c \
|
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checkpoint-arch.c uart1.c slip_uart1.c uart1-putchar.c
|
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|
|
|
@ -205,10 +205,10 @@ main(int argc, char **argv)
|
|||
|
||||
leds_on(LEDS_ALL);
|
||||
|
||||
uart1_init(BAUD2UBR(115200)); /* Must come before first printf */
|
||||
uart1_init(115200); /* Must come before first printf */
|
||||
|
||||
#if WITH_UIP
|
||||
slip_arch_init(BAUD2UBR(115200));
|
||||
slip_arch_init(115200);
|
||||
#endif /* WITH_UIP */
|
||||
|
||||
//ds2411_init();
|
||||
|
|
|
@ -1,92 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011, Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file
|
||||
* Basic SPI macros
|
||||
* \author
|
||||
* Niclas Finne <nfi@sics.se>
|
||||
* Joakim Eriksson <joakime@sics.se>
|
||||
*/
|
||||
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
/* Define macros to use for checking SPI transmission status depending
|
||||
on if it is possible to wait for TX buffer ready. This is possible
|
||||
on for example MSP430 but not on AVR. */
|
||||
#ifdef SPI_WAITFORTxREADY
|
||||
#define SPI_WAITFORTx_BEFORE() SPI_WAITFORTxREADY()
|
||||
#define SPI_WAITFORTx_AFTER()
|
||||
#define SPI_WAITFORTx_ENDED() SPI_WAITFOREOTx()
|
||||
#else /* SPI_WAITFORTxREADY */
|
||||
#define SPI_WAITFORTx_BEFORE()
|
||||
#define SPI_WAITFORTx_AFTER() SPI_WAITFOREOTx()
|
||||
#define SPI_WAITFORTx_ENDED()
|
||||
#endif /* SPI_WAITFORTxREADY */
|
||||
|
||||
extern unsigned char spi_busy;
|
||||
|
||||
void spi_init(void);
|
||||
|
||||
/* Write one character to SPI */
|
||||
#define SPI_WRITE(data) \
|
||||
do { \
|
||||
UCB0IFG &= ~UCRXIFG; \
|
||||
SPI_TXBUF = data; \
|
||||
SPI_WAITFORTxREADY(); \
|
||||
} while(0)
|
||||
|
||||
/* Write one character to SPI - will not wait for end
|
||||
useful for multiple writes with wait after final */
|
||||
#define SPI_WRITE_FAST(data) \
|
||||
do { \
|
||||
UCB0IFG &= ~UCRXIFG; \
|
||||
SPI_TXBUF = data; \
|
||||
SPI_WAITFORTxREADY(); \
|
||||
} while(0)
|
||||
|
||||
/* Read one character from SPI */
|
||||
#define SPI_READ(data) \
|
||||
do { \
|
||||
UCB0IFG &= ~UCRXIFG; \
|
||||
SPI_TXBUF = 0; \
|
||||
SPI_WAITFORTxREADY(); \
|
||||
SPI_BUSY_WAIT(); \
|
||||
data = SPI_RXBUF; \
|
||||
} while(0)
|
||||
|
||||
/* Flush the SPI read register */
|
||||
#define SPI_FLUSH() \
|
||||
do { \
|
||||
SPI_RXBUF; \
|
||||
SPI_RXBUF; \
|
||||
} while(0);
|
||||
|
||||
#endif /* __SPI_H__ */
|
|
@ -39,8 +39,6 @@
|
|||
* Definitions below are dictated by the hardware and not really
|
||||
* changeable!
|
||||
*/
|
||||
/* Platform WISMOTE */
|
||||
#define WISMOTE 1
|
||||
|
||||
#define PLATFORM_HAS_LEDS 1
|
||||
#define PLATFORM_HAS_BUTTON 1
|
||||
|
@ -52,7 +50,7 @@
|
|||
#define CLOCK_CONF_SECOND 128UL
|
||||
#define RTIMER_CONF_SECOND (4096U*8)
|
||||
|
||||
#define BAUD2UBR(baud) ((F_CPU/baud))
|
||||
#define BAUD2UBR(baud) (baud)
|
||||
|
||||
#define CCIF
|
||||
#define CLIF
|
||||
|
@ -96,16 +94,25 @@ typedef unsigned long off_t;
|
|||
#define SPI_RXBUF UCB0RXBUF
|
||||
|
||||
/* USART0 Tx ready? */
|
||||
#define SPI_WAITFOREOTx() while (!(UCB0IFG & UCRXIFG))
|
||||
#define SPI_WAITFOREOTx() while ((UCB0STAT & UCBUSY) != 0)
|
||||
/* USART0 Rx ready? */
|
||||
#define SPI_WAITFOREORx() while (!(UCB0IFG & UCRXIFG))
|
||||
#define SPI_WAITFOREORx() while ((UCB0IFG & UCRXIFG) == 0)
|
||||
/* USART0 Tx buffer ready? */
|
||||
#define SPI_WAITFORTxREADY() while (!(UCB0IFG & UCRXIFG))
|
||||
#define SPI_BUSY_WAIT() while ((UCB0STAT & UCBUSY) == 1)
|
||||
#define SPI_WAITFORTxREADY() while ((UCB0IFG & UCTXIFG) == 0)
|
||||
/* /\* USART0 Tx ready? *\/ */
|
||||
/* #define SPI_WAITFOREOTx() while (!(UCB0IFG & UCRXIFG)) */
|
||||
/* /\* USART0 Rx ready? *\/ */
|
||||
/* #define SPI_WAITFOREORx() while (!(UCB0IFG & UCRXIFG)) */
|
||||
/* /\* USART0 Tx buffer ready? *\/ */
|
||||
/* #define SPI_WAITFORTxREADY() while (!(UCB0IFG & UCRXIFG)) */
|
||||
/* #define SPI_BUSY_WAIT() while ((UCB0STAT & UCBUSY) == 1) */
|
||||
|
||||
#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
|
||||
#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
|
||||
#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
|
||||
#define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
|
||||
#define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
|
||||
#define SCK 3 /* P3.3 - Output: SPI Serial Clock (SCLK) */
|
||||
/* #define SCK 1 /\* P3.1 - Output: SPI Serial Clock (SCLK) *\/ */
|
||||
/* #define MOSI 2 /\* P3.2 - Output: SPI Master out - slave in (MOSI) *\/ */
|
||||
/* #define MISO 3 /\* P3.3 - Input: SPI Master in - slave out (MISO) *\/ */
|
||||
|
||||
/*
|
||||
* SPI bus - M25P80 external flash configuration.
|
||||
|
|
|
@ -16,9 +16,9 @@ CLEAN += symbols.c symbols.h
|
|||
|
||||
|
||||
ARCH=msp430.c leds.c watchdog.c xmem.c \
|
||||
spix.c cc2420.c cc2420-aes.c cc2420-arch.c cc2420-arch-sfd.c\
|
||||
spi.c cc2420.c cc2420-aes.c cc2420-arch.c cc2420-arch-sfd.c\
|
||||
node-id.c sensors.c button-sensor.c cfs-coffee.c \
|
||||
radio-sensor.c uart0x.c uart0-putchar.c uip-ipchksum.c \
|
||||
radio-sensor.c uart0.c uart0-putchar.c uip-ipchksum.c \
|
||||
checkpoint-arch.c slip.c slip_uart0.c \
|
||||
z1-phidgets.c sht11.c sht11-sensor.c light-sensor.c \
|
||||
battery-sensor.c sky-sensors.c tmp102.c temperature-sensor.c
|
||||
|
|
Loading…
Reference in a new issue