New Contiki port to STM32W108.
This commit is contained in:
salvopitru
parent
324796cd1a
commit
ec5e3ce0d7
130 changed files with 43157 additions and 0 deletions
33
cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h
Normal file
33
cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/** @file board.h
|
||||
* @brief Header file x STM32W108 Kits boards
|
||||
*
|
||||
* <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
|
||||
*/
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#ifdef BOARD_MB851
|
||||
|
||||
/* leds definitions */
|
||||
#define LED_D1 PORTB_PIN(6)
|
||||
#define LED_D3 PORTB_PIN(5)
|
||||
|
||||
|
||||
/** Description buttons definition */
|
||||
#define BUTTON_S1 PORTA_PIN(7)
|
||||
#define BUTTON_S1_INPUT_GPIO GPIO_PAIN
|
||||
#define BUTTON_S1_OUTPUT_GPIO GPIO_PAOUT
|
||||
#define BUTTON_S1_GPIO_PIN PA7_BIT
|
||||
#define BUTTON_S1_WAKE_SOURCE 0x00000080
|
||||
|
||||
/** Description uart definition */
|
||||
#define UART_TX PORTB_PIN(1)
|
||||
#define UART_RX PORTB_PIN(2)
|
||||
#define UART_RX_WAKE_SOURCE 0x00000400
|
||||
|
||||
/** Description temperature sensor GPIO */
|
||||
#define TEMPERATURE_SENSOR_GPIO PORTB_PIN(7)
|
||||
#endif /* BOARD_MB851 */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
||||
362
cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c
Normal file
362
cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c
Normal file
|
|
@ -0,0 +1,362 @@
|
|||
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
|
||||
* File Name : stm32f10x_vector.c
|
||||
* Author : MCD Tools Team
|
||||
* Date First Issued : 05/14/2007
|
||||
* Description : This file contains the vector table for STM32F10x.
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/14/2007: V0.2
|
||||
*
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include <sys/stat.h>
|
||||
#define RESERVED 0
|
||||
//#define DUMMY_MALLOC
|
||||
|
||||
/* Includes ----------------------------------------------------------------------*/
|
||||
#include PLATFORM_HEADER
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMonitor_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void halTimer1Isr(void);
|
||||
void halTimer2Isr(void);
|
||||
void halManagementIsr(void);
|
||||
void halBaseBandIsr(void);
|
||||
void halSleepTimerIsr(void);
|
||||
void halSc1Isr(void);
|
||||
void halSc2Isr(void);
|
||||
void halSecurityIsr(void);
|
||||
void halStackMacTimerIsr(void);
|
||||
void stmRadioTransmitIsr(void);
|
||||
void stmRadioReceiveIsr(void);
|
||||
void halAdcIsr(void);
|
||||
void halIrqAIsr(void);
|
||||
void halIrqBIsr(void);
|
||||
void halIrqCIsr(void);
|
||||
void halIrqDIsr(void);
|
||||
void halDebugIsr(void);
|
||||
|
||||
/* Exported types --------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
extern unsigned long _etext;
|
||||
extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */
|
||||
extern unsigned long _sdata; /* start address for the .data section. defined in linker script */
|
||||
extern unsigned long _edata; /* end address for the .data section. defined in linker script */
|
||||
|
||||
extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */
|
||||
extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */
|
||||
|
||||
extern void _estack; /* init value for the stack pointer. defined in linker script */
|
||||
|
||||
#include "hal/micro/cortexm3/memmap.h"
|
||||
VAR_AT_SEGMENT(const HalFixedAddressTableType halFixedAddressTable, __FAT__);
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
|
||||
/* function prototypes ------------------------------------------------------*/
|
||||
void Reset_Handler(void) __attribute__((__interrupt__));
|
||||
extern int main(void);
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) =
|
||||
{
|
||||
&_estack, // The initial stack pointer
|
||||
Reset_Handler, // 1 The reset handler
|
||||
NMI_Handler, // 2
|
||||
HardFault_Handler, // 3
|
||||
MemManage_Handler, // 4
|
||||
BusFault_Handler, // 5
|
||||
UsageFault_Handler, // 6
|
||||
RESERVED, // 7
|
||||
RESERVED, // 8
|
||||
RESERVED, // 9
|
||||
RESERVED, // 10
|
||||
SVC_Handler, // 11
|
||||
DebugMonitor_Handler, // 12
|
||||
RESERVED, // 13
|
||||
PendSV_Handler, // 14
|
||||
SysTick_Handler, // 15
|
||||
halTimer1Isr, // 16
|
||||
halTimer2Isr, // 17
|
||||
halManagementIsr, // 18
|
||||
halBaseBandIsr, // 19
|
||||
halSleepTimerIsr, // 20
|
||||
halSc1Isr, // 21
|
||||
halSc2Isr, // 22
|
||||
halSecurityIsr, // 23
|
||||
halStackMacTimerIsr, // 24
|
||||
stmRadioTransmitIsr, // 25
|
||||
stmRadioReceiveIsr, // 26
|
||||
halAdcIsr, // 27
|
||||
halIrqAIsr, // 28
|
||||
halIrqBIsr, // 29
|
||||
halIrqCIsr, // 30
|
||||
halIrqDIsr, // 31
|
||||
halDebugIsr, // 32
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Reset_Handler
|
||||
* Description : This is the code that gets called when the processor first starts execution
|
||||
* following a reset event. Only the absolutely necessary set is performed,
|
||||
* after which the application supplied main() routine is called.
|
||||
* Input :
|
||||
* Output :
|
||||
* Return :
|
||||
*******************************************************************************/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
//Ensure there is enough margin on VREG_1V8 for stable RAM reads by
|
||||
//setting it to a code of 6. VREG_1V2 can be left at its reset value.
|
||||
VREG = 0x00000307;
|
||||
|
||||
// This code should be careful about the use of local variables in case the
|
||||
// reset type happens to be a deep sleep reset. If the reset is not from
|
||||
// deep sleep, then locals can be freely used
|
||||
|
||||
//When the Cortex-M3 exits reset, interrupts are enable. Explicitely
|
||||
//disable them immediately using the standard set PRIMASK instruction.
|
||||
//Injecting an assembly instruction this early does not effect optimization.
|
||||
asm("CPSID i");
|
||||
|
||||
//It is quite possible that when the Cortex-M3 begins executing code the
|
||||
//Core Reset Vector Catch is still left enabled. Because this VC would
|
||||
//cause us to halt at reset if another reset event tripped, we should
|
||||
//clear it as soon as possible. If a debugger wants to halt at reset,
|
||||
//it will set this bit again.
|
||||
DEBUG_EMCR &= ~DEBUG_EMCR_VC_CORERESET;
|
||||
|
||||
//Configure flash access for optimal current consumption early
|
||||
//during boot to save as much current as we can.
|
||||
FLASH_ACCESS = (FLASH_ACCESS_PREFETCH_EN |
|
||||
(1<<FLASH_ACCESS_CODE_LATENCY_BIT));
|
||||
|
||||
////---- Always Configure Interrupt Priorities ----////
|
||||
//The STM32W support 5 bits of priority configuration.
|
||||
// The cortex allows this to be further divided into preemption and a
|
||||
// "tie-breaker" sub-priority.
|
||||
//We configure a scheme that allows for 3 bits (8 values) of preemption and
|
||||
// 2 bits (4 values) of tie-breaker by using the value 4 in PRIGROUP.
|
||||
//The value 0x05FA0000 is a special key required to write to this register.
|
||||
SCS_AIRCR = (0x05FA0000 | (4 <<SCS_AIRCR_PRIGROUP_BIT));
|
||||
|
||||
//A few macros to help with interrupt priority configuration. Really only
|
||||
// uses 6 of the possible levels, and ignores the tie-breaker sub-priority
|
||||
// for now.
|
||||
//Don't forget that the priority level values need to be shifted into the
|
||||
// top 5 bits of the 8 bit priority fields. (hence the <<3)
|
||||
//
|
||||
// NOTE: The ATOMIC and DISABLE_INTERRUPTS macros work by setting the
|
||||
// current priority to a value of 12, which still allows CRITICAL and
|
||||
// HIGH priority interrupts to fire, while blocking MED and LOW.
|
||||
// If a different value is desired, spmr.s79 will need to be edited.
|
||||
#define CRITICAL (0 <<3)
|
||||
#define HIGH (8 <<3)
|
||||
#define MED (16 <<3)
|
||||
#define LOW (28 <<3)
|
||||
#define NONE (31 <<3)
|
||||
|
||||
//With optimization turned on, the compiler will indentify all the values
|
||||
//and variables used here as constants at compile time and will truncate
|
||||
//this entire block of code to 98 bytes, comprised of 7 load-load-store
|
||||
//operations.
|
||||
//vect00 is fixed //Stack pointer
|
||||
//vect01 is fixed //Reset Vector
|
||||
//vect02 is fixed //NMI Handler
|
||||
//vect03 is fixed //Hard Fault Handler
|
||||
SCS_SHPR_7to4 = ((CRITICAL <<SCS_SHPR_7to4_PRI_4_BIT) | //Memory Fault Handler
|
||||
(CRITICAL <<SCS_SHPR_7to4_PRI_5_BIT) | //Bus Fault Handler
|
||||
(CRITICAL <<SCS_SHPR_7to4_PRI_6_BIT) | //Usage Fault Handler
|
||||
(NONE <<SCS_SHPR_7to4_PRI_7_BIT)); //Reserved
|
||||
SCS_SHPR_11to8 = ((NONE <<SCS_SHPR_11to8_PRI_8_BIT) | //Reserved
|
||||
(NONE <<SCS_SHPR_11to8_PRI_9_BIT) | //Reserved
|
||||
(NONE <<SCS_SHPR_11to8_PRI_10_BIT) | //Reserved
|
||||
(HIGH <<SCS_SHPR_11to8_PRI_11_BIT)); //SVCall Handler
|
||||
SCS_SHPR_15to12 = ((MED <<SCS_SHPR_15to12_PRI_12_BIT) | //Debug Monitor Handler
|
||||
(NONE <<SCS_SHPR_15to12_PRI_13_BIT) | //Reserved
|
||||
(HIGH <<SCS_SHPR_15to12_PRI_14_BIT) | //PendSV Handler
|
||||
(MED <<SCS_SHPR_15to12_PRI_15_BIT)); //SysTick Handler
|
||||
NVIC_IPR_3to0 = ((MED <<NVIC_IPR_3to0_PRI_0_BIT) | //Timer 1 Handler
|
||||
(MED <<NVIC_IPR_3to0_PRI_1_BIT) | //Timer 2 Handler
|
||||
(HIGH <<NVIC_IPR_3to0_PRI_2_BIT) | //Management Handler
|
||||
(MED <<NVIC_IPR_3to0_PRI_3_BIT)); //BaseBand Handler
|
||||
NVIC_IPR_7to4 = ((MED <<NVIC_IPR_7to4_PRI_4_BIT) | //Sleep Timer Handler
|
||||
(MED <<NVIC_IPR_7to4_PRI_5_BIT) | //SC1 Handler
|
||||
(MED <<NVIC_IPR_7to4_PRI_6_BIT) | //SC2 Handler
|
||||
(MED <<NVIC_IPR_7to4_PRI_7_BIT)); //Security Handler
|
||||
NVIC_IPR_11to8 = ((MED <<NVIC_IPR_11to8_PRI_8_BIT) | //MAC Timer Handler
|
||||
(MED <<NVIC_IPR_11to8_PRI_9_BIT) | //MAC TX Handler
|
||||
(MED <<NVIC_IPR_11to8_PRI_10_BIT) | //MAC RX Handler
|
||||
(MED <<NVIC_IPR_11to8_PRI_11_BIT)); //ADC Handler
|
||||
NVIC_IPR_15to12 = ((MED <<NVIC_IPR_15to12_PRI_12_BIT) | //GPIO IRQA Handler
|
||||
(MED <<NVIC_IPR_15to12_PRI_13_BIT) | //GPIO IRQB Handler
|
||||
(MED <<NVIC_IPR_15to12_PRI_14_BIT) | //GPIO IRQC Handler
|
||||
(MED <<NVIC_IPR_15to12_PRI_15_BIT)); //GPIO IRQD Handler
|
||||
NVIC_IPR_19to16 = ((LOW <<NVIC_IPR_19to16_PRI_16_BIT)); //Debug Handler
|
||||
//vect33 not implemented
|
||||
//vect34 not implemented
|
||||
//vect35 not implemented
|
||||
|
||||
////---- Always Configure System Handlers Control and Configuration ----////
|
||||
SCS_CCR = SCS_CCR_DIV_0_TRP_MASK;
|
||||
SCS_SHCSR = ( SCS_SHCSR_USGFAULTENA_MASK
|
||||
| SCS_SHCSR_BUSFAULTENA_MASK
|
||||
| SCS_SHCSR_MEMFAULTENA_MASK );
|
||||
|
||||
|
||||
if((RESET_EVENT&RESET_DSLEEP) == RESET_DSLEEP) {
|
||||
//Since the 13 NVIC registers above are fixed values, they are restored
|
||||
//above (where they get set anyways during normal boot sequences) instead
|
||||
//of inside of the halInternalSleep code:
|
||||
|
||||
void halTriggerContextRestore(void);
|
||||
extern volatile boolean halPendSvSaveContext;
|
||||
halPendSvSaveContext = 0; //0 means restore context
|
||||
SCS_ICSR |= SCS_ICSR_PENDSVSET; //pend halPendSvIsr to enable later
|
||||
halTriggerContextRestore(); //sets MSP, enables interrupts
|
||||
//if the context restore worked properly, we should never return here
|
||||
while(1) { ; }
|
||||
}
|
||||
|
||||
INTERRUPTS_OFF();
|
||||
asm("CPSIE i");
|
||||
|
||||
/*==================================*/
|
||||
/* Choose if segment initialization */
|
||||
/* should be done or not. */
|
||||
/* Return: 0 to omit seg_init */
|
||||
/* 1 to run seg_init */
|
||||
/*==================================*/
|
||||
//return 1;
|
||||
unsigned long *pulSrc, *pulDest;
|
||||
|
||||
//
|
||||
// Copy the data segment initializers from flash to SRAM.
|
||||
//
|
||||
pulSrc = &_sidata;
|
||||
for(pulDest = &_sdata; pulDest < &_edata; )
|
||||
{
|
||||
*(pulDest++) = *(pulSrc++);
|
||||
}
|
||||
|
||||
//
|
||||
// Zero fill the bss segment.
|
||||
//
|
||||
for(pulDest = &_sbss; pulDest < &_ebss; )
|
||||
{
|
||||
*(pulDest++) = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// Call the application's entry point.
|
||||
//
|
||||
main();
|
||||
}
|
||||
#ifdef USE_HEAP
|
||||
static unsigned char __HEAP_START[1024*3-560+0x200];
|
||||
caddr_t _sbrk ( int incr )
|
||||
{
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
|
||||
//printf ("_sbrk (%d)\n\r", incr);
|
||||
if (heap == NULL) {
|
||||
heap = (unsigned char *)__HEAP_START;
|
||||
}
|
||||
prev_heap = heap;
|
||||
/* check removed to show basic approach */
|
||||
if ((heap + incr) > (__HEAP_START + sizeof(__HEAP_START))) {
|
||||
prev_heap = NULL;
|
||||
} else {
|
||||
heap += incr;
|
||||
}
|
||||
if (prev_heap == NULL) {
|
||||
printf ("_sbrk %d return %p\n\r", incr, prev_heap);
|
||||
}
|
||||
return (caddr_t) prev_heap;
|
||||
}
|
||||
#else
|
||||
# ifdef DUMMY_MALLOC
|
||||
caddr_t _sbrk ( int incr )
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
int _lseek (int file,
|
||||
int ptr,
|
||||
int dir)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
int _close (int file)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _exit (int n)
|
||||
{
|
||||
/* FIXME: return code is thrown away. */
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int _kill (int n, int m)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
int _fstat(int file, struct stat *st)
|
||||
{
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
int _isatty (int fd)
|
||||
{
|
||||
return 1;
|
||||
fd = fd;
|
||||
}
|
||||
int _getpid (int n)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
int _open (const char * path,
|
||||
int flags,
|
||||
...)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
int _fflush_r(struct _reent *r, FILE *f)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/********************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
245
cpu/stm32w108/hal/micro/cortexm3/stm32w108/gnu.ld
Normal file
245
cpu/stm32w108/hal/micro/cortexm3/stm32w108/gnu.ld
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
/*SEARCH_DIR("C:\Program Files\Raisonance\Ride\Lib\ARM")
|
||||
EXTERN( __io_putchar )
|
||||
EXTERN( _write )
|
||||
GROUP(
|
||||
"std_sbrk_thumb.lib"
|
||||
"smallprintf_thumb.a"
|
||||
"libc.a"
|
||||
"libm.a"
|
||||
)
|
||||
*/
|
||||
/* default stack sizes.
|
||||
|
||||
These are used by the startup in order to allocate stacks for the different modes.
|
||||
*/
|
||||
|
||||
__Stack_Size = 0x400 ;
|
||||
|
||||
PROVIDE ( _Stack_Size = __Stack_Size ) ;
|
||||
|
||||
__Stack_Init = _estack - __Stack_Size ;
|
||||
|
||||
/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
|
||||
PROVIDE ( _Stack_Init = __Stack_Init ) ;
|
||||
|
||||
/*
|
||||
There will be a link error if there is not this amount of RAM free at the end.
|
||||
*/
|
||||
_Minimum_Stack_Size = 0x400 ;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
this sends all unreferenced IRQHandlers to reset
|
||||
*/
|
||||
|
||||
PROVIDE(Default_Handler = 0 );
|
||||
PROVIDE(NMI_Handler = Default_Handler );
|
||||
PROVIDE(HardFault_Handler = Default_Handler );
|
||||
PROVIDE(MemManage_Handler = Default_Handler );
|
||||
PROVIDE(BusFault_Handler = Default_Handler );
|
||||
PROVIDE(UsageFault_Handler = Default_Handler );
|
||||
PROVIDE(SVC_Handler = Default_Handler );
|
||||
PROVIDE(DebugMonitor_Handler = Default_Handler );
|
||||
PROVIDE(PendSV_Handler = Default_Handler );
|
||||
PROVIDE(SysTick_Handler = Default_Handler );
|
||||
PROVIDE(halTimer1Isr = Default_Handler );
|
||||
PROVIDE(halTimer2Isr = Default_Handler );
|
||||
PROVIDE(halManagementIsr = Default_Handler );
|
||||
PROVIDE(halBaseBandIsr = Default_Handler );
|
||||
PROVIDE(halSleepTimerIsr = Default_Handler );
|
||||
PROVIDE(halSc1Isr = Default_Handler );
|
||||
PROVIDE(halSc2Isr = Default_Handler );
|
||||
PROVIDE(halSecurityIsr = Default_Handler );
|
||||
PROVIDE(halStackMacTimerIsr = Default_Handler );
|
||||
PROVIDE(stmRadioTransmitIsr = Default_Handler );
|
||||
PROVIDE(stmRadioReceiveIsr = Default_Handler );
|
||||
PROVIDE(halAdcIsr = Default_Handler );
|
||||
PROVIDE(halIrqAIsr = Default_Handler );
|
||||
PROVIDE(halIrqBIsr = Default_Handler );
|
||||
PROVIDE(halIrqCIsr = Default_Handler );
|
||||
PROVIDE(halIrqDIsr = Default_Handler );
|
||||
PROVIDE(halDebugIsr = Default_Handler );
|
||||
/*PROVIDE(stSerialPrintf = printf );*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/*this allows to compile the ST lib in "non-debug" mode*/
|
||||
|
||||
|
||||
/* include the memory spaces definitions sub-script */
|
||||
MEMORY
|
||||
{
|
||||
RAM_region (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||
ROM_region (rx) : ORIGIN = 0x08000000, LENGTH = 128K-3K
|
||||
NVM_region (rx) : ORIGIN = 0x0801F400, LENGTH = 3K
|
||||
FIB_region (ra) : ORIGIN = 0x08040000, LENGTH = 2K
|
||||
}
|
||||
|
||||
/* higher address of the user mode stack */
|
||||
_estack = 0x20002000;
|
||||
|
||||
/* Sections management for FLASH mode */
|
||||
|
||||
/* Sections Definitions */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >ROM_region
|
||||
|
||||
/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
|
||||
.flashtext :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.flashtext) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >ROM_region
|
||||
|
||||
/* the program code is stored in the .text section, which goes to Flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = _etext;
|
||||
} >ROM_region
|
||||
|
||||
NVM (NOLOAD):
|
||||
{
|
||||
. = ALIGN(1024);
|
||||
KEEP(*(NVM))
|
||||
. = ALIGN(4);
|
||||
} > NVM_region
|
||||
|
||||
|
||||
FAT (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(FAT))
|
||||
. = ALIGN(4);
|
||||
} > FIB_region
|
||||
|
||||
/*
|
||||
.FAT (NOLOAD):
|
||||
{
|
||||
KEEP(*(.FAT))
|
||||
} > FIB_region
|
||||
*/
|
||||
/* after that it's only debugging information. */
|
||||
|
||||
|
||||
/* This is the initialized data section
|
||||
The program executes knowing that the data is in the RAM
|
||||
but the loader puts the initial values in the FLASH (inidata).
|
||||
It is one task of the startup to copy the initial values from FLASH to RAM. */
|
||||
.data : AT ( _sidata )
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM_region
|
||||
|
||||
|
||||
|
||||
/* This is the uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
} >RAM_region
|
||||
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
|
||||
/* This is the user stack section
|
||||
This is just to check that there is enough RAM left for the User mode stack
|
||||
It should generate an error if it's full.
|
||||
*/
|
||||
._usrstack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_susrstack = . ;
|
||||
|
||||
. = . + _Minimum_Stack_Size ;
|
||||
|
||||
. = ALIGN(4);
|
||||
_eusrstack = . ;
|
||||
} >RAM_region
|
||||
|
||||
__exidx_start = .;
|
||||
__exidx_end = .;
|
||||
|
||||
/* remove the debugging information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
30
cpu/stm32w108/hal/micro/cortexm3/stm32w108/iar-cfg.icf
Normal file
30
cpu/stm32w108/hal/micro/cortexm3/stm32w108/iar-cfg.icf
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||
define symbol __ICFEDIT_region_FIB_start__ = 0x08040000;
|
||||
define symbol __ICFEDIT_region_FIB_end__ = 0x080407FF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x500;
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section FAT,
|
||||
section NVM };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place at address mem:__ICFEDIT_region_FIB_start__ { section FAT };
|
||||
place in ROM_region { readonly };
|
||||
place at end of ROM_region { section NVM };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK };
|
||||
173
cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c
Normal file
173
cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
/**************************************************
|
||||
*
|
||||
* This module contains the function `__low_level_init', a function
|
||||
* that is called before the `main' function of the program. Normally
|
||||
* low-level initializations - such as setting the prefered interrupt
|
||||
* level or setting the watchdog - can be performed here.
|
||||
*
|
||||
* Note that this function is called before the data segments are
|
||||
* initialized, this means that this function cannot rely on the
|
||||
* values of global or static variables.
|
||||
*
|
||||
* When this function returns zero, the startup code will inhibit the
|
||||
* initialization of the data segments. The result is faster startup,
|
||||
* the drawback is that neither global nor static data will be
|
||||
* initialized.
|
||||
*
|
||||
* Copyright 1999-2004 IAR Systems. All rights reserved.
|
||||
* Customized by STMicroelectronics for STM32W
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
#include PLATFORM_HEADER
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#pragma language=extended
|
||||
|
||||
#include "hal/micro/cortexm3/memmap.h"
|
||||
__root __no_init const HalFixedAddressTableType halFixedAddressTable @ __FAT__;
|
||||
|
||||
extern const HalVectorTableType __vector_table[];
|
||||
|
||||
|
||||
__interwork int __low_level_init(void);
|
||||
|
||||
__interwork int __low_level_init(void)
|
||||
{
|
||||
//Ensure there is enough margin on VREG_1V8 for stable RAM reads by
|
||||
//setting it to a code of 6. VREG_1V2 can be left at its reset value.
|
||||
VREG = 0x00000307;
|
||||
|
||||
// This code should be careful about the use of local variables in case the
|
||||
// reset type happens to be a deep sleep reset. If the reset is not from
|
||||
// deep sleep, then locals can be freely used
|
||||
|
||||
//When the Cortex-M3 exits reset, interrupts are enable. Explicitely
|
||||
//disable them immediately using the standard set PRIMASK instruction.
|
||||
//Injecting an assembly instruction this early does not effect optimization.
|
||||
asm("CPSID i");
|
||||
|
||||
//It is quite possible that when the Cortex-M3 begins executing code the
|
||||
//Core Reset Vector Catch is still left enabled. Because this VC would
|
||||
//cause us to halt at reset if another reset event tripped, we should
|
||||
//clear it as soon as possible. If a debugger wants to halt at reset,
|
||||
//it will set this bit again.
|
||||
DEBUG_EMCR &= ~DEBUG_EMCR_VC_CORERESET;
|
||||
|
||||
//Configure flash access for optimal current consumption early
|
||||
//during boot to save as much current as we can.
|
||||
FLASH_ACCESS = (FLASH_ACCESS_PREFETCH_EN |
|
||||
(1<<FLASH_ACCESS_CODE_LATENCY_BIT));
|
||||
|
||||
////---- Always remap the vector table ----////
|
||||
// We might be coming from a bootloader at the base of flash, or even in the
|
||||
// NULL_BTL case, the BAT/AAT will be at the beginning of the image
|
||||
SCS_VTOR = (int32u)__vector_table;
|
||||
|
||||
////---- Always Configure Interrupt Priorities ----////
|
||||
//The STM32W support 5 bits of priority configuration.
|
||||
// The cortex allows this to be further divided into preemption and a
|
||||
// "tie-breaker" sub-priority.
|
||||
//We configure a scheme that allows for 3 bits (8 values) of preemption and
|
||||
// 2 bits (4 values) of tie-breaker by using the value 4 in PRIGROUP.
|
||||
//The value 0x05FA0000 is a special key required to write to this register.
|
||||
SCS_AIRCR = (0x05FA0000 | (4 <<SCS_AIRCR_PRIGROUP_BIT));
|
||||
|
||||
//A few macros to help with interrupt priority configuration. Really only
|
||||
// uses 6 of the possible levels, and ignores the tie-breaker sub-priority
|
||||
// for now.
|
||||
//Don't forget that the priority level values need to be shifted into the
|
||||
// top 5 bits of the 8 bit priority fields. (hence the <<3)
|
||||
//
|
||||
// NOTE: The ATOMIC and DISABLE_INTERRUPTS macros work by setting the
|
||||
// current priority to a value of 12, which still allows CRITICAL and
|
||||
// HIGH priority interrupts to fire, while blocking MED and LOW.
|
||||
// If a different value is desired, spmr.s79 will need to be edited.
|
||||
#define CRITICAL (0 <<3)
|
||||
#define HIGH (8 <<3)
|
||||
#define MED (16 <<3)
|
||||
#define LOW (28 <<3)
|
||||
#define NONE (31 <<3)
|
||||
|
||||
//With optimization turned on, the compiler will indentify all the values
|
||||
//and variables used here as constants at compile time and will truncate
|
||||
//this entire block of code to 98 bytes, comprised of 7 load-load-store
|
||||
//operations.
|
||||
//vect00 is fixed //Stack pointer
|
||||
//vect01 is fixed //Reset Vector
|
||||
//vect02 is fixed //NMI Handler
|
||||
//vect03 is fixed //Hard Fault Handler
|
||||
SCS_SHPR_7to4 = ((CRITICAL <<SCS_SHPR_7to4_PRI_4_BIT) | //Memory Fault Handler
|
||||
(CRITICAL <<SCS_SHPR_7to4_PRI_5_BIT) | //Bus Fault Handler
|
||||
(CRITICAL <<SCS_SHPR_7to4_PRI_6_BIT) | //Usage Fault Handler
|
||||
(NONE <<SCS_SHPR_7to4_PRI_7_BIT)); //Reserved
|
||||
SCS_SHPR_11to8 = ((NONE <<SCS_SHPR_11to8_PRI_8_BIT) | //Reserved
|
||||
(NONE <<SCS_SHPR_11to8_PRI_9_BIT) | //Reserved
|
||||
(NONE <<SCS_SHPR_11to8_PRI_10_BIT) | //Reserved
|
||||
(HIGH <<SCS_SHPR_11to8_PRI_11_BIT)); //SVCall Handler
|
||||
SCS_SHPR_15to12 = ((MED <<SCS_SHPR_15to12_PRI_12_BIT) | //Debug Monitor Handler
|
||||
(NONE <<SCS_SHPR_15to12_PRI_13_BIT) | //Reserved
|
||||
(HIGH <<SCS_SHPR_15to12_PRI_14_BIT) | //PendSV Handler
|
||||
(MED <<SCS_SHPR_15to12_PRI_15_BIT)); //SysTick Handler
|
||||
NVIC_IPR_3to0 = ((MED <<NVIC_IPR_3to0_PRI_0_BIT) | //Timer 1 Handler
|
||||
(MED <<NVIC_IPR_3to0_PRI_1_BIT) | //Timer 2 Handler
|
||||
(HIGH <<NVIC_IPR_3to0_PRI_2_BIT) | //Management Handler
|
||||
(MED <<NVIC_IPR_3to0_PRI_3_BIT)); //BaseBand Handler
|
||||
NVIC_IPR_7to4 = ((MED <<NVIC_IPR_7to4_PRI_4_BIT) | //Sleep Timer Handler
|
||||
(MED <<NVIC_IPR_7to4_PRI_5_BIT) | //SC1 Handler
|
||||
(MED <<NVIC_IPR_7to4_PRI_6_BIT) | //SC2 Handler
|
||||
(MED <<NVIC_IPR_7to4_PRI_7_BIT)); //Security Handler
|
||||
NVIC_IPR_11to8 = ((MED <<NVIC_IPR_11to8_PRI_8_BIT) | //MAC Timer Handler
|
||||
(MED <<NVIC_IPR_11to8_PRI_9_BIT) | //MAC TX Handler
|
||||
(MED <<NVIC_IPR_11to8_PRI_10_BIT) | //MAC RX Handler
|
||||
(MED <<NVIC_IPR_11to8_PRI_11_BIT)); //ADC Handler
|
||||
NVIC_IPR_15to12 = ((MED <<NVIC_IPR_15to12_PRI_12_BIT) | //GPIO IRQA Handler
|
||||
(MED <<NVIC_IPR_15to12_PRI_13_BIT) | //GPIO IRQB Handler
|
||||
(MED <<NVIC_IPR_15to12_PRI_14_BIT) | //GPIO IRQC Handler
|
||||
(MED <<NVIC_IPR_15to12_PRI_15_BIT)); //GPIO IRQD Handler
|
||||
NVIC_IPR_19to16 = ((LOW <<NVIC_IPR_19to16_PRI_16_BIT)); //Debug Handler
|
||||
//vect33 not implemented
|
||||
//vect34 not implemented
|
||||
//vect35 not implemented
|
||||
|
||||
////---- Always Configure System Handlers Control and Configuration ----////
|
||||
SCS_CCR = SCS_CCR_DIV_0_TRP_MASK;
|
||||
SCS_SHCSR = ( SCS_SHCSR_USGFAULTENA_MASK
|
||||
| SCS_SHCSR_BUSFAULTENA_MASK
|
||||
| SCS_SHCSR_MEMFAULTENA_MASK );
|
||||
|
||||
|
||||
if((RESET_EVENT&RESET_DSLEEP) == RESET_DSLEEP) {
|
||||
//Since the 13 NVIC registers above are fixed values, they are restored
|
||||
//above (where they get set anyways during normal boot sequences) instead
|
||||
//of inside of the halInternalSleep code:
|
||||
|
||||
void halTriggerContextRestore(void);
|
||||
extern volatile boolean halPendSvSaveContext;
|
||||
halPendSvSaveContext = 0; //0 means restore context
|
||||
SCS_ICSR |= SCS_ICSR_PENDSVSET; //pend halPendSvIsr to enable later
|
||||
halTriggerContextRestore(); //sets MSP, enables interrupts
|
||||
//if the context restore worked properly, we should never return here
|
||||
while(1) { ; }
|
||||
}
|
||||
|
||||
INTERRUPTS_OFF();
|
||||
asm("CPSIE i");
|
||||
|
||||
/*==================================*/
|
||||
/* Choose if segment initialization */
|
||||
/* should be done or not. */
|
||||
/* Return: 0 to omit seg_init */
|
||||
/* 1 to run seg_init */
|
||||
/*==================================*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
#pragma language=default
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
57
cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h
Normal file
57
cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/** @file hal/micro/cortexm3/stm32w108/memmap.h
|
||||
* @brief Definition of STM32W108 chip specific memory map information
|
||||
*
|
||||
* <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
|
||||
*/
|
||||
|
||||
#ifndef __MEMMAP_H__
|
||||
#error This header should not be included directly, use hal/micro/cortexm3/memmap.h
|
||||
#endif
|
||||
|
||||
#ifndef __STM32W108_MEMMAP_H__
|
||||
#define __STM32W108_MEMMAP_H__
|
||||
|
||||
#define RAM_BOTTOM (0x20000000u)
|
||||
#define RAM_SIZE_B (0x2000)
|
||||
#define RAM_SIZE_W (RAM_SIZE_B/4)
|
||||
#define RAM_TOP (RAM_BOTTOM+RAM_SIZE_B-1)
|
||||
|
||||
#define MFB_BOTTOM (0x08000000u)
|
||||
#define MFB_SIZE_B (0x20000)
|
||||
#define MFB_SIZE_W (MFB_SIZE_B/4)
|
||||
#define MFB_TOP (MFB_BOTTOM+MFB_SIZE_B-1)
|
||||
#define MFB_PAGE_SIZE_B (1024)
|
||||
#define MFB_PAGE_SIZE_W (MFB_PAGE_SIZE_B/4)
|
||||
#define MFB_PAGE_MASK_B (0xFFFFFC00)
|
||||
#define MFB_REGION_SIZE (4) // One write protection region is 4 pages.
|
||||
#define MFB_ADDR_MASK (0x0003FFFFu)
|
||||
|
||||
#define CIB_BOTTOM (0x08040800u)
|
||||
#define CIB_SIZE_B (0x200)
|
||||
#define CIB_SIZE_W (CIB_SIZE_B/4)
|
||||
#define CIB_TOP (CIB_BOTTOM+CIB_SIZE_B-1)
|
||||
#define CIB_PAGE_SIZE_B (512)
|
||||
#define CIB_PAGE_SIZE_W (CIB_PAGE_SIZE_B/4)
|
||||
#define CIB_OB_BOTTOM (CIB_BOTTOM+0x00) //bottom address of CIB option bytes
|
||||
#define CIB_OB_TOP (CIB_BOTTOM+0x0F) //top address of CIB option bytes
|
||||
|
||||
#define FIB_BOTTOM (0x08040000u)
|
||||
#define FIB_SIZE_B (0x800)
|
||||
#define FIB_SIZE_W (FIB_SIZE_B/4)
|
||||
#define FIB_TOP (FIB_BOTTOM+FIB_SIZE_B-1)
|
||||
#define FIB_PAGE_SIZE_B (1024)
|
||||
#define FIB_PAGE_SIZE_W (FIB_PAGE_SIZE_B/4)
|
||||
|
||||
#define FPEC_KEY1 0x45670123 //magic key defined in hardware
|
||||
#define FPEC_KEY2 0xCDEF89AB //magic key defined in hardware
|
||||
|
||||
//Translation between page number and simee (word based) address
|
||||
#define SIMEE_ADDR_TO_PAGE(x) ((int8u)(((int16u)(x)) >> 9))
|
||||
#define PAGE_TO_SIMEE_ADDR(x) (((int16u)(x)) << 9)
|
||||
|
||||
//Translation between page number and code addresses, used by bootloaders
|
||||
#define PROG_ADDR_TO_PAGE(x) ((int8u)((((int32u)(x))&MFB_ADDR_MASK) >> 10))
|
||||
#define PAGE_TO_PROG_ADDR(x) ((((int32u)(x)) << 10)|MFB_BOTTOM)
|
||||
|
||||
|
||||
#endif //__STM32W108_MEMMAP_H__
|
||||
924
cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.ddf
Normal file
924
cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.ddf
Normal file
|
|
@ -0,0 +1,924 @@
|
|||
;------------------------------------------------------------------------------
|
||||
; @file regs.ddf
|
||||
; @brief Device Description File for use with IAR's C-SPY
|
||||
;
|
||||
; To see all registers defined in Embedded Workbench's C-SPY Register window,
|
||||
; this file must be pointed to under
|
||||
; Project > Options > Debugger > Device description file
|
||||
;
|
||||
; Please Note: This file is automatically generated, and should not
|
||||
; be directly edited
|
||||
;
|
||||
; COPYRIGHT 2010 STMicroelectronics. All rights reserved.
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
|
||||
; Start of SFR definition.
|
||||
[Sfr]
|
||||
; Name Zone Address Bytesize Displaybase Bitrange
|
||||
; ---- ---- ------- -------- ----------- --------
|
||||
|
||||
sfr = "INT_TIM1FLAG", "Memory", 0x4000A800, 4, base=16
|
||||
sfr = "INT_TIM1FLAG.INT_TIMRSVD", "Memory", 0x4000A800, 4, base=16, bitMask=0x00001E00
|
||||
sfr = "INT_TIM1FLAG.INT_TIMTIF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_TIM1FLAG.INT_TIMCC4IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_TIM1FLAG.INT_TIMCC3IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_TIM1FLAG.INT_TIMCC2IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_TIM1FLAG.INT_TIMCC1IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_TIM1FLAG.INT_TIMUIF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_TIM2FLAG", "Memory", 0x4000A804, 4, base=16
|
||||
sfr = "INT_TIM2FLAG.INT_TIMRSVD", "Memory", 0x4000A804, 4, base=16, bitMask=0x00001E00
|
||||
sfr = "INT_TIM2FLAG.INT_TIMTIF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_TIM2FLAG.INT_TIMCC4IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_TIM2FLAG.INT_TIMCC3IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_TIM2FLAG.INT_TIMCC2IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_TIM2FLAG.INT_TIMCC1IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_TIM2FLAG.INT_TIMUIF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_SC1FLAG", "Memory", 0x4000A808, 4, base=16
|
||||
sfr = "INT_SC1FLAG.INT_SC1PARERR", "Memory", 0x4000A808, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_SC1FLAG.INT_SC1FRMERR", "Memory", 0x4000A808, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_SC1FLAG.INT_SCTXULDB", "Memory", 0x4000A808, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_SC1FLAG.INT_SCTXULDA", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_SC1FLAG.INT_SCRXULDB", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_SC1FLAG.INT_SCRXULDA", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_SC1FLAG.INT_SCNAK", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_SC1FLAG.INT_SCCMDFIN", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_SC1FLAG.INT_SCTXFIN", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_SC1FLAG.INT_SCRXFIN", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_SC1FLAG.INT_SCTXUND", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_SC1FLAG.INT_SCRXOVF", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_SC1FLAG.INT_SCTXIDLE", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_SC1FLAG.INT_SCTXFREE", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_SC1FLAG.INT_SCRXVAL", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_SC2FLAG", "Memory", 0x4000A80C, 4, base=16
|
||||
sfr = "INT_SC2FLAG.INT_SCTXULDB", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_SC2FLAG.INT_SCTXULDA", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_SC2FLAG.INT_SCRXULDB", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_SC2FLAG.INT_SCRXULDA", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_SC2FLAG.INT_SCNAK", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_SC2FLAG.INT_SCCMDFIN", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_SC2FLAG.INT_SCTXFIN", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_SC2FLAG.INT_SCRXFIN", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_SC2FLAG.INT_SCTXUND", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_SC2FLAG.INT_SCRXOVF", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_SC2FLAG.INT_SCTXIDLE", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_SC2FLAG.INT_SCTXFREE", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_SC2FLAG.INT_SCRXVAL", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_ADCFLAG", "Memory", 0x4000A810, 4, base=16
|
||||
sfr = "INT_ADCFLAG.INT_ADCOVF", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_ADCFLAG.INT_ADCSAT", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_ADCFLAG.INT_ADCULDFULL", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_ADCFLAG.INT_ADCULDHALF", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_ADCFLAG.INT_ADCFLAGRSVD", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_GPIOFLAG", "Memory", 0x4000A814, 4, base=16
|
||||
sfr = "INT_GPIOFLAG.INT_IRQDFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_GPIOFLAG.INT_IRQCFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_GPIOFLAG.INT_IRQBFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_GPIOFLAG.INT_IRQAFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_TIM1MISS", "Memory", 0x4000A818, 4, base=16
|
||||
sfr = "INT_TIM1MISS.INT_TIMMISSCC4IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_TIM1MISS.INT_TIMMISSCC3IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_TIM1MISS.INT_TIMMISSCC2IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_TIM1MISS.INT_TIMMISSCC1IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_TIM1MISS.INT_TIMMISSRSVD", "Memory", 0x4000A818, 4, base=16, bitMask=0x0000007F
|
||||
|
||||
sfr = "INT_TIM2MISS", "Memory", 0x4000A81C, 4, base=16
|
||||
sfr = "INT_TIM2MISS.INT_TIMMISSCC4IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_TIM2MISS.INT_TIMMISSCC3IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_TIM2MISS.INT_TIMMISSCC2IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_TIM2MISS.INT_TIMMISSCC1IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_TIM2MISS.INT_TIMMISSRSVD", "Memory", 0x4000A81C, 4, base=16, bitMask=0x0000007F
|
||||
|
||||
sfr = "INT_MISS", "Memory", 0x4000A820, 4, base=16
|
||||
sfr = "INT_MISS.INT_MISSIRQD", "Memory", 0x4000A820, 4, base=16, bitMask=0x00008000
|
||||
sfr = "INT_MISS.INT_MISSIRQC", "Memory", 0x4000A820, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_MISS.INT_MISSIRQB", "Memory", 0x4000A820, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_MISS.INT_MISSIRQA", "Memory", 0x4000A820, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_MISS.INT_MISSADC", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_MISS.INT_MISSMACRX", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_MISS.INT_MISSMACTX", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_MISS.INT_MISSMACTMR", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_MISS.INT_MISSSEC", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_MISS.INT_MISSSC2", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_MISS.INT_MISSSC1", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_MISS.INT_MISSSLEEP", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_MISS.INT_MISSBB", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_MISS.INT_MISSMGMT", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000004
|
||||
|
||||
sfr = "INT_TIM1CFG", "Memory", 0x4000A840, 4, base=16
|
||||
sfr = "INT_TIM1CFG.INT_TIMTIF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_TIM1CFG.INT_TIMCC4IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_TIM1CFG.INT_TIMCC3IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_TIM1CFG.INT_TIMCC2IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_TIM1CFG.INT_TIMCC1IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_TIM1CFG.INT_TIMUIF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_TIM2CFG", "Memory", 0x4000A844, 4, base=16
|
||||
sfr = "INT_TIM2CFG.INT_TIMTIF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_TIM2CFG.INT_TIMCC4IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_TIM2CFG.INT_TIMCC3IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_TIM2CFG.INT_TIMCC2IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_TIM2CFG.INT_TIMCC1IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_TIM2CFG.INT_TIMUIF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_SC1CFG", "Memory", 0x4000A848, 4, base=16
|
||||
sfr = "INT_SC1CFG.INT_SC1PARERR", "Memory", 0x4000A848, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_SC1CFG.INT_SC1FRMERR", "Memory", 0x4000A848, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_SC1CFG.INT_SCTXULDB", "Memory", 0x4000A848, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_SC1CFG.INT_SCTXULDA", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_SC1CFG.INT_SCRXULDB", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_SC1CFG.INT_SCRXULDA", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_SC1CFG.INT_SCNAK", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_SC1CFG.INT_SCCMDFIN", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_SC1CFG.INT_SCTXFIN", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_SC1CFG.INT_SCRXFIN", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_SC1CFG.INT_SCTXUND", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_SC1CFG.INT_SCRXOVF", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_SC1CFG.INT_SCTXIDLE", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_SC1CFG.INT_SCTXFREE", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_SC1CFG.INT_SCRXVAL", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_SC2CFG", "Memory", 0x4000A84C, 4, base=16
|
||||
sfr = "INT_SC2CFG.INT_SCTXULDB", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_SC2CFG.INT_SCTXULDA", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_SC2CFG.INT_SCRXULDB", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_SC2CFG.INT_SCRXULDA", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_SC2CFG.INT_SCNAK", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_SC2CFG.INT_SCCMDFIN", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_SC2CFG.INT_SCTXFIN", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_SC2CFG.INT_SCRXFIN", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_SC2CFG.INT_SCTXUND", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_SC2CFG.INT_SCRXOVF", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_SC2CFG.INT_SCTXIDLE", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_SC2CFG.INT_SCTXFREE", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_SC2CFG.INT_SCRXVAL", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_ADCCFG", "Memory", 0x4000A850, 4, base=16
|
||||
sfr = "INT_ADCCFG.INT_ADCOVF", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_ADCCFG.INT_ADCSAT", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_ADCCFG.INT_ADCULDFULL", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_ADCCFG.INT_ADCULDHALF", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_ADCCFG.INT_ADCCFGRSVD", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_INTMODE", "Memory", 0x4000A854, 4, base=16
|
||||
sfr = "SC1_INTMODE.SC_TXIDLELEVEL", "Memory", 0x4000A854, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_INTMODE.SC_TXFREELEVEL", "Memory", 0x4000A854, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_INTMODE.SC_RXVALLEVEL", "Memory", 0x4000A854, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_INTMODE", "Memory", 0x4000A858, 4, base=16
|
||||
sfr = "SC2_INTMODE.SC_TXIDLELEVEL", "Memory", 0x4000A858, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_INTMODE.SC_TXFREELEVEL", "Memory", 0x4000A858, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_INTMODE.SC_RXVALLEVEL", "Memory", 0x4000A858, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_INTCFGA", "Memory", 0x4000A860, 4, base=16
|
||||
sfr = "GPIO_INTCFGA.GPIO_INTFILT", "Memory", 0x4000A860, 4, base=16, bitMask=0x00000100
|
||||
sfr = "GPIO_INTCFGA.GPIO_INTMOD", "Memory", 0x4000A860, 4, base=16, bitMask=0x000000E0
|
||||
|
||||
sfr = "GPIO_INTCFGB", "Memory", 0x4000A864, 4, base=16
|
||||
sfr = "GPIO_INTCFGB.GPIO_INTFILT", "Memory", 0x4000A864, 4, base=16, bitMask=0x00000100
|
||||
sfr = "GPIO_INTCFGB.GPIO_INTMOD", "Memory", 0x4000A864, 4, base=16, bitMask=0x000000E0
|
||||
|
||||
sfr = "GPIO_INTCFGC", "Memory", 0x4000A868, 4, base=16
|
||||
sfr = "GPIO_INTCFGC.GPIO_INTFILT", "Memory", 0x4000A868, 4, base=16, bitMask=0x00000100
|
||||
sfr = "GPIO_INTCFGC.GPIO_INTMOD", "Memory", 0x4000A868, 4, base=16, bitMask=0x000000E0
|
||||
|
||||
sfr = "GPIO_INTCFGD", "Memory", 0x4000A86C, 4, base=16
|
||||
sfr = "GPIO_INTCFGD.GPIO_INTFILT", "Memory", 0x4000A86C, 4, base=16, bitMask=0x00000100
|
||||
sfr = "GPIO_INTCFGD.GPIO_INTMOD", "Memory", 0x4000A86C, 4, base=16, bitMask=0x000000E0
|
||||
|
||||
sfr = "GPIO_PACFGL", "Memory", 0x4000B000, 4, base=16
|
||||
sfr = "GPIO_PACFGL.PA3_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "GPIO_PACFGL.PA2_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "GPIO_PACFGL.PA1_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "GPIO_PACFGL.PA0_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "GPIO_PACFGH", "Memory", 0x4000B004, 4, base=16
|
||||
sfr = "GPIO_PACFGH.PA7_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "GPIO_PACFGH.PA6_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "GPIO_PACFGH.PA5_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "GPIO_PACFGH.PA4_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "GPIO_PAIN", "Memory", 0x4000B008, 4, base=16
|
||||
sfr = "GPIO_PAIN.PA7", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PAIN.PA6", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PAIN.PA5", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PAIN.PA4", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PAIN.PA3", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PAIN.PA2", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PAIN.PA1", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PAIN.PA0", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PAOUT", "Memory", 0x4000B00C, 4, base=16
|
||||
sfr = "GPIO_PAOUT.PA7", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PAOUT.PA6", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PAOUT.PA5", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PAOUT.PA4", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PAOUT.PA3", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PAOUT.PA2", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PAOUT.PA1", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PAOUT.PA0", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PASET", "Memory", 0x4000B010, 4, base=16
|
||||
sfr = "GPIO_PASET.GPIO_PXSETRSVD", "Memory", 0x4000B010, 4, base=16, bitMask=0x0000FF00
|
||||
sfr = "GPIO_PASET.PA7", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PASET.PA6", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PASET.PA5", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PASET.PA4", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PASET.PA3", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PASET.PA2", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PASET.PA1", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PASET.PA0", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PACLR", "Memory", 0x4000B014, 4, base=16
|
||||
sfr = "GPIO_PACLR.PA7", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PACLR.PA6", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PACLR.PA5", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PACLR.PA4", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PACLR.PA3", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PACLR.PA2", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PACLR.PA1", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PACLR.PA0", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PBCFGL", "Memory", 0x4000B400, 4, base=16
|
||||
sfr = "GPIO_PBCFGL.PB3_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "GPIO_PBCFGL.PB2_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "GPIO_PBCFGL.PB1_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "GPIO_PBCFGL.PB0_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "GPIO_PBCFGH", "Memory", 0x4000B404, 4, base=16
|
||||
sfr = "GPIO_PBCFGH.PB7_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "GPIO_PBCFGH.PB6_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "GPIO_PBCFGH.PB5_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "GPIO_PBCFGH.PB4_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "GPIO_PBIN", "Memory", 0x4000B408, 4, base=16
|
||||
sfr = "GPIO_PBIN.PB7", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PBIN.PB6", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PBIN.PB5", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PBIN.PB4", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PBIN.PB3", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PBIN.PB2", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PBIN.PB1", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PBIN.PB0", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PBOUT", "Memory", 0x4000B40C, 4, base=16
|
||||
sfr = "GPIO_PBOUT.PB7", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PBOUT.PB6", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PBOUT.PB5", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PBOUT.PB4", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PBOUT.PB3", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PBOUT.PB2", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PBOUT.PB1", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PBOUT.PB0", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PBSET", "Memory", 0x4000B410, 4, base=16
|
||||
sfr = "GPIO_PBSET.GPIO_PXSETRSVD", "Memory", 0x4000B410, 4, base=16, bitMask=0x0000FF00
|
||||
sfr = "GPIO_PBSET.PB7", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PBSET.PB6", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PBSET.PB5", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PBSET.PB4", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PBSET.PB3", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PBSET.PB2", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PBSET.PB1", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PBSET.PB0", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PBCLR", "Memory", 0x4000B414, 4, base=16
|
||||
sfr = "GPIO_PBCLR.PB7", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PBCLR.PB6", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PBCLR.PB5", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PBCLR.PB4", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PBCLR.PB3", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PBCLR.PB2", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PBCLR.PB1", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PBCLR.PB0", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PCCFGL", "Memory", 0x4000B800, 4, base=16
|
||||
sfr = "GPIO_PCCFGL.PC3_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "GPIO_PCCFGL.PC2_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "GPIO_PCCFGL.PC1_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "GPIO_PCCFGL.PC0_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "GPIO_PCCFGH", "Memory", 0x4000B804, 4, base=16
|
||||
sfr = "GPIO_PCCFGH.PC7_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "GPIO_PCCFGH.PC6_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "GPIO_PCCFGH.PC5_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "GPIO_PCCFGH.PC4_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "GPIO_PCIN", "Memory", 0x4000B808, 4, base=16
|
||||
sfr = "GPIO_PCIN.PC7", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PCIN.PC6", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PCIN.PC5", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PCIN.PC4", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PCIN.PC3", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PCIN.PC2", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PCIN.PC1", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PCIN.PC0", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PCOUT", "Memory", 0x4000B80C, 4, base=16
|
||||
sfr = "GPIO_PCOUT.PC7", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PCOUT.PC6", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PCOUT.PC5", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PCOUT.PC4", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PCOUT.PC3", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PCOUT.PC2", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PCOUT.PC1", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PCOUT.PC0", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PCSET", "Memory", 0x4000B810, 4, base=16
|
||||
sfr = "GPIO_PCSET.GPIO_PXSETRSVD", "Memory", 0x4000B810, 4, base=16, bitMask=0x0000FF00
|
||||
sfr = "GPIO_PCSET.PC7", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PCSET.PC6", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PCSET.PC5", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PCSET.PC4", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PCSET.PC3", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PCSET.PC2", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PCSET.PC1", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PCSET.PC0", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PCCLR", "Memory", 0x4000B814, 4, base=16
|
||||
sfr = "GPIO_PCCLR.PC7", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PCCLR.PC6", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PCCLR.PC5", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PCCLR.PC4", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PCCLR.PC3", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PCCLR.PC2", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PCCLR.PC1", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PCCLR.PC0", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_DBGCFG", "Memory", 0x4000BC00, 4, base=16
|
||||
sfr = "GPIO_DBGCFG.GPIO_DEBUGDIS", "Memory", 0x4000BC00, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_DBGCFG.GPIO_EXTREGEN", "Memory", 0x4000BC00, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_DBGCFG.GPIO_DBGCFGRSVD", "Memory", 0x4000BC00, 4, base=16, bitMask=0x00000008
|
||||
|
||||
sfr = "GPIO_DBGSTAT", "Memory", 0x4000BC04, 4, base=16
|
||||
sfr = "GPIO_DBGSTAT.GPIO_BOOTMODE", "Memory", 0x4000BC04, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_DBGSTAT.GPIO_FORCEDBG", "Memory", 0x4000BC04, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_DBGSTAT.GPIO_SWEN", "Memory", 0x4000BC04, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PAWAKE", "Memory", 0x4000BC08, 4, base=16
|
||||
sfr = "GPIO_PAWAKE.PA7", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PAWAKE.PA6", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PAWAKE.PA5", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PAWAKE.PA4", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PAWAKE.PA3", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PAWAKE.PA2", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PAWAKE.PA1", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PAWAKE.PA0", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PBWAKE", "Memory", 0x4000BC0C, 4, base=16
|
||||
sfr = "GPIO_PBWAKE.PB7", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PBWAKE.PB6", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PBWAKE.PB5", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PBWAKE.PB4", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PBWAKE.PB3", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PBWAKE.PB2", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PBWAKE.PB1", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PBWAKE.PB0", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_PCWAKE", "Memory", 0x4000BC10, 4, base=16
|
||||
sfr = "GPIO_PCWAKE.PC7", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000080
|
||||
sfr = "GPIO_PCWAKE.PC6", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000040
|
||||
sfr = "GPIO_PCWAKE.PC5", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000020
|
||||
sfr = "GPIO_PCWAKE.PC4", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000010
|
||||
sfr = "GPIO_PCWAKE.PC3", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_PCWAKE.PC2", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_PCWAKE.PC1", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_PCWAKE.PC0", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "GPIO_IRQCSEL", "Memory", 0x4000BC14, 4, base=16
|
||||
|
||||
sfr = "GPIO_IRQDSEL", "Memory", 0x4000BC18, 4, base=16
|
||||
|
||||
sfr = "GPIO_WAKEFILT", "Memory", 0x4000BC1C, 4, base=16
|
||||
sfr = "GPIO_WAKEFILT.IRQD_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "GPIO_WAKEFILT.SC2_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "GPIO_WAKEFILT.SC1_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "GPIO_WAKEFILT.GPIO_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_RXBEGA", "Memory", 0x4000C000, 4, base=16
|
||||
|
||||
sfr = "SC2_RXENDA", "Memory", 0x4000C004, 4, base=16
|
||||
|
||||
sfr = "SC2_RXBEGB", "Memory", 0x4000C008, 4, base=16
|
||||
|
||||
sfr = "SC2_RXENDB", "Memory", 0x4000C00C, 4, base=16
|
||||
|
||||
sfr = "SC2_TXBEGA", "Memory", 0x4000C010, 4, base=16
|
||||
|
||||
sfr = "SC2_TXENDA", "Memory", 0x4000C014, 4, base=16
|
||||
|
||||
sfr = "SC2_TXBEGB", "Memory", 0x4000C018, 4, base=16
|
||||
|
||||
sfr = "SC2_TXENDB", "Memory", 0x4000C01C, 4, base=16
|
||||
|
||||
sfr = "SC2_RXCNTA", "Memory", 0x4000C020, 4, base=16
|
||||
|
||||
sfr = "SC2_RXCNTB", "Memory", 0x4000C024, 4, base=16
|
||||
|
||||
sfr = "SC2_TXCNT", "Memory", 0x4000C028, 4, base=16
|
||||
|
||||
sfr = "SC2_DMASTAT", "Memory", 0x4000C02C, 4, base=16
|
||||
sfr = "SC2_DMASTAT.SC_RXSSEL", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00001C00
|
||||
sfr = "SC2_DMASTAT.SC_RXOVFB", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC2_DMASTAT.SC_RXOVFA", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC2_DMASTAT.SC_TXACTB", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC2_DMASTAT.SC_TXACTA", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_DMASTAT.SC_RXACTB", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_DMASTAT.SC_RXACTA", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_DMACTRL", "Memory", 0x4000C030, 4, base=16
|
||||
sfr = "SC2_DMACTRL.SC_TXDMARST", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC2_DMACTRL.SC_RXDMARST", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC2_DMACTRL.SC_TXLODB", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC2_DMACTRL.SC_TXLODA", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_DMACTRL.SC_RXLODB", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_DMACTRL.SC_RXLODA", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_RXERRA", "Memory", 0x4000C034, 4, base=16
|
||||
|
||||
sfr = "SC2_RXERRB", "Memory", 0x4000C038, 4, base=16
|
||||
|
||||
sfr = "SC2_DATA", "Memory", 0x4000C03C, 4, base=16
|
||||
|
||||
sfr = "SC2_SPISTAT", "Memory", 0x4000C040, 4, base=16
|
||||
sfr = "SC2_SPISTAT.SC_SPITXIDLE", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC2_SPISTAT.SC_SPITXFREE", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_SPISTAT.SC_SPIRXVAL", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_SPISTAT.SC_SPIRXOVF", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_TWISTAT", "Memory", 0x4000C044, 4, base=16
|
||||
sfr = "SC2_TWISTAT.SC_TWICMDFIN", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC2_TWISTAT.SC_TWIRXFIN", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_TWISTAT.SC_TWITXFIN", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_TWISTAT.SC_TWIRXNAK", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_TWICTRL1", "Memory", 0x4000C04C, 4, base=16
|
||||
sfr = "SC2_TWICTRL1.SC_TWISTOP", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC2_TWICTRL1.SC_TWISTART", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_TWICTRL1.SC_TWISEND", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_TWICTRL1.SC_TWIRECV", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_TWICTRL2", "Memory", 0x4000C050, 4, base=16
|
||||
|
||||
sfr = "SC2_MODE", "Memory", 0x4000C054, 4, base=16
|
||||
|
||||
sfr = "SC2_SPICFG", "Memory", 0x4000C058, 4, base=16
|
||||
sfr = "SC2_SPICFG.SC_SPIRXDRV", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC2_SPICFG.SC_SPIMST", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC2_SPICFG.SC_SPIRPT", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC2_SPICFG.SC_SPIORD", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC2_SPICFG.SC_SPIPHA", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC2_SPICFG.SC_SPIPOL", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC2_RATELIN", "Memory", 0x4000C060, 4, base=16
|
||||
sfr = "SC2_RATELIN.SC_RATELIN", "Memory", 0x4000C060, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "SC2_RATEEXP", "Memory", 0x4000C064, 4, base=16
|
||||
sfr = "SC2_RATEEXP.SC_RATEEXP", "Memory", 0x4000C064, 4, base=16, bitMask=0x0000000F
|
||||
|
||||
sfr = "SC2_RXCNTSAVED", "Memory", 0x4000C070, 4, base=16
|
||||
|
||||
sfr = "SC1_RXBEGA", "Memory", 0x4000C800, 4, base=16
|
||||
|
||||
sfr = "SC1_RXENDA", "Memory", 0x4000C804, 4, base=16
|
||||
|
||||
sfr = "SC1_RXBEGB", "Memory", 0x4000C808, 4, base=16
|
||||
|
||||
sfr = "SC1_RXENDB", "Memory", 0x4000C80C, 4, base=16
|
||||
|
||||
sfr = "SC1_TXBEGA", "Memory", 0x4000C810, 4, base=16
|
||||
|
||||
sfr = "SC1_TXENDA", "Memory", 0x4000C814, 4, base=16
|
||||
|
||||
sfr = "SC1_TXBEGB", "Memory", 0x4000C818, 4, base=16
|
||||
|
||||
sfr = "SC1_TXENDB", "Memory", 0x4000C81C, 4, base=16
|
||||
|
||||
sfr = "SC1_RXCNTA", "Memory", 0x4000C820, 4, base=16
|
||||
|
||||
sfr = "SC1_RXCNTB", "Memory", 0x4000C824, 4, base=16
|
||||
|
||||
sfr = "SC1_TXCNT", "Memory", 0x4000C828, 4, base=16
|
||||
|
||||
sfr = "SC1_DMASTAT", "Memory", 0x4000C82C, 4, base=16
|
||||
sfr = "SC1_DMASTAT.SC_RXSSEL", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00001C00
|
||||
sfr = "SC1_DMASTAT.SC_RXFRMB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000200
|
||||
sfr = "SC1_DMASTAT.SC_RXFRMA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000100
|
||||
sfr = "SC1_DMASTAT.SC_RXPARB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "SC1_DMASTAT.SC_RXPARA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "SC1_DMASTAT.SC_RXOVFB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC1_DMASTAT.SC_RXOVFA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC1_DMASTAT.SC_TXACTB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_DMASTAT.SC_TXACTA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_DMASTAT.SC_RXACTB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_DMASTAT.SC_RXACTA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_DMACTRL", "Memory", 0x4000C830, 4, base=16
|
||||
sfr = "SC1_DMACTRL.SC_TXDMARST", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC1_DMACTRL.SC_RXDMARST", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC1_DMACTRL.SC_TXLODB", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_DMACTRL.SC_TXLODA", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_DMACTRL.SC_RXLODB", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_DMACTRL.SC_RXLODA", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_RXERRA", "Memory", 0x4000C834, 4, base=16
|
||||
|
||||
sfr = "SC1_RXERRB", "Memory", 0x4000C838, 4, base=16
|
||||
|
||||
sfr = "SC1_DATA", "Memory", 0x4000C83C, 4, base=16
|
||||
|
||||
sfr = "SC1_SPISTAT", "Memory", 0x4000C840, 4, base=16
|
||||
sfr = "SC1_SPISTAT.SC_SPITXIDLE", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_SPISTAT.SC_SPITXFREE", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_SPISTAT.SC_SPIRXVAL", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_SPISTAT.SC_SPIRXOVF", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_TWISTAT", "Memory", 0x4000C844, 4, base=16
|
||||
sfr = "SC1_TWISTAT.SC_TWICMDFIN", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_TWISTAT.SC_TWIRXFIN", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_TWISTAT.SC_TWITXFIN", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_TWISTAT.SC_TWIRXNAK", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_UARTSTAT", "Memory", 0x4000C848, 4, base=16
|
||||
sfr = "SC1_UARTSTAT.SC_UARTTXIDLE", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000040
|
||||
sfr = "SC1_UARTSTAT.SC_UARTPARERR", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC1_UARTSTAT.SC_UARTFRMERR", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC1_UARTSTAT.SC_UARTRXOVF", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_UARTSTAT.SC_UARTTXFREE", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_UARTSTAT.SC_UARTRXVAL", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_UARTSTAT.SC_UARTCTS", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_TWICTRL1", "Memory", 0x4000C84C, 4, base=16
|
||||
sfr = "SC1_TWICTRL1.SC_TWISTOP", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_TWICTRL1.SC_TWISTART", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_TWICTRL1.SC_TWISEND", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_TWICTRL1.SC_TWIRECV", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_TWICTRL2", "Memory", 0x4000C850, 4, base=16
|
||||
|
||||
sfr = "SC1_MODE", "Memory", 0x4000C854, 4, base=16
|
||||
|
||||
sfr = "SC1_SPICFG", "Memory", 0x4000C858, 4, base=16
|
||||
sfr = "SC1_SPICFG.SC_SPIRXDRV", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC1_SPICFG.SC_SPIMST", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC1_SPICFG.SC_SPIRPT", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_SPICFG.SC_SPIORD", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_SPICFG.SC_SPIPHA", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_SPICFG.SC_SPIPOL", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_UARTCFG", "Memory", 0x4000C85C, 4, base=16
|
||||
sfr = "SC1_UARTCFG.SC_UARTAUTO", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000040
|
||||
sfr = "SC1_UARTCFG.SC_UARTFLOW", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000020
|
||||
sfr = "SC1_UARTCFG.SC_UARTODD", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000010
|
||||
sfr = "SC1_UARTCFG.SC_UARTPAR", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SC1_UARTCFG.SC_UART2STP", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SC1_UARTCFG.SC_UART8BIT", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SC1_UARTCFG.SC_UARTRTS", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SC1_RATELIN", "Memory", 0x4000C860, 4, base=16
|
||||
|
||||
sfr = "SC1_RATEEXP", "Memory", 0x4000C864, 4, base=16
|
||||
|
||||
sfr = "SC1_UARTPER", "Memory", 0x4000C868, 4, base=16
|
||||
|
||||
sfr = "SC1_UARTFRAC", "Memory", 0x4000C86C, 4, base=16
|
||||
|
||||
sfr = "SC1_RXCNTSAVED", "Memory", 0x4000C870, 4, base=16
|
||||
|
||||
sfr = "ADC_CFG", "Memory", 0x4000D004, 4, base=16
|
||||
sfr = "ADC_CFG.ADC_PERIOD", "Memory", 0x4000D004, 4, base=16, bitMask=0x0000E000
|
||||
sfr = "ADC_CFG.ADC_HVSELP", "Memory", 0x4000D004, 4, base=16, bitMask=0x00001000
|
||||
sfr = "ADC_CFG.ADC_HVSELN", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000800
|
||||
sfr = "ADC_CFG.ADC_MUXP", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000780
|
||||
sfr = "ADC_CFG.ADC_MUXN", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000078
|
||||
sfr = "ADC_CFG.ADC_1MHZCLK", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000004
|
||||
sfr = "ADC_CFG.ADC_CFGRSVD", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000002
|
||||
sfr = "ADC_CFG.ADC_ENABLE", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "ADC_OFFSET", "Memory", 0x4000D008, 4, base=16
|
||||
|
||||
sfr = "ADC_GAIN", "Memory", 0x4000D00C, 4, base=16
|
||||
|
||||
sfr = "ADC_DMACFG", "Memory", 0x4000D010, 4, base=16
|
||||
sfr = "ADC_DMACFG.ADC_DMARST", "Memory", 0x4000D010, 4, base=16, bitMask=0x00000010
|
||||
sfr = "ADC_DMACFG.ADC_DMAAUTOWRAP", "Memory", 0x4000D010, 4, base=16, bitMask=0x00000002
|
||||
sfr = "ADC_DMACFG.ADC_DMALOAD", "Memory", 0x4000D010, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "ADC_DMASTAT", "Memory", 0x4000D014, 4, base=16
|
||||
sfr = "ADC_DMASTAT.ADC_DMAOVF", "Memory", 0x4000D014, 4, base=16, bitMask=0x00000002
|
||||
sfr = "ADC_DMASTAT.ADC_DMAACT", "Memory", 0x4000D014, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "ADC_DMABEG", "Memory", 0x4000D018, 4, base=16
|
||||
|
||||
sfr = "ADC_DMASIZE", "Memory", 0x4000D01C, 4, base=16
|
||||
|
||||
sfr = "ADC_DMACUR", "Memory", 0x4000D020, 4, base=16
|
||||
|
||||
sfr = "ADC_DMACNT", "Memory", 0x4000D024, 4, base=16
|
||||
|
||||
sfr = "TIM1_CR1", "Memory", 0x4000E000, 4, base=16
|
||||
sfr = "TIM1_CR1.TIM_ARBE", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM1_CR1.TIM_CMS", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000060
|
||||
sfr = "TIM1_CR1.TIM_DIR", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM1_CR1.TIM_OPM", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM1_CR1.TIM_URS", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM1_CR1.TIM_UDIS", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000002
|
||||
sfr = "TIM1_CR1.TIM_CEN", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "TIM1_CR2", "Memory", 0x4000E004, 4, base=16
|
||||
sfr = "TIM1_CR2.TIM_TI1S", "Memory", 0x4000E004, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM1_CR2.TIM_MMS", "Memory", 0x4000E004, 4, base=16, bitMask=0x00000070
|
||||
|
||||
sfr = "TIM1_SMCR", "Memory", 0x4000E008, 4, base=16
|
||||
sfr = "TIM1_SMCR.TIM_ETP", "Memory", 0x4000E008, 4, base=16, bitMask=0x00008000
|
||||
sfr = "TIM1_SMCR.TIM_ECE", "Memory", 0x4000E008, 4, base=16, bitMask=0x00004000
|
||||
sfr = "TIM1_SMCR.TIM_ETPS", "Memory", 0x4000E008, 4, base=16, bitMask=0x00003000
|
||||
sfr = "TIM1_SMCR.TIM_ETF", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "TIM1_SMCR.TIM_MSM", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM1_SMCR.TIM_TS", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000070
|
||||
sfr = "TIM1_SMCR.TIM_SMS", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000007
|
||||
|
||||
sfr = "TIM1_EGR", "Memory", 0x4000E014, 4, base=16
|
||||
sfr = "TIM1_EGR.TIM_TG", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000040
|
||||
sfr = "TIM1_EGR.TIM_CC4G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM1_EGR.TIM_CC3G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM1_EGR.TIM_CC2G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM1_EGR.TIM_CC1G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000002
|
||||
sfr = "TIM1_EGR.TIM_UG", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "TIM1_CCMR1", "Memory", 0x4000E018, 4, base=16
|
||||
sfr = "TIM1_CCMR1.TIM_IC2F", "Memory", 0x4000E018, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "TIM1_CCMR1.TIM_IC2PSC", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000C00
|
||||
sfr = "TIM1_CCMR1.TIM_IC1F", "Memory", 0x4000E018, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "TIM1_CCMR1.TIM_IC1PSC", "Memory", 0x4000E018, 4, base=16, bitMask=0x0000000C
|
||||
sfr = "TIM1_CCMR1.TIM_OC2CE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00008000
|
||||
sfr = "TIM1_CCMR1.TIM_OC2M", "Memory", 0x4000E018, 4, base=16, bitMask=0x00007000
|
||||
sfr = "TIM1_CCMR1.TIM_OC2BE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000800
|
||||
sfr = "TIM1_CCMR1.TIM_OC2FE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000400
|
||||
sfr = "TIM1_CCMR1.TIM_CC2S", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000300
|
||||
sfr = "TIM1_CCMR1.TIM_OC1CE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM1_CCMR1.TIM_OC1M", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000070
|
||||
sfr = "TIM1_CCMR1.TIM_OC1PE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM1_CCMR1.TIM_OC1FE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM1_CCMR1.TIM_CC1S", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000003
|
||||
|
||||
sfr = "TIM1_CCMR2", "Memory", 0x4000E01C, 4, base=16
|
||||
sfr = "TIM1_CCMR2.TIM_IC4F", "Memory", 0x4000E01C, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "TIM1_CCMR2.TIM_IC4PSC", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000C00
|
||||
sfr = "TIM1_CCMR2.TIM_IC3F", "Memory", 0x4000E01C, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "TIM1_CCMR2.TIM_IC3PSC", "Memory", 0x4000E01C, 4, base=16, bitMask=0x0000000C
|
||||
sfr = "TIM1_CCMR2.TIM_OC4CE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00008000
|
||||
sfr = "TIM1_CCMR2.TIM_OC4M", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00007000
|
||||
sfr = "TIM1_CCMR2.TIM_OC4BE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000800
|
||||
sfr = "TIM1_CCMR2.TIM_OC4FE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000400
|
||||
sfr = "TIM1_CCMR2.TIM_CC4S", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000300
|
||||
sfr = "TIM1_CCMR2.TIM_OC3CE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM1_CCMR2.TIM_OC3M", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000070
|
||||
sfr = "TIM1_CCMR2.TIM_OC3BE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM1_CCMR2.TIM_OC3FE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM1_CCMR2.TIM_CC3S", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000003
|
||||
|
||||
sfr = "TIM1_CCER", "Memory", 0x4000E020, 4, base=16
|
||||
sfr = "TIM1_CCER.TIM_CC4P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00002000
|
||||
sfr = "TIM1_CCER.TIM_CC4E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00001000
|
||||
sfr = "TIM1_CCER.TIM_CC3P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000200
|
||||
sfr = "TIM1_CCER.TIM_CC3E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000100
|
||||
sfr = "TIM1_CCER.TIM_CC2P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000020
|
||||
sfr = "TIM1_CCER.TIM_CC2E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM1_CCER.TIM_CC1P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000002
|
||||
sfr = "TIM1_CCER.TIM_CC1E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "TIM1_CNT", "Memory", 0x4000E024, 4, base=16
|
||||
|
||||
sfr = "TIM1_PSC", "Memory", 0x4000E028, 4, base=16
|
||||
|
||||
sfr = "TIM1_ARR", "Memory", 0x4000E02C, 4, base=16
|
||||
|
||||
sfr = "TIM1_CCR1", "Memory", 0x4000E034, 4, base=16
|
||||
|
||||
sfr = "TIM1_CCR2", "Memory", 0x4000E038, 4, base=16
|
||||
|
||||
sfr = "TIM1_CCR3", "Memory", 0x4000E03C, 4, base=16
|
||||
|
||||
sfr = "TIM1_CCR4", "Memory", 0x4000E040, 4, base=16
|
||||
|
||||
sfr = "TIM1_OR", "Memory", 0x4000E050, 4, base=16
|
||||
sfr = "TIM1_OR.TIM_ORRSVD", "Memory", 0x4000E050, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM1_OR.TIM_CLKMSKEN", "Memory", 0x4000E050, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM1_OR.TIM1_EXTRIGSEL", "Memory", 0x4000E050, 4, base=16, bitMask=0x00000003
|
||||
|
||||
sfr = "TIM2_CR1", "Memory", 0x4000F000, 4, base=16
|
||||
sfr = "TIM2_CR1.TIM_ARBE", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM2_CR1.TIM_CMS", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000060
|
||||
sfr = "TIM2_CR1.TIM_DIR", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM2_CR1.TIM_OPM", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM2_CR1.TIM_URS", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM2_CR1.TIM_UDIS", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000002
|
||||
sfr = "TIM2_CR1.TIM_CEN", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "TIM2_CR2", "Memory", 0x4000F004, 4, base=16
|
||||
sfr = "TIM2_CR2.TIM_TI1S", "Memory", 0x4000F004, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM2_CR2.TIM_MMS", "Memory", 0x4000F004, 4, base=16, bitMask=0x00000070
|
||||
|
||||
sfr = "TIM2_SMCR", "Memory", 0x4000F008, 4, base=16
|
||||
sfr = "TIM2_SMCR.TIM_ETP", "Memory", 0x4000F008, 4, base=16, bitMask=0x00008000
|
||||
sfr = "TIM2_SMCR.TIM_ECE", "Memory", 0x4000F008, 4, base=16, bitMask=0x00004000
|
||||
sfr = "TIM2_SMCR.TIM_ETPS", "Memory", 0x4000F008, 4, base=16, bitMask=0x00003000
|
||||
sfr = "TIM2_SMCR.TIM_ETF", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000F00
|
||||
sfr = "TIM2_SMCR.TIM_MSM", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM2_SMCR.TIM_TS", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000070
|
||||
sfr = "TIM2_SMCR.TIM_SMS", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000007
|
||||
|
||||
sfr = "TIM2_EGR", "Memory", 0x4000F014, 4, base=16
|
||||
sfr = "TIM2_EGR.TIM_TG", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000040
|
||||
sfr = "TIM2_EGR.TIM_CC4G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM2_EGR.TIM_CC3G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM2_EGR.TIM_CC2G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM2_EGR.TIM_CC1G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000002
|
||||
sfr = "TIM2_EGR.TIM_UG", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "TIM2_CCMR1", "Memory", 0x4000F018, 4, base=16
|
||||
sfr = "TIM2_CCMR1.TIM_IC2F", "Memory", 0x4000F018, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "TIM2_CCMR1.TIM_IC2PSC", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000C00
|
||||
sfr = "TIM2_CCMR1.TIM_IC1F", "Memory", 0x4000F018, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "TIM2_CCMR1.TIM_IC1PSC", "Memory", 0x4000F018, 4, base=16, bitMask=0x0000000C
|
||||
sfr = "TIM2_CCMR1.TIM_OC2CE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00008000
|
||||
sfr = "TIM2_CCMR1.TIM_OC2M", "Memory", 0x4000F018, 4, base=16, bitMask=0x00007000
|
||||
sfr = "TIM2_CCMR1.TIM_OC2BE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000800
|
||||
sfr = "TIM2_CCMR1.TIM_OC2FE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000400
|
||||
sfr = "TIM2_CCMR1.TIM_CC2S", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000300
|
||||
sfr = "TIM2_CCMR1.TIM_OC1CE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM2_CCMR1.TIM_OC1M", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000070
|
||||
sfr = "TIM2_CCMR1.TIM_OC1PE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM2_CCMR1.TIM_OC1FE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM2_CCMR1.TIM_CC1S", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000003
|
||||
|
||||
sfr = "TIM2_CCMR2", "Memory", 0x4000F01C, 4, base=16
|
||||
sfr = "TIM2_CCMR2.TIM_IC4F", "Memory", 0x4000F01C, 4, base=16, bitMask=0x0000F000
|
||||
sfr = "TIM2_CCMR2.TIM_IC4PSC", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000C00
|
||||
sfr = "TIM2_CCMR2.TIM_IC3F", "Memory", 0x4000F01C, 4, base=16, bitMask=0x000000F0
|
||||
sfr = "TIM2_CCMR2.TIM_IC3PSC", "Memory", 0x4000F01C, 4, base=16, bitMask=0x0000000C
|
||||
sfr = "TIM2_CCMR2.TIM_OC4CE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00008000
|
||||
sfr = "TIM2_CCMR2.TIM_OC4M", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00007000
|
||||
sfr = "TIM2_CCMR2.TIM_OC4BE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000800
|
||||
sfr = "TIM2_CCMR2.TIM_OC4FE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000400
|
||||
sfr = "TIM2_CCMR2.TIM_CC4S", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000300
|
||||
sfr = "TIM2_CCMR2.TIM_OC3CE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM2_CCMR2.TIM_OC3M", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000070
|
||||
sfr = "TIM2_CCMR2.TIM_OC3BE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM2_CCMR2.TIM_OC3FE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM2_CCMR2.TIM_CC3S", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000003
|
||||
|
||||
sfr = "TIM2_CCER", "Memory", 0x4000F020, 4, base=16
|
||||
sfr = "TIM2_CCER.TIM_CC4P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00002000
|
||||
sfr = "TIM2_CCER.TIM_CC4E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00001000
|
||||
sfr = "TIM2_CCER.TIM_CC3P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000200
|
||||
sfr = "TIM2_CCER.TIM_CC3E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000100
|
||||
sfr = "TIM2_CCER.TIM_CC2P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000020
|
||||
sfr = "TIM2_CCER.TIM_CC2E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM2_CCER.TIM_CC1P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000002
|
||||
sfr = "TIM2_CCER.TIM_CC1E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "TIM2_CNT", "Memory", 0x4000F024, 4, base=16
|
||||
|
||||
sfr = "TIM2_PSC", "Memory", 0x4000F028, 4, base=16
|
||||
|
||||
sfr = "TIM2_ARR", "Memory", 0x4000F02C, 4, base=16
|
||||
|
||||
sfr = "TIM2_CCR1", "Memory", 0x4000F034, 4, base=16
|
||||
|
||||
sfr = "TIM2_CCR2", "Memory", 0x4000F038, 4, base=16
|
||||
|
||||
sfr = "TIM2_CCR3", "Memory", 0x4000F03C, 4, base=16
|
||||
|
||||
sfr = "TIM2_CCR4", "Memory", 0x4000F040, 4, base=16
|
||||
|
||||
sfr = "TIM2_OR", "Memory", 0x4000F050, 4, base=16
|
||||
sfr = "TIM2_OR.TIM_REMAPC4", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000080
|
||||
sfr = "TIM2_OR.TIM_REMAPC3", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000040
|
||||
sfr = "TIM2_OR.TIM_REMAPC2", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000020
|
||||
sfr = "TIM2_OR.TIM_REMAPC1", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000010
|
||||
sfr = "TIM2_OR.TIM_ORRSVD", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000008
|
||||
sfr = "TIM2_OR.TIM_CLKMSKEN", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000004
|
||||
sfr = "TIM2_OR.TIM1_EXTRIGSEL", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000003
|
||||
|
||||
sfr = "INT_CFGSET", "Memory", 0xE000E100, 4, base=16
|
||||
sfr = "INT_CFGSET.INT_DEBUG", "Memory", 0xE000E100, 4, base=16, bitMask=0x00010000
|
||||
sfr = "INT_CFGSET.INT_IRQD", "Memory", 0xE000E100, 4, base=16, bitMask=0x00008000
|
||||
sfr = "INT_CFGSET.INT_IRQC", "Memory", 0xE000E100, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_CFGSET.INT_IRQB", "Memory", 0xE000E100, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_CFGSET.INT_IRQA", "Memory", 0xE000E100, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_CFGSET.INT_ADC", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_CFGSET.INT_MACRX", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_CFGSET.INT_MACTX", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_CFGSET.INT_MACTMR", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_CFGSET.INT_SEC", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_CFGSET.INT_SC2", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_CFGSET.INT_SC1", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_CFGSET.INT_SLEEPTMR", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_CFGSET.INT_BB", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_CFGSET.INT_MGMT", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_CFGSET.INT_TIM2", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_CFGSET.INT_TIM1", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_CFGCLR", "Memory", 0xE000E180, 4, base=16
|
||||
sfr = "INT_CFGCLR.INT_DEBUG", "Memory", 0xE000E180, 4, base=16, bitMask=0x00010000
|
||||
sfr = "INT_CFGCLR.INT_IRQD", "Memory", 0xE000E180, 4, base=16, bitMask=0x00008000
|
||||
sfr = "INT_CFGCLR.INT_IRQC", "Memory", 0xE000E180, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_CFGCLR.INT_IRQB", "Memory", 0xE000E180, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_CFGCLR.INT_IRQA", "Memory", 0xE000E180, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_CFGCLR.INT_ADC", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_CFGCLR.INT_MACRX", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_CFGCLR.INT_MACTX", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_CFGCLR.INT_MACTMR", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_CFGCLR.INT_SEC", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_CFGCLR.INT_SC2", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_CFGCLR.INT_SC1", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_CFGCLR.INT_SLEEPTMR", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_CFGCLR.INT_BB", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_CFGCLR.INT_MGMT", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_CFGCLR.INT_TIM2", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_CFGCLR.INT_TIM1", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_PENDSET", "Memory", 0xE000E200, 4, base=16
|
||||
sfr = "INT_PENDSET.INT_DEBUG", "Memory", 0xE000E200, 4, base=16, bitMask=0x00010000
|
||||
sfr = "INT_PENDSET.INT_IRQD", "Memory", 0xE000E200, 4, base=16, bitMask=0x00008000
|
||||
sfr = "INT_PENDSET.INT_IRQC", "Memory", 0xE000E200, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_PENDSET.INT_IRQB", "Memory", 0xE000E200, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_PENDSET.INT_IRQA", "Memory", 0xE000E200, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_PENDSET.INT_ADC", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_PENDSET.INT_MACRX", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_PENDSET.INT_MACTX", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_PENDSET.INT_MACTMR", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_PENDSET.INT_SEC", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_PENDSET.INT_SC2", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_PENDSET.INT_SC1", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_PENDSET.INT_SLEEPTMR", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_PENDSET.INT_BB", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_PENDSET.INT_MGMT", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_PENDSET.INT_TIM2", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_PENDSET.INT_TIM1", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_PENDCLR", "Memory", 0xE000E280, 4, base=16
|
||||
sfr = "INT_PENDCLR.INT_DEBUG", "Memory", 0xE000E280, 4, base=16, bitMask=0x00010000
|
||||
sfr = "INT_PENDCLR.INT_IRQD", "Memory", 0xE000E280, 4, base=16, bitMask=0x00008000
|
||||
sfr = "INT_PENDCLR.INT_IRQC", "Memory", 0xE000E280, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_PENDCLR.INT_IRQB", "Memory", 0xE000E280, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_PENDCLR.INT_IRQA", "Memory", 0xE000E280, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_PENDCLR.INT_ADC", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_PENDCLR.INT_MACRX", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_PENDCLR.INT_MACTX", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_PENDCLR.INT_MACTMR", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_PENDCLR.INT_SEC", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_PENDCLR.INT_SC2", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_PENDCLR.INT_SC1", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_PENDCLR.INT_SLEEPTMR", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_PENDCLR.INT_BB", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_PENDCLR.INT_MGMT", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_PENDCLR.INT_TIM2", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_PENDCLR.INT_TIM1", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "INT_ACTIVE", "Memory", 0xE000E300, 4, base=16
|
||||
sfr = "INT_ACTIVE.INT_DEBUG", "Memory", 0xE000E300, 4, base=16, bitMask=0x00010000
|
||||
sfr = "INT_ACTIVE.INT_IRQD", "Memory", 0xE000E300, 4, base=16, bitMask=0x00008000
|
||||
sfr = "INT_ACTIVE.INT_IRQC", "Memory", 0xE000E300, 4, base=16, bitMask=0x00004000
|
||||
sfr = "INT_ACTIVE.INT_IRQB", "Memory", 0xE000E300, 4, base=16, bitMask=0x00002000
|
||||
sfr = "INT_ACTIVE.INT_IRQA", "Memory", 0xE000E300, 4, base=16, bitMask=0x00001000
|
||||
sfr = "INT_ACTIVE.INT_ADC", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000800
|
||||
sfr = "INT_ACTIVE.INT_MACRX", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000400
|
||||
sfr = "INT_ACTIVE.INT_MACTX", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000200
|
||||
sfr = "INT_ACTIVE.INT_MACTMR", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000100
|
||||
sfr = "INT_ACTIVE.INT_SEC", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000080
|
||||
sfr = "INT_ACTIVE.INT_SC2", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000040
|
||||
sfr = "INT_ACTIVE.INT_SC1", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000020
|
||||
sfr = "INT_ACTIVE.INT_SLEEPTMR", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000010
|
||||
sfr = "INT_ACTIVE.INT_BB", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000008
|
||||
sfr = "INT_ACTIVE.INT_MGMT", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000004
|
||||
sfr = "INT_ACTIVE.INT_TIM2", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000002
|
||||
sfr = "INT_ACTIVE.INT_TIM1", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000001
|
||||
|
||||
sfr = "SCS_AFSR", "Memory", 0xE000ED3C, 4, base=16
|
||||
sfr = "SCS_AFSR.WRONGSIZE", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000008
|
||||
sfr = "SCS_AFSR.PROTECTED", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000004
|
||||
sfr = "SCS_AFSR.RESERVED", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000002
|
||||
sfr = "SCS_AFSR.MISSED", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000001
|
||||
|
||||
|
||||
|
||||
; Group info for SFR Window.
|
||||
[SfrGroupInfo]
|
||||
group = "GPIO" , "GPIO_PACFGL" , "GPIO_PACFGH" , "GPIO_PAIN" , "GPIO_PAOUT" , "GPIO_PASET" , "GPIO_PACLR" , "GPIO_PBCFGL" , "GPIO_PBCFGH" , "GPIO_PBIN" , "GPIO_PBOUT" , "GPIO_PBSET" , "GPIO_PBCLR" , "GPIO_PCCFGL" , "GPIO_PCCFGH" , "GPIO_PCIN" , "GPIO_PCOUT" , "GPIO_PCSET" , "GPIO_PCCLR" , "GPIO_DBGCFG" , "GPIO_DBGSTAT"
|
||||
group = "Top-level Interrupts" , "INT_CFGSET" , "INT_CFGCLR" , "INT_PENDSET" , "INT_PENDCLR" , "INT_MISS" , "INT_ACTIVE" , "SCS_AFSR"
|
||||
group = "External Interrupts" , "GPIO_IRQCSEL" , "GPIO_IRQDSEL" , "GPIO_INTCFGA" , "GPIO_INTCFGB" , "GPIO_INTCFGC" , "GPIO_INTCFGD" , "INT_GPIOFLAG"
|
||||
group = "Serial Controller 1" , "INT_SC1CFG" , "SC1_INTMODE" , "INT_SC1FLAG" , "SC1_RXBEGA" , "SC1_RXENDA" , "SC1_RXBEGB" , "SC1_RXENDB" , "SC1_TXBEGA" , "SC1_TXENDA" , "SC1_TXBEGB" , "SC1_TXENDB" , "SC1_RXCNTA" , "SC1_RXCNTB" , "SC1_TXCNT" , "SC1_DMASTAT" , "SC1_DMACTRL" , "SC1_RXERRA" , "SC1_RXERRB" , "SC1_DATA" , "SC1_SPISTAT" , "SC1_TWISTAT" , "SC1_UARTSTAT" , "SC1_TWICTRL1" , "SC1_TWICTRL2" , "SC1_MODE" , "SC1_SPICFG" , "SC1_UARTCFG" , "SC1_RATELIN" , "SC1_RATEEXP" , "SC1_UARTPER" , "SC1_UARTFRAC" , "SC1_RXCNTSAVED"
|
||||
group = "Serial Controller 2" , "INT_SC2CFG" , "SC2_INTMODE" , "INT_SC2FLAG" , "SC2_RXBEGA" , "SC2_RXENDA" , "SC2_RXBEGB" , "SC2_RXENDB" , "SC2_TXBEGA" , "SC2_TXENDA" , "SC2_TXBEGB" , "SC2_TXENDB" , "SC2_RXCNTA" , "SC2_RXCNTB" , "SC2_TXCNT" , "SC2_DMASTAT" , "SC2_DMACTRL" , "SC2_RXERRA" , "SC2_RXERRB" , "SC2_DATA" , "SC2_SPISTAT" , "SC2_TWISTAT" , "SC2_TWICTRL1" , "SC2_TWICTRL2" , "SC2_MODE" , "SC2_SPICFG" , "SC2_RATELIN" , "SC2_RATEEXP" , "SC2_RXCNTSAVED"
|
||||
group = "ADC" , "INT_ADCCFG" , "INT_ADCFLAG" , "ADC_CFG" , "ADC_OFFSET" , "ADC_GAIN" , "ADC_DMACFG" , "ADC_DMASTAT" , "ADC_DMABEG" , "ADC_DMASIZE" , "ADC_DMACUR" , "ADC_DMACNT"
|
||||
group = "Timer 1" , "INT_TIM1CFG" , "INT_TIM1FLAG" , "INT_TIM1MISS" , "TIM1_CR1" , "TIM1_CR2" , "TIM1_SMCR" , "TIM1_EGR" , "TIM1_CCMR1" , "TIM1_CCMR2" , "TIM1_CCER" , "TIM1_CNT" , "TIM1_PSC" , "TIM1_ARR" , "TIM1_CCR1" , "TIM1_CCR2" , "TIM1_CCR3" , "TIM1_CCR4" , "TIM1_OR"
|
||||
group = "Timer 2" , "INT_TIM2CFG" , "INT_TIM2FLAG" , "INT_TIM2MISS" ,"TIM2_CR1" , "TIM2_CR2" , "TIM2_SMCR" , "TIM2_EGR" , "TIM2_CCMR1" , "TIM2_CCMR2" , "TIM2_CCER" , "TIM2_CNT" , "TIM2_PSC" , "TIM2_ARR" , "TIM2_CCR1" , "TIM2_CCR2" , "TIM2_CCR3" , "TIM2_CCR4" , "TIM2_OR"
|
||||
group = "Wake-Up Controls" , "GPIO_PAWAKE" , "GPIO_PBWAKE" , "GPIO_PCWAKE" , "GPIO_WAKEFILT"
|
||||
11541
cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h
Normal file
11541
cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h
Normal file
File diff suppressed because it is too large
Load diff
80
cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h
Normal file
80
cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
|
||||
* File Name : stm32w108_type.h
|
||||
* Author : MCD Application Team
|
||||
* Version : V1.0
|
||||
* Date : 10/08/2009
|
||||
* Description : This file contains all the common data types used for the
|
||||
* STM32W108 firmware library.
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32W108_TYPE_H
|
||||
#define __STM32W108_TYPE_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef signed long s32;
|
||||
typedef signed short s16;
|
||||
typedef signed char s8;
|
||||
|
||||
typedef signed long const sc32; /* Read Only */
|
||||
typedef signed short const sc16; /* Read Only */
|
||||
typedef signed char const sc8; /* Read Only */
|
||||
|
||||
typedef volatile signed long vs32;
|
||||
typedef volatile signed short vs16;
|
||||
typedef volatile signed char vs8;
|
||||
|
||||
typedef volatile signed long const vsc32; /* Read Only */
|
||||
typedef volatile signed short const vsc16; /* Read Only */
|
||||
typedef volatile signed char const vsc8; /* Read Only */
|
||||
|
||||
typedef unsigned long u32;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef unsigned long const uc32; /* Read Only */
|
||||
typedef unsigned short const uc16; /* Read Only */
|
||||
typedef unsigned char const uc8; /* Read Only */
|
||||
|
||||
typedef volatile unsigned long vu32;
|
||||
typedef volatile unsigned short vu16;
|
||||
typedef volatile unsigned char vu8;
|
||||
|
||||
typedef volatile unsigned long const vuc32; /* Read Only */
|
||||
typedef volatile unsigned short const vuc16; /* Read Only */
|
||||
typedef volatile unsigned char const vuc8; /* Read Only */
|
||||
|
||||
//typedef enum {FALSE = 0, TRUE = !FALSE} bool;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))
|
||||
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
||||
|
||||
#define U8_MAX ((u8)255)
|
||||
#define S8_MAX ((s8)127)
|
||||
#define S8_MIN ((s8)-128)
|
||||
#define U16_MAX ((u16)65535u)
|
||||
#define S16_MAX ((s16)32767)
|
||||
#define S16_MIN ((s16)-32768)
|
||||
#define U32_MAX ((u32)4294967295uL)
|
||||
#define S32_MAX ((s32)2147483647)
|
||||
#define S32_MIN ((s32)2147483648uL)
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
#endif /* __STM32W108_TYPE_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
|
||||
Loading…
Add table
Add a link
Reference in a new issue