From ec5e3ce0d7fe7df41a4df869e19bfe99b32d14eb Mon Sep 17 00:00:00 2001 From: salvopitru Date: Mon, 25 Oct 2010 09:03:38 +0000 Subject: [PATCH] New Contiki port to STM32W108. --- cpu/stm32w108/Makefile.stm32w108 | 178 + cpu/stm32w108/clock.c | 130 + cpu/stm32w108/dev/cortexm3_macro.h | 53 + cpu/stm32w108/dev/stm32w-radio.c | 596 + cpu/stm32w108/dev/stm32w-radio.h | 57 + cpu/stm32w108/dev/stm32w_conf.h | 174 + cpu/stm32w108/dev/stm32w_systick.c | 181 + cpu/stm32w108/dev/stm32w_systick.h | 109 + cpu/stm32w108/dev/stm32w_type.h | 80 + cpu/stm32w108/dev/uart1-putchar.c | 67 + cpu/stm32w108/dev/uart1.c | 225 + cpu/stm32w108/dev/uart1.h | 53 + cpu/stm32w108/hal/doxygen/Doxygen_Release | 1557 +++ cpu/stm32w108/hal/doxygen/STFooterHTML.html | 18 + cpu/stm32w108/hal/doxygen/STHeaderHTML.html | 16 + cpu/stm32w108/hal/doxygen/ST_Logo.gif | Bin 0 -> 1123 bytes cpu/stm32w108/hal/doxygen/makefile | 5 + cpu/stm32w108/hal/error-def.h | 1318 ++ cpu/stm32w108/hal/error.h | 56 + cpu/stm32w108/hal/hal.h | 43 + cpu/stm32w108/hal/micro/adc.h | 303 + cpu/stm32w108/hal/micro/button.h | 28 + cpu/stm32w108/hal/micro/cortexm3/adc.c | 349 + .../cortexm3/bootloader/fib-bootloader.h | 56 + cpu/stm32w108/hal/micro/cortexm3/button.c | 29 + cpu/stm32w108/hal/micro/cortexm3/clocks.c | 473 + .../hal/micro/cortexm3/compiler/asm.h | 57 + .../hal/micro/cortexm3/compiler/gnu.h | 521 + .../hal/micro/cortexm3/compiler/iar.h | 516 + .../hal/micro/cortexm3/context-switch.s79 | 158 + cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s | 149 + .../hal/micro/cortexm3/e_stdio/Makefile | 42 + .../micro/cortexm3/e_stdio/src/_SP_printf.c | 80 + .../hal/micro/cortexm3/e_stdio/src/_SP_puts.c | 43 + .../micro/cortexm3/e_stdio/src/_SP_snprintf.c | 124 + .../micro/cortexm3/e_stdio/src/_SP_sprintf.c | 393 + .../micro/cortexm3/e_stdio/src/_SP_vfprintf.c | 1780 +++ .../hal/micro/cortexm3/e_stdio/src/floatio.h | 32 + .../hal/micro/cortexm3/e_stdio/src/fvwrite.h | 38 + .../hal/micro/cortexm3/e_stdio/src/local.h | 89 + .../hal/micro/cortexm3/e_stdio/src/mbctype.h | 20 + .../hal/micro/cortexm3/e_stdio/src/scanf.c | 79 + .../micro/cortexm3/e_stdio/src/small_dtoa.c | 1174 ++ .../micro/cortexm3/e_stdio/src/small_mprec.c | 1963 +++ .../micro/cortexm3/e_stdio/src/small_mprec.h | 383 + .../micro/cortexm3/e_stdio/src/small_strtod.c | 936 ++ .../cortexm3/e_stdio/src/small_vfsscanf.c | 1481 ++ .../cortexm3/e_stdio/src/small_wcrtomb.c | 59 + .../cortexm3/e_stdio/src/small_wcsrtombs.c | 97 + .../cortexm3/e_stdio/src/small_wctomb_r.c | 188 + .../hal/micro/cortexm3/e_stdio/src/sscanf.c | 453 + .../hal/micro/cortexm3/e_stdio/src/swi.h | 60 + .../hal/micro/cortexm3/e_stdio/src/syscalls.c | 403 + .../hal/micro/cortexm3/e_stdio/src/test.c | 254 + .../hal/micro/cortexm3/e_stdio/src/test_mes.c | 44 + .../micro/cortexm3/e_stdio/src/test_printf.c | 87 + .../micro/cortexm3/e_stdio/src/test_scanf.c | 14 + .../hal/micro/cortexm3/e_stdio/src/vfieeefp.h | 284 + cpu/stm32w108/hal/micro/cortexm3/flash.c | 362 + cpu/stm32w108/hal/micro/cortexm3/flash.h | 126 + cpu/stm32w108/hal/micro/cortexm3/led.c | 52 + cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h | 51 + cpu/stm32w108/hal/micro/cortexm3/memmap.h | 64 + cpu/stm32w108/hal/micro/cortexm3/mems.c | 241 + cpu/stm32w108/hal/micro/cortexm3/mfg-token.c | 104 + cpu/stm32w108/hal/micro/cortexm3/mfg-token.h | 163 + .../micro/cortexm3/micro-common-internal.c | 294 + .../hal/micro/cortexm3/micro-common.c | 115 + .../hal/micro/cortexm3/micro-common.h | 271 + cpu/stm32w108/hal/micro/cortexm3/micro.c | 108 + cpu/stm32w108/hal/micro/cortexm3/mpu.h | 12 + cpu/stm32w108/hal/micro/cortexm3/nvm-def.h | 53 + cpu/stm32w108/hal/micro/cortexm3/nvm.c | 377 + cpu/stm32w108/hal/micro/cortexm3/nvm.h | 279 + cpu/stm32w108/hal/micro/cortexm3/sleep.c | 873 ++ .../hal/micro/cortexm3/small_printf/Makefile | 35 + .../micro/cortexm3/small_printf/_SP_printf.c | 78 + .../micro/cortexm3/small_printf/_SP_puts.c | 34 + .../cortexm3/small_printf/_SP_snprintf.c | 124 + .../micro/cortexm3/small_printf/_SP_sprintf.c | 389 + .../cortexm3/small_printf/_SP_vfprintf.c | 1774 +++ .../micro/cortexm3/small_printf/vfieeefp.h | 284 + cpu/stm32w108/hal/micro/cortexm3/spmr.s79 | 181 + .../hal/micro/cortexm3/stm32w108/board.h | 33 + .../micro/cortexm3/stm32w108/crt_stm32w108.c | 362 + .../hal/micro/cortexm3/stm32w108/gnu.ld | 245 + .../hal/micro/cortexm3/stm32w108/iar-cfg.icf | 30 + .../micro/cortexm3/stm32w108/low_level_init.c | 173 + .../hal/micro/cortexm3/stm32w108/memmap.h | 57 + .../hal/micro/cortexm3/stm32w108/regs.ddf | 924 ++ .../hal/micro/cortexm3/stm32w108/regs.h | 11541 ++++++++++++++++ .../micro/cortexm3/stm32w108/stm32w108_type.h | 80 + .../hal/micro/cortexm3/system-timer.c | 172 + .../hal/micro/cortexm3/temperature_sensor.c | 54 + .../hal/micro/cortexm3/token-manufacturing.h | 369 + cpu/stm32w108/hal/micro/cortexm3/uart.c | 259 + cpu/stm32w108/hal/micro/cortexm3/uart.h | 72 + .../micro/generic/compiler/platform-common.h | 362 + cpu/stm32w108/hal/micro/led.h | 65 + cpu/stm32w108/hal/micro/mems.h | 36 + cpu/stm32w108/hal/micro/mems_regs.h | 125 + cpu/stm32w108/hal/micro/micro-common.h | 116 + cpu/stm32w108/hal/micro/system-timer.h | 84 + cpu/stm32w108/hal/micro/temperature_sensor.h | 27 + cpu/stm32w108/hal/token-phy.h | 51 + cpu/stm32w108/leds-arch.c | 72 + cpu/stm32w108/mtarch.h | 13 + cpu/stm32w108/rand.c | 62 + cpu/stm32w108/rtimer-arch.c | 175 + cpu/stm32w108/rtimer-arch.h | 80 + cpu/stm32w108/simplemac/include/phy-library.h | 831 ++ cpu/stm32w108/slip_uart1.c | 62 + cpu/stm32w108/uip_arch.c | 67 + cpu/stm32w108/watchdog.c | 86 + platform/mb851/Makefile.mb851 | 18 + platform/mb851/apps/shell-sensors.c | 97 + platform/mb851/apps/shell-sensors.h | 48 + platform/mb851/contiki-conf.h | 165 + platform/mb851/contiki-init-net.c | 136 + platform/mb851/contiki-init-net.h | 6 + platform/mb851/contiki-main.c | 245 + platform/mb851/dev/acc-sensor.c | 148 + platform/mb851/dev/acc-sensor.h | 78 + platform/mb851/dev/button-sensor.c | 185 + platform/mb851/dev/irq.c | 5 + platform/mb851/dev/mems.c | 368 + platform/mb851/dev/mems.h | 59 + platform/mb851/dev/mems_regs.h | 139 + platform/mb851/dev/temperature-sensor.c | 114 + platform/mb851/dev/temperature-sensor.h | 62 + 130 files changed, 43157 insertions(+) create mode 100644 cpu/stm32w108/Makefile.stm32w108 create mode 100644 cpu/stm32w108/clock.c create mode 100644 cpu/stm32w108/dev/cortexm3_macro.h create mode 100644 cpu/stm32w108/dev/stm32w-radio.c create mode 100644 cpu/stm32w108/dev/stm32w-radio.h create mode 100644 cpu/stm32w108/dev/stm32w_conf.h create mode 100644 cpu/stm32w108/dev/stm32w_systick.c create mode 100644 cpu/stm32w108/dev/stm32w_systick.h create mode 100644 cpu/stm32w108/dev/stm32w_type.h create mode 100644 cpu/stm32w108/dev/uart1-putchar.c create mode 100644 cpu/stm32w108/dev/uart1.c create mode 100644 cpu/stm32w108/dev/uart1.h create mode 100644 cpu/stm32w108/hal/doxygen/Doxygen_Release create mode 100644 cpu/stm32w108/hal/doxygen/STFooterHTML.html create mode 100644 cpu/stm32w108/hal/doxygen/STHeaderHTML.html create mode 100644 cpu/stm32w108/hal/doxygen/ST_Logo.gif create mode 100644 cpu/stm32w108/hal/doxygen/makefile create mode 100644 cpu/stm32w108/hal/error-def.h create mode 100644 cpu/stm32w108/hal/error.h create mode 100644 cpu/stm32w108/hal/hal.h create mode 100644 cpu/stm32w108/hal/micro/adc.h create mode 100644 cpu/stm32w108/hal/micro/button.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/adc.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/button.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/clocks.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/compiler/asm.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 create mode 100644 cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/Makefile create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_printf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_puts.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_snprintf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_sprintf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_vfprintf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/floatio.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/fvwrite.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/local.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/mbctype.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/scanf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_dtoa.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_strtod.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_vfsscanf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcrtomb.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcsrtombs.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wctomb_r.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/sscanf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/swi.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/syscalls.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_mes.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_printf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_scanf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/vfieeefp.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/flash.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/flash.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/led.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/memmap.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/mems.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/mfg-token.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/mfg-token.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/micro-common.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/micro-common.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/micro.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/mpu.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/nvm-def.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/nvm.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/nvm.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/sleep.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/Makefile create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_printf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_puts.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_snprintf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_sprintf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_vfprintf.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/small_printf/vfieeefp.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/spmr.s79 create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/gnu.ld create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/iar-cfg.icf create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.ddf create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/system-timer.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h create mode 100644 cpu/stm32w108/hal/micro/cortexm3/uart.c create mode 100644 cpu/stm32w108/hal/micro/cortexm3/uart.h create mode 100644 cpu/stm32w108/hal/micro/generic/compiler/platform-common.h create mode 100644 cpu/stm32w108/hal/micro/led.h create mode 100644 cpu/stm32w108/hal/micro/mems.h create mode 100644 cpu/stm32w108/hal/micro/mems_regs.h create mode 100644 cpu/stm32w108/hal/micro/micro-common.h create mode 100644 cpu/stm32w108/hal/micro/system-timer.h create mode 100644 cpu/stm32w108/hal/micro/temperature_sensor.h create mode 100644 cpu/stm32w108/hal/token-phy.h create mode 100644 cpu/stm32w108/leds-arch.c create mode 100644 cpu/stm32w108/mtarch.h create mode 100644 cpu/stm32w108/rand.c create mode 100644 cpu/stm32w108/rtimer-arch.c create mode 100644 cpu/stm32w108/rtimer-arch.h create mode 100644 cpu/stm32w108/simplemac/include/phy-library.h create mode 100644 cpu/stm32w108/slip_uart1.c create mode 100644 cpu/stm32w108/uip_arch.c create mode 100644 cpu/stm32w108/watchdog.c create mode 100644 platform/mb851/Makefile.mb851 create mode 100644 platform/mb851/apps/shell-sensors.c create mode 100644 platform/mb851/apps/shell-sensors.h create mode 100644 platform/mb851/contiki-conf.h create mode 100644 platform/mb851/contiki-init-net.c create mode 100644 platform/mb851/contiki-init-net.h create mode 100644 platform/mb851/contiki-main.c create mode 100644 platform/mb851/dev/acc-sensor.c create mode 100644 platform/mb851/dev/acc-sensor.h create mode 100644 platform/mb851/dev/button-sensor.c create mode 100644 platform/mb851/dev/irq.c create mode 100644 platform/mb851/dev/mems.c create mode 100644 platform/mb851/dev/mems.h create mode 100644 platform/mb851/dev/mems_regs.h create mode 100644 platform/mb851/dev/temperature-sensor.c create mode 100644 platform/mb851/dev/temperature-sensor.h diff --git a/cpu/stm32w108/Makefile.stm32w108 b/cpu/stm32w108/Makefile.stm32w108 new file mode 100644 index 000000000..91f0e294f --- /dev/null +++ b/cpu/stm32w108/Makefile.stm32w108 @@ -0,0 +1,178 @@ + +.SUFFIXES: + +ifdef IAR +${info Using IAR...} +#IAR_PATH = C:/Program\ Files/IAR\ Systems/Embedded\ Workbench\ 5.4\ Evaluation +ifeq ($(IAR_PATH),) + ${error IAR_PATH not defined! You must specify IAR root directory} +endif +endif + +### Define the CPU directory +CONTIKI_CPU=$(CONTIKI)/cpu/stm32w108 + +### Define the source files we have in the STM32W port + +CONTIKI_CPU_DIRS = . dev hal simplemac hal/micro/cortexm3 hal/micro/cortexm3/stm32w108 + +STM32W_C = leds-arch.c leds.c clock.c watchdog.c uart1.c uart1-putchar.c slip_uart1.c \ + stm32w-radio.c stm32w_systick.c uip_arch.c rtimer-arch.c adc.c micro.c sleep.c \ + micro-common.c micro-common-internal.c clocks.c mfg-token.c nvm.c flash.c rand.c + +STM32W_S = spmr.s79 context-switch.s79 + +ifdef IAR +STM32W_C += low_level_init.c +STM32W_S += cstartup_M.s +else +STM32W_C += crt_stm32w108.c +endif + +# .s and .s79 not specified here because in Makefile.include only .c and .S suffixes are replaced with .o. +CONTIKI_TARGET_SOURCEFILES += $(STM32W_C) \ + $(SYSAPPS) $(ELFLOADER) \ + $(TARGETLIBS) + +CONTIKI_SOURCEFILES += $(CONTIKI_TARGET_SOURCEFILES) + +ifdef IAR +TARGET_LIBFILES = $(CONTIKI_CPU)/simplemac/library/simplemac-library.a +else + ifdef PRINTF_FLOAT + TARGET_LIBFILES = $(CONTIKI_CPU)/simplemac/library/simplemac-library.a $(CONTIKI_CPU)/hal/micro/cortexm3/e_stdio_thumb2.a + else + TARGET_LIBFILES = $(CONTIKI_CPU)/simplemac/library/simplemac-library.a $(CONTIKI_CPU)/hal/micro/cortexm3/e_stdio_intonly_thumb2.a + endif +endif +# `$(CC) -print-file-name=thumb2/libc.a` `$(CC) -print-file-name=thumb2/libgcc.a` + +### Compiler definitions +ifdef IAR +CC = iccarm +LD = ilinkarm +AS = iasmarm +AR = iarchive +OBJCOPY = ielftool +STRIP = strip +OPTI = -Ohz --no_unroll +CFLAGSNO = --endian=little --cpu=Cortex-M3 -e --diag_suppress Pa050 -D BOARD_HEADER=\"board.h\" \ + -D BOARD_MB851 -D "PLATFORM_HEADER=\"hal/micro/cortexm3/compiler/iar.h\"" -D CORTEXM3 \ + -D CORTEXM3_STM32W108 -D PHY_STM32W108XX -D DISABLE_WATCHDOG -D ENABLE_ADC_EXTENDED_RANGE_BROKEN \ + -D __SOURCEFILE__=\"$*.c\" -lC $(OBJECTDIR) \ + -I $(IAR_PATH)/arm/inc --dlib_config=DLib_Config_Normal.h + +CFLAGS += $(CFLAGSNO) $(OPTI) +AROPTS = --create +ASFLAGS = -s+ -w+ --cpu Cortex-M3 -L$(OBJECTDIR) +LDFLAGS += --redirect _Printf=_PrintfSmall --redirect _Scanf=_ScanfSmall --map=contiki-$(TARGET).map \ + --config $(CONTIKI_CPU)/hal/micro/cortexm3/stm32w108/iar-cfg.icf +OBJOPTS = --bin + +else +CC = arm-none-eabi-gcc +LD = arm-none-eabi-gcc +AS = arm-none-eabi-gcc +AR = arm-none-eabi-ar +OBJCOPY = arm-none-eabi-objcopy +STRIP = arm-none-eabi-strip +SIZE = arm-none-eabi-size +OPTI = -Os -ffunction-sections -fshort-enums +CFLAGSNO = -mthumb -mcpu=cortex-m3 -fsigned-char -D "PLATFORM_HEADER=\"hal/micro/cortexm3/compiler/gnu.h\"" \ + -D BOARD_HEADER=\"board.h\" -g -Wall -Wno-strict-aliasing -mlittle-endian \ + -D BOARD_MB851 -D CORTEXM3 -D CORTEXM3_STM32W108 -D PHY_STM32W108XX -D DISABLE_WATCHDOG -D ENABLE_ADC_EXTENDED_RANGE_BROKEN \ + -D __SOURCEFILE__=\"$*.c\" +CFLAGS += $(CFLAGSNO) $(OPTI) +ASFLAGS = -mthumb -mcpu=cortex-m3 -fsigned-char -c -g -Wall -Os -ffunction-sections \ + -mlittle-endian -fshort-enums -x assembler-with-cpp -Wa,-EL +LDFLAGS += -mcpu=cortex-m3 \ + -mthumb \ + -Wl,-T -Xlinker $(CONTIKI_CPU)/hal/micro/cortexm3/stm32w108/gnu.ld \ + -Wl,-static \ + -u Default_Handler \ + -nostartfiles \ + -Wl,-Map -Xlinker contiki-$(TARGET).map \ + -Wl,--gc-sections +SIZEFLAGS = -A +OBJOPTS = -O binary + +endif + +FLASHER = $(CONTIKI)/tools/stm32w/stm32w_flasher/linux/stm32w_flasher + +# Check if we are running under Windows +ifdef OS + ifneq (,$(findstring Windows,$(OS))) + FLASHER = $(CONTIKI)/tools/stm32w/stm32w_flasher/win/stm32w_flasher + endif +endif + + +ifndef PORT +# Flash with jlink +FLASHEROPTS = -f -r +else +# Flash on serial port with on-board bootloader +FLASHEROPTS = -f -i rs232 -p $(PORT) -r +endif + + +### Custom rules + +OBJECTDIR = obj_$(TARGET) + +ssubst = ${patsubst %.s,%.o,${patsubst %.s79,%.o,$(1)}} + +CONTIKI_OBJECTFILES += ${addprefix $(OBJECTDIR)/,${call ssubst, $(STM32W_S)}} + +vpath %.s79 $(CONTIKI_CPU)/hal/micro/cortexm3 +vpath %.s $(CONTIKI_CPU)/hal/micro/cortexm3 + + +ifdef IAR +# Check if we are in cygwin environment, so we must have paths like /cygdrive/c/... (checking TERM doesn't always work.) +ifneq ($(shell ls /cygdrive 2>/dev/null),) + ${info Cygwin detected.} + SEDCOMMAND = sed -e '1s,\($(OBJECTDIR)\\$*\)\.o: \(.\):,\1.o : /cygdrive/\l\2,g' -e '1!s,\($(OBJECTDIR)\\$*\)\.o: \(.\):, /cygdrive/\l\2,g' -e 's,\\\([^ ]\),/\1,g' -e 's,$$, \\,' -e '$$s, \\$$,,' < $(@:.o=.P) > $(@:.o=.d) +else + SEDCOMMAND = sed -e '1s,\($(OBJECTDIR)\\$*\)\.o:,\1.o : ,g' -e '1!s,\($(OBJECTDIR)\\$*\)\.o:, ,g' -e 's,\\\([^ ]\),/\1,g' -e 's,$$, \\,' -e '$$s, \\$$,,' < $(@:.o=.P) > $(@:.o=.d) +endif + +CUSTOM_RULE_C_TO_OBJECTDIR_O = 1 +$(OBJECTDIR)/%.o: %.c + $(CC) $(CFLAGS) $< --dependencies=m $(@:.o=.P) -o $@ + @$(SEDCOMMAND); rm -f $(@:.o=.P) + @$(FINALIZE_DEPENDENCY) + +CUSTOM_RULE_C_TO_CO = 1 +%.co: %.c + $(CC) $(CFLAGS) -DAUTOSTART_ENABLE $< -o $@ +else #IAR + +CUSTOM_RULE_LINK = 1 + +%.$(TARGET): %.co $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) contiki-$(TARGET).a + $(LD) $(LDFLAGS) $(TARGET_STARTFILES) ${filter-out %.a,$^} -Wl,-\( ${filter %.a,$^} $(TARGET_LIBFILES) -Wl,-\) -o $@ + @echo >> contiki-$(TARGET).map + @$(SIZE) $(SIZEFLAGS) $@ >> contiki-$(TARGET).map + +#%.$(TARGET): %.co $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) $(CONTIKI_OBJECTFILES) +# $(LD) $(LDFLAGS) $(TARGET_STARTFILES) ${filter-out %.a,$^} ${filter %.a,$^} $(TARGET_LIBFILES) -o $@ +# @echo "\n" >> contiki-$(TARGET).map +# @$(SIZE) $(SIZEFLAGS) $@ >> contiki-$(TARGET).map + + +endif #IAR + +$(OBJECTDIR)/%.o: %.s79 + $(AS) $(ASFLAGS) -o $@ $< + +$(OBJECTDIR)/%.o: %.s + $(AS) $(ASFLAGS) -o $@ $< + +%.bin: %.$(TARGET) + $(OBJCOPY) $(OBJOPTS) $< $@ + +%.flash: %.bin + $(FLASHER) $(FLASHEROPTS) $< + diff --git a/cpu/stm32w108/clock.c b/cpu/stm32w108/clock.c new file mode 100644 index 000000000..f40af1ae5 --- /dev/null +++ b/cpu/stm32w108/clock.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: clock.c,v 1.1 2010/10/25 09:03:38 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Clock. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include PLATFORM_HEADER +#include "hal/error.h" +#include "hal/hal.h" +#include "dev/stm32w_systick.h" + +#include "sys/clock.h" +#include "sys/etimer.h" + +// The value that will be load in the SysTick value register. +#define RELOAD_VALUE 24000-1 // 1 ms with a 24 MHz clock + +static volatile clock_time_t count; +static volatile unsigned long current_seconds = 0; +static unsigned int second_countdown = CLOCK_SECOND; + +/*---------------------------------------------------------------------------*/ +void SysTick_Handler(void) +{ + + count++; + + if(etimer_pending()) { + etimer_request_poll(); + } + + if (--second_countdown == 0) { + current_seconds++; + second_countdown = CLOCK_SECOND; + } + +} + +/*---------------------------------------------------------------------------*/ + +void clock_init(void) +{ + + INTERRUPTS_OFF(); + + //Counts the number of ticks. + count = 0; + + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); + SysTick_SetReload(RELOAD_VALUE); + SysTick_ITConfig(ENABLE); + SysTick_CounterCmd(SysTick_Counter_Enable); + + INTERRUPTS_ON(); +} + +/*---------------------------------------------------------------------------*/ + +clock_time_t clock_time(void) +{ + return count; +} + +/*---------------------------------------------------------------------------*/ +/** + * Delay the CPU for a multiple of TODO + */ +void clock_delay(unsigned int i) +{ + for (; i > 0; i--) { /* Needs fixing XXX */ + unsigned j; + for (j = 50; j > 0; j--) + asm ("nop"); + } +} + +/*---------------------------------------------------------------------------*/ +/** + * Wait for a multiple of 1 ms. + * + */ +void clock_wait(int i) +{ + clock_time_t start; + + start = clock_time(); + while(clock_time() - start < (clock_time_t)i); +} +/*---------------------------------------------------------------------------*/ + +unsigned long clock_seconds(void) +{ + return current_seconds; +} diff --git a/cpu/stm32w108/dev/cortexm3_macro.h b/cpu/stm32w108/dev/cortexm3_macro.h new file mode 100644 index 000000000..b16dc0c41 --- /dev/null +++ b/cpu/stm32w108/dev/cortexm3_macro.h @@ -0,0 +1,53 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32w_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +u32 __MRS_PSP(void); +void __MSR_PSP(u32 TopOfProcessStack); +u32 __MRS_MSP(void); +void __MSR_MSP(u32 TopOfMainStack); +void __RESETPRIMASK(void); +void __SETPRIMASK(void); +u32 __READ_PRIMASK(void); +void __RESETFAULTMASK(void); +void __SETFAULTMASK(void); +u32 __READ_FAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/stm32w-radio.c b/cpu/stm32w108/dev/stm32w-radio.c new file mode 100644 index 000000000..267dedf7c --- /dev/null +++ b/cpu/stm32w108/dev/stm32w-radio.c @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Machine dependent STM32W radio code. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include PLATFORM_HEADER +#include "hal/error.h" +#include "hal/hal.h" + +#include "contiki.h" + +#include "net/mac/frame802154.h" + +#include "dev/stm32w-radio.h" +#include "net/netstack.h" + +#include "net/packetbuf.h" +#include "net/rime/rimestats.h" + + + +#define DEBUG 0 +#include "dev/leds.h" +#define LED_ACTIVITY 0 + + +#if DEBUG > 0 +#include +#define PRINTF(...) printf(__VA_ARGS__) +#else +#define PRINTF(...) do {} while (0) +#endif + +#if LED_ACTIVITY +#define LED_TX_ON() leds_on(LEDS_GREEN) +#define LED_TX_OFF() leds_off(LEDS_GREEN) +#define LED_RX_ON() leds_on(LEDS_RED) +#define LED_RX_OFF() leds_off(LEDS_RED) +#else +#define LED_TX_ON() +#define LED_TX_OFF() +#define LED_RX_ON() +#define LED_RX_OFF() +#endif + +#ifndef MAC_RETRIES +#define MAC_RETRIES 1 +#endif + +#if MAC_RETRIES + + int8_t mac_retries_left; + + #define INIT_RETRY_CNT() (mac_retries_left = packetbuf_attr(PACKETBUF_ATTR_MAX_MAC_TRANSMISSIONS)) + #define DEC_RETRY_CNT() (mac_retries_left--) + #define RETRY_CNT_GTZ() (mac_retries_left > 0) + +#else + + #define INIT_RETRY_CNT() + #define DEC_RETRY_CNT() + #define RETRY_CNT_GTZ() 0 + +#endif + + +/* If set to 1, a send() returns only after the packet has been transmitted. + This is necessary if you use the x-mac module, for example. */ +#ifndef RADIO_WAIT_FOR_PACKET_SENT +#define RADIO_WAIT_FOR_PACKET_SENT 1 +#endif + +#define TO_PREV_STATE() { \ + if(onoroff == OFF){ \ + ST_RadioSleep(); \ + ENERGEST_OFF(ENERGEST_TYPE_LISTEN); \ + } \ + } + +const RadioTransmitConfig radioTransmitConfig = { + TRUE, // waitForAck; + TRUE, // checkCca; // Set to FALSE with low-power MACs. + 4, // ccaAttemptMax; + 2, // backoffExponentMin; + 6, // backoffExponentMax; + TRUE // appendCrc; +}; + +/* + * The buffers which hold incoming data. + */ +#ifndef RADIO_RXBUFS +#define RADIO_RXBUFS 1 +#endif + +static uint8_t stm32w_rxbufs[RADIO_RXBUFS][STM32W_MAX_PACKET_LEN+1]; // +1 because of the first byte, which will contain the length of the packet. + +#if RADIO_RXBUFS > 1 +static volatile int8_t first = -1, last=0; +#else +static const int8_t first=0, last=0; +#endif + +#if RADIO_RXBUFS > 1 + #define CLEAN_RXBUFS() do{first = -1; last = 0;}while(0) + #define RXBUFS_EMPTY() (first == -1) + +int RXBUFS_FULL(){ + + int8_t first_tmp = first; + return first_tmp == last; +} + +#else /* RADIO_RXBUFS > 1 */ + #define CLEAN_RXBUFS() (stm32w_rxbufs[0][0] = 0) + #define RXBUFS_EMPTY() (stm32w_rxbufs[0][0] == 0) + #define RXBUFS_FULL() (stm32w_rxbufs[0][0] != 0) +#endif /* RADIO_RXBUFS > 1 */ + +static uint8_t __attribute__(( aligned(2) )) stm32w_txbuf[STM32W_MAX_PACKET_LEN+1]; + + +#define CLEAN_TXBUF() (stm32w_txbuf[0] = 0) +#define TXBUF_EMPTY() (stm32w_txbuf[0] == 0) + +#define CHECKSUM_LEN 2 + +/* + * The transceiver state. + */ +#define ON 0 +#define OFF 1 + +static volatile uint8_t onoroff = OFF; +static uint8_t receiving_packet = 0; +static s8 last_rssi; +static volatile StStatus last_tx_status; + +/*---------------------------------------------------------------------------*/ +PROCESS(stm32w_radio_process, "STM32W radio driver"); +/*---------------------------------------------------------------------------*/ + +static int stm32w_radio_init(void); +static int stm32w_radio_prepare(const void *payload, unsigned short payload_len); +static int stm32w_radio_transmit(unsigned short payload_len); +static int stm32w_radio_send(const void *data, unsigned short len); +static int stm32w_radio_read(void *buf, unsigned short bufsize); +static int stm32w_radio_channel_clear(void); +static int stm32w_radio_receiving_packet(void); +static int stm32w_radio_pending_packet(void); +static int stm32w_radio_on(void); +static int stm32w_radio_off(void); + +static int add_to_rxbuf(uint8_t * src); +static int read_from_rxbuf(void * dest, unsigned short len); + + +const struct radio_driver stm32w_radio_driver = + { + stm32w_radio_init, + stm32w_radio_prepare, + stm32w_radio_transmit, + stm32w_radio_send, + stm32w_radio_read, + stm32w_radio_channel_clear, + stm32w_radio_receiving_packet, + stm32w_radio_pending_packet, + stm32w_radio_on, + stm32w_radio_off, + }; +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_init(void) +{ + + // A channel needs also to be setted. + ST_RadioSetChannel(RF_CHANNEL); + + // Initialize radio (analog section, digital baseband and MAC). + // Leave radio powered up in non-promiscuous rx mode. + ST_RadioInit(ST_RADIO_POWER_MODE_OFF); + onoroff = OFF; + ST_RadioSetNodeId(STM32W_NODE_ID); // To be deleted. + ST_RadioSetPanId(IEEE802154_PANID); + + ST_RadioEnableAutoAck(TRUE); + + + CLEAN_RXBUFS(); + CLEAN_TXBUF(); + + process_start(&stm32w_radio_process, NULL); + + return 0; +} +/*---------------------------------------------------------------------------*/ +int stm32w_radio_set_channel(u8_t channel) +{ + if (ST_RadioSetChannel(channel) == ST_SUCCESS) + return 0; + else + return 1; +} +/*---------------------------------------------------------------------------*/ +static int wait_for_tx(void){ + + struct timer t; + + timer_set(&t, CLOCK_SECOND/10); + while(!TXBUF_EMPTY()){ + if(timer_expired(&t)){ + PRINTF("stm32w: tx buffer full.\r\n"); + return 1; + } + /* Put CPU in sleep mode. */ + halSleepWithOptions(SLEEPMODE_IDLE,0); + } + return 0; +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_prepare(const void *payload, unsigned short payload_len) +{ + if(payload_len > STM32W_MAX_PACKET_LEN){ + PRINTF("stm32w: payload length=%d is too long.\r\n", payload_len); + return RADIO_TX_ERR; + } + +#if !RADIO_WAIT_FOR_PACKET_SENT + /* Check if the txbuf is empty. + * Wait for a finite time. + * This sould not occur if we wait for the end of transmission in stm32w_radio_transmit(). + */ + if(wait_for_tx()){ + PRINTF("stm32w: tx buffer full.\r\n"); + return RADIO_TX_ERR; + } +#endif /* RADIO_WAIT_FOR_PACKET_SENT */ + + /* Copy to the txbuf. + * The first byte must be the packet length. + */ + CLEAN_TXBUF(); + memcpy(stm32w_txbuf + 1, payload, payload_len); + + return RADIO_TX_OK; + +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_transmit(unsigned short payload_len) +{ + stm32w_txbuf[0] = payload_len + CHECKSUM_LEN; + + INIT_RETRY_CNT(); + + if(onoroff == OFF){ + PRINTF("stm32w: Radio is off, turning it on.\r\n"); + ST_RadioWake(); + ENERGEST_ON(ENERGEST_TYPE_LISTEN); + } + + LED_TX_ON(); + if(ST_RadioTransmit(stm32w_txbuf)==ST_SUCCESS){ + + ENERGEST_OFF(ENERGEST_TYPE_LISTEN); + ENERGEST_ON(ENERGEST_TYPE_TRANSMIT); + + PRINTF("stm32w: sending %d bytes\r\n", payload_len); + +#if DEBUG > 1 + for(u8_t c=1; c <= stm32w_txbuf[0]-2; c++){ + PRINTF("%x:",stm32w_txbuf[c]); + } + PRINTF("\r\n"); +#endif + +#if RADIO_WAIT_FOR_PACKET_SENT + + if(wait_for_tx()){ + PRINTF("stm32w: unknown tx error.\r\n"); + TO_PREV_STATE(); + LED_TX_OFF(); + return RADIO_TX_ERR; + } + + TO_PREV_STATE(); + if(last_tx_status == ST_SUCCESS || last_tx_status == ST_PHY_ACK_RECEIVED){ + return RADIO_TX_OK; + } + LED_TX_OFF(); + return RADIO_TX_ERR; + +#else /* RADIO_WAIT_FOR_PACKET_SENT */ + + TO_PREV_STATE(); + LED_TX_OFF(); + return RADIO_TX_OK; + +#endif /* RADIO_WAIT_FOR_PACKET_SENT */ + + } + + TO_PREV_STATE(); + + PRINTF("stm32w: transmission never started.\r\n"); + /* TODO: Do we have to retransmit? */ + + CLEAN_TXBUF(); + LED_TX_OFF(); + return RADIO_TX_ERR; + +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_send(const void *payload, unsigned short payload_len) +{ + if(stm32w_radio_prepare(payload, payload_len) == RADIO_TX_ERR) + return RADIO_TX_ERR; + + return stm32w_radio_transmit(payload_len); + +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_channel_clear(void) +{ + return ST_RadioChannelIsClear(); +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_receiving_packet(void) +{ + return receiving_packet; +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_pending_packet(void) +{ + return !RXBUFS_EMPTY(); +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_off(void) +{ + /* Any transmit or receive packets in progress are aborted. + * Waiting for end of transmission or reception have to be done. + */ + if(onoroff == ON){ + ST_RadioSleep(); + onoroff = OFF; + CLEAN_TXBUF(); + CLEAN_RXBUFS(); + + ENERGEST_OFF(ENERGEST_TYPE_LISTEN); + } + + return 1; +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_on(void) +{ + if(onoroff == OFF){ + ST_RadioWake(); + onoroff = ON; + + ENERGEST_ON(ENERGEST_TYPE_LISTEN); + } + + return 1; +} + +/*---------------------------------------------------------------------------*/ + + +void ST_RadioReceiveIsrCallback(u8 *packet, + boolean ackFramePendingSet, + u32 time, + u16 errors, + s8 rssi) +{ + LED_RX_ON(); + receiving_packet = 0; + /* Copy packet into the buffer. It is better to do this here. */ + if(add_to_rxbuf(packet)){ + process_poll(&stm32w_radio_process); + last_rssi = rssi; + } + LED_RX_OFF(); +} + + +void ST_RadioTransmitCompleteIsrCallback(StStatus status, + u32 txSyncTime, + boolean framePending) +{ + + ENERGEST_OFF(ENERGEST_TYPE_TRANSMIT); + ENERGEST_ON(ENERGEST_TYPE_LISTEN); + LED_TX_OFF(); + + last_tx_status = status; + + if(status == ST_SUCCESS || status == ST_PHY_ACK_RECEIVED){ + CLEAN_TXBUF(); + } + else { + + if(RETRY_CNT_GTZ()){ + // Retransmission + LED_TX_ON(); + if(ST_RadioTransmit(stm32w_txbuf)==ST_SUCCESS){ + + ENERGEST_OFF(ENERGEST_TYPE_LISTEN); + ENERGEST_ON(ENERGEST_TYPE_TRANSMIT); + + PRINTF("stm32w: retransmission.\r\n"); + + DEC_RETRY_CNT(); + } + else { + CLEAN_TXBUF(); + LED_TX_OFF(); + PRINTF("stm32w: retransmission failed.\r\n"); + } + } + else { + CLEAN_TXBUF(); + } + } + + /* Debug outputs. */ + if(status == ST_SUCCESS || status == ST_PHY_ACK_RECEIVED){ + PRINTF("TX_END"); + } + else if (status == ST_MAC_NO_ACK_RECEIVED){ + PRINTF("TX_END_NOACK!!!"); + } + else if (status == ST_PHY_TX_CCA_FAIL){ + PRINTF("TX_END_CCA!!!"); + } + else if(status == ST_PHY_TX_UNDERFLOW){ + PRINTF("TX_END_UFL!!!"); + } + else { + PRINTF("TX_END_INCOMPL!!!"); + } +} + + +boolean ST_RadioDataPendingShortIdIsrCallback(int16u shortId) { + receiving_packet = 1; + return FALSE; +} + +boolean ST_RadioDataPendingLongIdIsrCallback(int8u* longId) { + receiving_packet = 1; + return FALSE; +} +/*---------------------------------------------------------------------------*/ +PROCESS_THREAD(stm32w_radio_process, ev, data) +{ + int len; + + PROCESS_BEGIN(); + + PRINTF("stm32w_radio_process: started\r\n"); + + while(1) { + + PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); + + PRINTF("stm32w_radio_process: calling receiver callback\r\n"); + +#if DEBUG > 1 + for(u8_t c=1; c <= RCVD_PACKET_LEN; c++){ + PRINTF("%x",stm32w_rxbuf[c]); + } + PRINTF("\r\n"); +#endif + + packetbuf_clear(); + len = stm32w_radio_read(packetbuf_dataptr(), PACKETBUF_SIZE); + if(len > 0) { + packetbuf_set_datalen(len); + NETSTACK_RDC.input(); + } + if(!RXBUFS_EMPTY()){ + // Some data packet still in rx buffer (this appens because process_poll doesn't queue requests), + // so stm32w_radio_process need to be called again. + process_poll(&stm32w_radio_process); + } + } + + PROCESS_END(); +} +/*---------------------------------------------------------------------------*/ +static int stm32w_radio_read(void *buf, unsigned short bufsize) +{ + return read_from_rxbuf(buf,bufsize); +} + +/*---------------------------------------------------------------------------*/ +void ST_RadioOverflowIsrCallback(void) +{ + PRINTF("OVERFLOW\r\n"); +} +/*---------------------------------------------------------------------------*/ +void ST_RadioSfdSentIsrCallback(u32 sfdSentTime) +{ +} +/*---------------------------------------------------------------------------*/ +void ST_RadioMacTimerCompareIsrCallback(void) +{ +} +/*---------------------------------------------------------------------------*/ +static int add_to_rxbuf(uint8_t * src) +{ + if(RXBUFS_FULL()){ + return 0; + } + + memcpy(stm32w_rxbufs[last], src, src[0] + 1); +#if RADIO_RXBUFS > 1 + last = (last + 1) % RADIO_RXBUFS; + if(first == -1){ + first = 0; + } +#endif + + return 1; +} +/*---------------------------------------------------------------------------*/ +static int read_from_rxbuf(void * dest, unsigned short len) +{ + + if(RXBUFS_EMPTY()){ // Buffers are all empty + return 0; + } + + if(stm32w_rxbufs[first][0] > len){ // Too large packet for dest. + len = 0; + } + else { + len = stm32w_rxbufs[first][0]; + memcpy(dest,stm32w_rxbufs[first]+1,len); + packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi); + } + +#if RADIO_RXBUFS > 1 + ATOMIC( + first = (first + 1) % RADIO_RXBUFS; + int first_tmp = first; + if(first_tmp == last){ + CLEAN_RXBUFS(); + } + ) +#else + CLEAN_RXBUFS(); +#endif + + return len; +} +/*---------------------------------------------------------------------------*/ +short last_packet_rssi(){ + return last_rssi; +} + diff --git a/cpu/stm32w108/dev/stm32w-radio.h b/cpu/stm32w108/dev/stm32w-radio.h new file mode 100644 index 000000000..a94e9b016 --- /dev/null +++ b/cpu/stm32w108/dev/stm32w-radio.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2007, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * $Id: stm32w-radio.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ + +/** + * \file + * STM32W radio driver header file + * \author + * Adam Dunkels + */ + +#ifndef __STM32W_H__ +#define __STM32W_H__ + +#include "contiki.h" +#include "dev/radio.h" +#include "hal/hal.h" +#include "simplemac/include/phy-library.h" + +int stm32w_radio_set_channel(u8_t channel); +short last_packet_rssi(); + +#define STM32W_MAX_PACKET_LEN 127 + +extern const struct radio_driver stm32w_radio_driver; + + +#endif /* __STM32W_H__ */ diff --git a/cpu/stm32w108/dev/stm32w_conf.h b/cpu/stm32w108/dev/stm32w_conf.h new file mode 100644 index 000000000..c7b64e64c --- /dev/null +++ b/cpu/stm32w108/dev/stm32w_conf.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32w_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the library in DEBUG mode, this will expanse + the "assert_param" macro in the firmware library code (see "Exported macro" + section below) */ +/*#define DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +//#define _ADC +//#define _ADC1 +//#define _ADC2 +//#define _ADC3 + +/************************************* BKP ************************************/ +//#define _BKP + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* CRC ************************************/ +//#define _CRC + +/************************************* DAC ************************************/ +//#define _DAC + +/************************************* DBGMCU *********************************/ +//#define _DBGMCU + +/************************************* DMA ************************************/ +//#define _DMA +//#define _DMA1_Channel1 +//#define _DMA1_Channel2 +//#define _DMA1_Channel3 +//#define _DMA1_Channel4 +//#define _DMA1_Channel5 +//#define _DMA1_Channel6 +//#define _DMA1_Channel7 +//#define _DMA2_Channel1 +//#define _DMA2_Channel2 +//#define _DMA2_Channel3 +//#define _DMA2_Channel4 +//#define _DMA2_Channel5 + +/************************************* EXTI ***********************************/ +//#define _EXTI + +/************************************* FLASH and Option Bytes *****************/ +#define _FLASH +/* Uncomment the line below to enable FLASH program/erase/protections functions, + otherwise only FLASH configuration (latency, prefetch, half cycle) functions + are enabled */ +/* #define _FLASH_PROG */ + +/************************************* FSMC ***********************************/ +//#define _FSMC + +/************************************* GPIO ***********************************/ +#define _GPIO +//#define _GPIOA +//#define _GPIOB +#define _GPIOC +//#define _GPIOD +//#define _GPIOE +#define _GPIOF +//#define _GPIOG +#define _AFIO + +/************************************* I2C ************************************/ +//#define _I2C +//#define _I2C1 +//#define _I2C2 + +/************************************* IWDG ***********************************/ +//#define _IWDG + +/************************************* NVIC ***********************************/ +#define _NVIC + +/************************************* PWR ************************************/ +//#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* SDIO ***********************************/ +//#define _SDIO + +/************************************* SPI ************************************/ +//#define _SPI +//#define _SPI1 +//#define _SPI2 +//#define _SPI3 + +/************************************* SysTick ********************************/ +#define _SysTick + +/************************************* TIM ************************************/ +//#define _TIM +//#define _TIM1 +//#define _TIM2 +//#define _TIM3 +//#define _TIM4 +//#define _TIM5 +//#define _TIM6 +//#define _TIM7 +//#define _TIM8 + +/************************************* USART **********************************/ +//#define _USART +//#define _USART1 +//#define _USART2 +//#define _USART3 +//#define _UART4 +//#define _UART5 + +/************************************* WWDG ***********************************/ +//#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value */ +#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef DEBUG +/******************************************************************************* +* Macro Name : assert_param +* Description : The assert_param macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert_param(expr) ((void)0) +#endif /* DEBUG */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/stm32w_systick.c b/cpu/stm32w108/dev/stm32w_systick.c new file mode 100644 index 000000000..11c3a2f6a --- /dev/null +++ b/cpu/stm32w108/dev/stm32w_systick.c @@ -0,0 +1,181 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_systick.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the SysTick firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32w_systick.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- SysTick registers bit mask -------------------- */ +/* CTRL TICKINT Mask */ +#define CTRL_TICKINT_Set ((u32)0x00000002) +#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SysTick_CLKSourceConfig +* Description : Configures the SysTick clock source. +* Input : - SysTick_CLKSource: specifies the SysTick clock source. +* This parameter can be one of the following values: +* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 +* selected as SysTick clock source. +* - SysTick_CLKSource_HCLK: AHB clock selected as +* SysTick clock source. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/******************************************************************************* +* Function Name : SysTick_SetReload +* Description : Sets SysTick Reload value. +* Input : - Reload: SysTick Reload new value. +* This parameter must be a number between 1 and 0xFFFFFF. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_SetReload(u32 Reload) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_RELOAD(Reload)); + + SysTick->LOAD = Reload; +} + +/******************************************************************************* +* Function Name : SysTick_CounterCmd +* Description : Enables or disables the SysTick counter. +* Input : - SysTick_Counter: new state of the SysTick counter. +* This parameter can be one of the following values: +* - SysTick_Counter_Disable: Disable counter +* - SysTick_Counter_Enable: Enable counter +* - SysTick_Counter_Clear: Clear counter value to 0 +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SysTick_Counter_Enable) + { + SysTick->CTRL |= SysTick_Counter_Enable; + } + else if (SysTick_Counter == SysTick_Counter_Disable) + { + SysTick->CTRL &= SysTick_Counter_Disable; + } + else /* SysTick_Counter == SysTick_Counter_Clear */ + { + SysTick->VAL = SysTick_Counter_Clear; + } +} + +/******************************************************************************* +* Function Name : SysTick_ITConfig +* Description : Enables or disables the SysTick Interrupt. +* Input : - NewState: new state of the SysTick Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_Set; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_Reset; + } +} + +/******************************************************************************* +* Function Name : SysTick_GetCounter +* Description : Gets SysTick counter value. +* Input : None +* Output : None +* Return : SysTick current value +*******************************************************************************/ +u32 SysTick_GetCounter(void) +{ + return(SysTick->VAL); +} + +/******************************************************************************* +* Function Name : SysTick_GetFlagStatus +* Description : Checks whether the specified SysTick flag is set or not. +* Input : - SysTick_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SysTick_FLAG_COUNT +* - SysTick_FLAG_SKEW +* - SysTick_FLAG_NOREF +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG) +{ + u32 statusreg = 0, tmp = 0 ; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SYSTICK_FLAG(SysTick_FLAG)); + + /* Get the SysTick register index */ + tmp = SysTick_FLAG >> 3; + + if (tmp == 2) /* The flag to check is in CTRL register */ + { + statusreg = SysTick->CTRL; + } + else /* The flag to check is in CALIB register */ + { + statusreg = SysTick->CALIB; + } + + if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/stm32w_systick.h b/cpu/stm32w108/dev/stm32w_systick.h new file mode 100644 index 000000000..c9ca99176 --- /dev/null +++ b/cpu/stm32w108/dev/stm32w_systick.h @@ -0,0 +1,109 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_systick.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* SysTick firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32W_SYSTICK_H +#define __STM32W_SYSTICK_H + +#include "stm32w_type.h" +#include "stm32w_conf.h" + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */ +#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */ +#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */ + + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ + + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */ + + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */ + + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* SysTick clock source */ +#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) + +/* SysTick counter state */ +#define SysTick_Counter_Disable ((u32)0xFFFFFFFE) +#define SysTick_Counter_Enable ((u32)0x00000001) +#define SysTick_Counter_Clear ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \ + ((COUNTER) == SysTick_Counter_Enable) || \ + ((COUNTER) == SysTick_Counter_Clear)) + +/* SysTick Flag */ +#define SysTick_FLAG_COUNT ((u32)0x00000010) +#define SysTick_FLAG_SKEW ((u32)0x0000001E) +#define SysTick_FLAG_NOREF ((u32)0x0000001F) + +#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \ + ((FLAG) == SysTick_FLAG_SKEW) || \ + ((FLAG) == SysTick_FLAG_NOREF)) + +#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource); +void SysTick_SetReload(u32 Reload); +void SysTick_CounterCmd(u32 SysTick_Counter); +void SysTick_ITConfig(FunctionalState NewState); +u32 SysTick_GetCounter(void); +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG); + +#endif /* __STM32F10x_SYSTICK_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/stm32w_type.h b/cpu/stm32w108/dev/stm32w_type.h new file mode 100644 index 000000000..e3a5fda06 --- /dev/null +++ b/cpu/stm32w108/dev/stm32w_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +//typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/uart1-putchar.c b/cpu/stm32w108/dev/uart1-putchar.c new file mode 100644 index 000000000..b0da0ac15 --- /dev/null +++ b/cpu/stm32w108/dev/uart1-putchar.c @@ -0,0 +1,67 @@ +#include +#include "dev/uart1.h" + + +#include PLATFORM_HEADER +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" +//#include "uart.h" + +#ifdef __GNUC__ +# define _LLIO_STDIN ((int) stdin) +# define _LLIO_STDOUT ((int) stdout) +# define _LLIO_STDERR ((int) stderr) +# define _LLIO_ERROR (-1) +#else +# ifdef __ICCARM__ +# include +# endif +#endif + +void __io_putchar(char c) +{ + uart1_writeb(c); +} + +#undef putchar + +int putchar(int c) +{ + __io_putchar((char) c); + return c; +} + +size_t _write(int handle, const unsigned char * buffer, size_t size) +{ + size_t nChars = 0; + + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + if (buffer == 0) { + // This means that we should flush internal buffers. + //spin until TX complete (TX is idle) + while ((SC1_UARTSTAT&SC_UARTTXIDLE)!=SC_UARTTXIDLE) {} + return 0; + } + + // ensure port is configured for UART + if(SC1_MODE != SC1_MODE_UART) { + return _LLIO_ERROR; + } + + while(size--) { + __io_putchar(*buffer++); + ++nChars; + } + + return nChars; +} + + +size_t _read(int handle, unsigned char * buffer, size_t size) +{ + return 0; +} + diff --git a/cpu/stm32w108/dev/uart1.c b/cpu/stm32w108/dev/uart1.c new file mode 100644 index 000000000..3a0db2742 --- /dev/null +++ b/cpu/stm32w108/dev/uart1.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Machine dependent STM32W UART1 code. +* \author +* Salvatore Pitrulli +* \version +* 0.1 +* \since +* 03.04.2010 +*/ +/*---------------------------------------------------------------------------*/ + +#include +#include +//#include +//#include + +#include "sys/energest.h" +#include "dev/uart1.h" +#include "dev/watchdog.h" + +#include "lib/ringbuf.h" + +#include "dev/leds.h" + +static int (*uart1_input_handler)(unsigned char c); + +static volatile uint8_t transmitting; + +#ifdef UART1_CONF_TX_WITH_INTERRUPT +#define TX_WITH_INTERRUPT UART1_CONF_TX_WITH_INTERRUPT +#else /* UART1_CONF_TX_WITH_INTERRUPT */ +#define TX_WITH_INTERRUPT 1 +#endif /* UART1_CONF_TX_WITH_INTERRUPT */ + + +#if TX_WITH_INTERRUPT + +#ifdef UART1_CONF_TX_BUFSIZE +#define UART1_TX_BUFSIZE UART1_CONF_TX_BUFSIZE +#else /* UART1_CONF_TX_BUFSIZE */ +#define UART1_TX_BUFSIZE 64 +#endif /* UART1_CONF_TX_BUFSIZE */ + +static struct ringbuf txbuf; +static uint8_t txbuf_data[UART1_TX_BUFSIZE]; +#endif /* TX_WITH_INTERRUPT */ + +/*---------------------------------------------------------------------------*/ +//uint8_t +//uart1_active(void) +//{ +// return ((~ UTCTL1) & TXEPT) | transmitting; +//} +/*---------------------------------------------------------------------------*/ +void +uart1_set_input(int (*input)(unsigned char c)) +{ + uart1_input_handler = input; +} +/*---------------------------------------------------------------------------*/ +void +uart1_writeb(unsigned char c) +{ + watchdog_periodic(); +#if TX_WITH_INTERRUPT + + /* Put the outgoing byte on the transmission buffer. If the buffer + is full, we just keep on trying to put the byte into the buffer + until it is possible to put it there. */ + while(ringbuf_put(&txbuf, c) == 0); + + /* If there is no transmission going, we need to start it by putting + the first byte into the UART. */ + if(transmitting == 0) { + transmitting = 1; + SC1_DATA = ringbuf_get(&txbuf); + INT_SC1FLAG = INT_SCTXFREE; + INT_SC1CFG |= INT_SCTXFREE; + } + +#else /* TX_WITH_INTERRUPT */ + + /* Loop until the transmission buffer is available. */ + while((INT_SC1FLAG & INT_SCTXFREE) == 0); + + /* Transmit the data. */ + SC1_DATA = c; + + INT_SC1FLAG = INT_SCTXFREE; +#endif /* TX_WITH_INTERRUPT */ +} +/*---------------------------------------------------------------------------*/ +#if ! WITH_UIP /* If WITH_UIP is defined, putchar() is defined by the SLIP driver */ +#endif /* ! WITH_UIP */ +/*---------------------------------------------------------------------------*/ +/** + * Initalize the RS232 port. + * + */ +void +uart1_init(unsigned long ubr) +{ + + GPIO_PBCFGL &= 0xF00F; + GPIO_PBCFGL |= 0x0490; + + u16_t uartper = (u32_t)24e6/(2*ubr); + u32_t rest = (u32_t)24e6%(2*ubr); + + SC1_UARTFRAC = 0; + + if(rest > (2*ubr)/4 && rest < (3*2*ubr)/4){ + SC1_UARTFRAC = 1; // + 0.5 + } + else if(rest >= (3*2*ubr)/4){ + uartper++; // + 1 + } + + SC1_UARTPER = uartper; + + SC1_UARTCFG = SC_UART8BIT; + + SC1_MODE = SC1_MODE_UART; + + SC1_INTMODE = SC_RXVALLEVEL | SC_TXFREELEVEL; // Receive buffer has data interrupt mode and Transmit buffer free interrupt mode: Level triggered. + + INT_SC1CFG = INT_SCRXVAL; // Receive buffer has data interrupt enable + + transmitting = 0; + +#if TX_WITH_INTERRUPT + ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data)); +#endif /* TX_WITH_INTERRUPT */ + + + INT_SC1FLAG = 0xFFFF; + + INT_CFGSET = INT_SC1; +} +/*---------------------------------------------------------------------------*/ +void uart1_rx_interrupt(void); +void uart1_tx_interrupt(void); + +void halSc1Isr(void) +{ + + ENERGEST_ON(ENERGEST_TYPE_IRQ); + + if(INT_SC1FLAG & INT_SCRXVAL){ + uart1_rx_interrupt(); + INT_SC1FLAG = INT_SCRXVAL; + } + #if TX_WITH_INTERRUPT + else if(INT_SC1FLAG & INT_SCTXFREE){ + uart1_tx_interrupt(); + INT_SC1FLAG = INT_SCTXFREE; + } + #endif /* TX_WITH_INTERRUPT */ + + + + ENERGEST_OFF(ENERGEST_TYPE_IRQ); + +} + +void uart1_rx_interrupt(void) +{ + uint8_t c; + + c = SC1_DATA; + + if(uart1_input_handler != NULL) { + uart1_input_handler(c); + } + +} +/*---------------------------------------------------------------------------*/ +#if TX_WITH_INTERRUPT +void uart1_tx_interrupt(void) +{ + + if(ringbuf_elements(&txbuf) == 0) { + transmitting = 0; + INT_SC1CFG &= ~INT_SCTXFREE; + } else { + SC1_DATA = ringbuf_get(&txbuf); + } + +} +#endif /* TX_WITH_INTERRUPT */ +/*---------------------------------------------------------------------------*/ diff --git a/cpu/stm32w108/dev/uart1.h b/cpu/stm32w108/dev/uart1.h new file mode 100644 index 000000000..53434ed8e --- /dev/null +++ b/cpu/stm32w108/dev/uart1.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2007, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * $Id: uart1.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ + +/** + * \file + * A brief description of what this file is. + * \author + * Adam Dunkels + */ + +#ifndef __UART1_H__ +#define __UART1_H__ + +//#include "msp430.h" +// +//#define UART1_BAUD2UBR(baud) ((MSP430_CPU_SPEED)/(baud)) + +void uart1_set_input(int (*input)(unsigned char c)); +void uart1_writeb(unsigned char c); +void uart1_init(unsigned long ubr); +//uint8_t uart1_active(void); + +#endif /* __UART1_H__ */ diff --git a/cpu/stm32w108/hal/doxygen/Doxygen_Release b/cpu/stm32w108/hal/doxygen/Doxygen_Release new file mode 100644 index 000000000..bd72919f3 --- /dev/null +++ b/cpu/stm32w108/hal/doxygen/Doxygen_Release @@ -0,0 +1,1557 @@ +# Doxyfile 1.6.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = "Hardware Abstraction Layer" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = 1.0.0 + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = . + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. 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For larger projects a too small cache size can cause +# doxygen to be busy swapping symbols to and from disk most of the time +# causing a significant performance penality. +# If the system has enough physical memory increasing the cache will improve the +# performance by keeping more symbols in memory. Note that the value works on +# a logarithmic scale so increasing the size by one will rougly double the +# memory usage. The cache size is given by this formula: +# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols + +SYMBOL_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespace are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by +# doxygen. The layout file controls the global structure of the generated output files +# in an output format independent way. The create the layout file that represents +# doxygen's defaults, run doxygen with the -l option. You can optionally specify a +# file name after the option, if omitted DoxygenLayout.xml will be used as the name +# of the layout file. + +LAYOUT_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be abled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = ../ + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx +# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.d \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.cs \ + *.php \ + *.php3 \ + *.inc \ + *.m \ + *.mm \ + *.dox \ + *.py \ + *.f90 \ + *.f \ + *.vhd \ + *.vhdl + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix filesystem feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = */hal_test/* + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = NO + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = STHeaderHTML.html + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = STFooterHTML.html + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER +# are set, an additional index file will be generated that can be used as input for +# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated +# HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add. +# For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's +# filter section matches. +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 4 + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# When the SEARCHENGINE tag is enable doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP) or Qt help (GENERATE_QHP) +# there is already a search function so this one should typically +# be disabled. + +SEARCHENGINE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse +# the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option is superseded by the HAVE_DOT option below. This is only a +# fallback. It is recommended to install and use dot, since it yields more +# powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# By default doxygen will write a font called FreeSans.ttf to the output +# directory and reference it in all dot files that doxygen generates. This +# font does not include all possible unicode characters however, so when you need +# these (or just want a differently looking font) you can specify the font name +# using DOT_FONTNAME. You need need to make sure dot is able to find the font, +# which can be done by putting it in a standard location or by setting the +# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory +# containing the font. + +DOT_FONTNAME = FreeSans + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 10 + +# By default doxygen will tell dot to use the output directory to look for the +# FreeSans.ttf font (which doxygen will put there itself). If you specify a +# different font using DOT_FONTNAME you can set the path where dot +# can find it using this tag. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 50 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = NO + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES diff --git a/cpu/stm32w108/hal/doxygen/STFooterHTML.html b/cpu/stm32w108/hal/doxygen/STFooterHTML.html new file mode 100644 index 000000000..4f4cad439 --- /dev/null +++ b/cpu/stm32w108/hal/doxygen/STFooterHTML.html @@ -0,0 +1,18 @@ +
+ + + + + +
+$projectname.
+$projectnumber. +
+		 +
+Copyright © 2009 by STMicrolectronics. All rights reserved.
+Generated $datetime with Doxygen $doxygenversion. +
+
+ + \ No newline at end of file diff --git a/cpu/stm32w108/hal/doxygen/STHeaderHTML.html b/cpu/stm32w108/hal/doxygen/STHeaderHTML.html new file mode 100644 index 000000000..76acc6ee9 --- /dev/null +++ b/cpu/stm32w108/hal/doxygen/STHeaderHTML.html @@ -0,0 +1,16 @@ + + +$title + + + + + + +
+Home  + |  Modules  + |  Data Structures  + |  File List  + |  Index
+
diff --git a/cpu/stm32w108/hal/doxygen/ST_Logo.gif b/cpu/stm32w108/hal/doxygen/ST_Logo.gif new file mode 100644 index 0000000000000000000000000000000000000000..1b401a59c210c025b0d39e787b1eaae51bffd654 GIT binary patch literal 1123 zcmWlXQD|K?7{^aXiyyOvDAO8kaVx`_BC<%7vZoVWikeuMd+Tc00J27A>qy2N4`xWV-035-cKd3cZ_yUcYci#`w+h%m$%B3ON`1EGd!LntFU%S)j|Oo@PTmSBV;P7wk1wYG#Rq7|Wlm08J_ zh$<0j98<3BHJtK!?t>@B6P9F|&%MsG;PcE|Pn0K6mzmcYEBLbZ+&HeB3@)TjN~Dld z$RI-OLM&KtOd^GeoxyGFm~jRx8B$0lq!Ek>X0Tp|n3`Cdn6g+iqa`NjkZLKBR7xrX zWkEBEqy|0H20f$FP{t@TG_OBAHl;Y^iOCZloJ}2d4FyKQP@5+zPb4Jb)uEszM^eeDw3J!RIFcIlpbdJU zQc(t!DVo=RXsoaUSz@w;TW1T7bEM#0a4Wz%;7Fm+gHz~1a3uf)AeH7At8GDZj-;GZ zZYfv|97z>=&+!?K{4jQ)fClrIdd3=x-Lp62Pn*wG7T&#ep8Wax=UcvQX}oZI@XF-fr~TQR zw^yep_gr89;PmLhAJ3(0E5AI})pH;^a(7|o&gA?%CtvIPrztLW{Q7m@jrE7_Wh1@U zqRrKhFaG=Z4@=u>n|k&8rl(=*#^HYc?8NVIDqm^$~J0FHa;mF1P7dB=Getzb^ knaW_t@%OIWIdSs07gowT4E=rY!S +*/ + +/** + * @addtogroup status_codes + * + * Many StZNet API functions return an ::StStatus value to indicate + * the success or failure of the call. + * Return codes are one byte long. + * This page documents the possible status codes and their meanings. + * + * See error-def.h for source code. + * + * See also error.h for information on how the values for the return codes are + * built up from these definitions. + * The file error-def.h is separated from error.h because utilities will use this file + * to parse the return codes. + * + * @note Do not include error-def.h directly. It is included by + * error.h inside an enum typedef, which is in turn included by st.h. + * + * @{ + */ + +/** + * @name Generic Messages + * These messages are system wide. + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The generic "no error" message. + */ +#define ST_SUCCESS(0x00) +#else +DEFINE_ERROR(SUCCESS, 0) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The generic "fatal error" message. + */ +#define ST_ERR_FATAL(0x01) +#else +DEFINE_ERROR(ERR_FATAL, 0x01) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An invalid value was passed as an argument to a function. + */ +#define ST_BAD_ARGUMENT(0x02) +#else +DEFINE_ERROR(BAD_ARGUMENT, 0x02) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The manufacturing and stack token format in non-volatile memory + * is different than what the stack expects (returned at initialization). + */ +#define ST_EEPROM_MFG_STACK_VERSION_MISMATCH(0x04) +#else +DEFINE_ERROR(EEPROM_MFG_STACK_VERSION_MISMATCH, 0x04) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The static memory definitions in st-static-memory.h + * are incompatible with this stack version. + */ +#define ST_INCOMPATIBLE_STATIC_MEMORY_DEFINITIONS(0x05) +#else +DEFINE_ERROR(INCOMPATIBLE_STATIC_MEMORY_DEFINITIONS, 0x05) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The manufacturing token format in non-volatile memory is + * different than what the stack expects (returned at initialization). + */ +#define ST_EEPROM_MFG_VERSION_MISMATCH(0x06) +#else +DEFINE_ERROR(EEPROM_MFG_VERSION_MISMATCH, 0x06) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The stack token format in non-volatile memory is different + * than what the stack expects (returned at initialization). + */ +#define ST_EEPROM_STACK_VERSION_MISMATCH(0x07) +#else +DEFINE_ERROR(EEPROM_STACK_VERSION_MISMATCH, 0x07) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} // END Generic Messages + + +/** + * @name Packet Buffer Module Errors + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief There are no more buffers. + */ +#define ST_NO_BUFFERS(0x18) +#else +DEFINE_ERROR(NO_BUFFERS, 0x18) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} / END Packet Buffer Module Errors + +/** + * @name Serial Manager Errors + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Specified an invalid baud rate. + */ +#define ST_SERIAL_INVALID_BAUD_RATE(0x20) +#else +DEFINE_ERROR(SERIAL_INVALID_BAUD_RATE, 0x20) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Specified an invalid serial port. + */ +#define ST_SERIAL_INVALID_PORT(0x21) +#else +DEFINE_ERROR(SERIAL_INVALID_PORT, 0x21) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Tried to send too much data. + */ +#define ST_SERIAL_TX_OVERFLOW(0x22) +#else +DEFINE_ERROR(SERIAL_TX_OVERFLOW, 0x22) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief There was not enough space to store a received character + * and the character was dropped. + */ +#define ST_SERIAL_RX_OVERFLOW(0x23) +#else +DEFINE_ERROR(SERIAL_RX_OVERFLOW, 0x23) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Detected a UART framing error. + */ +#define ST_SERIAL_RX_FRAME_ERROR(0x24) +#else +DEFINE_ERROR(SERIAL_RX_FRAME_ERROR, 0x24) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Detected a UART parity error. + */ +#define ST_SERIAL_RX_PARITY_ERROR(0x25) +#else +DEFINE_ERROR(SERIAL_RX_PARITY_ERROR, 0x25) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief There is no received data to process. + */ +#define ST_SERIAL_RX_EMPTY(0x26) +#else +DEFINE_ERROR(SERIAL_RX_EMPTY, 0x26) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The receive interrupt was not handled in time, and a + * character was dropped. + */ +#define ST_SERIAL_RX_OVERRUN_ERROR(0x27) +#else +DEFINE_ERROR(SERIAL_RX_OVERRUN_ERROR, 0x27) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + +/** + * @name MAC Errors + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The MAC transmit queue is full. + */ +#define ST_MAC_TRANSMIT_QUEUE_FULL(0x39) +#else +// Internal +DEFINE_ERROR(MAC_TRANSMIT_QUEUE_FULL, 0x39) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief MAC header FCF error on receive. + */ +#define ST_MAC_UNKNOWN_HEADER_TYPE(0x3A) +#else +DEFINE_ERROR(MAC_UNKNOWN_HEADER_TYPE, 0x3A) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief MAC ACK header received. + */ +#define ST_MAC_ACK_HEADER_TYPE(0x3B) +#else +DEFINE_ERROR(MAC_ACK_HEADER_TYPE, 0x3B) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The MAC can't complete this task because it is scanning. + */ +#define ST_MAC_SCANNING(0x3D) +#else +DEFINE_ERROR(MAC_SCANNING, 0x3D) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief No pending data exists for device doing a data poll. + */ +#define ST_MAC_NO_DATA(0x31) +#else +DEFINE_ERROR(MAC_NO_DATA, 0x31) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Attempt to scan when we are joined to a network. + */ +#define ST_MAC_JOINED_NETWORK(0x32) +#else +DEFINE_ERROR(MAC_JOINED_NETWORK, 0x32) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Scan duration must be 0 to 14 inclusive. Attempt was made to + * scan with an incorrect duration value. + */ +#define ST_MAC_BAD_SCAN_DURATION(0x33) +#else +DEFINE_ERROR(MAC_BAD_SCAN_DURATION, 0x33) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief stStartScan was called with an incorrect scan type. + */ +#define ST_MAC_INCORRECT_SCAN_TYPE(0x34) +#else +DEFINE_ERROR(MAC_INCORRECT_SCAN_TYPE, 0x34) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief stStartScan was called with an invalid channel mask. + */ +#define ST_MAC_INVALID_CHANNEL_MASK(0x35) +#else +DEFINE_ERROR(MAC_INVALID_CHANNEL_MASK, 0x35) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Failed to scan current channel because we were unable to + * transmit the relevent MAC command. + */ +#define ST_MAC_COMMAND_TRANSMIT_FAILURE(0x36) +#else +DEFINE_ERROR(MAC_COMMAND_TRANSMIT_FAILURE, 0x36) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief We expected to receive an ACK following the transmission, but + * the MAC level ACK was never received. + */ +#define ST_MAC_NO_ACK_RECEIVED(0x40) +#else +DEFINE_ERROR(MAC_NO_ACK_RECEIVED, 0x40) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Indirect data message timed out before polled. + */ +#define ST_MAC_INDIRECT_TIMEOUT(0x42) +#else +DEFINE_ERROR(MAC_INDIRECT_TIMEOUT, 0x42) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + + +/** + * @name Simulated EEPROM Errors + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The Simulated EEPROM is telling the application that there + * is at least one flash page to be erased. The GREEN status means the + * current page has not filled above the ::ERASE_CRITICAL_THRESHOLD. + * + * The application should call the function ::halSimEepromErasePage() when it can + * to erase a page. + */ +#define ST_SIM_EEPROM_ERASE_PAGE_GREEN(0x43) +#else +DEFINE_ERROR(SIM_EEPROM_ERASE_PAGE_GREEN, 0x43) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The Simulated EEPROM is telling the application that there + * is at least one flash page to be erased. The RED status means the + * current page has filled above the ::ERASE_CRITICAL_THRESHOLD. + * + * Due to the shrinking availablity of write space, there is a danger of + * data loss. The application must call the function ::halSimEepromErasePage() + * as soon as possible to erase a page. + */ +#define ST_SIM_EEPROM_ERASE_PAGE_RED(0x44) +#else +DEFINE_ERROR(SIM_EEPROM_ERASE_PAGE_RED, 0x44) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The Simulated EEPROM has run out of room to write any new data + * and the data trying to be set has been lost. This error code is the + * result of ignoring the ::SIM_EEPROM_ERASE_PAGE_RED error code. + * + * The application must call the function ::halSimEepromErasePage() to make room for + * any further calls to set a token. + */ +#define ST_SIM_EEPROM_FULL(0x45) +#else +DEFINE_ERROR(SIM_EEPROM_FULL, 0x45) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +// Errors 46 and 47 are now defined below in the +// flash error block (was attempting to prevent renumbering) + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Attempt 1 to initialize the Simulated EEPROM has failed. + * + * This failure means the information already stored in Flash (or a lack + * thereof), is fatally incompatible with the token information compiled + * into the code image being run. + */ +#define ST_SIM_EEPROM_INIT_1_FAILED(0x48) +#else +DEFINE_ERROR(SIM_EEPROM_INIT_1_FAILED, 0x48) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Attempt 2 to initialize the Simulated EEPROM has failed. + * + * This failure means Attempt 1 failed, and the token system failed to + * properly reload default tokens and reset the Simulated EEPROM. + */ +#define ST_SIM_EEPROM_INIT_2_FAILED(0x49) +#else +DEFINE_ERROR(SIM_EEPROM_INIT_2_FAILED, 0x49) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Attempt 3 to initialize the Simulated EEPROM has failed. + * + * This failure means one or both of the tokens ::TOKEN_MFG_NVDATA_VERSION or + * ::TOKEN_STACK_NVDATA_VERSION were incorrect and the token system failed to + * properly reload default tokens and reset the Simulated EEPROM. + */ +#define ST_SIM_EEPROM_INIT_3_FAILED(0x4A) +#else +DEFINE_ERROR(SIM_EEPROM_INIT_3_FAILED, 0x4A) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + + +/** + * @name Flash Errors + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief A fatal error has occured while trying to write data to the + * Flash. The target memory attempting to be programmed is already programmed. + * The flash write routines were asked to flip a bit from a 0 to 1, which is + * physically impossible and the write was therefore inhibited. The data in + * the flash cannot be trusted after this error. + */ +#define ST_ERR_FLASH_WRITE_INHIBITED(0x46) +#else +DEFINE_ERROR(ERR_FLASH_WRITE_INHIBITED, 0x46) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief A fatal error has occured while trying to write data to the + * Flash and the write verification has failed. The data in the flash + * cannot be trusted after this error, and it is possible this error is the + * result of exceeding the life cycles of the flash. + */ +#define ST_ERR_FLASH_VERIFY_FAILED(0x47) +#else +DEFINE_ERROR(ERR_FLASH_VERIFY_FAILED, 0x47) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @description A fatal error has occured while trying to write data to the + * flash, possibly due to write protection or an invalid address. The data in + * the flash cannot be trusted after this error, and it is possible this error + * is the result of exceeding the life cycles of the flash. + */ +#define ST_ERR_FLASH_PROG_FAIL(0x4B) +#else +DEFINE_ERROR(ERR_FLASH_PROG_FAIL, 0x4B) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @description A fatal error has occured while trying to erase flash, possibly + * due to write protection. The data in the flash cannot be trusted after + * this error, and it is possible this error is the result of exceeding the + * life cycles of the flash. + */ +#define ST_ERR_FLASH_ERASE_FAIL(0x4C) +#else +DEFINE_ERROR(ERR_FLASH_ERASE_FAIL, 0x4C) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + + +/** + * @name Bootloader Errors + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The bootloader received an invalid message (failed attempt + * to go into bootloader). + */ +#define ST_ERR_BOOTLOADER_TRAP_TABLE_BAD(0x58) +#else +DEFINE_ERROR(ERR_BOOTLOADER_TRAP_TABLE_BAD, 0x58) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Bootloader received an invalid message (failed attempt to go + * into bootloader). + */ +#define ST_ERR_BOOTLOADER_TRAP_UNKNOWN(0x59) +#else +DEFINE_ERROR(ERR_BOOTLOADER_TRAP_UNKNOWN, 0x59) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The bootloader cannot complete the bootload operation because + * either an image was not found or the image exceeded memory bounds. + */ +#define ST_ERR_BOOTLOADER_NO_IMAGE(0x05A) +#else +DEFINE_ERROR(ERR_BOOTLOADER_NO_IMAGE, 0x5A) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + + +/** + * @name Transport Errors + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The APS layer attempted to send or deliver a message, but + * it failed. + */ +#define ST_DELIVERY_FAILED(0x66) +#else +DEFINE_ERROR(DELIVERY_FAILED, 0x66) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief This binding index is out of range for the current binding table. + */ +#define ST_BINDING_INDEX_OUT_OF_RANGE(0x69) +#else +DEFINE_ERROR(BINDING_INDEX_OUT_OF_RANGE, 0x69) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief This address table index is out of range for the current + * address table. + */ +#define ST_ADDRESS_TABLE_INDEX_OUT_OF_RANGE(0x6A) +#else +DEFINE_ERROR(ADDRESS_TABLE_INDEX_OUT_OF_RANGE, 0x6A) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An invalid binding table index was given to a function. + */ +#define ST_INVALID_BINDING_INDEX(0x6C) +#else +DEFINE_ERROR(INVALID_BINDING_INDEX, 0x6C) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The API call is not allowed given the current state of the + * stack. + */ +#define ST_INVALID_CALL(0x70) +#else +DEFINE_ERROR(INVALID_CALL, 0x70) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The link cost to a node is not known. + */ +#define ST_COST_NOT_KNOWN(0x71) +#else +DEFINE_ERROR(COST_NOT_KNOWN, 0x71) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The maximum number of in-flight messages (i.e. + * ::ST_APS_UNICAST_MESSAGE_COUNT) has been reached. + */ +#define ST_MAX_MESSAGE_LIMIT_REACHED(0x72) +#else +DEFINE_ERROR(MAX_MESSAGE_LIMIT_REACHED, 0x72) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The message to be transmitted is too big to fit into a + * single over-the-air packet. + */ +#define ST_MESSAGE_TOO_LONG(0x74) +#else +DEFINE_ERROR(MESSAGE_TOO_LONG, 0x74) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The application is trying to delete or overwrite a binding + * that is in use. + */ +#define ST_BINDING_IS_ACTIVE(0x75) +#else +DEFINE_ERROR(BINDING_IS_ACTIVE, 0x75) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The application is trying to overwrite an address table entry + * that is in use. + */ +#define ST_ADDRESS_TABLE_ENTRY_IS_ACTIVE(0x76) +#else +DEFINE_ERROR(ADDRESS_TABLE_ENTRY_IS_ACTIVE, 0x76) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + +/** + * @name HAL Module Errors + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Conversion is complete. + */ +#define ST_ADC_CONVERSION_DONE(0x80) +#else +DEFINE_ERROR(ADC_CONVERSION_DONE, 0x80) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Conversion cannot be done because a request is being + * processed. + */ +#define ST_ADC_CONVERSION_BUSY(0x81) +#else +DEFINE_ERROR(ADC_CONVERSION_BUSY, 0x81) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Conversion is deferred until the current request has been + * processed. + */ +#define ST_ADC_CONVERSION_DEFERRED(0x82) +#else +DEFINE_ERROR(ADC_CONVERSION_DEFERRED, 0x82) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief No results are pending. + */ +#define ST_ADC_NO_CONVERSION_PENDING(0x84) +#else +DEFINE_ERROR(ADC_NO_CONVERSION_PENDING, 0x84) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief Sleeping (for a duration) has been abnormally interrupted + * and exited prematurely. + */ +#define ST_SLEEP_INTERRUPTED(0x85) +#else +DEFINE_ERROR(SLEEP_INTERRUPTED, 0x85) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + +/** + * @name PHY Errors + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The transmit hardware buffer underflowed. + */ +#define ST_PHY_TX_UNDERFLOW(0x88) +#else +DEFINE_ERROR(PHY_TX_UNDERFLOW, 0x88) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The transmit hardware did not finish transmitting a packet. + */ +#define ST_PHY_TX_INCOMPLETE(0x89) +#else +DEFINE_ERROR(PHY_TX_INCOMPLETE, 0x89) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An unsupported channel setting was specified. + */ +#define ST_PHY_INVALID_CHANNEL(0x8A) +#else +DEFINE_ERROR(PHY_INVALID_CHANNEL, 0x8A) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An unsupported power setting was specified. + */ +#define ST_PHY_INVALID_POWER(0x8B) +#else +DEFINE_ERROR(PHY_INVALID_POWER, 0x8B) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The requested operation cannot be completed because the radio + * is currently busy, either transmitting a packet or performing calibration. + */ +#define ST_PHY_TX_BUSY(0x8C) +#else +DEFINE_ERROR(PHY_TX_BUSY, 0x8C) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The transmit attempt failed because all CCA attempts indicated that + * the channel was busy. + */ +#define ST_PHY_TX_CCA_FAIL(0x8D) +#else +DEFINE_ERROR(PHY_TX_CCA_FAIL, 0x8D) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The software installed on the hardware doesn't recognize the + * hardware radio type. + */ +#define ST_PHY_OSCILLATOR_CHECK_FAILED(0x8E) +#else +DEFINE_ERROR(PHY_OSCILLATOR_CHECK_FAILED, 0x8E) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The expected ACK was received after the last transmission. + */ +#define ST_PHY_ACK_RECEIVED(0x8F) +#else +DEFINE_ERROR(PHY_ACK_RECEIVED, 0x8F) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} + +/** + * @name Return Codes Passed to stStackStatusHandler() + * See also ::stStackStatusHandler(). + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The stack software has completed initialization and is ready + * to send and receive packets over the air. + */ +#define ST_NETWORK_UP(0x90) +#else +DEFINE_ERROR(NETWORK_UP, 0x90) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The network is not operating. + */ +#define ST_NETWORK_DOWN(0x91) +#else +DEFINE_ERROR(NETWORK_DOWN, 0x91) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An attempt to join a network failed. + */ +#define ST_JOIN_FAILED(0x94) +#else +DEFINE_ERROR(JOIN_FAILED, 0x94) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief After moving, a mobile node's attempt to re-establish contact + * with the network failed. + */ +#define ST_MOVE_FAILED(0x96) +#else +DEFINE_ERROR(MOVE_FAILED, 0x96) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An attempt to join as a router failed due to a Zigbee + * versus Zigbee Pro incompatibility. Zigbee devices joining Zigbee Pro networks + * (or vica versa) must join as End Devices, not Routers. + */ +#define ST_CANNOT_JOIN_AS_ROUTER(0x98) +#else +DEFINE_ERROR(CANNOT_JOIN_AS_ROUTER, 0x98) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief The local node ID has changed. The application can obtain the new + * node ID by calling ::stGetNodeId(). + */ +#define ST_NODE_ID_CHANGED(0x99) +#else +DEFINE_ERROR(NODE_ID_CHANGED, 0x99) +#endif + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief The local PAN ID has changed. The application can obtain the new PAN + * ID by calling ::stGetPanId(). + */ +#define ST_PAN_ID_CHANGED(0x9A) +#else +DEFINE_ERROR(PAN_ID_CHANGED, 0x9A) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief The channel has changed. + */ +#define ST_CHANNEL_CHANGED(0x9B) +#else +DEFINE_ERROR(CHANNEL_CHANGED, 0x9B) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief An attempt to join or rejoin the network failed because + * no router beacons could be heard by the joining node. + */ +#define ST_NO_BEACONS(0xAB) +#else +DEFINE_ERROR(NO_BEACONS, 0xAB) +#endif + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief An attempt was made to join a Secured Network using a pre-configured + * key, but the Trust Center sent back a Network Key in-the-clear when + * an encrypted Network Key was required. (::ST_REQUIRE_ENCRYPTED_KEY). + */ +#define ST_RECEIVED_KEY_IN_THE_CLEAR(0xAC) +#else +DEFINE_ERROR(RECEIVED_KEY_IN_THE_CLEAR, 0xAC) +#endif + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief An attempt was made to join a Secured Network, but the device did + * not receive a Network Key. + */ +#define ST_NO_NETWORK_KEY_RECEIVED(0xAD) +#else +DEFINE_ERROR(NO_NETWORK_KEY_RECEIVED, 0xAD) +#endif + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief After a device joined a Secured Network, a Link Key was requested + * (::ST_GET_LINK_KEY_WHEN_JOINING) but no response was ever received. + */ +#define ST_NO_LINK_KEY_RECEIVED(0xAE) +#else +DEFINE_ERROR(NO_LINK_KEY_RECEIVED, 0xAE) +#endif + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief An attempt was made to join a Secured Network without a + * pre-configured key, but the Trust Center sent encrypted data using a + * pre-configured key. + */ +#define ST_PRECONFIGURED_KEY_REQUIRED(0xAF) +#else +DEFINE_ERROR(PRECONFIGURED_KEY_REQUIRED, 0xAF) +#endif + + +//@} + +/** + * @name Security Errors + */ +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The passed key data is not valid. A key of all zeros or + * all F's are reserved values and cannot be used. + */ +#define ST_KEY_INVALID(0xB2) +#else +DEFINE_ERROR(KEY_INVALID, 0xB2) +#endif // DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The chosen security level (the value of ::ST_SECURITY_LEVEL) + * is not supported by the stack. + */ +#define ST_INVALID_SECURITY_LEVEL(0x95) +#else +DEFINE_ERROR(INVALID_SECURITY_LEVEL, 0x95) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief There was an error in trying to encrypt at the APS Level. + * + * This could result from either an inability to determine the long address + * of the recipient from the short address (no entry in the binding table) + * or there is no link key entry in the table associated with the destination, + * or there was a failure to load the correct key into the encryption core. + */ +#define ST_APS_ENCRYPTION_ERROR(0xA6) +#else + DEFINE_ERROR(APS_ENCRYPTION_ERROR, 0xA6) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief There was an attempt to form a network using High + * security without setting the Trust Center master key first. + */ +#define ST_TRUST_CENTER_MASTER_KEY_NOT_SET(0xA7) +#else + DEFINE_ERROR(TRUST_CENTER_MASTER_KEY_NOT_SET, 0xA7) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief There was an attempt to form or join a network with security + * without calling ::stSetInitialSecurityState() first. + */ +#define ST_SECURITY_STATE_NOT_SET(0xA8) +#else + DEFINE_ERROR(SECURITY_STATE_NOT_SET, 0xA8) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief There was an attempt to set an entry in the key table using + * an invalid long address. An entry cannot be set using either + * the local device's or Trust Center's IEEE address. Or an entry + * already exists in the table with the same IEEE address. + * An Address of all zeros or all F's are not valid + * addresses in 802.15.4. + */ +#define ST_KEY_TABLE_INVALID_ADDRESS(0xB3) +#else +DEFINE_ERROR(KEY_TABLE_INVALID_ADDRESS, 0xB3) +#endif //DOYXGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief There was an attempt to set a security configuration that + * is not valid given the other security settings. + */ +#define ST_SECURITY_CONFIGURATION_INVALID(0xB7) +#else +DEFINE_ERROR(SECURITY_CONFIGURATION_INVALID, 0xB7) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief There was an attempt to broadcast a key switch too quickly after + * broadcasting the next network key. The Trust Center must wait at + * least a period equal to the broadcast timeout so that all routers + * have a chance to receive the broadcast of the new network key. + */ +#define ST_TOO_SOON_FOR_SWITCH_KEY(0xB8) +#else + DEFINE_ERROR(TOO_SOON_FOR_SWITCH_KEY, 0xB8) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief The received signature corresponding to the message that was passed + to the CBKE Library failed verification, it is not valid. +*/ +#define ST_SIGNATURE_VERIFY_FAILURE(0xB9) +#else + DEFINE_ERROR(SIGNATURE_VERIFY_FAILURE, 0xB9) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief The message could not be sent because the link key corresponding + to the destination is not authorized for use in APS data messages. + APS Commands (sent by the stack) are allowed. To use it for encryption + of APS data messages it must be authorized using a key agreement protocol + (such as CBKE). +*/ +#define ST_KEY_NOT_AUTHORIZED(0xBB) +#else + DEFINE_ERROR(KEY_NOT_AUTHORIZED, 0xBB) +#endif + + +//@} + + +/** + * @name Miscellaneous Network Errors + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The node has not joined a network. + */ +#define ST_NOT_JOINED(0x93) +#else +DEFINE_ERROR(NOT_JOINED, 0x93) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief A message cannot be sent because the network is currently + * overloaded. + */ +#define ST_NETWORK_BUSY(0xA1) +#else +DEFINE_ERROR(NETWORK_BUSY, 0xA1) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The application tried to send a message using an + * endpoint that it has not defined. + */ +#define ST_INVALID_ENDPOINT(0xA3) +#else +DEFINE_ERROR(INVALID_ENDPOINT, 0xA3) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The application tried to use a binding that has been remotely + * modified and the change has not yet been reported to the application. + */ +#define ST_BINDING_HAS_CHANGED(0xA4) +#else +DEFINE_ERROR(BINDING_HAS_CHANGED, 0xA4) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An attempt to generate random bytes failed because of + * insufficient random data from the radio. + */ +#define ST_INSUFFICIENT_RANDOM_DATA(0xA5) +#else + DEFINE_ERROR(INSUFFICIENT_RANDOM_DATA, 0xA5) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** A ZigBee route error command frame was received indicating + * that a source routed message from this node failed en route. + */ +#define ST_SOURCE_ROUTE_FAILURE(0xA9) +#else + DEFINE_ERROR(SOURCE_ROUTE_FAILURE, 0xA9) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** A ZigBee route error command frame was received indicating + * that a message sent to this node along a many-to-one route + * failed en route. The route error frame was delivered by + * an ad-hoc search for a functioning route. + */ +#define ST_MANY_TO_ONE_ROUTE_FAILURE(0xAA) +#else + DEFINE_ERROR(MANY_TO_ONE_ROUTE_FAILURE, 0xAA) +#endif + + +//@} + +/** + * @name Miscellaneous Utility Errors + */ +//@{ + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief A critical and fatal error indicating that the version of the + * stack trying to run does not match with the chip it is running on. The + * software (stack) on the chip must be replaced with software that is + * compatible with the chip. + */ +#define ST_STACK_AND_HARDWARE_MISMATCH(0xB0) +#else +DEFINE_ERROR(STACK_AND_HARDWARE_MISMATCH, 0xB0) +#endif //DOXYGEN_SHOULD_SKIP_THIS + + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief An index was passed into the function that was larger + * than the valid range. + */ +#define ST_INDEX_OUT_OF_RANGE(0xB1) +#else +DEFINE_ERROR(INDEX_OUT_OF_RANGE, 0xB1) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief There are no empty entries left in the table. + */ +#define ST_TABLE_FULL(0xB4) +#else +DEFINE_ERROR(TABLE_FULL, 0xB4) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The requested table entry has been erased and contains + * no valid data. + */ +#define ST_TABLE_ENTRY_ERASED(0xB6) +#else +DEFINE_ERROR(TABLE_ENTRY_ERASED, 0xB6) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The requested function cannot be executed because + * the library that contains the necessary functionality is not present. + */ +#define ST_LIBRARY_NOT_PRESENT(0xB5) +#else +DEFINE_ERROR(LIBRARY_NOT_PRESENT, 0xB5) +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief The stack accepted the command and is currently processing + * the request. The results will be returned via an appropriate handler. + */ +#define ST_OPERATION_IN_PROGRESS(0xBA) +#else +DEFINE_ERROR(OPERATION_IN_PROGRESS, 0xBA) +#endif + +//@} + +/** + * @name Application Errors + * These error codes are available for application use. + */ +//@{ + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** + * @brief This error is reserved for customer application use. + * This will never be returned from any portion of the network stack or HAL. + */ +#define ST_APPLICATION_ERROR_0(0xF0) +#define ST_APPLICATION_ERROR_1(0xF1) +#define ST_APPLICATION_ERROR_2(0xF2) +#define ST_APPLICATION_ERROR_3(0xF3) +#define ST_APPLICATION_ERROR_4(0xF4) +#define ST_APPLICATION_ERROR_5(0xF5) +#define ST_APPLICATION_ERROR_6(0xF6) +#define ST_APPLICATION_ERROR_7(0xF7) +#define ST_APPLICATION_ERROR_8(0xF8) +#define ST_APPLICATION_ERROR_9(0xF9) +#define ST_APPLICATION_ERROR_10(0xFA) +#define ST_APPLICATION_ERROR_11(0xFB) +#define ST_APPLICATION_ERROR_12(0xFC) +#define ST_APPLICATION_ERROR_13(0xFD) +#define ST_APPLICATION_ERROR_14(0xFE) +#define ST_APPLICATION_ERROR_15(0xFF) +#else +DEFINE_ERROR( APPLICATION_ERROR_0, 0xF0) +DEFINE_ERROR( APPLICATION_ERROR_1, 0xF1) +DEFINE_ERROR( APPLICATION_ERROR_2, 0xF2) +DEFINE_ERROR( APPLICATION_ERROR_3, 0xF3) +DEFINE_ERROR( APPLICATION_ERROR_4, 0xF4) +DEFINE_ERROR( APPLICATION_ERROR_5, 0xF5) +DEFINE_ERROR( APPLICATION_ERROR_6, 0xF6) +DEFINE_ERROR( APPLICATION_ERROR_7, 0xF7) +DEFINE_ERROR( APPLICATION_ERROR_8, 0xF8) +DEFINE_ERROR( APPLICATION_ERROR_9, 0xF9) +DEFINE_ERROR( APPLICATION_ERROR_10, 0xFA) +DEFINE_ERROR( APPLICATION_ERROR_11, 0xFB) +DEFINE_ERROR( APPLICATION_ERROR_12, 0xFC) +DEFINE_ERROR( APPLICATION_ERROR_13, 0xFD) +DEFINE_ERROR( APPLICATION_ERROR_14, 0xFE) +DEFINE_ERROR( APPLICATION_ERROR_15, 0xFF) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +//@} // END name group + +/** @} END addtogroup */ + +/** + * + */ + +/** + * + */ + diff --git a/cpu/stm32w108/hal/error.h b/cpu/stm32w108/hal/error.h new file mode 100644 index 000000000..768cf486c --- /dev/null +++ b/cpu/stm32w108/hal/error.h @@ -0,0 +1,56 @@ +/** + * @file error.h + * @brief Return codes for API functions and module definitions. + * + * See @ref status_codes for documentation. + * + * + */ + +#ifndef __ERRORS_H__ +#define __ERRORS_H__ + +/** + * @brief Return type for St functions. + */ +#ifndef __STSTATUS_TYPE__ +#define __STSTATUS_TYPE__ + typedef int8u StStatus; +#endif //__STSTATUS_TYPE__ + +/** + * @addtogroup status_codes + * @{ + */ + +/** + * @brief Macro used by error-def.h to define all of the return codes. + * + * @param symbol The name of the constant being defined. All St returns + * begin with ST_. For example, ::ST_CONNECTION_OPEN. + * + * @param value The value of the return code. For example, 0x61. + */ +#define DEFINE_ERROR(symbol, value) \ + ST_ ## symbol = value, + + +enum { +#ifndef DOXYGEN_SHOULD_SKIP_THIS +#include "error-def.h" +#endif //DOXYGEN_SHOULD_SKIP_THIS + /** Gets defined as a count of all the possible return codes in the + * StZNet stack API. + */ + ST_ERROR_CODE_COUNT + +}; + +#undef DEFINE_ERROR + +#endif // __ERRORS_H__ + +/**@} // End of addtogroup + */ + + diff --git a/cpu/stm32w108/hal/hal.h b/cpu/stm32w108/hal/hal.h new file mode 100644 index 000000000..e0fb7bbe7 --- /dev/null +++ b/cpu/stm32w108/hal/hal.h @@ -0,0 +1,43 @@ +/** @file hal/hal.h + * @brief Generic set of HAL includes for all platforms. + * + * See also @ref hal for more documentation. + * + * + */ + +/** @addtogroup hal + * @if STM32W10XX + *

STM32W108xx Microprocessors

+ * @endif + * + * HAL function names have the following conventions: + * + * HAL which SimpleMAC library depends upon: API that is required for proper operation of the SimpleMAC library. As with all of the HAL, it is provided as source and it is possible for the end customer to modify this code. However, unlike other portions of the HAL, if the customer does modify this code, it must ensure that equivalent functionality is still provided to ensure proper operation of the SimpleMAC library. + * + * + * HAL for other chip capabilities: API which SimpleMAC does not directly depend on. However, much of this functionality may be required for proper operation of all features of the chip. + * + * Additional HAL for sample applications: API which is included to assist the development of the included sample applications. This functionality may be very useful, but is not required for proper operation of the chip. This code and functionality may be freely modified by the end customer. + * + *

+ * + * See also hal.h. + */ + + +#ifndef __HAL_H__ +#define __HAL_H__ + +// Keep micro first for specifics used by other headers +#include "micro/micro-common.h" +#include "micro/cortexm3/micro-common.h" + +#include "micro/led.h" +#include "micro/button.h" +#include "micro/system-timer.h" +#include "micro/cortexm3/nvm.h" +#include "hal/micro/cortexm3/uart.h" + +#endif //__HAL_H__ + diff --git a/cpu/stm32w108/hal/micro/adc.h b/cpu/stm32w108/hal/micro/adc.h new file mode 100644 index 000000000..76fe07de4 --- /dev/null +++ b/cpu/stm32w108/hal/micro/adc.h @@ -0,0 +1,303 @@ +/** @file /hal/micro/adc.h + * @brief Header for A/D converter. + * + * + */ +/** @addtogroup adc + * Sample A/D converter driver. + * + * See adc.h for source code. + * + * @note Stm32w108xx ADC driver support is preliminary and essentailly untested - + * please do not attempt to use this ADC driver on this platform. + * + * @note Except for the Stm32w108xx, the StZNet stack does use these functions. + * + * To use the ADC system, include this file and ensure that + * ::halInternalInitAdc() is called whenever the microcontroller is + * started. Call ::halInternalSleepAdc() to sleep the module and + * ::halInternalInitAdc() to wake up the module. + * + * A "user" is a separate thread of execution and usage. That is, + * internal St code is one user and clients are a different user. + * But a client that is calling the ADC in two different functions + * constitutes only one user, as long as the ADC access is not + * interleaved. + * + * @note This code does not allow access to the continuous reading mode of + * the ADC, which some clients may require. + * + * Many functions in this file return an ::StStatus value. See + * error-def.h for definitions of all ::StStatus return values. + * + *@{ + */ +#ifndef __ADC_H__ +#define __ADC_H__ + +// A type for the ADC User enumeration. +typedef int8u ADCUser; +enum +{ + /** LQI User ID. */ + ADC_USER_LQI = 0, + /** Application User ID */ + ADC_USER_APP = 1, + /** Application User ID */ + ADC_USER_APP2 = 2 +}; + +/** @brief Be sure to update ::NUM_ADC_USERS if additional users are added + * to the ::ADCUser list. + */ +#define NUM_ADC_USERS 3 // make sure to update if the above is adjusted + + +// A type for the reference enumeration. +typedef int8u ADCReferenceType; +enum +{ + /** AREF pin reference. */ + ADC_REF_AREF = 0x00, + /** AVCC pin reference. */ + ADC_REF_AVCC = 0x40, + /** Internal reference. */ + ADC_REF_INT = 0xC0 +}; + +// A type for the rate enumeration. +typedef int8u ADCRateType; +enum +{ + /** Rate 32 us, 5 effective bits in ADC_DATA[15:11] */ + ADC_CONVERSION_TIME_US_32 = 0x0, + /** Rate 64 us, 6 effective bits in ADC_DATA[15:10] */ + ADC_CONVERSION_TIME_US_64 = 0x1, + /** Rate 128 us, 7 effective bits in ADC_DATA[15:9] */ + ADC_CONVERSION_TIME_US_128 = 0x2, + /** Rate 256 us, 8 effective bits in ADC_DATA[15:8] */ + ADC_CONVERSION_TIME_US_256 = 0x3, + /** Rate 512 us, 9 effective bits in ADC_DATA[15:7] */ + ADC_CONVERSION_TIME_US_512 = 0x4, + /** Rate 1024 us, 10 effective bits in ADC_DATA[15:6] */ + ADC_CONVERSION_TIME_US_1024 = 0x5, + /** Rate 2048 us, 11 effective bits in ADC_DATA[15:5] */ + ADC_CONVERSION_TIME_US_2048 = 0x6, + /** Rate 4096 us, 12 effective bits in ADC_DATA[15:4] */ + ADC_CONVERSION_TIME_US_4096 = 0x7, +}; + + +#if defined (CORTEXM3) + /** Channel 0 : ADC0 on PB5 */ +#define ADC_MUX_ADC0 0x0 + /** Channel 1 : ADC0 on PB6 */ +#define ADC_MUX_ADC1 0x1 + /** Channel 2 : ADC0 on PB7 */ +#define ADC_MUX_ADC2 0x2 + /** Channel 3 : ADC0 on PC1 */ +#define ADC_MUX_ADC3 0x3 + /** Channel 4 : ADC0 on PA4 */ +#define ADC_MUX_ADC4 0x4 + /** Channel 5 : ADC0 on PA5 */ +#define ADC_MUX_ADC5 0x5 + /** Channel 8 : VSS (0V) - not for high voltage range */ +#define ADC_MUX_GND 0x8 + /** Channel 9 : VREF/2 (0.6V) */ +#define ADC_MUX_VREF2 0x9 + /** Channel A : VREF (1.2V)*/ +#define ADC_MUX_VREF 0xA + /** Channel B : Regulator/2 (0.9V) - not for high voltage range */ +#define ADC_MUX_VREG2 0xB + +// ADC_SOURCE__ selects as the positive input and as +// the negative input. +enum +{ + ADC_SOURCE_ADC0_VREF2 = ((ADC_MUX_ADC0 < + */ + +#ifndef _BUTTON_H_ +#define _BUTTON_H_ + +/* button status */ +#define BUTTON_PRESSED 0 +#define BUTTON_RELEASED 1 +#define BUTTON_UNKNOWN 3 + + +typedef int8u HalBoardButton; + +/* Functions -----------------------------------------------------------------*/ + +/** @brief Init buttons */ +void halInitButton(void); + +/** @brief Get button status */ +int8u halGetButtonStatus(HalBoardButton button); + +#endif /* _BUTTON_H_ */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/hal/micro/cortexm3/adc.c b/cpu/stm32w108/hal/micro/cortexm3/adc.c new file mode 100644 index 000000000..79e017f6c --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/adc.c @@ -0,0 +1,349 @@ +/** @file adc.c + * @brief ADC HAL functions + * + * + */ +#include PLATFORM_HEADER +#include "hal/error.h" +#include "hal/hal.h" +#include "hal/micro/adc.h" + + +#if (NUM_ADC_USERS > 8) + #error NUM_ADC_USERS must not be greater than 8, or int8u variables in adc.c must be changed +#endif + +static int16u adcData; // conversion result written by DMA +static int8u adcPendingRequests; // bitmap of pending requests +volatile static int8u adcPendingConversion; // id of pending conversion +static int8u adcReadingValid; // bitmap of valid adcReadings +static int16u adcReadings[NUM_ADC_USERS]; +static int16u adcConfig[NUM_ADC_USERS]; +static boolean adcCalibrated; +static int16s Nvss; +static int16s Nvdd; +/* Modified the original ADC driver for enabling the ADC extended range mode required for + supporting the STLM20 temperature sensor. + NOTE: + The ADC extended range is inaccurate due to the high voltage mode bug of the general purpose ADC + (see STM32W108 errata). As consequence, it is not reccomended to use this ADC driver for getting + the temperature values +*/ +#ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN +static int16s Nvref; +static int16s Nvref2; +#endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ +static int16u adcStaticConfig; + +void halAdcSetClock(boolean slow) +{ + if (slow) { + adcStaticConfig |= ADC_1MHZCLK_MASK; + } else { + adcStaticConfig &= ~ADC_1MHZCLK_MASK; + } +} + +void halAdcSetRange(boolean high) +{ + if (high) { + adcStaticConfig |= (ADC_HVSELP_MASK | ADC_HVSELN_MASK); + } else { + adcStaticConfig &= ~(ADC_HVSELP_MASK | ADC_HVSELN_MASK); + } +} + +boolean halAdcGetClock(void) +{ + /* Fix original function code */ + return (adcStaticConfig & ADC_1MHZCLK_MASK) ? TRUE : FALSE; +} + +boolean halAdcGetRange(void) +{ + /* Fix original function code */ + return (adcStaticConfig & ((ADC_HVSELP_MASK | ADC_HVSELN_MASK))) ? TRUE : FALSE; +} + + + +// Define a channel field that combines ADC_MUXP and ADC_MUXN +#define ADC_CHAN (ADC_MUXP | ADC_MUXN) +#define ADC_CHAN_BIT ADC_MUXN_BIT + +void halAdcIsr(void) +{ + int8u i; + int8u conversion = adcPendingConversion; //fix 'volatile' warning; costs no flash + + // make sure data is ready and the desired conversion is valid + if ( (INT_ADCFLAG & INT_ADCULDFULL) + && (conversion < NUM_ADC_USERS) ) { + adcReadings[conversion] = adcData; + adcReadingValid |= BIT(conversion); // mark the reading as valid + // setup the next conversion if any + if (adcPendingRequests) { + for (i = 0; i < NUM_ADC_USERS; i++) { + if (BIT(i) & adcPendingRequests) { + adcPendingConversion = i; // set pending conversion + adcPendingRequests ^= BIT(i); //clear request: conversion is starting + ADC_CFG = adcConfig[i]; + break; //conversion started, so we're done here (only one at a time) + } + } + } else { // no conversion to do + ADC_CFG = 0; // disable adc + adcPendingConversion = NUM_ADC_USERS; //nothing pending, so go "idle" + } + } + INT_ADCFLAG = 0xFFFF; + asm("DMB"); +} + +// An internal support routine called from functions below. +// Returns the user number of the started conversion, or NUM_ADC_USERS +// otherwise. +ADCUser startNextConversion() +{ + int8u i; + + ATOMIC ( + // start the next requested conversion if any + if (adcPendingRequests && !(ADC_CFG & ADC_ENABLE)) { + for (i = 0; i < NUM_ADC_USERS; i++) { + if ( BIT(i) & adcPendingRequests) { + adcPendingConversion = i; // set pending conversion + adcPendingRequests ^= BIT(i); // clear request + ADC_CFG = adcConfig[i]; // set the configuration to desired + INT_ADCFLAG = 0xFFFF; + INT_CFGSET = INT_ADC; + } + } + } else { + i = NUM_ADC_USERS; + } + ) + return i; +} + +void halInternalInitAdc(void) +{ + // reset the state variables + adcPendingRequests = 0; + adcPendingConversion = NUM_ADC_USERS; + adcCalibrated = FALSE; + adcStaticConfig = ADC_1MHZCLK | ADC_ENABLE; // init config: 1MHz, low voltage + + // set all adcReadings as invalid + adcReadingValid = 0; + + // turn off the ADC + ADC_CFG = 0; // disable ADC, turn off HV buffers + ADC_OFFSET = ADC_OFFSET_RESET; + ADC_GAIN = ADC_GAIN_RESET; + ADC_DMACFG = ADC_DMARST; + ADC_DMABEG = (int32u)&adcData; + ADC_DMASIZE = 1; + ADC_DMACFG = (ADC_DMAAUTOWRAP | ADC_DMALOAD); + + // clear the ADC interrupts and enable + INT_ADCCFG = INT_ADCULDFULL; + INT_ADCFLAG = 0xFFFF; + INT_CFGSET = INT_ADC; + + stCalibrateVref(); +} + +StStatus halStartAdcConversion(ADCUser id, + ADCReferenceType reference, + ADCChannelType channel, + ADCRateType rate) +{ + + if(reference != ADC_REF_INT) + return ST_ERR_FATAL; + + // save the chosen configuration for this user + adcConfig[id] = ( ((rate << ADC_PERIOD_BIT) & ADC_PERIOD) + | ((channel << ADC_CHAN_BIT) & ADC_CHAN) + | adcStaticConfig); + + // if the user already has a pending request, overwrite params + if (adcPendingRequests & BIT(id)) { + return ST_ADC_CONVERSION_DEFERRED; + } + + ATOMIC ( + // otherwise, queue the transaction + adcPendingRequests |= BIT(id); + // try and start the conversion if there is not one happening + adcReadingValid &= ~BIT(id); + ) + if (startNextConversion() == id) + return ST_ADC_CONVERSION_BUSY; + else + return ST_ADC_CONVERSION_DEFERRED; +} + +StStatus halRequestAdcData(ADCUser id, int16u *value) +{ + //Both the ADC interrupt and the global interrupt need to be enabled, + //otherwise the ADC ISR cannot be serviced. + boolean intsAreOff = ( INTERRUPTS_ARE_OFF() + || !(INT_CFGSET & INT_ADC) + || !(INT_ADCCFG & INT_ADCULDFULL) ); + StStatus stat; + + ATOMIC ( + // If interupts are disabled but the flag is set, + // manually run the isr... + //FIXME -= is this valid??? + if( intsAreOff + && ( (INT_CFGSET & INT_ADC) && (INT_ADCCFG & INT_ADCULDFULL) )) { + halAdcIsr(); + } + + // check if we are done + if (BIT(id) & adcReadingValid) { + *value = adcReadings[id]; + adcReadingValid ^= BIT(id); + stat = ST_ADC_CONVERSION_DONE; + } else if (adcPendingRequests & BIT(id)) { + stat = ST_ADC_CONVERSION_DEFERRED; + } else if (adcPendingConversion == id) { + stat = ST_ADC_CONVERSION_BUSY; + } else { + stat = ST_ADC_NO_CONVERSION_PENDING; + } + ) + return stat; +} + +StStatus halReadAdcBlocking(ADCUser id, int16u *value) +{ + StStatus stat; + + do { + stat = halRequestAdcData(id, value); + if (stat == ST_ADC_NO_CONVERSION_PENDING) + break; + } while(stat != ST_ADC_CONVERSION_DONE); + return stat; +} + +StStatus halAdcCalibrate(ADCUser id) +{ + StStatus stat; +/* Modified the original ADC driver for enabling the ADC extended range mode required for + supporting the STLM20 temperature sensor. + NOTE: + The ADC extended range is inaccurate due to the high voltage mode bug of the general purpose ADC + (see STM32W108 errata). As consequence, it is not reccomended to use this ADC driver for getting + the temperature values + */ +#ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN + if(halAdcGetRange()){ + + halStartAdcConversion(id, + ADC_REF_INT, + ADC_SOURCE_VREF_VREF2, + ADC_CONVERSION_TIME_US_4096); + + stat = halReadAdcBlocking(id, (int16u *)(&Nvref)); + if (stat == ST_ADC_CONVERSION_DONE) { + halStartAdcConversion(id, + ADC_REF_INT, + ADC_SOURCE_VREF2_VREF2, + ADC_CONVERSION_TIME_US_4096); + stat = halReadAdcBlocking(id, (int16u *)(&Nvref2)); + } + if (stat == ST_ADC_CONVERSION_DONE) { + adcCalibrated = TRUE; + } else { + adcCalibrated = FALSE; + stat = ST_ERR_FATAL; + } + return stat; + + } +#endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ + halStartAdcConversion(id, + ADC_REF_INT, + ADC_SOURCE_GND_VREF2, + ADC_CONVERSION_TIME_US_4096); + stat = halReadAdcBlocking(id, (int16u *)(&Nvss)); + if (stat == ST_ADC_CONVERSION_DONE) { + halStartAdcConversion(id, + ADC_REF_INT, + ADC_SOURCE_VREG2_VREF2, + ADC_CONVERSION_TIME_US_4096); + stat = halReadAdcBlocking(id, (int16u *)(&Nvdd)); + } + if (stat == ST_ADC_CONVERSION_DONE) { + Nvdd -= Nvss; + adcCalibrated = TRUE; + } else { + adcCalibrated = FALSE; + stat = ST_ERR_FATAL; + } + return stat; +} + +// Use the ratio of the sample reading to the of VDD_PADSA/2, known to be 900mV, +// to convert to 100uV units. +// FIXME: support external Vref +// use #define of Vref, ignore VDD_PADSA +// FIXME: support high voltage range +// use Vref-Vref/2 to calibrate +// FIXME: check for mfg token specifying measured VDD_PADSA +int16s halConvertValueToVolts(int16u value) +{ + int32s N; + int16s V; + int32s nvalue; + + if (!adcCalibrated) { + halAdcCalibrate(ADC_USER_LQI); + } + if (adcCalibrated) { + /* Modified the original ADC driver for enabling the ADC extended range mode required for + supporting the STLM20 temperature sensor. + NOTE: + The ADC extended range is inaccurate due to the high voltage mode bug of the general purpose ADC + (see STM32W108 errata). As consequence, it is not reccomended to use this ADC driver for getting + the temperature values + */ +#ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN + if(halAdcGetRange()){ // High range. + + N = (((int32s)value + Nvref - 2*Nvref2) << 16)/(2*(Nvref-Nvref2)); + // Calculate voltage with: V = (N * VREF) / (2^16) where VDD = 1.2 volts + // Mutiplying by 1.2*10000 makes the result of this equation 100 uVolts + V = (int16s)((N*12000L) >> 16); + if (V > 21000) { // VDD_PADS ? + V = 21000; + } + + } + else { + #endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ + assert(Nvdd); + nvalue = value - Nvss; + // Convert input value (minus ground) to a fraction of VDD/2. + N = ((nvalue << 16) + Nvdd/2) / Nvdd; + // Calculate voltage with: V = (N * VDD/2) / (2^16) where VDD/2 = 0.9 volts + // Mutiplying by0.9*10000 makes the result of this equation 100 uVolts + // (in fixed point E-4 which allows for 13.5 bits vs millivolts + // which is only 10.2 bits). + V = (int16s)((N*9000L) >> 16); + if (V > 12000) { + V = 12000; + } + #ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN + } + #endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ + } else { + V = -32768; + } + return V; +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h b/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h new file mode 100644 index 000000000..fe7775935 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h @@ -0,0 +1,56 @@ +/** @file hal/micro/cortexm3/bootloader/fib-bootloader.h + * @brief Definition and description of FIB bootloader shared functions. + * + * + */ + +#ifndef __FIB_BOOTLOADER_H__ +#define __FIB_BOOTLOADER_H__ + +//------------------------------------------------------------------------------ +// Reset signatures. + +#define FIB_RESET_GO_ZERO 0xF00F0100 +// Reset signatures 0xF00F0100 to 0xF00F010F can be chosen using the go command. +#define FIB_RESET_GO_JUMP 0xF00F0110 +#define FIB_RESET_BAUD_RATE 0xF00F0111 +#define FIB_RESET_READ_UNPROTECT 0xF00F0112 +#define FIB_RESET_GPIO_BOOTMODE 0xF00F0113 +#define FIB_RESET_PART_DATA 0xF00F0114 +#define FIB_RESET_NMI_HARD_FAULT 0xF00F0115 + +//------------------------------------------------------------------------------ +// Status values. + +typedef int32u FibStatus; + +#define FIB_SUCCESS 0 +#define FIB_ERR_UNALIGNED 1 +#define FIB_ERR_INVALID_ADDRESS 2 +#define FIB_ERR_INVALID_TYPE 3 +#define FIB_ERR_WRITE_PROTECTED 4 +#define FIB_ERR_WRITE_FAILED 5 +#define FIB_ERR_ERASE_REQUIRED 6 +#define FIB_ERR_VERIFY_FAILED 7 + +//------------------------------------------------------------------------------ +// Erase types. + +typedef int32u FibEraseType; + +#define MFB_MASS_ERASE 0x01 +#define MFB_PAGE_ERASE 0x02 +#define CIB_ERASE 0x03 + +#define DO_ERASE 0x0100 +#define DO_VERIFY 0x0200 + +//------------------------------------------------------------------------------ +// Shared flash functions. + +FibStatus fibFlashWrite(int32u address, int8u *data, + int32u writeLength, int32u verifyLength); + +FibStatus fibFlashErase(FibEraseType eraseType, int32u address); + +#endif //__FIB_BOOTLOADER_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/button.c b/cpu/stm32w108/hal/micro/cortexm3/button.c new file mode 100644 index 000000000..3b8f2297e --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/button.c @@ -0,0 +1,29 @@ +/** @file /hal/micro/cortexm3/button.c + * @brief button APIs + * + * + */ + +#include PLATFORM_HEADER +#include BOARD_HEADER +#include "hal/micro/button.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" + +void halInitButton(void) +{ + /* Set GPIO pin to PUD (input pull-up or pull-down) for button S1 */ + halGpioConfig(BUTTON_S1,GPIOCFG_IN_PUD); + /* Set the button S1 gpio pin to pull-up */ + BUTTON_S1_OUTPUT_GPIO |= GPIOOUT_PULLUP << BUTTON_S1_GPIO_PIN; +}/* end halInitButton() */ + + +int8u halGetButtonStatus(HalBoardButton button) +{ + if (button == BUTTON_S1) + return (BUTTON_S1_INPUT_GPIO & (1< + */ + +#include PLATFORM_HEADER +#include "error.h" + +#include "hal/hal.h" +#include "hal/micro/cortexm3/mpu.h" +#include "hal/micro/cortexm3/mfg-token.h" + + +//Provide a simple means for enabling calibration debug output +#define CALDBG(x) +//#define CALDBG(x) x + +//The slowest frequency for the 10kHz RC source is 8kHz (125us). The PERIOD +//register updates every 16 cycles, so to be safe 17 cycles = 2125us. But, +//we need twice this maximum time because the period measurement runs +//asynchronously, and the value of CLKRC_TUNE is changed immediately before +//the delay. +#define SLOWRC_PERIOD_SETTLE_TIME 4250 +//The CLK_PERIOD register measures the number of 12MHz clock cycles that +//occur in 16 cycles of the SlowRC clock. This is meant to smooth out the the +//noise inherently present in the analog RC source. While these 16 cycles +//smooths out most noise, there is still some jitter in the bottom bits of +//CLK_PERIOD. To further smooth out the noise, we take several readings of +//CLK_PERIOD and average them out. Testing has shown that the bottom 3 and 4 +//bits of CLK_PERIOD contain most of the jitter. Averaging 8 samples will +//smooth out 3 bits of jitter and provide a realiable and stable reading useful +//in the calculations, while taking much less time than 16 or 32 samples. +#define SLOWRC_PERIOD_SAMPLES 8 +//The register CLK1K_CAL is a fractional divider that divides the 10kHz analog +//source with the goal of generating a 1024Hz, clk1k output. +// 10000Hz / CLK1K_CAL = 1024Hz. +//Since the CLK_PERIOD register measures the number of 12MHz cycles in 16 +//cycles of the RC: +// 16 * 12000000 +// ------------- = ~10kHz +// CLK_PERIOD +//and +// ~10kHz / 1024 = X +//where X is the fractional number that belongs in CLK1K_CAL. Since the +//integer portion of CLK1K_CAL is bits 15:11 and the fractional is 10:0, +//multiplying X by 2048 (bit shift left by 11) generates the proper CLK1K_CAL +//register value. +// +//Putting this all together: +// 16 * 12000000 * 2048 384000000 +// -------------------- = ------------ = CLK1K_CAL +// CLK_PERIOD * 1024 CLK_PERIOD +// +#define CLK1K_NUMERATOR 384000000 +void halInternalCalibrateSlowRc( void ) +{ + int8u i; + int32u average=0; + int16s delta; + int32u period; + + CALDBG( + stSerialPrintf(ST_ASSERT_SERIAL_PORT, "halInternalCalibrateSlowRc:\r\n"); + ) + + ////---- STEP 1: coarsely tune SlowRC in analog section to ~10kHz ----//// + //To operate properly across the full temperature and voltage range, + //the RC source in the analog section needs to be first coarsely tuned + //to 10kHz. The CLKRC_TUNE register, which is 2's compliment, provides 16 + //steps at ~400Hz per step yielding approximate frequences of 8kHz at 7 + //and 15kHz at -8. + //Start with our reset values for TUNE and CAL + CLK_PERIODMODE = 0; //measure SlowRC + CLKRC_TUNE = CLKRC_TUNE_RESET; + CLK1K_CAL = CLK1K_CAL_RESET; + //wait for the PERIOD register to properly update + halCommonDelayMicroseconds(SLOWRC_PERIOD_SETTLE_TIME); + //Measure the current CLK_PERIOD to obtain a baseline + CALDBG( + stSerialPrintf(ST_ASSERT_SERIAL_PORT, + "period: %u, ", CLK_PERIOD); + stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u Hz\r\n", + ((int16u)(((int32u)192000000)/((int32u)CLK_PERIOD)))); + ) + //For 10kHz, the ideal CLK_PERIOD is 19200. Calculate the PERIOD delta. + //It's possible for a chip's 10kHz source RC to be too far out of range + //for the CLKRC_TUNE to bring it back to 10kHz. Therefore, we have to + //ensure that our delta correction does not exceed the tune range so + //tune has to be capped to the end of the vailable range so it does not + //wrap. Even if we cannot achieve 10kHz, the 1kHz calibration can still + //properly correct to 1kHz. + //Each CLKRC_TUNE step yields a CLK_PERIOD delta of *approximately* 800. + //Calculate how many steps we are off. While dividing by 800 may seem + //like an ugly calculation, the precision of the result is worth the small + //bit of code and time needed to do a divide. + period = CLK_PERIOD; + //Round to the nearest integer + delta = (19200+400) - period; + delta /= 800; + //CLKRC_TUNE is a 4 bit signed number. cap the delta to 7/-8 + if(delta > 7) { + delta = 7; + } + if(delta < -8) { + delta = -8; + } + CALDBG( + stSerialPrintf(ST_ASSERT_SERIAL_PORT, "TUNE steps delta: %d\r\n", + delta); + ) + CLKRC_TUNE = delta; + //wait for PERIOD to update before taking another sample + halCommonDelayMicroseconds(SLOWRC_PERIOD_SETTLE_TIME); + CALDBG( + stSerialPrintf(ST_ASSERT_SERIAL_PORT, + "period: %u, ", CLK_PERIOD); + stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u Hz\r\n", + ((int16u)(((int32u)192000000)/((int32u)CLK_PERIOD)))); + ) + //The analog section should now be producing an output of ~10kHz + + ////---- STEP 2: fine tune the SlowRC to 1024Hz ----//// + //Our goal is to generate a 1024Hz source. The register CLK1K_CAL is a + //fractional divider that divides the 10kHz analog source and generates + //the clk1k output. At reset, the default value is 0x5000 which yields a + //division of 10.000. By averaging several samples of CLK_PERIOD, we + //can then calculate the proper divisor need for CLK1K_CAL to make 1024Hz. + for(i=0;i=256) { + break; + } + } + CALDBG( + //Measure the current CLK_PERIOD to show the final result + stSerialPrintf(ST_ASSERT_SERIAL_PORT, + "period: %u, ", CLK_PERIOD); + stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u kHz\r\n", + ((int16u)((((int32u)3072000000)/((int32u)CLK_PERIOD))/1000))); + ) + + //The analog section should now be producing an output of 11.5MHz - 12.0MHz +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#define OSC24M_BIASTRIM_OFFSET (0x2) +#define OSC24M_BIASTRIM_MIN (0+OSC24M_BIASTRIM_OFFSET) +#define OSC24M_BIASTRIM_MAX OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK +#define OSC24M_BIASTRIM_MSB (1 << (OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS-1)) +#define OSC24M_BIASTRIM_UNINIT (0xFFFF) +tokTypeMfgOsc24mBiasTrim biasTrim=OSC24M_BIASTRIM_UNINIT; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//This function is intended to be called periodically, from the stack and +//application, to check the XTAL bias trim is within appropriate levels +//and adjust if not. This function is *not* designed to be used before +//halInternalSwitchToXtal has been called. +void halCommonCheckXtalBiasTrim(void) +{ + //HI is set indicating the trim value is too high. Decrement the trim. + if((OSC24M_COMP & OSC24M_HI) == OSC24M_HI) { + biasTrim--; + } + + //LO is cleared indicating the trim value is too low. Inrement the trim. + if((OSC24M_COMP & OSC24M_LO) != OSC24M_LO) { + biasTrim++; + //Add an offset to the bias trim as a factor of safety. + if(biasTrim < (OSC24M_BIASTRIM_MAX - OSC24M_BIASTRIM_OFFSET)) { + biasTrim += OSC24M_BIASTRIM_OFFSET; + } else { + biasTrim = OSC24M_BIASTRIM_MAX; + } + } + + //Don't allow bias trim to dip below the offset regardless of LO. + if(biasTrim>= 1; + biasTrim += bit; + //Set trim and wait for 1.5ms to allow the oscillator to stabilize. + if(setBiasCheckLow()) { + biasTrim -= bit; + } + } while(bit); + + //If the last bias value went too low, increment it. + if((OSC24M_COMP & OSC24M_LO) != OSC24M_LO) { + biasTrim++; + } + + //Add an offset to the bias trim as a factor of safety. + if(biasTrim < (OSC24M_BIASTRIM_MAX - OSC24M_BIASTRIM_OFFSET)) { + biasTrim += OSC24M_BIASTRIM_OFFSET; + } else { + biasTrim = OSC24M_BIASTRIM_MAX; + } + + //Using the shadow variable, the clock switch logic will take over from here, + //enabling, verifying, and tweaking as needed. +} + + +//This function configures the flash access controller for optimal +//current consumption when FCLK is operating at 24MHz. By providing +//this function the calling code does not have to be aware of the +//details of setting FLASH_ACCESS. +static void halInternalConfigXtal24MhzFlashAccess(void) +{ + ATOMIC( + BYPASS_MPU( + #if defined(CORTEXM3_STM32W108) + FLASH_ACCESS = (FLASH_ACCESS_PREFETCH_EN | + (1<OSC24M_BIASTRIM_MIN) { + biasTrim--; + setTrimOneLastTime = TRUE; + } + } + + //Kickout when HI=0 and LO=1 or we've hit the MAX or the MIN + } while( (hiSet || !loSet) && + (biasTrimOSC24M_BIASTRIM_MIN) ); + + //The LO bit being cleared means we've corrected up from the bottom and + //therefore need to apply the offset. Additionally, if our trim value + //is below the offset, we still need to apply the offset. And, when + //applying the offset respect the max possible value of the trim. + if(!loSet || (biasTrim= 5000000 + + // IAR V5 Definitions. + RSEG RESETINFO:DATA + RSEG CSTACK:DATA + #define __CODE__ SECTION .text:CODE:REORDER:NOROOT(2) + #define __BSS__ SECTION .bss:DATA:NOROOT(2) + #define __BEGIN_RESETINFO__(offset) SFB(RESETINFO + offset) + #define __END_RESETINFO__(offset) SFE(RESETINFO + offset) + #define __BEGIN_STACK__(offset) SFB(CSTACK + offset) + #define __END_STACK__(offset) SFE(CSTACK + offset) + #define __CFI__(x) + + #else // __VER__ + + #error IAR versions less that 5.xx are not supported + + #endif // __VER__ + +#endif // __IAR_SYSTEMS_ASM__ + +#ifdef __GNUC__ + + // GCC Definitions. + .syntax unified + .thumb + #define __CODE__ .text + #define __THUMB__ .thumb_func + #define __BSS__ .bss + #define __END__ .end + #define __EXPORT__ .global + #define __IMPORT__ .extern + #define __SPACE__ .space + #define __EQU__(a, b) .equ a, b + #define __WEAK__ .weak + #define __BEGIN_NVDATA__(offset) (_noinit + offset) + #define __BEGIN_STACK__(offset) (_stack + offset) + #define __END_STACK__(offset) (_estack + offset) + #define __CFI__(x) + +#endif // __GNUC__ + +#endif // __ASM_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h b/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h new file mode 100644 index 000000000..3030fdeba --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h @@ -0,0 +1,521 @@ +/** @file hal/micro/cortexm3/compiler/gnu.h + * See @ref gnu for detailed documentation. + * + */ + +/** @addtogroup gnu + * @brief Compiler and Platform specific definitions and typedefs for the + * GNU C ARM compiler. + * + * @note gnu.h should be included first in all source files by setting the + * preprocessor macro PLATFORM_HEADER to point to it. gnu.h automatically + * includes platform-common.h. + * + * See gnu.h and platform-common.h for source code. + *@{ + */ + +#ifndef __GNU_H__ +#define __GNU_H__ + +#ifndef __GNUC__ + #error Improper PLATFORM_HEADER +#endif + +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) + +#if GCC_VERSION < 40302 +#error Only GNU C version later than 4.3.2 are supported +#endif + + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +//#include + #include + #if defined (CORTEXM3_STM32W108) + #include "micro/cortexm3/stm32w108/regs.h" + #else + #error Unknown CORTEXM3 micro + #endif + //Provide a default NVIC configuration file. The build process can + //override this if it needs to. + #ifndef NVIC_CONFIG + #define NVIC_CONFIG "hal/micro/cortexm3/nvic-config.h" + #endif +//[[ +#ifdef EMU_TEST + #ifdef I_AM_AN_EMULATOR + // This register is defined for both the chip and the emulator with + // with distinct reset values. Need to undefine to avoid preprocessor + // collision. + #undef DATA_EMU_REGS_BASE + #undef DATA_EMU_REGS_END + #undef DATA_EMU_REGS_SIZE + #undef I_AM_AN_EMULATOR + #undef I_AM_AN_EMULATOR_REG + #undef I_AM_AN_EMULATOR_ADDR + #undef I_AM_AN_EMULATOR_RESET + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS + #endif//I_AM_AN_EMULATOR + #error MICRO currently not supported for emulator builds. +#endif//EMU_TEST +//]] + +// suppress warnings about unknown pragmas +// (as they may be pragmas known to other platforms) +//#pragma diag_suppress = pe161 + +#endif // DOXYGEN_SHOULD_SKIP_THIS + +// Define that the minimal hal is being used. +#define MINIMAL_HAL + + +/** \name Master Variable Types + * These are a set of typedefs to make the size of all variable declarations + * explicitly known. + */ +//@{ +/** + * @brief A typedef to make the size of the variable explicitly known. + */ +typedef unsigned char boolean; +typedef unsigned char int8u; +typedef signed char int8s; +typedef unsigned short int16u; +typedef signed short int16s; +typedef unsigned int int32u; +typedef signed int int32s; +typedef unsigned int PointerType; +//@} \\END MASTER VARIABLE TYPES + +/** + * @brief Use the Master Program Memory Declarations from platform-common.h + */ +#define _HAL_USE_COMMON_PGM_ + + + +//////////////////////////////////////////////////////////////////////////////// +/** \name Miscellaneous Macros + */ +//////////////////////////////////////////////////////////////////////////////// +//@{ + +/** + * @brief A convenient method for code to know what endiannes processor + * it is running on. For the Cortex-M3, we are little endian. + */ +#define BIGENDIAN_CPU FALSE + + +/** + * @brief A friendlier name for the compiler's intrinsic for not + * stripping. + */ +#define NO_STRIPPING /* __root ??? */ +#define __no_init /*__attribute__((section (".noinit")))*/ + +/** + * @brief A friendlier name for the compiler's intrinsic for eeprom + * reference. + */ +#define EEPROM errorerror + + +#ifndef __SOURCEFILE__ + /** + * @brief The __SOURCEFILE__ macro is used by asserts to list the + * filename if it isn't otherwise defined, set it to the compiler intrinsic + * which specifies the whole filename and path of the sourcefile + */ + #define __SOURCEFILE__ __FILE__ +#endif + + +//#include +#undef assert +#define assert(condition) do { if (! (condition)) {while (1); }} while(0) +#if 0 + do { if (! (condition)) { \ + printf ("Assert failed %s %d\r\n",__SOURCEFILE__, __LINE__); }} while(0) +#endif + +#ifndef BOOTLOADER + #undef __delay_cycles + /** + * @brief __delay_cycles() is an intrinsic IAR call; however, we + * have explicity disallowed it since it is too specific to the system clock. + * \note Please use halCommonDelayMicroseconds() instead, because it correctly + * accounts for various system clock speeds. + */ + #define __delay_cycles(x) please_use_halCommonDelayMicroseconds_instead_of_delay_cycles +#endif + +/** + * @brief Set debug level based on whether or DEBUG is defined. + * basic debugging support is included if DEBUG is not defined. + */ +#ifndef DEBUG_LEVEL + #ifdef DEBUG + #define DEBUG_LEVEL FULL_DEBUG + #else + #define DEBUG_LEVEL BASIC_DEBUG + #endif +#endif + +/** + * @brief Macro to reset the watchdog timer. Note: be very very + * careful when using this as you can easily get into an infinite loop if you + * are not careful. + */ +void halInternalResetWatchDog(void); +#define halResetWatchdog() halInternalResetWatchDog() + + +/** + * @brief Define __attribute__ to nothing since it isn't handled by IAR. + */ + + +/** + * @brief Declare a variable as unused to avoid a warning. Has no effect + * in IAR builds + */ +#define UNUSED + +/** + * @brief Some platforms need to cast enum values that have the high bit set. + */ +#define SIGNED_ENUM + + +/** + * @brief Define the magic value that is interpreted by IAR C-SPY's Stack View. + */ +#define STACK_FILL_VALUE 0xCDCDCDCD + +/** + * @brief Define a generic RAM function identifier to a compiler specific one. + */ +#ifdef RAMEXE + //If the whole build is running out of RAM, as chosen by the RAMEXE build + //define, then define RAMFUNC to nothing since it's not needed. + #define RAMFUNC +#else //RAMEXE + #define RAMFUNC __ramfunc +#endif //RAMEXE + +/** + * @brief Define a generic no operation identifier to a compiler specific one. + */ +#define NO_OPERATION() __no_operation() + +/** + * @brief A convenience macro that makes it easy to change the field of a + * register to any value. + */ +#define SET_REG_FIELD(reg, field, value) \ + do{ \ + reg = ((reg & (~field##_MASK)) | (value << field##_BIT)); \ + }while(0) + +/** + * @brief Stub for code not running in simulation. + */ +#define simulatedTimePasses() +/** + * @brief Stub for code not running in simulation. + */ +#define simulatedTimePassesMs(x) +/** + * @brief Stub for code not running in simulation. + */ +#define simulatedSerialTimePasses() + + +/** + * @brief Use the Divide and Modulus Operations from platform-common.h + */ +#define _HAL_USE_COMMON_DIVMOD_ + + +/** + * @brief Provide a portable way to specify the segment where a variable + * lives. + */ +#define VAR_AT_SEGMENT(__variableDeclaration, __segmentName) \ + __variableDeclaration __attribute__ ((section (__segmentName))) + +//////////////////////////////////////////////////////////////////////////////// +//@} // end of Miscellaneous Macros +//////////////////////////////////////////////////////////////////////////////// + +/** @name Portable segment names + *@{ + */ +/** + * @brief Portable segment names + */ +#define __NO_INIT__ ".noinit" +#define __INTVEC__ ".intvec" +#define __CSTACK__ "CSTACK" +#define __DATA_INIT__ ".data_init" +#define __DATA__ ".data" +#define __BSS__ ".bss" +#define __CONST__ ".rodata" +#define __TEXT__ ".text" +#define __TEXTRW_INIT__ ".textrw_init" +#define __TEXTRW__ ".textrw" +#define __FAT__ "FAT" // Fixed address table +#define __NVM__ "NVM" //Non-Volatile Memory data storage + +//============================================================================= +// The '#pragma segment=' declaration must be used before attempting to access +// the segments so the compiler properly handles the __segment_*() functions. +// +// The segment names used here are the default segment names used by IAR. Refer +// to the IAR Compiler Reference Guide for a proper description of these +// segments. +//============================================================================= +#if 0 +#pragma segment=__NO_INIT__ +#pragma segment=__INTVEC__ +#pragma segment=__CSTACK__ +#pragma segment=__DATA_INIT__ +#pragma segment=__DATA__ +#pragma segment=__BSS__ +#pragma segment=__CONST__ +#pragma segment=__TEXT__ +#pragma segment=__TEXTRW_INIT__ +#pragma segment=__TEXTRW__ +#pragma segment=__FAT__ +#pragma segment=__NVM__ +#endif +/**@} */ + +//A utility function for inserting barrier instructions. These +//instructions should be used whenever the MPU is enabled or disabled so +//that all memory/instruction accesses can complete before the MPU changes +//state. +void _executeBarrierInstructions(void); + +//////////////////////////////////////////////////////////////////////////////// +/** \name Global Interrupt Manipulation Macros + * + * \b Note: The special purpose BASEPRI register is used to enable and disable + * interrupts while permitting faults. + * When BASEPRI is set to 1 no interrupts can trigger. The configurable faults + * (usage, memory management, and bus faults) can trigger if enabled as well as + * the always-enabled exceptions (reset, NMI and hard fault). + * When BASEPRI is set to 0, it is disabled, so any interrupt can triggger if + * its priority is higher than the current priority. + */ +//////////////////////////////////////////////////////////////////////////////// +//@{ + +#define ATOMIC_LITE(blah) ATOMIC(blah) +#define DECLARE_INTERRUPT_STATE_LITE DECLARE_INTERRUPT_STATE +#define DISABLE_INTERRUPTS_LITE() DISABLE_INTERRUPTS() +#define RESTORE_INTERRUPTS_LITE() RESTORE_INTERRUPTS() + +#ifdef BOOTLOADER + #ifndef DOXYGEN_SHOULD_SKIP_THIS + // The bootloader does not use interrupts + #define DECLARE_INTERRUPT_STATE + #define DISABLE_INTERRUPTS() do { } while(0) + #define RESTORE_INTERRUPTS() do { } while(0) + #define INTERRUPTS_ON() do { } while(0) + #define INTERRUPTS_OFF() do { } while(0) + #define INTERRUPTS_ARE_OFF() (FALSE) + #define ATOMIC(blah) { blah } + #define HANDLE_PENDING_INTERRUPTS() do { } while(0) + #define SET_BASE_PRIORITY_LEVEL(basepri) do { } while(0) + #endif // DOXYGEN_SHOULD_SKIP_THIS +#else // BOOTLOADER + + #ifndef DOXYGEN_SHOULD_SKIP_THIS + /** + * @brief This macro should be called in the local variable + * declarations section of any function which calls DISABLE_INTERRUPTS() + * or RESTORE_INTERRUPTS(). + */ + #define DECLARE_INTERRUPT_STATE int8u _emIsrState + + // Prototypes for the BASEPRI and PRIMASK access functions. They are very + // basic and instantiated in assembly code in the file spmr.s37 (since + // there are no C functions that cause the compiler to emit code to access + // the BASEPRI/PRIMASK). This will inhibit the core from taking interrupts + // with a priority equal to or less than the BASEPRI value. + // Note that the priority values used by these functions are 5 bits and + // right-aligned + extern int8u _readBasePri(void); + extern void _writeBasePri(int8u priority); + + // Prototypes for BASEPRI functions used to disable and enable interrupts + // while still allowing enabled faults to trigger. + extern void _enableBasePri(void); + extern int8u _disableBasePri(void); + extern boolean _basePriIsDisabled(void); + + // Prototypes for setting and clearing PRIMASK for global interrupt + // enable/disable. + extern void _setPriMask(void); + extern void _clearPriMask(void); + #endif // DOXYGEN_SHOULD_SKIP_THIS + + //The core Global Interrupt Manipulation Macros start here. + + /** + * @brief Disable interrupts, saving the previous state so it can be + * later restored with RESTORE_INTERRUPTS(). + * \note Do not fail to call RESTORE_INTERRUPTS(). + * \note It is safe to nest this call. + */ + #define DISABLE_INTERRUPTS() \ + do { \ + _emIsrState = _disableBasePri(); \ + } while(0) + + + /** + * @brief Restore the global interrupt state previously saved by + * DISABLE_INTERRUPTS() + * \note Do not call without having first called DISABLE_INTERRUPTS() + * to have saved the state. + * \note It is safe to nest this call. + */ + #define RESTORE_INTERRUPTS() \ + do { \ + _writeBasePri(_emIsrState); \ + } while(0) + + + /** + * @brief Enable global interrupts without regard to the current or + * previous state. + */ + #define INTERRUPTS_ON() \ + do { \ + _enableBasePri(); \ + } while(0) + + + /** + * @brief Disable global interrupts without regard to the current or + * previous state. + */ + #define INTERRUPTS_OFF() \ + do { \ + (void)_disableBasePri(); \ + } while(0) + + + /** + * @returns TRUE if global interrupts are disabled. + */ + #define INTERRUPTS_ARE_OFF() ( _basePriIsDisabled() ) + + /** + * @returns TRUE if global interrupt flag was enabled when + * ::DISABLE_INTERRUPTS() was called. + */ + #define INTERRUPTS_WERE_ON() (_emIsrState == 0) + + /** + * @brief A block of code may be made atomic by wrapping it with this + * macro. Something which is atomic cannot be interrupted by interrupts. + */ + #define ATOMIC(blah) \ + { \ + DECLARE_INTERRUPT_STATE; \ + DISABLE_INTERRUPTS(); \ + { blah } \ + RESTORE_INTERRUPTS(); \ + } + + + /** + * @brief Allows any pending interrupts to be executed. Usually this + * would be called at a safe point while interrupts are disabled (such as + * within an ISR). + * + * Takes no action if interrupts are already enabled. + */ + #define HANDLE_PENDING_INTERRUPTS() \ + do { \ + if (INTERRUPTS_ARE_OFF()) { \ + INTERRUPTS_ON(); \ + INTERRUPTS_OFF(); \ + } \ + } while (0) + + + /** + * @brief Sets the base priority mask (BASEPRI) to the value passed, + * bit shifted up by PRIGROUP_POSITION+1. This will inhibit the core from + * taking all interrupts with a preemptive priority equal to or less than + * the BASEPRI mask. This macro is dependent on the value of + * PRIGROUP_POSITION in nvic-config.h. Note that the value 0 disables the + * the base priority mask. + * + * Refer to the "PRIGROUP" table in nvic-config.h to know the valid values + * for this macro depending on the value of PRIGROUP_POSITION. With respect + * to the table, this macro can only take the preemptive priority group + * numbers denoted by the parenthesis. + */ + #define SET_BASE_PRIORITY_LEVEL(basepri) \ + do { \ + _writeBasePri(basepri); \ + } while(0) + +#endif // BOOTLOADER +//////////////////////////////////////////////////////////////////////////////// +//@} // end of Global Interrupt Manipulation Macros +//////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Use the C Standard Library Memory Utilities from platform-common.h + */ +#define _HAL_USE_COMMON_MEMUTILS_ + +//////////////////////////////////////////////////////////////////////////////// +/** \name External Declarations + * These are routines that are defined in certain header files that we don't + * want to include, e.g. stdlib.h + */ +//////////////////////////////////////////////////////////////////////////////// +//@{ + +/** + * @brief Returns the absolute value of I (also called the magnitude of I). + * That is, if I is negative, the result is the opposite of I, but if I is + * nonnegative the result is I. + * + * @param I An integer. + * + * @return A nonnegative integer. + */ +int abs(int I); + +//////////////////////////////////////////////////////////////////////////////// +//@} // end of External Declarations +//////////////////////////////////////////////////////////////////////////////// + + +/** + * @brief Include platform-common.h last to pick up defaults and common definitions. + */ +#define PLATCOMMONOKTOINCLUDE + #include "hal/micro/generic/compiler/platform-common.h" +#undef PLATCOMMONOKTOINCLUDE + +#endif // __GNU_H__ + +/** @} END addtogroup */ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h b/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h new file mode 100644 index 000000000..796188544 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h @@ -0,0 +1,516 @@ +/** @file hal/micro/cortexm3/compiler/iar.h + * @brief iar for detailed documentation. + * + * + */ + +/** @addtogroup iar + * @brief Compiler and Platform specific definitions and typedefs for the + * IAR ARM C compiler. + * + * @note iar.h should be included first in all source files by setting the + * preprocessor macro PLATFORM_HEADER to point to it. iar.h automatically + * includes platform-common.h. + * + * See iar.h and platform-common.h for source code. + *@{ + */ + +#ifndef __IAR_H__ +#define __IAR_H__ + +#ifndef __ICCARM__ + #error Improper PLATFORM_HEADER +#endif + +#if (__VER__ < 5040005) + #error Only IAR EWARM versions later than 5.40.5 are supported +#endif // __VER__ + + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + #include + #include + #if defined (CORTEXM3_STM32W108) + #include "micro/cortexm3/stm32w108/regs.h" + #else + #error Unknown CORTEXM3 micro + #endif + //Provide a default NVIC configuration file. The build process can + //override this if it needs to. + #ifndef NVIC_CONFIG + #define NVIC_CONFIG "hal/micro/cortexm3/nvic-config.h" + #endif +//[[ +#ifdef ST_EMU_TEST + #ifdef I_AM_AN_EMULATOR + // This register is defined for both the chip and the emulator with + // with distinct reset values. Need to undefine to avoid preprocessor + // collision. + #undef DATA_EMU_REGS_BASE + #undef DATA_EMU_REGS_END + #undef DATA_EMU_REGS_SIZE + #undef I_AM_AN_EMULATOR + #undef I_AM_AN_EMULATOR_REG + #undef I_AM_AN_EMULATOR_ADDR + #undef I_AM_AN_EMULATOR_RESET + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT + #undef I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS + #endif//I_AM_AN_EMULATOR + + #error MICRO currently not supported for emulator builds. + +#endif//ST_EMU_TEST +//]] + +// suppress warnings about unknown pragmas +// (as they may be pragmas known to other platforms) +#pragma diag_suppress = pe161 + +#endif // DOXYGEN_SHOULD_SKIP_THIS + +// Define that the minimal hal is being used. +#define MINIMAL_HAL + + +/** \name Master Variable Types + * These are a set of typedefs to make the size of all variable declarations + * explicitly known. + */ +//@{ +/** + * @brief A typedef to make the size of the variable explicitly known. + */ +typedef unsigned char boolean; +typedef unsigned char int8u; +typedef signed char int8s; +typedef unsigned short int16u; +typedef signed short int16s; +typedef unsigned int int32u; +typedef signed int int32s; +typedef unsigned int PointerType; +//@} \\END MASTER VARIABLE TYPES + +/** + * @brief Use the Master Program Memory Declarations from platform-common.h + */ +#define _HAL_USE_COMMON_PGM_ + + + +//////////////////////////////////////////////////////////////////////////////// +/** \name Miscellaneous Macros + */ +//////////////////////////////////////////////////////////////////////////////// +//@{ + +/** + * @brief A convenient method for code to know what endiannes processor + * it is running on. For the Cortex-M3, we are little endian. + */ +#define BIGENDIAN_CPU FALSE + + +/** + * @brief A friendlier name for the compiler's intrinsic for not + * stripping. + */ +#define NO_STRIPPING __root + + +/** + * @brief A friendlier name for the compiler's intrinsic for eeprom + * reference. + */ +#define EEPROM errorerror + + +#ifndef __SOURCEFILE__ + /** + * @brief The __SOURCEFILE__ macro is used by asserts to list the + * filename if it isn't otherwise defined, set it to the compiler intrinsic + * which specifies the whole filename and path of the sourcefile + */ + #define __SOURCEFILE__ __FILE__ +#endif + + +#include + + +#ifndef BOOTLOADER + #undef __delay_cycles + /** + * @brief __delay_cycles() is an intrinsic IAR call; however, we + * have explicity disallowed it since it is too specific to the system clock. + * \note Please use halCommonDelayMicroseconds() instead, because it correctly + * accounts for various system clock speeds. + */ + #define __delay_cycles(x) please_use_halCommonDelayMicroseconds_instead_of_delay_cycles +#endif + +/** + * @brief Set debug level based on whether or DEBUG is defined. + * For the STM32W108xx, basic debugging support is included if DEBUG is not defined. + */ +#ifndef DEBUG_LEVEL + #ifdef DEBUG + #define DEBUG_LEVEL FULL_DEBUG + #else + #define DEBUG_LEVEL BASIC_DEBUG + #endif +#endif + +/** + * @brief Macro to reset the watchdog timer. Note: be very very + * careful when using this as you can easily get into an infinite loop if you + * are not careful. + */ +void halInternalResetWatchDog(void); +#define halResetWatchdog() halInternalResetWatchDog() + + +/** + * @brief Define __attribute__ to nothing since it isn't handled by IAR. + */ +#define __attribute__(nothing) + + +/** + * @brief Declare a variable as unused to avoid a warning. Has no effect + * in IAR builds + */ +#define UNUSED + +/** + * @brief Some platforms need to cast enum values that have the high bit set. + */ +#define SIGNED_ENUM + + +/** + * @brief Define the magic value that is interpreted by IAR C-SPY's Stack View. + */ +#define STACK_FILL_VALUE 0xCDCDCDCD + +/** + * @brief Define a generic RAM function identifier to a compiler specific one. + */ +#ifdef RAMEXE + //If the whole build is running out of RAM, as chosen by the RAMEXE build + //define, then define RAMFUNC to nothing since it's not needed. + #define RAMFUNC +#else //RAMEXE + #define RAMFUNC __ramfunc +#endif //RAMEXE + +/** + * @brief Define a generic no operation identifier to a compiler specific one. + */ +#define NO_OPERATION() __no_operation() + +/** + * @brief A convenience macro that makes it easy to change the field of a + * register to any value. + */ +#define SET_REG_FIELD(reg, field, value) \ + do{ \ + reg = ((reg & (~field##_MASK)) | (value << field##_BIT)); \ + }while(0) + +/** + * @brief Stub for code not running in simulation. + */ +#define simulatedTimePasses() +/** + * @brief Stub for code not running in simulation. + */ +#define simulatedTimePassesMs(x) +/** + * @brief Stub for code not running in simulation. + */ +#define simulatedSerialTimePasses() + + +/** + * @brief Use the Divide and Modulus Operations from platform-common.h + */ +#define _HAL_USE_COMMON_DIVMOD_ + + +/** + * @brief Provide a portable way to specify the segment where a variable + * lives. + */ +#define VAR_AT_SEGMENT(__variableDeclaration, __segmentName) \ + __variableDeclaration @ __segmentName + +//////////////////////////////////////////////////////////////////////////////// +//@} // end of Miscellaneous Macros +//////////////////////////////////////////////////////////////////////////////// + +/** @name Portable segment names + *@{ + */ +/** + * @brief Portable segment names + */ +#define __NO_INIT__ ".noinit" +#define __INTVEC__ ".intvec" +#define __CSTACK__ "CSTACK" +#define __DATA_INIT__ ".data_init" +#define __DATA__ ".data" +#define __BSS__ ".bss" +#define __CONST__ ".rodata" +#define __TEXT__ ".text" +#define __TEXTRW_INIT__ ".textrw_init" +#define __TEXTRW__ ".textrw" +#define __FAT__ "FAT" // Fixed address table +#define __NVM__ "NVM" //Non-Volatile Memory data storage + +//============================================================================= +// The '#pragma segment=' declaration must be used before attempting to access +// the segments so the compiler properly handles the __segment_*() functions. +// +// The segment names used here are the default segment names used by IAR. Refer +// to the IAR Compiler Reference Guide for a proper description of these +// segments. +//============================================================================= +#pragma segment=__NO_INIT__ +#pragma segment=__INTVEC__ +#pragma segment=__CSTACK__ +#pragma segment=__DATA_INIT__ +#pragma segment=__DATA__ +#pragma segment=__BSS__ +#pragma segment=__CONST__ +#pragma segment=__TEXT__ +#pragma segment=__TEXTRW_INIT__ +#pragma segment=__TEXTRW__ +#pragma segment=__FAT__ +#pragma segment=__NVM__ +/**@} */ + +//A utility function for inserting barrier instructions. These +//instructions should be used whenever the MPU is enabled or disabled so +//that all memory/instruction accesses can complete before the MPU changes +//state. +void _executeBarrierInstructions(void); +// MPU is unused with this platform header variant +#define _HAL_MPU_UNUSED_ + +//////////////////////////////////////////////////////////////////////////////// +/** \name Global Interrupt Manipulation Macros + * + * \b Note: The special purpose BASEPRI register is used to enable and disable + * interrupts while permitting faults. + * When BASEPRI is set to 1 no interrupts can trigger. The configurable faults + * (usage, memory management, and bus faults) can trigger if enabled as well as + * the always-enabled exceptions (reset, NMI and hard fault). + * When BASEPRI is set to 0, it is disabled, so any interrupt can triggger if + * its priority is higher than the current priority. + */ +//////////////////////////////////////////////////////////////////////////////// +//@{ + +#define ATOMIC_LITE(blah) ATOMIC(blah) +#define DECLARE_INTERRUPT_STATE_LITE DECLARE_INTERRUPT_STATE +#define DISABLE_INTERRUPTS_LITE() DISABLE_INTERRUPTS() +#define RESTORE_INTERRUPTS_LITE() RESTORE_INTERRUPTS() + +#ifdef BOOTLOADER + #ifndef DOXYGEN_SHOULD_SKIP_THIS + // The bootloader does not use interrupts + #define DECLARE_INTERRUPT_STATE + #define DISABLE_INTERRUPTS() do { } while(0) + #define RESTORE_INTERRUPTS() do { } while(0) + #define INTERRUPTS_ON() do { } while(0) + #define INTERRUPTS_OFF() do { } while(0) + #define INTERRUPTS_ARE_OFF() (FALSE) + #define ATOMIC(blah) { blah } + #define HANDLE_PENDING_INTERRUPTS() do { } while(0) + #define SET_BASE_PRIORITY_LEVEL(basepri) do { } while(0) + #endif // DOXYGEN_SHOULD_SKIP_THIS +#else // BOOTLOADER + + #ifndef DOXYGEN_SHOULD_SKIP_THIS + /** + * @brief This macro should be called in the local variable + * declarations section of any function which calls DISABLE_INTERRUPTS() + * or RESTORE_INTERRUPTS(). + */ + #define DECLARE_INTERRUPT_STATE int8u _emIsrState + + // Prototypes for the BASEPRI and PRIMASK access functions. They are very + // basic and instantiated in assembly code in the file spmr.s37 (since + // there are no C functions that cause the compiler to emit code to access + // the BASEPRI/PRIMASK). This will inhibit the core from taking interrupts + // with a priority equal to or less than the BASEPRI value. + // Note that the priority values used by these functions are 5 bits and + // right-aligned + extern int8u _readBasePri(void); + extern void _writeBasePri(int8u priority); + + // Prototypes for BASEPRI functions used to disable and enable interrupts + // while still allowing enabled faults to trigger. + extern void _enableBasePri(void); + extern int8u _disableBasePri(void); + extern boolean _basePriIsDisabled(void); + + // Prototypes for setting and clearing PRIMASK for global interrupt + // enable/disable. + extern void _setPriMask(void); + extern void _clearPriMask(void); + #endif // DOXYGEN_SHOULD_SKIP_THIS + + //The core Global Interrupt Manipulation Macros start here. + + /** + * @brief Disable interrupts, saving the previous state so it can be + * later restored with RESTORE_INTERRUPTS(). + * \note Do not fail to call RESTORE_INTERRUPTS(). + * \note It is safe to nest this call. + */ + #define DISABLE_INTERRUPTS() \ + do { \ + _emIsrState = _disableBasePri(); \ + } while(0) + + + /** + * @brief Restore the global interrupt state previously saved by + * DISABLE_INTERRUPTS() + * \note Do not call without having first called DISABLE_INTERRUPTS() + * to have saved the state. + * \note It is safe to nest this call. + */ + #define RESTORE_INTERRUPTS() \ + do { \ + _writeBasePri(_emIsrState); \ + } while(0) + + + /** + * @brief Enable global interrupts without regard to the current or + * previous state. + */ + #define INTERRUPTS_ON() \ + do { \ + _enableBasePri(); \ + } while(0) + + + /** + * @brief Disable global interrupts without regard to the current or + * previous state. + */ + #define INTERRUPTS_OFF() \ + do { \ + (void)_disableBasePri(); \ + } while(0) + + + /** + * @returns TRUE if global interrupts are disabled. + */ + #define INTERRUPTS_ARE_OFF() ( _basePriIsDisabled() ) + + /** + * @returns TRUE if global interrupt flag was enabled when + * ::DISABLE_INTERRUPTS() was called. + */ + #define INTERRUPTS_WERE_ON() (_emIsrState == 0) + + /** + * @brief A block of code may be made atomic by wrapping it with this + * macro. Something which is atomic cannot be interrupted by interrupts. + */ + #define ATOMIC(blah) \ + { \ + DECLARE_INTERRUPT_STATE; \ + DISABLE_INTERRUPTS(); \ + { blah } \ + RESTORE_INTERRUPTS(); \ + } + + + /** + * @brief Allows any pending interrupts to be executed. Usually this + * would be called at a safe point while interrupts are disabled (such as + * within an ISR). + * + * Takes no action if interrupts are already enabled. + */ + #define HANDLE_PENDING_INTERRUPTS() \ + do { \ + if (INTERRUPTS_ARE_OFF()) { \ + INTERRUPTS_ON(); \ + INTERRUPTS_OFF(); \ + } \ + } while (0) + + + /** + * @brief Sets the base priority mask (BASEPRI) to the value passed, + * bit shifted up by PRIGROUP_POSITION+1. This will inhibit the core from + * taking all interrupts with a preemptive priority equal to or less than + * the BASEPRI mask. This macro is dependent on the value of + * PRIGROUP_POSITION in nvic-config.h. Note that the value 0 disables the + * the base priority mask. + * + * Refer to the "PRIGROUP" table in nvic-config.h to know the valid values + * for this macro depending on the value of PRIGROUP_POSITION. With respect + * to the table, this macro can only take the preemptive priority group + * numbers denoted by the parenthesis. + */ + #define SET_BASE_PRIORITY_LEVEL(basepri) \ + do { \ + _writeBasePri(basepri); \ + } while(0) + +#endif // BOOTLOADER +//////////////////////////////////////////////////////////////////////////////// +//@} // end of Global Interrupt Manipulation Macros +//////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Use the C Standard Library Memory Utilities from platform-common.h + */ +#define _HAL_USE_COMMON_MEMUTILS_ + +//////////////////////////////////////////////////////////////////////////////// +/** \name External Declarations + * These are routines that are defined in certain header files that we don't + * want to include, e.g. stdlib.h + */ +//////////////////////////////////////////////////////////////////////////////// +//@{ + +/** + * @brief Returns the absolute value of I (also called the magnitude of I). + * That is, if I is negative, the result is the opposite of I, but if I is + * nonnegative the result is I. + * + * @param I An integer. + * + * @return A nonnegative integer. + */ +int abs(int I); + +//////////////////////////////////////////////////////////////////////////////// +//@} // end of External Declarations +//////////////////////////////////////////////////////////////////////////////// + + +/** + * @brief Include platform-common.h last to pick up defaults and common definitions. + */ +#define PLATCOMMONOKTOINCLUDE + #include "hal/micro/generic/compiler/platform-common.h" +#undef PLATCOMMONOKTOINCLUDE + +#endif // __IAR_H__ + +/** @} END addtogroup */ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 b/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 new file mode 100644 index 000000000..1fea855e4 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 @@ -0,0 +1,158 @@ +//------------------------------------------------------------------------------ +// @file hal/micro/cortexm3/context-switch.s79 +// @brief Context save/restore for deep sleep using the PendSV exception. +// +// This file also contains a simple halInternalIdleSleep() function that +// executes just the WFI instruction for idle sleeping. +// +// When the STM32W108XX enters deep sleep, the hardware will actually remove power +// from the Cortex-M3 core (in Deep Sleep 0, power is not removed but the core +// is held in reset). Since this will clear the internal state of the core, it +// must be properly restored such that execution can resume from the sleep code. +// The simplest and most secure mechanism to do this is to perform a context save +// and restore. Context save/restore is almost identical to a context switch +// used in multi-threaded systems with the main difference being only one stack +// pointer is used and the save/restore operations are disjoint. +// +// When an interrupt is triggered in the STM32W108XX, the core automatically saves 8 +// of the 16 CPU registers on the stack. The ISR then only needs to save the +// other 8 registers and store the resulting stack pointer. Restoring is the +// reverse operation where 8 registers are manually copied back with the other 8 +// being restored on the return from interrupt. +// +// As its last act, the deep sleep code will trigger the PendSV exception to +// perform a context save. When the core is booted upon deep sleep exit, the +// RESET_EVENT register informs cstartup if the chip just exited deep sleep. +// Cstartup will then trigger halTriggerContextRestore which sets up the stack +// pointer and trigger the PendSV exception to perform a restore. When PendSV +// returns from interrupt context the system will be back at the same point it +// was before deep sleep. +// +// +// +//------------------------------------------------------------------------------ + +#include "compiler/asm.h" + +//------------------------------------------------------------------------------ +// boolean halPendSvSaveContext +// +// A simple boolean flag used to indicate if a context save or a context restore +// should be performed. Since context switching is handled with the PendSV +// interrupt, parameters cannot be passed into the ISR and as such this boolean +// flag is used. If this flag is zero, PendSV should perform a context restore. +// If this flag is non-zero, PendSV should perform a context save. +// Note: The smallest unit of storage is a single byte. +// +// NOTE: This flag must be set before PendSV is triggered! +//------------------------------------------------------------------------------ + __BSS__ + __EXPORT__ halPendSvSaveContext +halPendSvSaveContext: + __SPACE__ 1 + + +//------------------------------------------------------------------------------ +// int32u savedMSP +// +// Private storage to hold the saved stack pointer. This variable is only used +// in this file and should not be extern'ed. In our current design we +// do not use real context switching, but only context saving and restoring. +// As such, we only need to keep track of the Main Stack Pointer (MSP). This +// variable is used to hold the MSP between a save and a restore. +//------------------------------------------------------------------------------ + __BSS__ + __EXPORT__ savedMSP +savedMSP: + __SPACE__ 4 + + +//------------------------------------------------------------------------------ +// void halPendSvIsr(void) +// +// This ISR is installed by cstartup in the vector table for the PendSV +// exception. The purpose of this ISR is to either save the current context +// and trigger sleeping through the 'WFI' instruction, or restore a +// previous context. The variable halPendSvSaveContext is used to +// decide if a save or a restore is performed. Since entering/exiting interrupt +// context automatically saves/restores 8 of the 16 CPU registers on the stack +// we need to manually save the other 8 onto the stack as well. +// +// When a context save is complete, the stack will have been expanded by 16 +// words with the current Stack Pointer stored in savedMSP. +// +// When a context restore is complete, the stack will have been shrunk by 16 +// words with the old context restored after the return instruction. +// +// NOTE: The IAR default handler name for PendSV, PendSV_Handler, is also +// instantiated here so it routes to the same code as the St +// name halPendSvIsr. +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __EXPORT__ PendSV_Handler + __EXPORT__ halPendSvIsr +PendSV_Handler: +halPendSvIsr: + LDR R0, =halPendSvSaveContext //load the variable's address + LDRB R0, [R0] //get the value in the variable + CBZ R0, contextRestore //if variable is zero, branch to contextRestore +contextSave: + MRS R0, MSP //load the main stack pointer into R0 + SUB R0, R0, #0x20 //make room on the stack for 8 words (32 bytes) + MSR MSP, R0 //load new MSP from adjusted stack pointer + STM R0, {R4-R11} //store R4-R11 (8 words) onto the stack + LDR R1, =savedMSP //load address of savedMSP into R1 + STR R0, [R1] //store the MSP into savedMSP + WFI //all saved, trigger deep sleep + // Even if we fall through the WFI instruction, we will immediately + // execute a context restore and end up where we left off with no + // ill effects. Normally at this point the core will either be + // powered off or reset (depending on the deep sleep level). +contextRestore: + LDR R0, =savedMSP //load address of savedMSP into R0 + LDR R0, [R0] //load the MSP from savedMSP + LDM R0, {R4-R11} //load R4-R11 (8 words) from the stack + ADD R0, R0, #0x20 //eliminate the 8 words (32 bytes) from the stack + MSR MSP, R0 //restore the MSP from R0 + BX LR //return to the old context + + +//------------------------------------------------------------------------------ +// void halTriggerContextRestore(void) +// +// Cstartup is responsible for triggering a context restore based upon the +// RESET_EVENT register. Since the stack pointer sits at the top of memory +// after the core boots, cstartup cannot simply trigger a PendSV to restore +// context as this will cause existing stack data to be over written. Cstartup +// disables interrupts, pends PendSV, and then calls this function. This +// function simply configures the Stack Pointer to be past the previous data +// such that when interrupts are enabled and PendSV fires it wont corrupt +// previous data. +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __EXPORT__ halTriggerContextRestore +halTriggerContextRestore: + LDR R0, =savedMSP //load address of savedMSP into R0 + LDR R0, [R0] //load the MSP from savedMSP + MSR MSP, R0 //restore the MSP from R0 + CPSIE i //enable interrupts and let PendSV fire + BX LR //this return should never be triggered + + +//------------------------------------------------------------------------------ +// void halInternalIdleSleep(void) +// +// A simple internal function call (to be called from halSleep) for executing +// the WFI instruction and entering the simple, idle sleep state. +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __EXPORT__ halInternalIdleSleep +halInternalIdleSleep: + WFI //trigger idle sleep + BX LR //return + + __END__ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s b/cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s new file mode 100644 index 000000000..e28e353b7 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s @@ -0,0 +1,149 @@ +/************************************************** + * + * Part one of the system initialization code, contains low-level + * initialization, plain thumb variant. + * + + * Customized by St Corporation for STM32W + * + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD __iar_program_start + + ;; Standard Cortex-M3 Vectors + DCD NMI_Handler ;;NMI Handler + DCD HardFault_Handler ;;Hard Fault Handler + DCD MemManage_Handler ;;Memory Fault Handler + DCD BusFault_Handler ;;Bus Fault Handler + DCD UsageFault_Handler ;;Usage Fault Handler + DCD 0 ;;Reserved + DCD 0 ;;Reserved + DCD 0 ;;Reserved + DCD 0 ;;Reserved + DCD SVC_Handler ;;SVCall Handler + DCD DebugMon_Handler ;;Debug Monitor Handler + DCD 0 ;;Reserved + DCD PendSV_Handler ;;PendSV Handler + DCD SysTick_Handler ;;SysTick Handler + + ;; STM32W Vectors + DCD halTimer1Isr ;;Timer 1 Handler + DCD halTimer2Isr ;;Timer 2 Handler + DCD halManagementIsr ;;Management Handler + DCD halBaseBandIsr ;;BaseBand Handler + DCD halSleepTimerIsr ;;Sleep Timer Handler + DCD halSc1Isr ;;SC1 Handler + DCD halSc2Isr ;;SC2 Handler + DCD halSecurityIsr ;;Security Handler + DCD halStackMacTimerIsr ;;MAC Timer Handler + DCD stmRadioTransmitIsr ;;MAC TX Handler + DCD stmRadioReceiveIsr ;;MAC RX Handler + DCD halAdcIsr ;;ADC Handler + DCD halIrqAIsr ;;GPIO IRQA Handler + DCD halIrqBIsr ;;GPIO IRQB Handler + DCD halIrqCIsr ;;GPIO IRQC Handler + DCD halIrqDIsr ;;GPIO IRQD Handler + DCD halDebugIsr ;;Debug Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + + PUBWEAK halTimer1Isr + PUBWEAK halTimer2Isr + PUBWEAK halManagementIsr + PUBWEAK halBaseBandIsr + PUBWEAK halSleepTimerIsr + PUBWEAK halSc1Isr + PUBWEAK halSc2Isr + PUBWEAK halSecurityIsr + PUBWEAK halStackMacTimerIsr + PUBWEAK stmRadioTransmitIsr + PUBWEAK stmRadioReceiveIsr + PUBWEAK halAdcIsr + PUBWEAK halIrqAIsr + PUBWEAK halIrqBIsr + PUBWEAK halIrqCIsr + PUBWEAK halIrqDIsr + PUBWEAK halDebugIsr + + + + + + + SECTION .text:CODE:REORDER(1) + THUMB + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +halTimer1Isr +halTimer2Isr +halManagementIsr +halBaseBandIsr +halSleepTimerIsr +halSc1Isr +halSc2Isr +halSecurityIsr +halStackMacTimerIsr +stmRadioTransmitIsr +stmRadioReceiveIsr +halAdcIsr +halIrqAIsr +halIrqBIsr +halIrqCIsr +halIrqDIsr +halDebugIsr +Default_Handler + B Default_Handler + + END diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/Makefile b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/Makefile new file mode 100644 index 000000000..0440c67f0 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/Makefile @@ -0,0 +1,42 @@ + + + +CC = arm-none-eabi-gcc +AR = arm-none-eabi-ar +CFLAGS = -mthumb -mcpu=cortex-m3 -I "." -I "C:/Program\ Files/Raisonance/Ride/Lib/ARM/include" \ + -fsigned-char -D SMALL_SCANF -D _SMALL_PRINTF -D INTEGER_ONLY -Os -ffunction-sections -mlittle-endian +# +AROPTS = cq + +SOURCE_DIR = src +SOURCE_FILES = small_mprec.c syscalls.c \ + _SP_printf.c _SP_vfprintf.c _SP_puts.c _SP_sprintf.c _SP_snprintf.c\ + small_dtoa.c small_wcsrtombs.c small_wcrtomb.c small_wctomb_r.c \ + scanf.c small_vfsscanf.c sscanf.c small_strtod.c + + +vpath %.c $(SOURCE_DIR) + + +SOURCE_OBJS = ${patsubst %.c,%.o,$(SOURCE_FILES)} + + +LIB = e_stdio_intonly_thumb2.a + + + +all: clean $(LIB) + +clean: + rm -f $(SOURCE_OBJS) $(LIB) + + +%.a: $(SOURCE_OBJS) + $(AR) $(AROPTS) $@ $^ + + +%.o: %.c + $(CC) $(CFLAGS) -c $< -o $@ + + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_printf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_printf.c new file mode 100644 index 000000000..b15fb7593 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_printf.c @@ -0,0 +1,80 @@ +#define _SMALL_PRINFT + +#ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #define _vfprintf _vfiprintf + #define vfprintf vfiprintf +#endif + +#include <_ansi.h> +#include + +#ifndef _SMALL_PRINTF + #include "local.h" +#endif + +#ifdef _HAVE_STDC +#include +#else +#include +#endif + +#ifndef _SMALL_PRINTF + + #ifdef _HAVE_STDC + int + _printf_r (struct _reent *ptr, const char *fmt, ...) + #else + int + _printf_r (ptr, fmt, va_alist) + struct _reent *ptr; + char *fmt; + va_dcl + #endif + { + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdout_r (ptr)); + #ifdef _HAVE_STDC + va_start (ap, fmt); + #else + va_start (ap); + #endif + ret = _vfprintf_r (ptr, _stdout_r (ptr), fmt, ap); + va_end (ap); + return ret; + } +#endif + +#ifndef _REENT_ONLY + +#ifdef _HAVE_STDC +int +printf (const char *fmt, ...) +#else +int +printf (fmt, va_alist) + char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdout_r (_REENT)); +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif +#ifndef _SMALL_PRINTF + ret = vfprintf (_stdout_r (_REENT), fmt, ap); +#else + ret = vfprintf (0, fmt, ap); +#endif + va_end (ap); + return ret; +} + +#endif /* ! _REENT_ONLY */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_puts.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_puts.c new file mode 100644 index 000000000..5ea5af096 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_puts.c @@ -0,0 +1,43 @@ +#include + + +void __io_putchar ( char ); + +void _SMALL_PRINTF_puts(const char *ptr, int len, FILE *fp) + { + if ( fp && ( fp->_file == -1 ) /* No file => sprintf */ + && (fp->_flags & (__SWR | __SSTR) ) ) + { + char *str = fp->_p; + + for ( ; len ; len-- ) + { + *str ++ = *ptr++; + } + fp->_p = str; + } + else /* file => printf */ + { + for ( ; len ; len-- ) + __io_putchar ( *ptr++ ); + } + + } + +int puts(const char *str) + { +#if 1 //VC090825: cleaner and faster version + int len = 0; + while ( str && (*str) ) + { + __io_putchar ( *(str++) ); + len++; + } +#else //VC090825: cleaner, lighter and faster version + int len = strlen ( str ); + _SMALL_PRINTF_puts(str, len, 0) ; +#endif //VC090825: cleaner, lighter and faster version + __io_putchar ( '\n' ); + return len; + } + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_snprintf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_snprintf.c new file mode 100644 index 000000000..2dfcd8599 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_snprintf.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +/* doc in _SP_sprintf.c */ +/* This code created by modifying _SP_sprintf.c so copyright inherited. */ + +#include +#ifdef _HAVE_STDC +#include +#else +#include +#endif +#include +#include +#include <_ansi.h> + +#ifndef _SMALL_PRINTF + #include "local.h" +#else + #ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #endif +#endif + + +#ifndef _SMALL_PRINTF + int + #ifdef _HAVE_STDC + _DEFUN (_snprintf_r, (ptr, str, size, fmt), struct _reent *ptr _AND char *str _AND size_t size _AND _CONST char *fmt _DOTS) + #else + _snprintf_r (ptr, str, size, fmt, va_alist) + struct _reent *ptr; + char *str; + size_t size; + _CONST char *fmt; + va_dcl + #endif + { + int ret; + va_list ap; + FILE f; + + if (size > INT_MAX) + { + ptr->_errno = EOVERFLOW; + return EOF; + } + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = (size > 0 ? size - 1 : 0); + f._file = -1; /* No file. */ + #ifdef _HAVE_STDC + va_start (ap, fmt); + #else + va_start (ap); + #endif + ret = _vfprintf_r (ptr, &f, fmt, ap); + va_end (ap); + if (ret < EOF) + ptr->_errno = EOVERFLOW; + if (size > 0) + *f._p = 0; + return (ret); + } +#endif + +#ifndef _REENT_ONLY +int +#ifdef _HAVE_STDC +_DEFUN (snprintf, (str, size, fmt), char *str _AND size_t size _AND _CONST char *fmt _DOTS) +#else +snprintf (str, size, fmt, va_alist) + char *str; + size_t size; + _CONST char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + FILE f; + + struct _reent *ptr = _REENT; + + if (size > INT_MAX) + { + ptr->_errno = EOVERFLOW; + return EOF; + } + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = (size > 0 ? size - 1 : 0); + f._file = -1; /* No file. */ +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = _vfprintf_r (ptr, &f, fmt, ap); + va_end (ap); + if (ret < EOF) + ptr->_errno = EOVERFLOW; + if (size > 0) + *f._p = 0; + return (ret); +} +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_sprintf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_sprintf.c new file mode 100644 index 000000000..69fb3001a --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_sprintf.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + +FUNCTION + <>, <>, <>, <>, <>---format output +INDEX + fprintf +INDEX + printf +INDEX + asprintf +INDEX + sprintf +INDEX + snprintf + +ANSI_SYNOPSIS + #include + + int printf(const char *<[format]> [, <[arg]>, ...]); + int fprintf(FILE *<[fd]>, const char *<[format]> [, <[arg]>, ...]); + int sprintf(char *<[str]>, const char *<[format]> [, <[arg]>, ...]); + int asprintf(char **<[strp]>, const char *<[format]> [, <[arg]>, ...]); + int snprintf(char *<[str]>, size_t <[size]>, const char *<[format]> [, <[arg]>, ...]); + +TRAD_SYNOPSIS + #include + + int printf(<[format]> [, <[arg]>, ...]) + char *<[format]>; + + int fprintf(<[fd]>, <[format]> [, <[arg]>, ...]); + FILE *<[fd]>; + char *<[format]>; + + int asprintf(<[strp]>, <[format]> [, <[arg]>, ...]); + char **<[strp]>; + char *<[format]>; + + int sprintf(<[str]>, <[format]> [, <[arg]>, ...]); + char *<[str]>; + char *<[format]>; + + int snprintf(<[str]>, size_t <[size]>, <[format]> [, <[arg]>, ...]); + char *<[str]>; + size_t <[size]>; + char *<[format]>; + +DESCRIPTION + <> accepts a series of arguments, applies to each a + format specifier from <<*<[format]>>>, and writes the + formatted data to <>, terminated with a null character. + The behavior of <> is undefined if there are not enough + arguments for the format. + <> returns when it reaches the end of the format string. + If there are more arguments than the format requires, excess + arguments are ignored. + + <>, <>, <> and <> are identical + to <>, other than the destination of the formatted output: + <> sends the output to a specified file <[fd]>, while + <> stores the output in a dynamically allocated buffer, + while <> stores the output in the specified char array + <[str]> and <> limits number of characters written to + <[str]> to at most <[size]> (including terminating <<0>>). For + <> and <>, the behavior is undefined if the + output <<*<[str]>>> overlaps with one of the arguments. For + <>, <[strp]> points to a pointer to char which is filled + in with the dynamically allocated buffer. <[format]> is a pointer + to a charater string containing two types of objects: ordinary + characters (other than <<%>>), which are copied unchanged to the + output, and conversion specifications, each of which is introduced + by <<%>>. (To include <<%>> in the output, use <<%%>> in the format + string.) A conversion specification has the following form: + +. %[<[flags]>][<[width]>][.<[prec]>][<[size]>][<[type]>] + + The fields of the conversion specification have the following meanings: + + O+ + o <[flags]> + + an optional sequence of characters which control + output justification, numeric signs, decimal points, + trailing zeroes, and octal and hex prefixes. + The flag characters are minus (<<->>), plus (<<+>>), + space ( ), zero (<<0>>), and sharp (<<#>>). They can + appear in any combination. + + o+ + o - + The result of the conversion is left justified, and the right is + padded with blanks. If you do not use this flag, the result is right + justified, and padded on the left. + + o + + The result of a signed conversion (as determined by <[type]>) + will always begin with a plus or minus sign. (If you do not use + this flag, positive values do not begin with a plus sign.) + + o " " (space) + If the first character of a signed conversion specification + is not a sign, or if a signed conversion results in no + characters, the result will begin with a space. If the + space ( ) flag and the plus (<<+>>) flag both appear, + the space flag is ignored. + + o 0 + If the <[type]> character is <>, <>, <>, <>, + <>, <>, <>, <>, <>, <>, or <>: leading zeroes, + are used to pad the field width (following any indication of sign or + base); no spaces are used for padding. If the zero (<<0>>) and + minus (<<->>) flags both appear, the zero (<<0>>) flag will + be ignored. For <>, <>, <>, <>, <>, and <> + conversions, if a precision <[prec]> is specified, the zero (<<0>>) + flag is ignored. + + Note that <<0>> is interpreted as a flag, not as the beginning + of a field width. + + o # + The result is to be converted to an alternative form, according + to the next character: + + o+ + o 0 + increases precision to force the first digit + of the result to be a zero. + + o x + a non-zero result will have a <<0x>> prefix. + + o X + a non-zero result will have a <<0X>> prefix. + + o e, E or f + The result will always contain a decimal point + even if no digits follow the point. + (Normally, a decimal point appears only if a + digit follows it.) Trailing zeroes are removed. + + o g or G + same as <> or <>, but trailing zeroes + are not removed. + + o all others + undefined. + + o- + o- + + o <[width]> + + <[width]> is an optional minimum field width. You can either + specify it directly as a decimal integer, or indirectly by + using instead an asterisk (<<*>>), in which case an <> + argument is used as the field width. Negative field widths + are not supported; if you attempt to specify a negative field + width, it is interpreted as a minus (<<->>) flag followed by a + positive field width. + + o <[prec]> + + an optional field; if present, it is introduced with `<<.>>' + (a period). This field gives the maximum number of + characters to print in a conversion; the minimum number of + digits of an integer to print, for conversions with <[type]> + <>, <>, <>, <>, <>, and <>; the maximum number of + significant digits, for the <> and <> conversions; + or the number of digits to print after the decimal + point, for <>, <>, and <> conversions. You can specify + the precision either directly as a decimal integer or + indirectly by using an asterisk (<<*>>), in which case + an <> argument is used as the precision. Supplying a negative + precision is equivalent to omitting the precision. + If only a period is specified the precision is zero. + If a precision appears with any other conversion <[type]> + than those listed here, the behavior is undefined. + + o <[size]> + + <>, <>, and <> are optional size characters which + override the default way that <> interprets the + data type of the corresponding argument. <> forces + the following <>, <>, <>, <>, <> or <> conversion + <[type]> to apply to a <> or <>. <> also + forces a following <> <[type]> to apply to + a pointer to a <>. Similarily, an + <> forces the following <>, <>, <>, <>, + <> or <> conversion <[type]> to apply to a <> or + <>. <> also forces a following <> <[type]> to + apply to a pointer to a <>. <> with <>, <> is + equivalent to <>, <> respectively. If an <> + or an <> appears with another conversion + specifier, the behavior is undefined. <> forces a + following <>, <>, <>, <> or <> conversion <[type]> to + apply to a <> argument. If <> appears with + any other conversion <[type]>, the behavior is undefined. + + o <[type]> + + <[type]> specifies what kind of conversion <> performs. + Here is a table of these: + + o+ + o % + prints the percent character (<<%>>) + + o c + prints <[arg]> as single character + + o C + prints wchar_t <[arg]> as single multibyte character + + o s + prints characters until precision is reached or a null terminator + is encountered; takes a string pointer + + o S + converts wchar_t characters to multibyte output characters until + precision is reached or a null wchar_t terminator + is encountered; takes a wchar_t pointer + + o d + prints a signed decimal integer; takes an <> (same as <>) + + o i + prints a signed decimal integer; takes an <> (same as <>) + + o o + prints a signed octal integer; takes an <> + + o u + prints an unsigned decimal integer; takes an <> + + o x + prints an unsigned hexadecimal integer (using <> as + digits beyond <<9>>); takes an <> + + o X + prints an unsigned hexadecimal integer (using <> as + digits beyond <<9>>); takes an <> + + o f + prints a signed value of the form <<[-]9999.9999>>; takes + a floating-point number + + o e + prints a signed value of the form <<[-]9.9999e[+|-]999>>; takes a + floating-point number + + o E + prints the same way as <>, but using <> to introduce the + exponent; takes a floating-point number + + o g + prints a signed value in either <> or <> form, based on given + value and precision---trailing zeros and the decimal point are + printed only if necessary; takes a floating-point number + + o G + prints the same way as <>, but using <> for the exponent if an + exponent is needed; takes a floating-point number + + o n + stores (in the same object) a count of the characters written; + takes a pointer to <> + + o p + prints a pointer in an implementation-defined format. + This implementation treats the pointer as an + <> (same as <>). + o- +O- + + +RETURNS +<> and <> return the number of bytes in the output string, +save that the concluding <> is not counted. +<> and <> return the number of characters transmitted. +If an error occurs, <> and <> return <> and +<> returns -1. No error returns occur for <>. + +PORTABILITY + The ANSI C standard specifies that implementations must + support at least formatted output of up to 509 characters. + +Supporting OS subroutines required: <>, <>, <>, +<>, <>, <>, <>. +*/ + + +#include +#ifdef _HAVE_STDC +#include +#else +#include +#endif +#include +#include <_ansi.h> + +#ifndef _SMALL_PRINTF + #include "local.h" +#else + #ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #endif +#endif + + + + + +#ifndef _SMALL_PRINTF + int + #ifdef _HAVE_STDC + _DEFUN (_sprintf_r, (ptr, str, fmt), struct _reent *ptr _AND char *str _AND _CONST char *fmt _DOTS) + #else + _sprintf_r (ptr, str, fmt, va_alist) + struct _reent *ptr; + char *str; + _CONST char *fmt; + va_dcl + #endif + { + int ret; + va_list ap; + FILE f; + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = INT_MAX; + f._file = -1; /* No file. */ + #ifdef _HAVE_STDC + va_start (ap, fmt); + #else + va_start (ap); + #endif + ret = _vfprintf_r (ptr, &f, fmt, ap); + va_end (ap); + *f._p = 0; + return (ret); + } +#endif + +#ifndef _REENT_ONLY +int +#ifdef _HAVE_STDC +_DEFUN (sprintf, (str, fmt), char *str _AND _CONST char *fmt _DOTS) +#else +sprintf (str, fmt, va_alist) + char *str; + _CONST char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + FILE f; + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = INT_MAX; + f._file = -1; /* No file. */ +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = _vfprintf_r (_REENT, &f, fmt, ap); + va_end (ap); + *f._p = 0; + return (ret); +} +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_vfprintf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_vfprintf.c new file mode 100644 index 000000000..8eb25819c --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/_SP_vfprintf.c @@ -0,0 +1,1780 @@ +/* +FUNCTION +<>, <>, <>---format argument list + +INDEX + vprintf +INDEX + vfprintf +INDEX + vsprintf +INDEX + vsnprintf + +ANSI_SYNOPSIS + #include + #include + int vprintf(const char *<[fmt]>, va_list <[list]>); + int vfprintf(FILE *<[fp]>, const char *<[fmt]>, va_list <[list]>); + int vsprintf(char *<[str]>, const char *<[fmt]>, va_list <[list]>); + int vasprintf(char **<[strp]>, const char *<[fmt]>, va_list <[list]>); + int vsnprintf(char *<[str]>, size_t <[size]>, const char *<[fmt]>, va_list <[list]>); + + int _vprintf_r(void *<[reent]>, const char *<[fmt]>, + va_list <[list]>); + int _vfprintf_r(void *<[reent]>, FILE *<[fp]>, const char *<[fmt]>, + va_list <[list]>); + int _vasprintf_r(void *<[reent]>, char **<[str]>, const char *<[fmt]>, + va_list <[list]>); + int _vsprintf_r(void *<[reent]>, char *<[str]>, const char *<[fmt]>, + va_list <[list]>); + int _vsnprintf_r(void *<[reent]>, char *<[str]>, size_t <[size]>, const char *<[fmt]>, + va_list <[list]>); + +TRAD_SYNOPSIS + #include + #include + int vprintf( <[fmt]>, <[list]>) + char *<[fmt]>; + va_list <[list]>; + + int vfprintf(<[fp]>, <[fmt]>, <[list]>) + FILE *<[fp]>; + char *<[fmt]>; + va_list <[list]>; + + int vasprintf(<[strp]>, <[fmt]>, <[list]>) + char **<[strp]>; + char *<[fmt]>; + va_list <[list]>; + + int vsprintf(<[str]>, <[fmt]>, <[list]>) + char *<[str]>; + char *<[fmt]>; + va_list <[list]>; + + int vsnprintf(<[str]>, <[size]>, <[fmt]>, <[list]>) + char *<[str]>; + size_t <[size]>; + char *<[fmt]>; + va_list <[list]>; + + int _vprintf_r(<[reent]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[fmt]>; + va_list <[list]>; + + int _vfprintf_r(<[reent]>, <[fp]>, <[fmt]>, <[list]>) + char *<[reent]>; + FILE *<[fp]>; + char *<[fmt]>; + va_list <[list]>; + + int _vasprintf_r(<[reent]>, <[strp]>, <[fmt]>, <[list]>) + char *<[reent]>; + char **<[strp]>; + char *<[fmt]>; + va_list <[list]>; + + int _vsprintf_r(<[reent]>, <[str]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[str]>; + char *<[fmt]>; + va_list <[list]>; + + int _vsnprintf_r(<[reent]>, <[str]>, <[size]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[str]>; + size_t <[size]>; + char *<[fmt]>; + va_list <[list]>; + +DESCRIPTION +<>, <>, <>, <> and <> are +(respectively) variants of <>, <>, <>, <>, +and <>. They differ only in allowing their caller to pass the +variable argument list as a <> object (initialized by <>) +rather than directly accepting a variable number of arguments. + +RETURNS +The return values are consistent with the corresponding functions: +<>/<> returns the number of bytes in the output string, +save that the concluding <> is not counted. +<> and <> return the number of characters transmitted. +If an error occurs, <> and <> return <> and +<> returns -1. No error returns occur for <>. + +PORTABILITY +ANSI C requires all three functions. + +Supporting OS subroutines required: <>, <>, <>, +<>, <>, <>, <>. +*/ + +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if defined(LIBC_SCCS) && !defined(lint) +static char *sccsid = "from: @(#)vfprintf.c 5.50 (Berkeley) 12/16/92"; +#endif /* LIBC_SCCS and not lint */ + +/* + * Actual printf innards. + * + * This code is large and complicated... + */ + + +#ifdef _SMALL_PRINTF +#define _NO_LONGDBL +#endif + + +#ifdef INTEGER_ONLY + #define VFPRINTF vfiprintf + #define _VFPRINTF_R _vfiprintf_r +#else + #define VFPRINTF vfprintf + #define _VFPRINTF_R _vfprintf_r + #ifndef NO_FLOATING_POINT + #define FLOATING_POINT + #endif +#endif + +#define _NO_LONGLONG +#if defined WANT_PRINTF_LONG_LONG && defined __GNUC__ +# undef _NO_LONGLONG +#endif + +#define _NO_POS_ARGS +#if defined WANT_IO_POS_ARGS +# undef _NO_POS_ARGS +#endif + +#include <_ansi.h> +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef _HAVE_STDC +#include +#else +#include +#endif + +#ifndef _SMALL_PRINTF + #include "local.h" + #include "fvwrite.h" +#else + #define MAXBUFLOC 80 +#endif + + #include "vfieeefp.h" + +/* Currently a test is made to see if long double processing is warranted. + This could be changed in the future should the _ldtoa_r code be + preferred over _dtoa_r. */ +#define _NO_LONGDBL +#if defined WANT_IO_LONG_DBL && (LDBL_MANT_DIG > DBL_MANT_DIG) +# undef _NO_LONGDBL +#endif + + +#ifndef _SMALL_PRINTF +/* + * Flush out all the vectors defined by the given uio, + * then reset it so that it can be reused. + */ +static int +__sprint(fp, uio) + FILE *fp; + register struct __suio *uio; +{ + register int err; + + if (uio->uio_resid == 0) { + uio->uio_iovcnt = 0; + return (0); + } + err = __sfvwrite(fp, uio); + uio->uio_resid = 0; + uio->uio_iovcnt = 0; + return (err); +} + +/* + * Helper function for `fprintf to unbuffered unix file': creates a + * temporary buffer. We only work on write-only files; this avoids + * worries about ungetc buffers and so forth. + */ +static int +__sbprintf(fp, fmt, ap) + register FILE *fp; + const char *fmt; + va_list ap; +{ + int ret; + FILE fake; + unsigned char buf[BUFSIZ]; + + /* copy the important variables */ + fake._flags = fp->_flags & ~__SNBF; + fake._file = fp->_file; + fake._cookie = fp->_cookie; + fake._write = fp->_write; + + /* set up the buffer */ + fake._bf._base = fake._p = buf; + fake._bf._size = fake._w = sizeof(buf); + fake._lbfsize = 0; /* not actually used, but Just In Case */ +#ifndef __SINGLE_THREAD__ + __lock_init_recursive (*(_LOCK_RECURSIVE_T *)&fake._lock); +#endif + + /* do the work, then copy any error status */ + ret = VFPRINTF(&fake, fmt, ap); + if (ret >= 0 && fflush(&fake)) + ret = EOF; + if (fake._flags & __SERR) + fp->_flags |= __SERR; + +#ifndef __SINGLE_THREAD__ + __lock_close_recursive (*(_LOCK_RECURSIVE_T *)&fake._lock); +#endif + return (ret); +} +#endif + + + +#ifdef FLOATING_POINT +#include +#include +#include "floatio.h" + +#if ((MAXEXP+MAXFRACT+1) > MB_LEN_MAX) +# define BUF (MAXEXP+MAXFRACT+1) /* + decimal point */ +#else +# define BUF MB_LEN_MAX +#endif + +#define DEFPREC 6 + +#ifdef _NO_LONGDBL +static char *cvt _PARAMS((struct _reent *, double, int, int, char *, int *, int, int *)); +#else +static char *cvt _PARAMS((struct _reent *, _LONG_DOUBLE, int, int, char *, int *, int, int *)); +extern int _ldcheck _PARAMS((_LONG_DOUBLE *)); +#endif + +static int exponent _PARAMS((char *, int, int)); + +#else /* no FLOATING_POINT */ + +#define BUF 40 + +#endif /* FLOATING_POINT */ + +#ifndef _NO_LONGLONG +#define quad_t long long +#define u_quad_t unsigned long long +#else +#define quad_t long +#define u_quad_t unsigned long +#endif + +typedef quad_t * quad_ptr_t; +typedef void * void_ptr_t; +typedef char * char_ptr_t; +typedef long * long_ptr_t; +typedef int * int_ptr_t; +typedef short * short_ptr_t; + +#ifndef _NO_POS_ARGS +#define MAX_POS_ARGS 32 + +union arg_val +{ + int val_int; + u_int val_u_int; + long val_long; + u_long val_u_long; + float val_float; + double val_double; + _LONG_DOUBLE val__LONG_DOUBLE; + int_ptr_t val_int_ptr_t; + short_ptr_t val_short_ptr_t; + long_ptr_t val_long_ptr_t; + char_ptr_t val_char_ptr_t; + quad_ptr_t val_quad_ptr_t; + void_ptr_t val_void_ptr_t; + quad_t val_quad_t; + u_quad_t val_u_quad_t; + wint_t val_wint_t; +}; + +static union arg_val *get_arg (struct _reent *data, int n, char *fmt, + va_list *ap, int *numargs, union arg_val *args, + int *arg_type, char **last_fmt); +#endif /* !_NO_POS_ARGS */ + +/* + * Macros for converting digits to letters and vice versa + */ +#define to_digit(c) ((c) - '0') +#define is_digit(c) ((unsigned)to_digit(c) <= 9) +#define to_char(n) ((n) + '0') + +/* + * Flags used during conversion. + */ +#define ALT 0x001 /* alternate form */ +#define HEXPREFIX 0x002 /* add 0x or 0X prefix */ +#define LADJUST 0x004 /* left adjustment */ +#define LONGDBL 0x008 /* long double */ +#define LONGINT 0x010 /* long integer */ +#ifndef _NO_LONGLONG +#define QUADINT 0x020 /* quad integer */ +#else /* ifdef _NO_LONGLONG, make QUADINT equivalent to LONGINT, so + that %lld behaves the same as %ld, not as %d, as expected if: + sizeof (long long) = sizeof long > sizeof int */ +#define QUADINT LONGINT +#endif +#define SHORTINT 0x040 /* short integer */ +#define ZEROPAD 0x080 /* zero (as opposed to blank) pad */ +#define FPT 0x100 /* Floating point number */ + + + int _EXFUN (_VFPRINTF_R, (struct _reent *, FILE *, _CONST char *, va_list)); + + int + _DEFUN (VFPRINTF, (fp, fmt0, ap), + FILE * fp _AND + _CONST char *fmt0 _AND + va_list ap) + { + int result; + _flockfile(fp); +#ifndef _SMALL_PRINTF + CHECK_INIT (fp); +#endif + result = _VFPRINTF_R (_REENT, fp, fmt0, ap); + _funlockfile(fp); + return result; + } + + + +int +_DEFUN (_VFPRINTF_R, (data, fp, fmt0, ap), + struct _reent *data _AND + FILE * fp _AND + _CONST char *fmt0 _AND + va_list ap) +{ + register char *fmt; /* format string */ + register int ch; /* character from fmt */ + register int n, m; /* handy integers (short term usage) */ + register char *cp; /* handy char pointer (short term usage) */ + register struct __siov *iovp;/* for PRINT macro */ + register int flags; /* flags as above */ + char *fmt_anchor; /* current format spec being processed */ + int N; /* arg number */ + int arg_index; /* index into args processed directly */ +#ifndef _NO_POS_ARGS + int numargs; /* number of varargs read */ + char *saved_fmt; /* saved fmt pointer */ + union arg_val args[MAX_POS_ARGS]; + int arg_type[MAX_POS_ARGS]; + int is_pos_arg; /* is current format positional? */ + int old_is_pos_arg; /* is current format positional? */ +#endif + int ret; /* return value accumulator */ + int width; /* width from format (%8d), or 0 */ + int prec; /* precision from format (%.3d), or -1 */ + char sign; /* sign prefix (' ', '+', '-', or \0) */ +#ifdef FLOATING_POINT +#ifdef _SMALL_PRINTF + char *decimal_point = "."; +#else + char *decimal_point = localeconv()->decimal_point; +#endif + char softsign; /* temporary negative sign for floats */ +#ifdef _NO_LONGDBL + union { int i; double d; } _double_ = {0}; + #define _fpvalue (_double_.d) +#else + union { int i; _LONG_DOUBLE ld; } _long_double_ = {0}; + #define _fpvalue (_long_double_.ld) + int tmp; +#endif + int expt; /* integer value of exponent */ + int expsize = 0; /* character count for expstr */ + int ndig; /* actual number of digits returned by cvt */ + char expstr[7]; /* buffer for exponent string */ +#endif + u_quad_t _uquad; /* integer arguments %[diouxX] */ + enum { OCT, DEC, HEX } base;/* base for [diouxX] conversion */ + int dprec; /* a copy of prec if [diouxX], 0 otherwise */ + int realsz; /* field size expanded by dprec */ + int size; /* size of converted field or string */ + char *xdigs = NULL; /* digits for [xX] conversion */ +#ifndef _SMALL_PRINTF + #define NIOV 8 + struct __suio uio; /* output information: summary */ + struct __siov iov[NIOV];/* ... and individual io vectors */ + char *malloc_buf = NULL;/* handy pointer for malloced buffers */ +#else + char malloc_buf [MAXBUFLOC]; /* local buffers */ +#endif + + char buf[BUF]; /* space for %c, %[diouxX], %[eEfgG] */ + char ox[2]; /* space for 0x hex-prefix */ +#ifdef MB_CAPABLE + wchar_t wc; + mbstate_t state; /* mbtowc calls from library must not change state */ +#endif + + + /* + * Choose PADSIZE to trade efficiency vs. size. If larger printf + * fields occur frequently, increase PADSIZE and make the initialisers + * below longer. + */ +#define PADSIZE 16 /* pad chunk size */ + static _CONST char blanks[PADSIZE] = + {' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '}; + static _CONST char zeroes[PADSIZE] = + {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0'}; + +#ifdef MB_CAPABLE + memset (&state, '\0', sizeof (state)); +#endif + +#ifndef _SMALL_PRINTF + /* + * BEWARE, these `goto error' on error, and PAD uses `n'. + */ + #define PRINT(ptr, len,f) { \ + iovp->iov_base = (ptr); \ + iovp->iov_len = (len); \ + uio.uio_resid += (len); \ + iovp++; \ + if (++uio.uio_iovcnt >= NIOV) { \ + if (__sprint(fp, &uio)) \ + goto error; \ + iovp = iov; \ + } \ + } + #define PAD(howmany, with,f) { \ + if ((n = (howmany)) > 0) { \ + while (n > PADSIZE) { \ + PRINT(with, PADSIZE,f); \ + n -= PADSIZE; \ + } \ + PRINT(with, n,f); \ + } \ + } + #define FLUSH() { \ + if (uio.uio_resid && __sprint(fp, &uio)) \ + goto error; \ + uio.uio_iovcnt = 0; \ + iovp = iov; \ + } +#else + //Macros for _SMALL_PRINTF + void _SMALL_PRINTF_puts(const char *ptr, int len, FILE *f); + #define PRINT(ptr, len, f) {_SMALL_PRINTF_puts(ptr,len,f);} + #define PAD(howmany, with, f) { \ + if ((n = (howmany)) > 0) { \ + while (n > PADSIZE) { \ + PRINT(with, PADSIZE,f); \ + n -= PADSIZE; \ + } \ + PRINT(with, n, f); \ + } \ + } + #define FLUSH() { ; } +#endif + + + /* Macros to support positional arguments */ +#ifndef _NO_POS_ARGS +#define GET_ARG(n, ap, type) \ + ( is_pos_arg \ + ? n < numargs \ + ? args[n].val_##type \ + : get_arg (data, n, fmt_anchor, &ap, &numargs, args, arg_type, &saved_fmt)->val_##type \ + : arg_index++ < numargs \ + ? args[n].val_##type \ + : numargs < MAX_POS_ARGS \ + ? args[numargs++].val_##type = va_arg(ap, type) \ + : va_arg(ap, type) \ + ) +#else +#define GET_ARG(n, ap, type) (va_arg(ap, type)) +#endif + + /* + * To extend shorts properly, we need both signed and unsigned + * argument extraction methods. + */ +#ifndef _NO_LONGLONG +#define SARG() \ + (flags&QUADINT ? GET_ARG(N, ap, quad_t) : \ + flags&LONGINT ? GET_ARG(N, ap, long) : \ + flags&SHORTINT ? (long)(short)GET_ARG(N, ap, int) : \ + (long)GET_ARG(N, ap, int)) +#define UARG() \ + (flags&QUADINT ? GET_ARG(N, ap, u_quad_t) : \ + flags&LONGINT ? GET_ARG(N, ap, u_long) : \ + flags&SHORTINT ? (u_long)(u_short)GET_ARG(N, ap, int) : \ + (u_long)GET_ARG(N, ap, u_int)) +#else +#define SARG() \ + (flags&LONGINT ? GET_ARG(N, ap, long) : \ + flags&SHORTINT ? (long)(short)GET_ARG(N, ap, int) : \ + (long)GET_ARG(N, ap, int)) +#define UARG() \ + (flags&LONGINT ? GET_ARG(N, ap, u_long) : \ + flags&SHORTINT ? (u_long)(u_short)GET_ARG(N, ap, int) : \ + (u_long)GET_ARG(N, ap, u_int)) +#endif + +#ifndef _SMALL_PRINTF + /* sorry, fprintf(read_only_file, "") returns EOF, not 0 */ + if (cantwrite(fp)) + return (EOF); + + /* optimise fprintf(stderr) (and other unbuffered Unix files) */ + if ((fp->_flags & (__SNBF|__SWR|__SRW)) == (__SNBF|__SWR) && + fp->_file >= 0) + return (__sbprintf(fp, fmt0, ap)); + + uio.uio_iov = iovp = iov; + uio.uio_resid = 0; + uio.uio_iovcnt = 0; +#endif + fmt = (char *)fmt0; + + ret = 0; + arg_index = 0; + +#ifndef _NO_POS_ARGS + saved_fmt = NULL; + arg_type[0] = -1; + numargs = 0; + is_pos_arg = 0; +#endif + + /* + * Scan the format for conversions (`%' character). + */ + for (;;) { + cp = fmt; +#ifdef MB_CAPABLE + while ((n = _mbtowc_r(data, &wc, fmt, MB_CUR_MAX, &state)) > 0) { + if (wc == '%') + break; + fmt += n; + } +#else + while (*fmt != '\0' && *fmt != '%') + fmt += 1; +#endif + if ((m = fmt - cp) != 0) { + PRINT(cp, m, fp); + ret += m; + } +#ifdef MB_CAPABLE + if (n <= 0) + goto done; +#else + if (*fmt == '\0') + goto done; +#endif + fmt_anchor = fmt; + fmt++; /* skip over '%' */ + + flags = 0; + dprec = 0; + width = 0; + prec = -1; + sign = '\0'; + N = arg_index; +#ifndef _NO_POS_ARGS + is_pos_arg = 0; +#endif + +rflag: ch = *fmt++; +reswitch: switch (ch) { + case ' ': + /* + * ``If the space and + flags both appear, the space + * flag will be ignored.'' + * -- ANSI X3J11 + */ + if (!sign) + sign = ' '; + goto rflag; + case '#': + flags |= ALT; + goto rflag; + case '*': + n = N; +#ifndef _NO_POS_ARGS + /* we must check for positional arg used for dynamic width */ + old_is_pos_arg = is_pos_arg; + is_pos_arg = 0; + if (is_digit(*fmt)) { + char *old_fmt = fmt; + + n = 0; + ch = *fmt++; + do { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); + + if (ch == '$') { + if (n <= MAX_POS_ARGS) { + n -= 1; + is_pos_arg = 1; + } + else + goto error; + } + else { + fmt = old_fmt; + goto rflag; + } + } +#endif /* !_NO_POS_ARGS */ + + /* + * ``A negative field width argument is taken as a + * - flag followed by a positive field width.'' + * -- ANSI X3J11 + * They don't exclude field widths read from args. + */ + width = GET_ARG(n, ap, int); +#ifndef _NO_POS_ARGS + is_pos_arg = old_is_pos_arg; +#endif + if (width >= 0) + goto rflag; + width = -width; + /* FALLTHROUGH */ + case '-': + flags |= LADJUST; + goto rflag; + case '+': + sign = '+'; + goto rflag; + case '.': + if ((ch = *fmt++) == '*') { + n = N; +#ifndef _NO_POS_ARGS + /* we must check for positional arg used for dynamic width */ + old_is_pos_arg = is_pos_arg; + is_pos_arg = 0; + if (is_digit(*fmt)) { + char *old_fmt = fmt; + + n = 0; + ch = *fmt++; + do { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); + + if (ch == '$') { + if (n <= MAX_POS_ARGS) { + n -= 1; + is_pos_arg = 1; + } + else + goto error; + } + else { + fmt = old_fmt; + goto rflag; + } + } +#endif /* !_NO_POS_ARGS */ + prec = GET_ARG(n, ap, int); +#ifndef _NO_POS_ARGS + is_pos_arg = old_is_pos_arg; +#endif + if (prec < 0) + prec = -1; + goto rflag; + } + n = 0; + while (is_digit(ch)) { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } + prec = n < 0 ? -1 : n; + goto reswitch; + case '0': + /* + * ``Note that 0 is taken as a flag, not as the + * beginning of a field width.'' + * -- ANSI X3J11 + */ + flags |= ZEROPAD; + goto rflag; + case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + n = 0; + do { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); +#ifndef _NO_POS_ARGS + if (ch == '$') { + if (n <= MAX_POS_ARGS) { + N = n - 1; + is_pos_arg = 1; + goto rflag; + } + else + goto error; + } +#endif /* !_NO_POS_ARGS */ + width = n; + goto reswitch; +#ifdef FLOATING_POINT + case 'L': + flags |= LONGDBL; + goto rflag; +#endif + case 'h': + flags |= SHORTINT; + goto rflag; + case 'l': + if (*fmt == 'l') { + fmt++; + flags |= QUADINT; + } else { + flags |= LONGINT; + } + goto rflag; + case 'q': + flags |= QUADINT; + goto rflag; + case 'c': + case 'C': + cp = buf; + if (ch == 'C' || (flags & LONGINT)) { + mbstate_t ps; + + memset((void *)&ps, '\0', sizeof(mbstate_t)); + if ((size = (int)_wcrtomb_r(data, cp, + (wchar_t)GET_ARG(N, ap, wint_t), + &ps)) == -1) + goto error; + } + else { + *cp = GET_ARG(N, ap, int); + size = 1; + } + sign = '\0'; + break; + case 'D': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'd': + case 'i': + _uquad = SARG(); +#ifndef _NO_LONGLONG + if ((quad_t)_uquad < 0) +#else + if ((long) _uquad < 0) +#endif + { + + _uquad = -_uquad; + sign = '-'; + } + base = DEC; + goto number; +#ifdef FLOATING_POINT + case 'e': + case 'E': + case 'f': + case 'g': + case 'G': + if (prec == -1) { + prec = DEFPREC; + } else if ((ch == 'g' || ch == 'G') && prec == 0) { + prec = 1; + } + +#ifdef _NO_LONGDBL + if (flags & LONGDBL) { + _fpvalue = (double) GET_ARG(N, ap, _LONG_DOUBLE); + } else { + _fpvalue = GET_ARG(N, ap, double); + } + + /* do this before tricky precision changes */ + if (isinf(_fpvalue)) { + if (_fpvalue < 0) + sign = '-'; + cp = "Inf"; + size = 3; + break; + } + if (isnan(_fpvalue)) { + cp = "NaN"; + size = 3; + break; + } + +#else /* !_NO_LONGDBL */ + + if (flags & LONGDBL) { + _fpvalue = GET_ARG(N, ap, _LONG_DOUBLE); + } else { + _fpvalue = (_LONG_DOUBLE)GET_ARG(N, ap, double); + } + + /* do this before tricky precision changes */ + tmp = _ldcheck (&_fpvalue); + if (tmp == 2) { + if (_fpvalue < 0) + sign = '-'; + cp = "Inf"; + size = 3; + break; + } + if (tmp == 1) { + cp = "NaN"; + size = 3; + break; + } +#endif /* !_NO_LONGDBL */ + + flags |= FPT; + + cp = cvt(data, _fpvalue, prec, flags, &softsign, + &expt, ch, &ndig); + + if (ch == 'g' || ch == 'G') { + if (expt <= -4 || expt > prec) + ch = (ch == 'g') ? 'e' : 'E'; + else + ch = 'g'; + } + if (ch <= 'e') { /* 'e' or 'E' fmt */ + --expt; + expsize = exponent(expstr, expt, ch); + size = expsize + ndig; + if (ndig > 1 || flags & ALT) + ++size; + } else if (ch == 'f') { /* f fmt */ + if (expt > 0) { + size = expt; + if (prec || flags & ALT) + size += prec + 1; + } else /* "0.X" */ + size = (prec || flags & ALT) + ? prec + 2 + : 1; + } else if (expt >= ndig) { /* fixed g fmt */ + size = expt; + if (flags & ALT) + ++size; + } else + size = ndig + (expt > 0 ? + 1 : 2 - expt); + + if (softsign) + sign = '-'; + break; +#endif /* FLOATING_POINT */ + case 'n': +#ifndef _NO_LONGLONG + if (flags & QUADINT) + *GET_ARG(N, ap, quad_ptr_t) = ret; + else +#endif + if (flags & LONGINT) + *GET_ARG(N, ap, long_ptr_t) = ret; + else if (flags & SHORTINT) + *GET_ARG(N, ap, short_ptr_t) = ret; + else + *GET_ARG(N, ap, int_ptr_t) = ret; + continue; /* no output */ + case 'O': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'o': + _uquad = UARG(); + base = OCT; + goto nosign; + case 'p': + /* + * ``The argument shall be a pointer to void. The + * value of the pointer is converted to a sequence + * of printable characters, in an implementation- + * defined manner.'' + * -- ANSI X3J11 + */ + /* NOSTRICT */ + _uquad = (u_long)(unsigned _POINTER_INT)GET_ARG(N, ap, void_ptr_t); + base = HEX; + xdigs = "0123456789abcdef"; + flags |= HEXPREFIX; + ch = 'x'; + goto nosign; + case 's': + case 'S': + sign = '\0'; + if ((cp = GET_ARG(N, ap, char_ptr_t)) == NULL) { + cp = "(null)"; + size = 6; + } + else if (ch == 'S' || (flags & LONGINT)) { + mbstate_t ps; + _CONST wchar_t *wcp; + + wcp = (_CONST wchar_t *)cp; + size = m = 0; + memset((void *)&ps, '\0', sizeof(mbstate_t)); + + /* Count number of bytes needed for multibyte + string that will be produced from widechar + string. */ + if (prec >= 0) { + while (1) { + if (wcp[m] == L'\0') + break; + if ((n = (int)_wcrtomb_r(data, + buf, wcp[m], &ps)) == -1) + goto error; + if (n + size > prec) + break; + m += 1; + size += n; + if (size == prec) + break; + } + } + else { + if ((size = (int)_wcsrtombs_r(data, + NULL, &wcp, 0, &ps)) == -1) + goto error; + wcp = (_CONST wchar_t *)cp; + } + + if (size == 0) + break; + + #ifndef _SMALL_PRINTF + if ((malloc_buf = + (char *)_malloc_r(data, size + 1)) == NULL) + goto error; + #endif + + /* Convert widechar string to multibyte string. */ + memset((void *)&ps, '\0', sizeof(mbstate_t)); + if (_wcsrtombs_r(data, malloc_buf, &wcp, size, &ps) != size) + goto error; + cp = malloc_buf; + cp[size] = '\0'; + } + else if (prec >= 0) { + /* + * can't use strlen; can only look for the + * NUL in the first `prec' characters, and + * strlen() will go further. + */ + char *p = memchr(cp, 0, prec); + + if (p != NULL) { + size = p - cp; + if (size > prec) + size = prec; + } else + size = prec; + } else + size = strlen(cp); + + break; + case 'U': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'u': + _uquad = UARG(); + base = DEC; + goto nosign; + case 'X': + xdigs = "0123456789ABCDEF"; + goto hex; + case 'x': + xdigs = "0123456789abcdef"; +hex: _uquad = UARG(); + base = HEX; + /* leading 0x/X only if non-zero */ + if (flags & ALT && _uquad != 0) + flags |= HEXPREFIX; + + /* unsigned conversions */ +nosign: sign = '\0'; + /* + * ``... diouXx conversions ... if a precision is + * specified, the 0 flag will be ignored.'' + * -- ANSI X3J11 + */ +number: if ((dprec = prec) >= 0) + flags &= ~ZEROPAD; + + /* + * ``The result of converting a zero value with an + * explicit precision of zero is no characters.'' + * -- ANSI X3J11 + */ + cp = buf + BUF; + if (_uquad != 0 || prec != 0) { + /* + * Unsigned mod is hard, and unsigned mod + * by a constant is easier than that by + * a variable; hence this switch. + */ + switch (base) { + case OCT: + do { + *--cp = to_char(_uquad & 7); + _uquad >>= 3; + } while (_uquad); + /* handle octal leading 0 */ + if (flags & ALT && *cp != '0') + *--cp = '0'; + break; + + case DEC: + /* many numbers are 1 digit */ + while (_uquad >= 10) { + *--cp = to_char(_uquad % 10); + _uquad /= 10; + } + *--cp = to_char(_uquad); + break; + + case HEX: + do { + *--cp = xdigs[_uquad & 15]; + _uquad >>= 4; + } while (_uquad); + break; + + default: + cp = "bug in vfprintf: bad base"; + size = strlen(cp); + goto skipsize; + } + } + /* + * ...result is to be converted to an 'alternate form'. + * For o conversion, it increases the precision to force + * the first digit of the result to be a zero." + * -- ANSI X3J11 + * + * To demonstrate this case, compile and run: + * printf ("%#.0o",0); + */ + else if (base == OCT && (flags & ALT)) + *--cp = '0'; + + size = buf + BUF - cp; + skipsize: + break; + default: /* "%?" prints ?, unless ? is NUL */ + if (ch == '\0') + goto done; + /* pretend it was %c with argument ch */ + cp = buf; + *cp = ch; + size = 1; + sign = '\0'; + break; + } + + /* + * All reasonable formats wind up here. At this point, `cp' + * points to a string which (if not flags&LADJUST) should be + * padded out to `width' places. If flags&ZEROPAD, it should + * first be prefixed by any sign or other prefix; otherwise, + * it should be blank padded before the prefix is emitted. + * After any left-hand padding and prefixing, emit zeroes + * required by a decimal [diouxX] precision, then print the + * string proper, then emit zeroes required by any leftover + * floating precision; finally, if LADJUST, pad with blanks. + * + * Compute actual size, so we know how much to pad. + * size excludes decimal prec; realsz includes it. + */ + realsz = dprec > size ? dprec : size; + if (sign) + realsz++; + else if (flags & HEXPREFIX) + realsz+= 2; + + /* right-adjusting blank padding */ + if ((flags & (LADJUST|ZEROPAD)) == 0) + PAD(width - realsz, blanks, fp); + + /* prefix */ + if (sign) { + PRINT(&sign, 1, fp); + } else if (flags & HEXPREFIX) { + ox[0] = '0'; + ox[1] = ch; + PRINT(ox, 2 ,fp); + } + + /* right-adjusting zero padding */ + if ((flags & (LADJUST|ZEROPAD)) == ZEROPAD) + PAD(width - realsz, zeroes, fp); + + /* leading zeroes from decimal precision */ + PAD(dprec - size, zeroes, fp); + + /* the string or number proper */ +#ifdef FLOATING_POINT + if ((flags & FPT) == 0) { + PRINT(cp, size, fp); + } else { /* glue together f_p fragments */ + if (ch >= 'f') { /* 'f' or 'g' */ + if (_fpvalue == 0) { + /* kludge for __dtoa irregularity */ + PRINT("0", 1, fp); + if (expt < ndig || (flags & ALT) != 0) { + PRINT(decimal_point, 1, fp); + PAD(ndig - 1, zeroes, fp); + } + } else if (expt <= 0) { + PRINT("0", 1, fp); + if(expt || ndig) { + PRINT(decimal_point, 1, fp); + PAD(-expt, zeroes, fp); + PRINT(cp, ndig, fp); + } + } else if (expt >= ndig) { + PRINT(cp, ndig, fp); + PAD(expt - ndig, zeroes, fp); + if (flags & ALT) + PRINT(".", 1, fp); + } else { + PRINT(cp, expt, fp); + cp += expt; + PRINT(".", 1, fp); + PRINT(cp, ndig-expt, fp); + } + } else { /* 'e' or 'E' */ + if (ndig > 1 || flags & ALT) { + ox[0] = *cp++; + ox[1] = '.'; + PRINT(ox, 2, fp); + if (_fpvalue) { + PRINT(cp, ndig-1, fp); + } else /* 0.[0..] */ + /* __dtoa irregularity */ + PAD(ndig - 1, zeroes, fp); + } else /* XeYYY */ + PRINT(cp, 1, fp); + PRINT(expstr, expsize, fp); + } + } +#else + PRINT(cp, size, fp); +#endif + /* left-adjusting padding (always blank) */ + if (flags & LADJUST) + PAD(width - realsz, blanks, fp); + + /* finally, adjust ret */ + ret += width > realsz ? width : realsz; + + FLUSH(); /* copy out the I/O vectors */ + +#ifndef _SMALL_PRINTF + if (malloc_buf != NULL) { + free(malloc_buf); + malloc_buf = NULL; + } +#endif + } +done: + FLUSH(); +error: + +#ifndef _SMALL_PRINTF + if (malloc_buf != NULL) + free(malloc_buf); + return (__sferror(fp) ? EOF : ret); +#else + return ret; +#endif + /* NOTREACHED */ +} + +#ifdef FLOATING_POINT + +#ifdef _NO_LONGDBL +extern char *_dtoa_r _PARAMS((struct _reent *, double, int, + int, int *, int *, char **)); +#else +extern char *_ldtoa_r _PARAMS((struct _reent *, _LONG_DOUBLE, int, + int, int *, int *, char **)); +#undef word0 +#define word0(x) ldword0(x) +#endif + +static char * +cvt(data, value, ndigits, flags, sign, decpt, ch, length) + struct _reent *data; +#ifdef _NO_LONGDBL + double value; +#else + _LONG_DOUBLE value; +#endif + int ndigits, flags, *decpt, ch, *length; + char *sign; +{ + int mode, dsgn; + char *digits, *bp, *rve; +#ifdef _NO_LONGDBL + union double_union tmp; +#else + struct ldieee *ldptr; +#endif + + if (ch == 'f') { + mode = 3; /* ndigits after the decimal point */ + } else { + /* To obtain ndigits after the decimal point for the 'e' + * and 'E' formats, round to ndigits + 1 significant + * figures. + */ + if (ch == 'e' || ch == 'E') { + ndigits++; + } + mode = 2; /* ndigits significant digits */ + } + +#ifdef _NO_LONGDBL + tmp.d = value; + + if (word0(tmp) & Sign_bit) { /* this will check for < 0 and -0.0 */ + value = -value; + *sign = '-'; + } else + *sign = '\000'; + + digits = _dtoa_r(data, value, mode, ndigits, decpt, &dsgn, &rve); +#else /* !_NO_LONGDBL */ + ldptr = (struct ldieee *)&value; + if (ldptr->sign) { /* this will check for < 0 and -0.0 */ + value = -value; + *sign = '-'; + } else + *sign = '\000'; + + digits = _ldtoa_r(data, value, mode, ndigits, decpt, &dsgn, &rve); +#endif /* !_NO_LONGDBL */ + + if ((ch != 'g' && ch != 'G') || flags & ALT) { /* Print trailing zeros */ + bp = digits + ndigits; + if (ch == 'f') { + if (*digits == '0' && value) + *decpt = -ndigits + 1; + bp += *decpt; + } + if (value == 0) /* kludge for __dtoa irregularity */ + rve = bp; + while (rve < bp) + *rve++ = '0'; + } + *length = rve - digits; + return (digits); +} + +static int +exponent(p0, exp, fmtch) + char *p0; + int exp, fmtch; +{ + register char *p, *t; + char expbuf[40]; + + p = p0; + *p++ = fmtch; + if (exp < 0) { + exp = -exp; + *p++ = '-'; + } + else + *p++ = '+'; + t = expbuf + 40; + if (exp > 9) { + do { + *--t = to_char(exp % 10); + } while ((exp /= 10) > 9); + *--t = to_char(exp); + for (; t < expbuf + 40; *p++ = *t++); + } + else { + *p++ = '0'; + *p++ = to_char(exp); + } + return (p - p0); +} +#endif /* FLOATING_POINT */ + + +#ifndef _NO_POS_ARGS + +/* Positional argument support. + Written by Jeff Johnston + + Copyright (c) 2002 Red Hat Incorporated. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + The name of Red Hat Incorporated may not be used to endorse + or promote products derived from this software without specific + prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + +typedef enum { + ZERO, /* '0' */ + DIGIT, /* '1-9' */ + DOLLAR, /* '$' */ + MODFR, /* spec modifier */ + SPEC, /* format specifier */ + DOT, /* '.' */ + STAR, /* '*' */ + FLAG, /* format flag */ + OTHER, /* all other chars */ + MAX_CH_CLASS /* place-holder */ +} CH_CLASS; + +typedef enum { + START, /* start */ + SFLAG, /* seen a flag */ + WDIG, /* seen digits in width area */ + WIDTH, /* processed width */ + SMOD, /* seen spec modifier */ + SDOT, /* seen dot */ + VARW, /* have variable width specifier */ + VARP, /* have variable precision specifier */ + PREC, /* processed precision */ + VWDIG, /* have digits in variable width specification */ + VPDIG, /* have digits in variable precision specification */ + DONE, /* done */ + MAX_STATE, /* place-holder */ +} STATE; + +typedef enum { + NOOP, /* do nothing */ + NUMBER, /* build a number from digits */ + SKIPNUM, /* skip over digits */ + GETMOD, /* get and process format modifier */ + GETARG, /* get and process argument */ + GETPW, /* get variable precision or width */ + GETPWB, /* get variable precision or width and pushback fmt char */ + GETPOS, /* get positional parameter value */ + PWPOS, /* get positional parameter value for variable width or precision */ +} ACTION; + +const static CH_CLASS chclass[256] = { + /* 00-07 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 08-0f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 10-17 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 18-1f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 20-27 */ FLAG, OTHER, OTHER, FLAG, DOLLAR, OTHER, OTHER, OTHER, + /* 28-2f */ OTHER, OTHER, STAR, FLAG, OTHER, FLAG, DOT, OTHER, + /* 30-37 */ ZERO, DIGIT, DIGIT, DIGIT, DIGIT, DIGIT, DIGIT, DIGIT, + /* 38-3f */ DIGIT, DIGIT, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 40-47 */ OTHER, OTHER, OTHER, SPEC, SPEC, SPEC, OTHER, SPEC, + /* 48-4f */ OTHER, OTHER, OTHER, OTHER, MODFR, OTHER, OTHER, SPEC, + /* 50-57 */ OTHER, OTHER, OTHER, SPEC, OTHER, SPEC, OTHER, SPEC, + /* 58-5f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 60-67 */ OTHER, OTHER, OTHER, SPEC, SPEC, SPEC, SPEC, SPEC, + /* 68-6f */ MODFR, SPEC, OTHER, OTHER, MODFR, OTHER, OTHER, SPEC, + /* 70-77 */ SPEC, MODFR, OTHER, SPEC, OTHER, SPEC, OTHER, OTHER, + /* 78-7f */ SPEC, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 80-87 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 88-8f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 90-97 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 98-9f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* a0-a7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* a8-af */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* b0-b7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* b8-bf */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* c0-c7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* c8-cf */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* d0-d7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* d8-df */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* e0-e7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* e8-ef */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* f0-f7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* f8-ff */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, +}; + +const static STATE state_table[MAX_STATE][MAX_CH_CLASS] = { + /* '0' '1-9' '$' MODFR SPEC '.' '*' FLAG OTHER */ + /* START */ { SFLAG, WDIG, DONE, SMOD, DONE, SDOT, VARW, SFLAG, DONE }, + /* SFLAG */ { SFLAG, WDIG, DONE, SMOD, DONE, SDOT, VARW, SFLAG, DONE }, + /* WDIG */ { DONE, DONE, WIDTH, SMOD, DONE, SDOT, DONE, DONE, DONE }, + /* WIDTH */ { DONE, DONE, DONE, SMOD, DONE, SDOT, DONE, DONE, DONE }, + /* SMOD */ { DONE, DONE, DONE, DONE, DONE, DONE, DONE, DONE, DONE }, + /* SDOT */ { SDOT, PREC, DONE, SMOD, DONE, DONE, VARP, DONE, DONE }, + /* VARW */ { DONE, VWDIG, DONE, SMOD, DONE, SDOT, DONE, DONE, DONE }, + /* VARP */ { DONE, VPDIG, DONE, SMOD, DONE, DONE, DONE, DONE, DONE }, + /* PREC */ { DONE, DONE, DONE, SMOD, DONE, DONE, DONE, DONE, DONE }, + /* VWDIG */ { DONE, DONE, WIDTH, DONE, DONE, DONE, DONE, DONE, DONE }, + /* VPDIG */ { DONE, DONE, PREC, DONE, DONE, DONE, DONE, DONE, DONE }, +}; + +const static ACTION action_table[MAX_STATE][MAX_CH_CLASS] = { + /* '0' '1-9' '$' MODFR SPEC '.' '*' FLAG OTHER */ + /* START */ { NOOP, NUMBER, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* SFLAG */ { NOOP, NUMBER, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* WDIG */ { NOOP, NOOP, GETPOS, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* WIDTH */ { NOOP, NOOP, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* SMOD */ { NOOP, NOOP, NOOP, NOOP, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* SDOT */ { NOOP, SKIPNUM, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* VARW */ { NOOP, NUMBER, NOOP, GETPW, GETPWB, GETPW, NOOP, NOOP, NOOP }, + /* VARP */ { NOOP, NUMBER, NOOP, GETPW, GETPWB, NOOP, NOOP, NOOP, NOOP }, + /* PREC */ { NOOP, NOOP, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* VWDIG */ { NOOP, NOOP, PWPOS, NOOP, NOOP, NOOP, NOOP, NOOP, NOOP }, + /* VPDIG */ { NOOP, NOOP, PWPOS, NOOP, NOOP, NOOP, NOOP, NOOP, NOOP }, +}; + +/* function to get positional parameter N where n = N - 1 */ +static union arg_val * +get_arg (struct _reent *data, int n, char *fmt, va_list *ap, + int *numargs_p, union arg_val *args, + int *arg_type, char **last_fmt) +{ + int ch; + int number, flags; + int spec_type; + int numargs = *numargs_p; + CH_CLASS chtype; + STATE state, next_state; + ACTION action; + int pos, last_arg; + int max_pos_arg = n; + enum types { INT, LONG_INT, SHORT_INT, QUAD_INT, CHAR, CHAR_PTR, DOUBLE, LONG_DOUBLE, WIDE_CHAR }; +#ifdef MB_CAPABLE + wchar_t wc; + mbstate_t wc_state; + int nbytes; +#endif + + /* if this isn't the first call, pick up where we left off last time */ + if (*last_fmt != NULL) + fmt = *last_fmt; + +#ifdef MB_CAPABLE + memset (&wc_state, '\0', sizeof (wc_state)); +#endif + + /* we need to process either to end of fmt string or until we have actually + read the desired parameter from the vararg list. */ + while (*fmt && n >= numargs) + { +#ifdef MB_CAPABLE + while ((nbytes = _mbtowc_r(data, &wc, fmt, MB_CUR_MAX, &wc_state)) > 0) + { + fmt += nbytes; + if (wc == '%') + break; + } + + if (nbytes <= 0) + break; +#else + while (*fmt != '\0' && *fmt != '%') + fmt += 1; + + if (*fmt == '\0') + break; +#endif + state = START; + flags = 0; + pos = -1; + number = 0; + spec_type = INT; + + /* Use state/action table to process format specifiers. We ignore invalid + formats and we are only interested in information that tells us how to + read the vararg list. */ + while (state != DONE) + { + ch = *fmt++; + chtype = chclass[ch]; + next_state = state_table[state][chtype]; + action = action_table[state][chtype]; + state = next_state; + + switch (action) + { + case GETMOD: /* we have format modifier */ + switch (ch) + { + case 'h': + flags |= SHORTINT; + break; + case 'L': + flags |= LONGDBL; + break; + case 'q': + flags |= QUADINT; + break; + case 'l': + default: + if (*fmt == 'l') + { + flags |= QUADINT; + ++fmt; + } + else + flags |= LONGINT; + break; + } + break; + case GETARG: /* we have format specifier */ + { + numargs &= (MAX_POS_ARGS - 1); + /* process the specifier and translate it to a type to fetch from varargs */ + switch (ch) + { + case 'd': + case 'i': + case 'o': + case 'x': + case 'X': + case 'u': + if (flags & LONGINT) + spec_type = LONG_INT; + else if (flags & SHORTINT) + spec_type = SHORT_INT; +#ifndef _NO_LONGLONG + else if (flags & QUADINT) + spec_type = QUAD_INT; +#endif + else + spec_type = INT; + break; + case 'D': + case 'U': + case 'O': + spec_type = LONG_INT; + break; + case 'f': + case 'g': + case 'G': + case 'E': + case 'e': +#ifndef _NO_LONGDBL + if (flags & LONGDBL) + spec_type = LONG_DOUBLE; + else +#endif + spec_type = DOUBLE; + break; + case 's': + case 'S': + case 'p': + spec_type = CHAR_PTR; + break; + case 'c': + spec_type = CHAR; + break; + case 'C': + spec_type = WIDE_CHAR; + break; + } + + /* if we have a positional parameter, just store the type, otherwise + fetch the parameter from the vararg list */ + if (pos != -1) + arg_type[pos] = spec_type; + else + { + switch (spec_type) + { + case LONG_INT: + args[numargs++].val_long = va_arg(*ap, long); + break; + case QUAD_INT: + args[numargs++].val_quad_t = va_arg(*ap, quad_t); + break; + case WIDE_CHAR: + args[numargs++].val_wint_t = va_arg(*ap, wint_t); + break; + case CHAR: + case SHORT_INT: + case INT: + args[numargs++].val_int = va_arg(*ap, int); + break; + case CHAR_PTR: + args[numargs++].val_char_ptr_t = va_arg(*ap, char *); + break; + case DOUBLE: + args[numargs++].val_double = va_arg(*ap, double); + break; + case LONG_DOUBLE: + args[numargs++].val__LONG_DOUBLE = va_arg(*ap, _LONG_DOUBLE); + break; + } + } + } + break; + case GETPOS: /* we have positional specifier */ + if (arg_type[0] == -1) + memset (arg_type, 0, sizeof(int) * MAX_POS_ARGS); + pos = number - 1; + max_pos_arg = (max_pos_arg > pos ? max_pos_arg : pos); + break; + case PWPOS: /* we have positional specifier for width or precision */ + if (arg_type[0] == -1) + memset (arg_type, 0, sizeof(int) * MAX_POS_ARGS); + number -= 1; + arg_type[number] = INT; + max_pos_arg = (max_pos_arg > number ? max_pos_arg : number); + break; + case GETPWB: /* we require format pushback */ + --fmt; + /* fallthrough */ + case GETPW: /* we have a variable precision or width to acquire */ + args[numargs++].val_int = va_arg(*ap, int); + break; + case NUMBER: /* we have a number to process */ + number = (ch - '0'); + while ((ch = *fmt) != '\0' && is_digit(ch)) + { + number = number * 10 + (ch - '0'); + ++fmt; + } + break; + case SKIPNUM: /* we have a number to skip */ + while ((ch = *fmt) != '\0' && is_digit(ch)) + ++fmt; + break; + case NOOP: + default: + break; /* do nothing */ + } + } + } + + /* process all arguments up to at least the one we are looking for and if we + have seen the end of the string, then process up to the max argument needed */ + if (*fmt == '\0') + last_arg = max_pos_arg; + else + last_arg = n; + + while (numargs <= last_arg) + { + switch (arg_type[numargs]) + { + case LONG_INT: + args[numargs++].val_long = va_arg(*ap, long); + break; + case QUAD_INT: + args[numargs++].val_quad_t = va_arg(*ap, quad_t); + break; + case CHAR_PTR: + args[numargs++].val_char_ptr_t = va_arg(*ap, char *); + break; + case DOUBLE: + args[numargs++].val_double = va_arg(*ap, double); + break; + case LONG_DOUBLE: + args[numargs++].val__LONG_DOUBLE = va_arg(*ap, _LONG_DOUBLE); + break; + case WIDE_CHAR: + args[numargs++].val_wint_t = va_arg(*ap, wint_t); + break; + case INT: + case SHORT_INT: + case CHAR: + default: + args[numargs++].val_int = va_arg(*ap, int); + break; + } + } + + /* alter the global numargs value and keep a reference to the last bit of the fmt + string we processed here because the caller will continue processing where we started */ + *numargs_p = numargs; + *last_fmt = fmt; + return &args[n]; +} +#endif /* !_NO_POS_ARGS */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/floatio.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/floatio.h new file mode 100644 index 000000000..496721b88 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/floatio.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * %W% (Berkeley) %G% + */ + +/* + * Floating point scanf/printf (input/output) definitions. + */ + +#ifdef _NO_LONGDBL +/* 11-bit exponent (VAX G floating point) is 308 decimal digits */ +#define MAXEXP 308 +#else /* !_NO_LONGDBL */ +/* 15-bit exponent (Intel extended floating point) is 4932 decimal digits */ +#define MAXEXP 4932 +#endif /* !_NO_LONGDBL */ +/* 128 bit fraction takes up 39 decimal digits; max reasonable precision */ +#define MAXFRACT 39 diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/fvwrite.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/fvwrite.h new file mode 100644 index 000000000..f27abdf81 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/fvwrite.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* %W% (Berkeley) %G% */ +#include <_ansi.h> + +/* + * I/O descriptors for __sfvwrite(). + */ +struct __siov { + _CONST _PTR iov_base; + size_t iov_len; +}; +struct __suio { + struct __siov *uio_iov; + int uio_iovcnt; + int uio_resid; +}; + + +extern int _EXFUN(__sfvwrite,(FILE *, struct __suio *)); +extern int _EXFUN(__swsetup,(FILE *)); + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/local.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/local.h new file mode 100644 index 000000000..b4f4457fc --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/local.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * %W% (UofMD/Berkeley) %G% + */ + +/* + * Information local to this implementation of stdio, + * in particular, macros and private variables. + */ + +#include <_ansi.h> +#include +#include +#include + +extern int _EXFUN(__svfscanf_r,(struct _reent *,FILE *, _CONST char *,va_list)); +extern FILE *_EXFUN(__sfp,(struct _reent *)); +extern int _EXFUN(__sflags,(struct _reent *,_CONST char*, int*)); +extern int _EXFUN(__srefill,(FILE *)); +extern _READ_WRITE_RETURN_TYPE _EXFUN(__sread,(void *, char *, int)); +extern _READ_WRITE_RETURN_TYPE _EXFUN(__swrite,(void *, char const *, int)); +extern _fpos_t _EXFUN(__sseek,(void *, _fpos_t, int)); +extern int _EXFUN(__sclose,(void *)); +extern int _EXFUN(__stextmode,(int)); +extern void _EXFUN(__sinit,(struct _reent *)); +extern void _EXFUN(_cleanup_r,(struct _reent *)); +extern void _EXFUN(__smakebuf,(FILE *)); +extern int _EXFUN(_fwalk,(struct _reent *, int (*)(FILE *))); +struct _glue * _EXFUN(__sfmoreglue,(struct _reent *,int n)); +extern int _EXFUN(__srefill,(FILE *fp)); + +/* Called by the main entry point fns to ensure stdio has been initialized. */ + +#define CHECK_INIT(fp) \ + do \ + { \ + if (!_REENT->__sdidinit) \ + __sinit (_REENT); \ + } \ + while (0) + +/* Return true iff the given FILE cannot be written now. */ + +#define cantwrite(fp) \ + ((((fp)->_flags & __SWR) == 0 || (fp)->_bf._base == NULL) && \ + __swsetup(fp)) + +/* Test whether the given stdio file has an active ungetc buffer; + release such a buffer, without restoring ordinary unread data. */ + +#define HASUB(fp) ((fp)->_ub._base != NULL) +#define FREEUB(fp) { \ + if ((fp)->_ub._base != (fp)->_ubuf) \ + _free_r(_REENT, (char *)(fp)->_ub._base); \ + (fp)->_ub._base = NULL; \ +} + +/* Test for an fgetline() buffer. */ + +#define HASLB(fp) ((fp)->_lb._base != NULL) +#define FREELB(fp) { _free_r(_REENT,(char *)(fp)->_lb._base); (fp)->_lb._base = NULL; } + +/* WARNING: _dcvt is defined in the stdlib directory, not here! */ + +char *_EXFUN(_dcvt,(struct _reent *, char *, double, int, int, char, int)); +char *_EXFUN(_sicvt,(char *, short, char)); +char *_EXFUN(_icvt,(char *, int, char)); +char *_EXFUN(_licvt,(char *, long, char)); +#ifdef __GNUC__ +char *_EXFUN(_llicvt,(char *, long long, char)); +#endif + +#define CVT_BUF_SIZE 128 + +#define NDYNAMIC 4 /* add four more whenever necessary */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/mbctype.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/mbctype.h new file mode 100644 index 000000000..6abcf3db0 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/mbctype.h @@ -0,0 +1,20 @@ +#ifndef _MBCTYPE_H_ + +#define _MBCTYPE_H_ + +/* escape character used for JIS encoding */ +#define ESC_CHAR 0x1b + +/* functions used to support SHIFT_JIS, EUC-JP, and JIS multibyte encodings */ + +int _EXFUN(_issjis1, (int c)); +int _EXFUN(_issjis2, (int c)); +int _EXFUN(_iseucjp, (int c)); +int _EXFUN(_isjis, (int c)); + +#define _issjis1(c) (((c) >= 0x81 && (c) <= 0x9f) || ((c) >= 0xe0 && (c) <= 0xef)) +#define _issjis2(c) (((c) >= 0x40 && (c) <= 0x7e) || ((c) >= 0x80 && (c) <= 0xfc)) +#define _iseucjp(c) ((c) >= 0xa1 && (c) <= 0xfe) +#define _isjis(c) ((c) >= 0x21 && (c) <= 0x7e) + +#endif /* _MBCTYPE_H_ */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/scanf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/scanf.c new file mode 100644 index 000000000..b05c31706 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/scanf.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include <_ansi.h> +#include +#include "local.h" + +#ifdef _HAVE_STDC +#include +#else +#include +#endif + +#ifndef _REENT_ONLY + +int +#ifdef _HAVE_STDC +scanf (const char *fmt, ...) +#else +scanf (fmt, va_alist) + char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdin_r (_REENT)); +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = __svfscanf_r (_REENT, _stdin_r (_REENT), fmt, ap); + va_end (ap); + return ret; +} + +#endif /* !_REENT_ONLY */ + +int +#ifdef _HAVE_STDC +_scanf_r (struct _reent *ptr, const char *fmt, ...) +#else +_scanf_r (ptr, fmt, va_alist) + struct _reent *ptr; + char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdin_r (ptr)); +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = __svfscanf_r (ptr, _stdin_r (ptr), fmt, ap); + va_end (ap); + return (ret); +} + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_dtoa.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_dtoa.c new file mode 100644 index 000000000..b83e5d653 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_dtoa.c @@ -0,0 +1,1174 @@ +/**************************************************************** + * + * The author of this software is David M. Gay. + * + * Copyright (c) 1991 by AT&T. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose without fee is hereby granted, provided that this entire notice + * is included in all copies of any software which is or includes a copy + * or modification of this software and in all copies of the supporting + * documentation for such software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY + * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + * + ***************************************************************/ + +/* Please send bug reports to + David M. Gay + AT&T Bell Laboratories, Room 2C-463 + 600 Mountain Avenue + Murray Hill, NJ 07974-2070 + U.S.A. + dmg@research.att.com or research!dmg + */ + + +#ifndef _SMALL_PRINTF + +#define small_lo0bits lo0bits +#define small_hi0bits hi0bits +#define small_i2b i2b +#define small_cmp cmp +#define small_ulp ulp +#define small_b2d b2d +#define small_d2b d2b +#define small_ratio ratio + +#define small_tens tens +#define small_bigtens bigtens +#define small_tinytens tinytens + +#endif + + + + + +#include <_ansi.h> +#include + +#ifndef _SMALL_PRINTF +#include +#endif + +#include +#include "small_mprec.h" + +static int +_DEFUN (quorem, + (b, S), + _Bigint * b _AND _Bigint * S) +{ + int n; + __Long borrow, y; + __ULong carry, q, ys; + __ULong *bx, *bxe, *sx, *sxe; +#ifdef Pack_32 + __Long z; + __ULong si, zs; +#endif + + n = S->_wds; +#ifdef DEBUG + /*debug*/ if (b->_wds > n) + /*debug*/ Bug ("oversize b in quorem"); +#endif + if (b->_wds < n) + return 0; + sx = S->_x; + sxe = sx + --n; + bx = b->_x; + bxe = bx + n; + q = *bxe / (*sxe + 1); /* ensure q <= true quotient */ +#ifdef DEBUG + /*debug*/ if (q > 9) + /*debug*/ Bug ("oversized quotient in quorem"); +#endif + if (q) + { + borrow = 0; + carry = 0; + do + { +#ifdef Pack_32 + si = *sx++; + ys = (si & 0xffff) * q + carry; + zs = (si >> 16) * q + (ys >> 16); + carry = zs >> 16; + y = (*bx & 0xffff) - (ys & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + z = (*bx >> 16) - (zs & 0xffff) + borrow; + borrow = z >> 16; + Sign_Extend (borrow, z); + Storeinc (bx, z, y); +#else + ys = *sx++ * q + carry; + carry = ys >> 16; + y = *bx - (ys & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + *bx++ = y & 0xffff; +#endif + } + while (sx <= sxe); + if (!*bxe) + { + bx = b->_x; + while (--bxe > bx && !*bxe) + --n; + b->_wds = n; + } + } + + if (small_cmp (b, S) >= 0) + { + q++; + borrow = 0; + carry = 0; + bx = b->_x; + sx = S->_x; + do + { +#ifdef Pack_32 + si = *sx++; + ys = (si & 0xffff) + carry; + zs = (si >> 16) + (ys >> 16); + carry = zs >> 16; + y = (*bx & 0xffff) - (ys & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + z = (*bx >> 16) - (zs & 0xffff) + borrow; + borrow = z >> 16; + Sign_Extend (borrow, z); + Storeinc (bx, z, y); +#else + ys = *sx++ + carry; + carry = ys >> 16; + y = *bx - (ys & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + *bx++ = y & 0xffff; +#endif + } + while (sx <= sxe); + bx = b->_x; + bxe = bx + n; + if (!*bxe) + { + while (--bxe > bx && !*bxe) + --n; + b->_wds = n; + } + } + return q; +} + +/* dtoa for IEEE arithmetic (dmg): convert double to ASCII string. + * + * Inspired by "How to Print Floating-Point Numbers Accurately" by + * Guy L. Steele, Jr. and Jon L. White [Proc. ACM SIGPLAN '90, pp. 92-101]. + * + * Modifications: + * 1. Rather than iterating, we use a simple numeric overestimate + * to determine k = floor(log10(d)). We scale relevant + * quantities using O(log2(k)) rather than O(k) multiplications. + * 2. For some modes > 2 (corresponding to ecvt and fcvt), we don't + * try to generate digits strictly left to right. Instead, we + * compute with fewer bits and propagate the carry if necessary + * when rounding the final digit up. This is often faster. + * 3. Under the assumption that input will be rounded nearest, + * mode 0 renders 1e23 as 1e23 rather than 9.999999999999999e22. + * That is, we allow equality in stopping tests when the + * round-nearest rule will give the same floating-point value + * as would satisfaction of the stopping test with strict + * inequality. + * 4. We remove common factors of powers of 2 from relevant + * quantities. + * 5. When converting floating-point integers less than 1e16, + * we use floating-point arithmetic rather than resorting + * to multiple-precision integers. + * 6. When asked to produce fewer than 15 digits, we first try + * to get by with floating-point arithmetic; we resort to + * multiple-precision integer arithmetic only if we cannot + * guarantee that the floating-point calculation has given + * the correctly rounded result. For k requested digits and + * "uniformly" distributed input, the probability is + * something like 10^(k-15) that we must resort to the long + * calculation. + */ + + + /* Scanf and printf call both the small_mprec.c file if small_printf + * has not been specfied optimizations concerning small_mprec.c and + * call of balloc will be performed anyway for printf. + */ + +#ifdef SMALL_SCANF +#ifndef _SMALL_PRINTF +#define _SMALL_PRINTF +#endif +#endif + + + +char * +_DEFUN (_dtoa_r, + (ptr, _d, mode, ndigits, decpt, sign, rve), + struct _reent *ptr _AND + double _d _AND + int mode _AND + int ndigits _AND + int *decpt _AND + int *sign _AND + char **rve) +{ + /* Arguments ndigits, decpt, sign are similar to those + of ecvt and fcvt; trailing zeros are suppressed from + the returned string. If not null, *rve is set to point + to the end of the return value. If d is +-Infinity or NaN, + then *decpt is set to 9999. + + mode: + 0 ==> shortest string that yields d when read in + and rounded to nearest. + 1 ==> like 0, but with Steele & White stopping rule; + e.g. with IEEE P754 arithmetic , mode 0 gives + 1e23 whereas mode 1 gives 9.999999999999999e22. + 2 ==> max(1,ndigits) significant digits. This gives a + return value similar to that of ecvt, except + that trailing zeros are suppressed. + 3 ==> through ndigits past the decimal point. This + gives a return value similar to that from fcvt, + except that trailing zeros are suppressed, and + ndigits can be negative. + 4-9 should give the same return values as 2-3, i.e., + 4 <= mode <= 9 ==> same return as mode + 2 + (mode & 1). These modes are mainly for + debugging; often they run slower but sometimes + faster than modes 2-3. + 4,5,8,9 ==> left-to-right digit generation. + 6-9 ==> don't try fast floating-point estimate + (if applicable). + + Values of mode other than 0-9 are treated as mode 0. + + Sufficient space is allocated to the return value + to hold the suppressed trailing zeros. + */ + + int bbits, b2, b5, be, dig, i, ieps, ilim, ilim0, ilim1, j, j1, k, k0, + k_check, leftright, m2, m5, s2, s5, spec_case, try_quick; + union double_union d, d2, eps; + __Long L; +#ifndef Sudden_Underflow + int denorm; + __ULong x; +#endif + _Bigint *b, *b1, *delta, *mlo = NULL, *mhi, *S; + double ds; + #ifndef _SMALL_PRINTF + char *s, *s0; + + #else //Declarations for SMALL_PRINTF + + /* + * SIZE have been chosen regarding size allocated by default printf it seems that most of time 32 is sufficient except + * for lshift that allocated 40 + * Nevertheless for some examples greater buffer size can be usefull. + */ + + #define BUF_LSHIFT_SIZE 40// Size of each buffer for variables of _Bigint type + #define BUF_SIZE 32 + #define S0_SIZE 32 // Size of the buffer result that will be provided by _dtoa_r + + /* + * For the SMALL_PRINTF implementation for floating points numbers : + * - To avoid the call of allocator we defined a buffer for each variable : instead of taking the adress + * provided by Balloc variables are initialized to the beginning of the array. + * - For some variables many buffers have been declared, in fact for each call of small_lshift we used a + * buffer that has not been used at the moment + * - This buffers are used in the call of function declared in small_mprec.h + * To have more informations look at small_mprec.c + */ + +_Bigint tab_b[BUF_LSHIFT_SIZE],tab_b1[BUF_SIZE],tab_delta[BUF_SIZE],tab_mlo[BUF_SIZE],tab_mhi[BUF_LSHIFT_SIZE],tab_S[BUF_LSHIFT_SIZE]; +_Bigint tab_blshift[BUF_LSHIFT_SIZE],tab_Slshift[BUF_LSHIFT_SIZE],tab_mhilshift[BUF_LSHIFT_SIZE],tab_mlolshift[BUF_LSHIFT_SIZE]; + char tab_s0[S0_SIZE]; + char *s, *s0; + #endif //Declarations for SMALL_PRINTF + + d.d = _d; +#ifndef _SMALL_PRINTF + _REENT_CHECK_MP(ptr); + if (_REENT_MP_RESULT(ptr)) + { + _REENT_MP_RESULT(ptr)->_k = _REENT_MP_RESULT_K(ptr); + _REENT_MP_RESULT(ptr)->_maxwds = 1 << _REENT_MP_RESULT_K(ptr); + Bfree (ptr, _REENT_MP_RESULT(ptr)); + _REENT_MP_RESULT(ptr) = 0; + } + #endif + if (word0 (d) & Sign_bit) + { + /* set sign for everything, including 0's and NaNs */ + *sign = 1; + word0 (d) &= ~Sign_bit; /* clear sign bit */ + } + else + *sign = 0; + +#if defined(IEEE_Arith) + defined(VAX) +#ifdef IEEE_Arith + if ((word0 (d) & Exp_mask) == Exp_mask) +#else + if (word0 (d) == 0x8000) +#endif + { + /* Infinity or NaN */ + *decpt = 9999; + s = +#ifdef IEEE_Arith + !word1 (d) && !(word0 (d) & 0xfffff) ? "Infinity" : +#endif + "NaN"; + if (rve) + *rve = +#ifdef IEEE_Arith + s[3] ? s + 8 : +#endif + s + 3; + + + return s; + } + +#ifdef IBM + d.d += 0; /* normalize */ +#endif + if (!d.d) + { + *decpt = 1; + s = "0"; + if (rve) + *rve = s + 1; + + return s; + } + #ifdef _SMALL_PRINTF + b = small_d2b (ptr, d.d, &be, &bbits,&tab_b[0]); + #else + b = small_d2b (ptr, d.d, &be, &bbits); + #endif + +#ifdef Sudden_Underflow + i = (int) (word0 (d) >> Exp_shift1 & (Exp_mask >> Exp_shift1)); +#else + if ((i = (int) (word0 (d) >> Exp_shift1 & (Exp_mask >> Exp_shift1))) != 0) + { +#endif + d2.d = d.d; + word0 (d2) &= Frac_mask1; + word0 (d2) |= Exp_11; +#ifdef IBM + if (j = 11 - hi0bits (word0 (d2) & Frac_mask)) + d2.d /= 1 << j; +#endif + + /* log(x) ~=~ log(1.5) + (x-1.5)/1.5 + * log10(x) = log(x) / log(10) + * ~=~ log(1.5)/log(10) + (x-1.5)/(1.5*log(10)) + * log10(d) = (i-Bias)*log(2)/log(10) + log10(d2) + * + * This suggests computing an approximation k to log10(d) by + * + * k = (i - Bias)*0.301029995663981 + * + ( (d2-1.5)*0.289529654602168 + 0.176091259055681 ); + * + * We want k to be too large rather than too small. + * The error in the first-order Taylor series approximation + * is in our favor, so we just round up the constant enough + * to compensate for any error in the multiplication of + * (i - Bias) by 0.301029995663981; since |i - Bias| <= 1077, + * and 1077 * 0.30103 * 2^-52 ~=~ 7.2e-14, + * adding 1e-13 to the constant term more than suffices. + * Hence we adjust the constant term to 0.1760912590558. + * (We could get a more accurate k by invoking log10, + * but this is probably not worthwhile.) + */ + + i -= Bias; +#ifdef IBM + i <<= 2; + i += j; +#endif +#ifndef Sudden_Underflow + denorm = 0; + } + else + { + /* d is denormalized */ + + i = bbits + be + (Bias + (P - 1) - 1); + x = (i > 32) ? (word0 (d) << (64 - i)) | (word1 (d) >> (i - 32)) + : (word1 (d) << (32 - i)); + d2.d = x; + word0 (d2) -= 31 * Exp_msk1; /* adjust exponent */ + i -= (Bias + (P - 1) - 1) + 1; + denorm = 1; + } +#endif + ds = (d2.d - 1.5) * 0.289529654602168 + 0.1760912590558 + i * 0.301029995663981; + k = (int) ds; + if (ds < 0. && ds != k) + k--; /* want k = floor(ds) */ + k_check = 1; + if (k >= 0 && k <= Ten_pmax) + { + if (d.d < small_tens[k]) + k--; + k_check = 0; + } + j = bbits - i - 1; + if (j >= 0) + { + b2 = 0; + s2 = j; + } + else + { + b2 = -j; + s2 = 0; + } + if (k >= 0) + { + b5 = 0; + s5 = k; + s2 += k; + } + else + { + b2 -= k; + b5 = -k; + s5 = 0; + } + if (mode < 0 || mode > 9) + mode = 0; + try_quick = 1; + if (mode > 5) + { + mode -= 4; + try_quick = 0; + } + leftright = 1; + ilim = ilim1 = -1; + switch (mode) + { + case 0: + case 1: + i = 18; + ndigits = 0; + break; + case 2: + leftright = 0; + /* no break */ + case 4: + if (ndigits <= 0) + ndigits = 1; + ilim = ilim1 = i = ndigits; + break; + case 3: + leftright = 0; + /* no break */ + case 5: + i = ndigits + k + 1; + ilim = i; + ilim1 = i - 1; + if (i <= 0) + i = 1; + } + j = sizeof (__ULong); + #ifndef _SMALL_PRINTF + for (_REENT_MP_RESULT_K(ptr) = 0; sizeof (_Bigint) - sizeof (__ULong) + j <= i; + j <<= 1) + _REENT_MP_RESULT_K(ptr)++; + _REENT_MP_RESULT(ptr) = Balloc (ptr, _REENT_MP_RESULT_K(ptr)); + s = s0 = (char *) _REENT_MP_RESULT(ptr); + #else + s = s0 = &tab_s0[0]; + #endif + + if (ilim >= 0 && ilim <= Quick_max && try_quick) + { + /* Try to get by with floating-point arithmetic. */ + + i = 0; + d2.d = d.d; + k0 = k; + ilim0 = ilim; + ieps = 2; /* conservative */ + if (k > 0) + { + ds = small_tens[k & 0xf]; + j = k >> 4; + if (j & Bletch) + { + /* prevent overflows */ + j &= Bletch - 1; + d.d /= small_bigtens[n_bigtens - 1]; + ieps++; + } + for (; j; j >>= 1, i++) + if (j & 1) + { + ieps++; + ds *= small_bigtens[i]; + } + d.d /= ds; + } + else if ((j1 = -k) != 0) + { + d.d *= small_tens[j1 & 0xf]; + for (j = j1 >> 4; j; j >>= 1, i++) + if (j & 1) + { + ieps++; + d.d *= small_bigtens[i]; + } + } + if (k_check && d.d < 1. && ilim > 0) + { + if (ilim1 <= 0) + goto fast_failed; + ilim = ilim1; + k--; + d.d *= 10.; + ieps++; + } + eps.d = ieps * d.d + 7.; + word0 (eps) -= (P - 1) * Exp_msk1; + if (ilim == 0) + { + S = mhi = 0; + d.d -= 5.; + if (d.d > eps.d) + goto one_digit; + if (d.d < -eps.d) + goto no_digits; + goto fast_failed; + } +#ifndef No_leftright + if (leftright) + { + /* Use Steele & White method of only + * generating digits needed. + */ + eps.d = 0.5 / small_tens[ilim - 1] - eps.d; + for (i = 0;;) + { + L = d.d; + d.d -= L; + + *s++ = '0' + (int) L; + + if (d.d < eps.d) + goto ret1; + if (1. - d.d < eps.d) + goto bump_up; + if (++i >= ilim) + break; + eps.d *= 10.; + d.d *= 10.; + } + } + else + { +#endif + /* Generate ilim digits, then fix them up. */ + eps.d *= small_tens[ilim - 1]; + for (i = 1;; i++, d.d *= 10.) + { + L = d.d; + d.d -= L; + *s++ = '0' + (int) L; + if (i == ilim) + { + if (d.d > 0.5 + eps.d) + goto bump_up; + else if (d.d < 0.5 - eps.d) + { + while (*--s == '0'); + s++; + goto ret1; + } + break; + } + } +#ifndef No_leftright + } +#endif + fast_failed: + s = s0; + d.d = d2.d; + k = k0; + ilim = ilim0; + } + + /* Do we have a "small" integer? */ + + if (be >= 0 && k <= Int_max) + { + /* Yes. */ + ds = small_tens[k]; + if (ndigits < 0 && ilim <= 0) + { + S = mhi = 0; + if (ilim < 0 || d.d <= 5 * ds) + goto no_digits; + goto one_digit; + } + for (i = 1;; i++) + { + L = d.d / ds; + d.d -= L * ds; +#ifdef Check_FLT_ROUNDS + /* If FLT_ROUNDS == 2, L will usually be high by 1 */ + if (d.d < 0) + { + L--; + d.d += ds; + } +#endif + + *s++ = '0' + (int) L; + + if (i == ilim) + { + d.d += d.d; + if ((d.d > ds) || ((d.d == ds) && (L & 1))) + { + bump_up: + + + + while (*--s == '9') + if (s == s0) + { + k++; + *s = '0'; + break; + } + ++*s++; + + } + break; + } + if (!(d.d *= 10.)) + break; + } + goto ret1; + } + + m2 = b2; + m5 = b5; + mhi = mlo = 0; + if (leftright) + { + if (mode < 2) + { + i = +#ifndef Sudden_Underflow + denorm ? be + (Bias + (P - 1) - 1 + 1) : +#endif +#ifdef IBM + 1 + 4 * P - 3 - bbits + ((bbits + be - 1) & 3); +#else + 1 + P - bbits; +#endif + } + else + { + j = ilim - 1; + if (m5 >= j) + m5 -= j; + else + { + s5 += j -= m5; + b5 += j; + m5 = 0; + } + if ((i = ilim) < 0) + { + m2 -= i; + i = 0; + } + } + b2 += i; + s2 += i; + + #ifdef _SMALL_PRINTF + mhi = small_i2b (ptr, 1,&tab_mhi[0]); + #else + mhi=i2b(ptr,1); + #endif + } + if (m2 > 0 && s2 > 0) + { + i = m2 < s2 ? m2 : s2; + b2 -= i; + m2 -= i; + s2 -= i; + } + if (b5 > 0) + { + if (leftright) + { + if (m5 > 0) + { + #ifdef _SMALL_PRINTF + if (mhi == &tab_mhi[0]){ + mhi = small_pow5mult (ptr, mhi, m5,&tab_mhilshift[0]); + } + else{ + mhi = small_pow5mult (ptr, mhi, m5,&tab_mhi[0]); + } + + b1 = small_mult (ptr, mhi, b,&tab_b1[0]); + #else + mhi = pow5mult (ptr, mhi, m5); + b1 = mult (ptr, mhi, b); + Bfree (ptr, b); + #endif + } + if ((j = b5 - m5) != 0) + #ifdef _SMALL_PRINTF + if( b == &tab_b[0]){ + b = small_pow5mult (ptr, b, b5,&tab_blshift[0]); + } + else{ + b = small_pow5mult (ptr, b, b5,&tab_b[0]); + } + #else + b = pow5mult (ptr, b, j); + #endif + + + + } + else + #ifdef _SMALL_PRINTF + if( b == &tab_b[0]){ + b = small_pow5mult (ptr, b, b5,&tab_blshift[0]); + } + else{ + b = small_pow5mult (ptr, b, b5,&tab_b[0]); + } + + #else + b = pow5mult (ptr, b, b5); + #endif + + } + #ifdef _SMALL_PRINTF + S = small_i2b (ptr, 1,&tab_S[0]); + #else + S = small_i2b (ptr, 1); + #endif + if (s5 > 0) + #ifdef _SMALL_PRINTF + if (S == &tab_S[0]){ + S = small_pow5mult (ptr, S, s5,&tab_Slshift[0]); + } + else{ + S = small_pow5mult (ptr, S, s5,&tab_S[0]); + } + + #else + S = pow5mult (ptr, S, s5); + #endif + + /* Check for special case that d is a normalized power of 2. */ + + spec_case = 0; + if (mode < 2) + { + if (!word1 (d) && !(word0 (d) & Bndry_mask) +#ifndef Sudden_Underflow + && word0 (d) & Exp_mask +#endif + ) + { + /* The special case */ + b2 += Log2P; + s2 += Log2P; + spec_case = 1; + } + } + + /* Arrange for convenient computation of quotients: + * shift left if necessary so divisor has 4 leading 0 bits. + * + * Perhaps we should just compute leading 28 bits of S once + * and for all and pass them and a shift to quorem, so it + * can do shifts and ors to compute the numerator for q. + */ + +#ifdef Pack_32 + if ((i = ((s5 ? 32 -small_hi0bits (S->_x[S->_wds - 1]) : 1) + s2) & 0x1f) != 0) + i = 32 - i; +#else + if ((i = ((s5 ? 32 - small_hi0bits (S->_x[S->_wds - 1]) : 1) + s2) & 0xf) != 0) + i = 16 - i; +#endif + if (i > 4) + { + i -= 4; + b2 += i; + m2 += i; + s2 += i; + } + else if (i < 4) + { + i += 28; + b2 += i; + m2 += i; + s2 += i; + } + if (b2 > 0) + #ifdef _SMALL_PRINTF + if (b==&tab_b[0]){ + b = small_lshift (ptr, b, b2,&tab_blshift[0]); + } + else { + b = small_lshift (ptr, b, b2,&tab_b[0]); + } + #else + b = lshift (ptr, b, b2); + #endif + if (s2 > 0) + #ifdef _SMALL_PRINTF + if ( S == tab_S) { + S = small_lshift (ptr, S, s2,&tab_Slshift[0]); + } + else { + S = small_lshift (ptr, S, s2,&tab_S[0]); + } + #else + S = lshift (ptr, S, s2); + #endif + if (k_check) + { + if (small_cmp (b, S) < 0) + { + k--; /* we botched the k estimate */ + #ifdef _SMALL_PRINTF + if (b == &tab_b[0] ){ + + b = small_multadd (ptr, b, 10, 0,&tab_blshift[0]); + } + else{ + b = small_multadd (ptr, b, 10, 0,&tab_b[0]); + } + #else + b = multadd (ptr, b, 10, 0); + #endif + + + if (leftright) + #ifdef _SMALL_PRINTF + if (mhi == &tab_mhi[0] ){ + + mhi = small_multadd (ptr, mhi, 10, 0,&tab_mhilshift[0]); + } + else{ + mhi = small_multadd (ptr, mhi, 10, 0,&tab_mhi[0]); + } + #else + mhi = multadd (ptr, mhi, 10, 0); + #endif + ilim = ilim1; + } + } + if (ilim <= 0 && mode > 2) + { + #ifdef _SMALL_PRINTF + _Bigint * tab; + if ( S == &tab_S[0] ){ + tab = tab_Slshift; + } + else { + tab = tab_S; + } + + if (ilim < 0 || small_cmp (b, S = small_multadd (ptr, S, 5, 0,&tab[0])) <= 0) + { + #else + if (ilim < 0 || small_cmp (b, S = multadd (ptr, S, 5, 0)) <= 0) + { + #endif + /* no digits, fcvt style */ + no_digits: + k = -1 - ndigits; + goto ret; + } + one_digit: + *s++ = '1'; + k++; + goto ret; + } + if (leftright) + { + if (m2 > 0) + #ifdef _SMALL_PRINTF + if (mhi == &tab_mhi[0]){ + mhi = small_lshift (ptr, mhi, m2,&tab_mhilshift[0]); + } + else { + mhi = small_lshift (ptr, mhi, m2,&tab_mhi[0]); + } + + #else + mhi = lshift (ptr, mhi, m2); + #endif + /* Compute mlo -- check for special case + * that d is a normalized power of 2. + */ + + mlo = mhi; + if (spec_case) + { + #ifndef _SMALL_PRINTF + + mhi = Balloc (ptr, mhi->_k); + + #else + int sauv_k =mhi->_k; + mhi =&tab_mhi[0]; + mhi->_k = sauv_k; + mhi->_maxwds = (1<_sign = mhi->_wds =0 ; + #endif + Bcopy (mhi, mlo); + + #ifdef _SMALL_PRINTF + if( mhi == &tab_mhi[0]){ + mhi = small_lshift (ptr, mhi, Log2P,&tab_mhilshift[0]); + } + else { + mhi = small_lshift (ptr, mhi, Log2P,&tab_mhi[0]); + } + #else + mhi = lshift (ptr, mhi, Log2P); + #endif + } + + for (i = 1;; i++) + { + dig = quorem (b, S) + '0'; + /* Do we yet have the shortest decimal string + * that will round to d? + */ + j = small_cmp (b, mlo); + #ifdef _SMALL_PRINTF + delta = small_diff (ptr, S, mhi,&tab_delta[0]); + #else + delta = diff (ptr, S, mhi); + #endif + j1 = delta->_sign ? 1 : small_cmp (b, delta); + #ifndef _SMALL_PRINTF + Bfree (ptr, delta); + #endif +#ifndef ROUND_BIASED + if (j1 == 0 && !mode && !(word1 (d) & 1)) + { + if (dig == '9') + goto round_9_up; + if (j > 0) + dig++; + + *s++ = dig; + + goto ret; + } +#endif + if ((j < 0) || ((j == 0) && !mode +#ifndef ROUND_BIASED + && !(word1 (d) & 1) +#endif + )) + { + if (j1 > 0) + { + + #ifdef _SMALL_PRINTF + if (b == &tab_b[0]){ + b = small_lshift (ptr, b, 1,&tab_blshift[0]); + } + else { + b = small_lshift (ptr, b, 1,&tab_b[0]); + } + #else + b = lshift (ptr, b, 1); + #endif + + j1 = small_cmp (b, S); + if (((j1 > 0) || ((j1 == 0) && (dig & 1))) + && dig++ == '9') + goto round_9_up; + } + + *s++ = dig; + + goto ret; + } + if (j1 > 0) + { + if (dig == '9') + { /* possible if i == 1 */ + round_9_up: + + *s++ = '9'; + + goto roundoff; + } + + *s++ = dig+1; + + goto ret; + } + + *s++ = dig; + + if (i == ilim) + break; + #ifdef _SMALL_PRINTF + if (b == tab_b ){ + b = small_multadd (ptr, b, 10, 0,&tab_blshift[0]); + } + else{ + b = small_multadd (ptr, b, 10, 0,&tab_b[0]); + } + + #else + b = multadd (ptr, b, 10, 0); + #endif + + + if (mlo == mhi) + #ifdef _SMALL_PRINTF + if ( mhi = &tab_mhi[0] ) { + mlo = mhi = small_multadd (ptr, mhi, 10, 0,&tab_mhilshift[0]); + } + else{ + mlo = mhi = small_multadd (ptr, mhi, 10, 0,&tab_mhi[0]); + } + + #else + mlo = mhi = multadd (ptr, mhi, 10, 0); + #endif + else + { + + #ifdef _SMALL_PRINTF + if ( mlo = &tab_mhi[0] ) { + mlo = small_multadd (ptr, mlo, 10, 0,&tab_mlolshift[0]); + } + else{ + mlo = small_multadd (ptr, mlo, 10, 0,&tab_mlo[0]); + } + if ( mhi = &tab_mhi[0] ) { + mhi = small_multadd (ptr, mhi, 10, 0,&tab_mhilshift[0]); + } + else{ + mhi = small_multadd (ptr, mhi, 10, 0,&tab_mhi[0]); + } + #else + mlo = multadd (ptr, mlo, 10, 0); + mhi = multadd (ptr, mhi, 10, 0); + #endif + } + } + } + else + for (i = 1;; i++) + { + + *s++ = dig =quorem (b, S) + '0'; + + + if (i >= ilim) + break; + #ifdef _SMALL_PRINTF + if ( b == &tab_b[0] ) { + b = small_multadd (ptr, b, 10, 0,&tab_blshift[0]); + } + else { + b = small_multadd (ptr, b, 10, 0,&tab_b[0]); + } + #else + b = multadd (ptr, b, 10, 0); + #endif + } + + /* Round off last digit */ + #ifdef _SMALL_PRINTF + if (b == &tab_b[0]) { + b = small_lshift (ptr, b, 1,&tab_blshift[0]); + } + else { + b = small_lshift (ptr, b, 1,&tab_b[0]); + } + #else + b = lshift (ptr, b, 1); + #endif + + j = small_cmp (b, S); + if ((j > 0) || ((j == 0) && (dig & 1))) + { + roundoff: + + + while (*--s == '9') + if (s == s0) + { + k++; + *s++ = '1'; + goto ret; + } + ++*s++; + } + else + { + while (*--s == '0'); + s++; + } + + + +ret: + #ifndef _SMALL_PRINTF + Bfree (ptr, S); + + if (mhi) + { + if (mlo && mlo != mhi) + Bfree (ptr, mlo); + Bfree (ptr, mhi); + } + #endif +ret1: + #ifndef _SMALL_PRINTF + Bfree (ptr, b); + #endif + *s = 0; + #endif + *decpt = k + 1; + if (rve) + *rve = s; + return s0; +} + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.c new file mode 100644 index 000000000..f7df01d59 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.c @@ -0,0 +1,1963 @@ +/**************************************************************** + * + * The author of this software is David M. Gay. + * + * Copyright (c) 1991 by AT&T. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose without fee is hereby granted, provided that this entire notice + * is included in all copies of any software which is or includes a copy + * or modification of this software and in all copies of the supporting + * documentation for such software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY + * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + * + ***************************************************************/ + +/* Please send bug reports to + David M. Gay + AT&T Bell Laboratories, Room 2C-463 + 600 Mountain Avenue + Murray Hill, NJ 07974-2070 + U.S.A. + dmg@research.att.com or research!dmg + */ + +/* strtod for IEEE-, VAX-, and IBM-arithmetic machines. + * + * This strtod returns a nearest machine number to the input decimal + * string (or sets errno to ERANGE). With IEEE arithmetic, ties are + * broken by the IEEE round-even rule. Otherwise ties are broken by + * biased rounding (add half and chop). + * + * Inspired loosely by William D. Clinger's paper "How to Read Floating + * Point Numbers Accurately" [Proc. ACM SIGPLAN '90, pp. 92-101]. + * + * Modifications: + * + * 1. We only require IEEE, IBM, or VAX double-precision + * arithmetic (not IEEE double-extended). + * 2. We get by with floating-point arithmetic in a case that + * Clinger missed -- when we're computing d * 10^n + * for a small integer d and the integer n is not too + * much larger than 22 (the maximum integer k for which + * we can represent 10^k exactly), we may be able to + * compute (d*10^k) * 10^(e-k) with just one roundoff. + * 3. Rather than a bit-at-a-time adjustment of the binary + * result in the hard case, we use floating-point + * arithmetic to determine the adjustment to within + * one bit; only in really hard cases do we need to + * compute a second residual. + * 4. Because of 3., we don't need a large table of powers of 10 + * for ten-to-e (just some small tables, e.g. of 10^k + * for 0 <= k <= 22). + */ + +/* + * #define IEEE_8087 for IEEE-arithmetic machines where the least + * significant byte has the lowest address. + * #define IEEE_MC68k for IEEE-arithmetic machines where the most + * significant byte has the lowest address. + * #define Sudden_Underflow for IEEE-format machines without gradual + * underflow (i.e., that flush to zero on underflow). + * #define IBM for IBM mainframe-style floating-point arithmetic. + * #define VAX for VAX-style floating-point arithmetic. + * #define Unsigned_Shifts if >> does treats its left operand as unsigned. + * #define No_leftright to omit left-right logic in fast floating-point + * computation of dtoa. + * #define Check_FLT_ROUNDS if FLT_ROUNDS can assume the values 2 or 3. + * #define RND_PRODQUOT to use rnd_prod and rnd_quot (assembly routines + * that use extended-precision instructions to compute rounded + * products and quotients) with IBM. + * #define ROUND_BIASED for IEEE-format with biased rounding. + * #define Inaccurate_Divide for IEEE-format with correctly rounded + * products but inaccurate quotients, e.g., for Intel i860. + * #define Just_16 to store 16 bits per 32-bit long when doing high-precision + * integer arithmetic. Whether this speeds things up or slows things + * down depends on the machine and the number being converted. + */ + + + +#include <_ansi.h> +#include +#include +#include +#include "small_mprec.h" + +/* reent.c knows this value */ +#define _Kmax 15 + +#if defined (_SMALL_PRINTF) || defined(SMALL_SCANF) +#define SMALL_LIB +#else +#define FULL_LIB +#endif + +/* SMALL_LIB is only defined if _SMALL_PRINTF or SMALL_SCANF have been defined + * which means that if you do only specified _SMALL_PRINTF and not SMALL_SCANF + * optimization about call of balloc in small_dtoa_r.c or smal_strtod.c will be + * performed for both printf and scanf + */ + + + +#ifdef FULL_LIB + + + +_Bigint * +_DEFUN (Balloc, (ptr, k), struct _reent *ptr _AND int k) +{ + int x; + _Bigint *rv ; + + _REENT_CHECK_MP(ptr); + if (_REENT_MP_FREELIST(ptr) == NULL) + { + /* Allocate a list of pointers to the mprec objects */ + _REENT_MP_FREELIST(ptr) = (struct _Bigint **) _calloc_r (ptr, + sizeof (struct _Bigint *), + _Kmax + 1); + if (_REENT_MP_FREELIST(ptr) == NULL) + { + return NULL; + } + } + + if ((rv = _REENT_MP_FREELIST(ptr)[k]) != 0) + { + _REENT_MP_FREELIST(ptr)[k] = rv->_next; + } + else + { + x = 1 << k; + /* Allocate an mprec Bigint and stick in in the freelist */ + rv = (_Bigint *) _calloc_r (ptr, + 1, + sizeof (_Bigint) + + (x-1) * sizeof(rv->_x)); + if (rv == NULL) return NULL; + rv->_k = k; + rv->_maxwds = x; + } + rv->_sign = rv->_wds = 0; + return rv; +} + +void +_DEFUN (Bfree, (ptr, v), struct _reent *ptr _AND _Bigint * v) +{ + _REENT_CHECK_MP(ptr); + if (v) + { + v->_next = _REENT_MP_FREELIST(ptr)[v->_k]; + _REENT_MP_FREELIST(ptr)[v->_k] = v; + } +} + + +_Bigint * +_DEFUN (multadd, (ptr, b, m, a), + struct _reent *ptr _AND + _Bigint * b _AND + int m _AND + int a) +{ + int i, wds; + __ULong *x, y; +#ifdef Pack_32 + __ULong xi, z; +#endif + _Bigint *b1; + + wds = b->_wds; + x = b->_x; + i = 0; + do + { +#ifdef Pack_32 + xi = *x; + y = (xi & 0xffff) * m + a; + z = (xi >> 16) * m + (y >> 16); + a = (int) (z >> 16); + *x++ = (z << 16) + (y & 0xffff); +#else + y = *x * m + a; + a = (int) (y >> 16); + *x++ = y & 0xffff; +#endif + } + while (++i < wds); + if (a) + { + if (wds >= b->_maxwds) + { + b1 = Balloc (ptr, b->_k + 1); + Bcopy (b1, b); + Bfree (ptr, b); + b = b1; + } + b->_x[wds++] = a; + b->_wds = wds; + } + return b; +} + +_Bigint * +_DEFUN (s2b, (ptr, s, nd0, nd, y9), + struct _reent * ptr _AND + _CONST char *s _AND + int nd0 _AND + int nd _AND + __ULong y9) +{ + _Bigint *b; + int i, k; + __Long x, y; + + x = (nd + 8) / 9; + for (k = 0, y = 1; x > y; y <<= 1, k++); +#ifdef Pack_32 + b = Balloc (ptr, k); + b->_x[0] = y9; + b->_wds = 1; +#else + b = Balloc (ptr, k + 1); + b->_x[0] = y9 & 0xffff; + b->_wds = (b->_x[1] = y9 >> 16) ? 2 : 1; +#endif + + i = 9; + if (9 < nd0) + { + s += 9; + do + b = multadd (ptr, b, 10, *s++ - '0'); + while (++i < nd0); + s++; + } + else + s += 10; + for (; i < nd; i++) + b = multadd (ptr, b, 10, *s++ - '0'); + return b; +} + +int +_DEFUN (hi0bits, + (x), register __ULong x) +{ + register int k = 0; + + if (!(x & 0xffff0000)) + { + k = 16; + x <<= 16; + } + if (!(x & 0xff000000)) + { + k += 8; + x <<= 8; + } + if (!(x & 0xf0000000)) + { + k += 4; + x <<= 4; + } + if (!(x & 0xc0000000)) + { + k += 2; + x <<= 2; + } + if (!(x & 0x80000000)) + { + k++; + if (!(x & 0x40000000)) + return 32; + } + return k; +} + +int +_DEFUN (lo0bits, (y), __ULong *y) +{ + register int k; + register __ULong x = *y; + + if (x & 7) + { + if (x & 1) + return 0; + if (x & 2) + { + *y = x >> 1; + return 1; + } + *y = x >> 2; + return 2; + } + k = 0; + if (!(x & 0xffff)) + { + k = 16; + x >>= 16; + } + if (!(x & 0xff)) + { + k += 8; + x >>= 8; + } + if (!(x & 0xf)) + { + k += 4; + x >>= 4; + } + if (!(x & 0x3)) + { + k += 2; + x >>= 2; + } + if (!(x & 1)) + { + k++; + x >>= 1; + if (!x & 1) + return 32; + } + *y = x; + return k; +} + +_Bigint * +_DEFUN (i2b, (ptr, i), struct _reent * ptr _AND int i) +{ + _Bigint *b; + + b = Balloc (ptr, 1); + b->_x[0] = i; + b->_wds = 1; + return b; +} + +_Bigint * +_DEFUN (mult, (ptr, a, b), struct _reent * ptr _AND _Bigint * a _AND _Bigint * b) +{ + _Bigint *c; + int k, wa, wb, wc; + __ULong carry, y, z; + __ULong *x, *xa, *xae, *xb, *xbe, *xc, *xc0; +#ifdef Pack_32 + __ULong z2; +#endif + + if (a->_wds < b->_wds) + { + c = a; + a = b; + b = c; + } + k = a->_k; + wa = a->_wds; + wb = b->_wds; + wc = wa + wb; + if (wc > a->_maxwds) + k++; + c = Balloc (ptr, k); + for (x = c->_x, xa = x + wc; x < xa; x++) + *x = 0; + xa = a->_x; + xae = xa + wa; + xb = b->_x; + xbe = xb + wb; + xc0 = c->_x; +#ifdef Pack_32 + for (; xb < xbe; xb++, xc0++) + { + if ((y = *xb & 0xffff) != 0) + { + x = xa; + xc = xc0; + carry = 0; + do + { + z = (*x & 0xffff) * y + (*xc & 0xffff) + carry; + carry = z >> 16; + z2 = (*x++ >> 16) * y + (*xc >> 16) + carry; + carry = z2 >> 16; + Storeinc (xc, z2, z); + } + while (x < xae); + *xc = carry; + } + if ((y = *xb >> 16) != 0) + { + x = xa; + xc = xc0; + carry = 0; + z2 = *xc; + do + { + z = (*x & 0xffff) * y + (*xc >> 16) + carry; + carry = z >> 16; + Storeinc (xc, z, z2); + z2 = (*x++ >> 16) * y + (*xc & 0xffff) + carry; + carry = z2 >> 16; + } + while (x < xae); + *xc = z2; + } + } +#else + for (; xb < xbe; xc0++) + { + if (y = *xb++) + { + x = xa; + xc = xc0; + carry = 0; + do + { + z = *x++ * y + *xc + carry; + carry = z >> 16; + *xc++ = z & 0xffff; + } + while (x < xae); + *xc = carry; + } + } +#endif + for (xc0 = c->_x, xc = xc0 + wc; wc > 0 && !*--xc; --wc); + c->_wds = wc; + return c; +} + +_Bigint * +_DEFUN (pow5mult, + (ptr, b, k), struct _reent * ptr _AND _Bigint * b _AND int k) +{ + _Bigint *b1, *p5, *p51; + int i; + static _CONST int p05[3] = {5, 25, 125}; + + if ((i = k & 3) != 0) + b = multadd (ptr, b, p05[i - 1], 0); + + if (!(k >>= 2)) + return b; + _REENT_CHECK_MP(ptr); + if (!(p5 = _REENT_MP_P5S(ptr))) + { + /* first time */ + p5 = _REENT_MP_P5S(ptr) = i2b (ptr, 625); + p5->_next = 0; + } + for (;;) + { + if (k & 1) + { + b1 = mult (ptr, b, p5); + Bfree (ptr, b); + b = b1; + } + if (!(k >>= 1)) + break; + if (!(p51 = p5->_next)) + { + p51 = p5->_next = mult (ptr, p5, p5); + p51->_next = 0; + } + p5 = p51; + } + return b; +} + +_Bigint * +_DEFUN (lshift, (ptr, b, k), struct _reent * ptr _AND _Bigint * b _AND int k) +{ + int i, k1, n, n1; + _Bigint *b1; + __ULong *x, *x1, *xe, z; + +#ifdef Pack_32 + n = k >> 5; +#else + n = k >> 4; +#endif + k1 = b->_k; + n1 = n + b->_wds + 1; + for (i = b->_maxwds; n1 > i; i <<= 1) + k1++; + b1 = Balloc (ptr, k1); + x1 = b1->_x; + for (i = 0; i < n; i++) + *x1++ = 0; + x = b->_x; + xe = x + b->_wds; +#ifdef Pack_32 + if (k &= 0x1f) + { + k1 = 32 - k; + z = 0; + do + { + *x1++ = *x << k | z; + z = *x++ >> k1; + } + while (x < xe); + if ((*x1 = z) != 0) + ++n1; + } +#else + if (k &= 0xf) + { + k1 = 16 - k; + z = 0; + do + { + *x1++ = *x << k & 0xffff | z; + z = *x++ >> k1; + } + while (x < xe); + if (*x1 = z) + ++n1; + } +#endif + else + do + *x1++ = *x++; + while (x < xe); + b1->_wds = n1 - 1; + Bfree (ptr, b); + return b1; +} + +int +_DEFUN (cmp, (a, b), _Bigint * a _AND _Bigint * b) +{ + __ULong *xa, *xa0, *xb, *xb0; + int i, j; + + i = a->_wds; + j = b->_wds; +#ifdef DEBUG + if (i > 1 && !a->_x[i - 1]) + Bug ("cmp called with a->_x[a->_wds-1] == 0"); + if (j > 1 && !b->_x[j - 1]) + Bug ("cmp called with b->_x[b->_wds-1] == 0"); +#endif + if (i -= j) + return i; + xa0 = a->_x; + xa = xa0 + j; + xb0 = b->_x; + xb = xb0 + j; + for (;;) + { + if (*--xa != *--xb) + return *xa < *xb ? -1 : 1; + if (xa <= xa0) + break; + } + return 0; +} + +_Bigint * +_DEFUN (diff, (ptr, a, b), struct _reent * ptr _AND + _Bigint * a _AND _Bigint * b) +{ + _Bigint *c; + int i, wa, wb; + __Long borrow, y; /* We need signed shifts here. */ + __ULong *xa, *xae, *xb, *xbe, *xc; +#ifdef Pack_32 + __Long z; +#endif + + i = cmp (a, b); + if (!i) + { + c = Balloc (ptr, 0); + c->_wds = 1; + c->_x[0] = 0; + return c; + } + if (i < 0) + { + c = a; + a = b; + b = c; + i = 1; + } + else + i = 0; + c = Balloc (ptr, a->_k); + c->_sign = i; + wa = a->_wds; + xa = a->_x; + xae = xa + wa; + wb = b->_wds; + xb = b->_x; + xbe = xb + wb; + xc = c->_x; + borrow = 0; +#ifdef Pack_32 + do + { + y = (*xa & 0xffff) - (*xb & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + z = (*xa++ >> 16) - (*xb++ >> 16) + borrow; + borrow = z >> 16; + Sign_Extend (borrow, z); + Storeinc (xc, z, y); + } + while (xb < xbe); + while (xa < xae) + { + y = (*xa & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + z = (*xa++ >> 16) + borrow; + borrow = z >> 16; + Sign_Extend (borrow, z); + Storeinc (xc, z, y); + } +#else + do + { + y = *xa++ - *xb++ + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + *xc++ = y & 0xffff; + } + while (xb < xbe); + while (xa < xae) + { + y = *xa++ + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + *xc++ = y & 0xffff; + } +#endif + while (!*--xc) + wa--; + c->_wds = wa; + return c; +} + +double +_DEFUN (ulp, (_x), double _x) +{ + union double_union x, a; + register __Long L; + + x.d = _x; + + L = (word0 (x) & Exp_mask) - (P - 1) * Exp_msk1; +#ifndef Sudden_Underflow + if (L > 0) + { +#endif +#ifdef IBM + L |= Exp_msk1 >> 4; +#endif + word0 (a) = L; +#ifndef _DOUBLE_IS_32BITS + word1 (a) = 0; +#endif + +#ifndef Sudden_Underflow + } + else + { + L = -L >> Exp_shift; + if (L < Exp_shift) + { + word0 (a) = 0x80000 >> L; +#ifndef _DOUBLE_IS_32BITS + word1 (a) = 0; +#endif + } + else + { + word0 (a) = 0; + L -= Exp_shift; +#ifndef _DOUBLE_IS_32BITS + word1 (a) = L >= 31 ? 1 : 1 << (31 - L); +#endif + } + } +#endif + return a.d; +} + +double +_DEFUN (b2d, (a, e), + _Bigint * a _AND int *e) +{ + __ULong *xa, *xa0, w, y, z; + int k; + union double_union d; +#ifdef VAX + __ULong d0, d1; +#else +#define d0 word0(d) +#define d1 word1(d) +#endif + + xa0 = a->_x; + xa = xa0 + a->_wds; + y = *--xa; +#ifdef DEBUG + if (!y) + Bug ("zero y in b2d"); +#endif + k = hi0bits (y); + *e = 32 - k; +#ifdef Pack_32 + if (k < Ebits) + { + d0 = Exp_1 | y >> (Ebits - k); + w = xa > xa0 ? *--xa : 0; +#ifndef _DOUBLE_IS_32BITS + d1 = y << ((32 - Ebits) + k) | w >> (Ebits - k); +#endif + goto ret_d; + } + z = xa > xa0 ? *--xa : 0; + if (k -= Ebits) + { + d0 = Exp_1 | y << k | z >> (32 - k); + y = xa > xa0 ? *--xa : 0; +#ifndef _DOUBLE_IS_32BITS + d1 = z << k | y >> (32 - k); +#endif + } + else + { + d0 = Exp_1 | y; +#ifndef _DOUBLE_IS_32BITS + d1 = z; +#endif + } +#else + if (k < Ebits + 16) + { + z = xa > xa0 ? *--xa : 0; + d0 = Exp_1 | y << k - Ebits | z >> Ebits + 16 - k; + w = xa > xa0 ? *--xa : 0; + y = xa > xa0 ? *--xa : 0; + d1 = z << k + 16 - Ebits | w << k - Ebits | y >> 16 + Ebits - k; + goto ret_d; + } + z = xa > xa0 ? *--xa : 0; + w = xa > xa0 ? *--xa : 0; + k -= Ebits + 16; + d0 = Exp_1 | y << k + 16 | z << k | w >> 16 - k; + y = xa > xa0 ? *--xa : 0; + d1 = w << k + 16 | y << k; +#endif +ret_d: +#ifdef VAX + word0 (d) = d0 >> 16 | d0 << 16; + word1 (d) = d1 >> 16 | d1 << 16; +#else +#undef d0 +#undef d1 +#endif + return d.d; +} + +_Bigint * +_DEFUN (d2b, + (ptr, _d, e, bits), + struct _reent * ptr _AND + double _d _AND + int *e _AND + int *bits) + +{ + union double_union d; + _Bigint *b; + int de, i, k; + __ULong *x, y, z; +#ifdef VAX + __ULong d0, d1; +#endif + d.d = _d; +#ifdef VAX + d0 = word0 (d) >> 16 | word0 (d) << 16; + d1 = word1 (d) >> 16 | word1 (d) << 16; +#else +#define d0 word0(d) +#define d1 word1(d) + d.d = _d; +#endif + +#ifdef Pack_32 + b = Balloc (ptr, 1); +#else + b = Balloc (ptr, 2); +#endif + x = b->_x; + + z = d0 & Frac_mask; + d0 &= 0x7fffffff; /* clear sign bit, which we ignore */ +#ifdef Sudden_Underflow + de = (int) (d0 >> Exp_shift); +#ifndef IBM + z |= Exp_msk11; +#endif +#else + if ((de = (int) (d0 >> Exp_shift)) != 0) + z |= Exp_msk1; +#endif +#ifdef Pack_32 +#ifndef _DOUBLE_IS_32BITS + if (d1) + { + y = d1; + k = lo0bits (&y); + if (k) + { + x[0] = y | z << (32 - k); + z >>= k; + } + else + x[0] = y; + i = b->_wds = (x[1] = z) ? 2 : 1; + } + else +#endif + { +#ifdef DEBUG + if (!z) + Bug ("Zero passed to d2b"); +#endif + k = lo0bits (&z); + x[0] = z; + i = b->_wds = 1; +#ifndef _DOUBLE_IS_32BITS + k += 32; +#endif + } +#else + if (d1) + { + y = d1; + k = lo0bits (&y); + if (k) + if (k >= 16) + { + x[0] = y | z << 32 - k & 0xffff; + x[1] = z >> k - 16 & 0xffff; + x[2] = z >> k; + i = 2; + } + else + { + x[0] = y & 0xffff; + x[1] = y >> 16 | z << 16 - k & 0xffff; + x[2] = z >> k & 0xffff; + x[3] = z >> k + 16; + i = 3; + } + else + { + x[0] = y & 0xffff; + x[1] = y >> 16; + x[2] = z & 0xffff; + x[3] = z >> 16; + i = 3; + } + } + else + { +#ifdef DEBUG + if (!z) + Bug ("Zero passed to d2b"); +#endif + k = lo0bits (&z); + if (k >= 16) + { + x[0] = z; + i = 0; + } + else + { + x[0] = z & 0xffff; + x[1] = z >> 16; + i = 1; + } + k += 32; + } + while (!x[i]) + --i; + b->_wds = i + 1; +#endif +#ifndef Sudden_Underflow + if (de) + { +#endif +#ifdef IBM + *e = (de - Bias - (P - 1) << 2) + k; + *bits = 4 * P + 8 - k - hi0bits (word0 (d) & Frac_mask); +#else + *e = de - Bias - (P - 1) + k; + *bits = P - k; +#endif +#ifndef Sudden_Underflow + } + else + { + *e = de - Bias - (P - 1) + 1 + k; +#ifdef Pack_32 + *bits = 32 * i - hi0bits (x[i - 1]); +#else + *bits = (i + 2) * 16 - hi0bits (x[i]); +#endif + } +#endif + return b; +} +#undef d0 +#undef d1 + +double +_DEFUN (ratio, (a, b), _Bigint * a _AND _Bigint * b) + +{ + union double_union da, db; + int k, ka, kb; + + da.d = b2d (a, &ka); + db.d = b2d (b, &kb); +#ifdef Pack_32 + k = ka - kb + 32 * (a->_wds - b->_wds); +#else + k = ka - kb + 16 * (a->_wds - b->_wds); +#endif +#ifdef IBM + if (k > 0) + { + word0 (da) += (k >> 2) * Exp_msk1; + if (k &= 3) + da.d *= 1 << k; + } + else + { + k = -k; + word0 (db) += (k >> 2) * Exp_msk1; + if (k &= 3) + db.d *= 1 << k; + } +#else + if (k > 0) + word0 (da) += k * Exp_msk1; + else + { + k = -k; + word0 (db) += k * Exp_msk1; + } +#endif + return da.d / db.d; +} + + +_CONST double + tens[] = +{ + 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, + 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, 1e16, 1e17, 1e18, 1e19, + 1e20, 1e21, 1e22, 1e23, 1e24 + +}; + +#if !defined(_DOUBLE_IS_32BITS) && !defined(__v800) +_CONST double bigtens[] = +{1e16, 1e32, 1e64, 1e128, 1e256}; + +_CONST double tinytens[] = +{1e-16, 1e-32, 1e-64, 1e-128, 1e-256}; +#else +_CONST double bigtens[] = +{1e16, 1e32}; + +_CONST double tinytens[] = +{1e-16, 1e-32}; +#endif + + +double +_DEFUN (_mprec_log10, (dig), + int dig) +{ + double v = 1.0; + if (dig < 24) + return tens[dig]; + while (dig > 0) + { + v *= 10; + dig--; + } + return v; +} + +#endif // SMALL_LIB + + +/*****************************************************************************************/ +/* FOR SMALL_LIB */ +/*****************************************************************************************/ + + +#ifdef SMALL_LIB + + /* + * For SMALL_LIB, all references to balloc or bfree have been taken off + * so as to avoided call of malloc libraries + * For each function returning a _Bigint * we added to the function a parameter + * of array type. The purpose of this array is to iniatialized pointers of _Bigint + * with the address of the array instead of the adress provided by balloc. + * + */ + + + +_Bigint * +_DEFUN (small_multadd, (ptr, b, m, a, tab), + struct _reent *ptr _AND + _Bigint * b _AND + int m _AND + int a _AND + _Bigint tab[]) +{ + int i, wds; + __ULong *x, y; +#ifdef Pack_32 + __ULong xi, z; +#endif + _Bigint *b1; + + wds = b->_wds; + x = b->_x; + i = 0; + do + { +#ifdef Pack_32 + xi = *x; + y = (xi & 0xffff) * m + a; + z = (xi >> 16) * m + (y >> 16); + a = (int) (z >> 16); + *x++ = (z << 16) + (y & 0xffff); +#else + y = *x * m + a; + a = (int) (y >> 16); + *x++ = y & 0xffff; +#endif + } + while (++i < wds); + if (a) + { + if (wds >= b->_maxwds) + { + b1=&tab[0]; + b1->_k=b->_k+1; + b1->_maxwds = (1 <<(b->_k+1)); + b1->_sign=b1->_wds=0; + Bcopy(b1,b); + b=b1; + } + b->_x[wds++] = a; + b->_wds = wds; + } + return b; +} + + +_Bigint * +_DEFUN (small_s2b, (ptr, s, nd0, nd, y9,tab), + struct _reent * ptr _AND + _CONST char *s _AND + int nd0 _AND + int nd _AND + __ULong y9 _AND + _Bigint tab[]) +{ + _Bigint *b; + _Bigint tab_b[50]; + int i, k; + __Long x, y; + + x = (nd + 8) / 9; + for (k = 0, y = 1; x > y; y <<= 1, k++); +#ifdef Pack_32 + b = &tab[0]; + b->_k=k; + b->_maxwds = 1 <_sign=0; + b->_x[0] = y9; + b->_wds = 1; +#else + b = &tab[0]; + b = &tab[0]; + b->_k=k+1; + b->_mawxds = 1 <<(k+1); + b->_sign=0; + b->_x[0] = y9 & 0xffff; + b->_wds = (b->_x[1] = y9 >> 16) ? 2 : 1; +#endif + + i = 9; + if (9 < nd0) + { + s += 9; + + while (++i < nd0); + s++; + } + else + s += 10; + for (; i < nd; i++) + b = small_multadd (ptr, b, 10, *s++ - '0',tab); + return b; +} + +int +_DEFUN (small_hi0bits, + (x), register __ULong x) +{ + register int k = 0; + + if (!(x & 0xffff0000)) + { + k = 16; + x <<= 16; + } + if (!(x & 0xff000000)) + { + k += 8; + x <<= 8; + } + if (!(x & 0xf0000000)) + { + k += 4; + x <<= 4; + } + if (!(x & 0xc0000000)) + { + k += 2; + x <<= 2; + } + if (!(x & 0x80000000)) + { + k++; + if (!(x & 0x40000000)) + return 32; + } + return k; +} + +int +_DEFUN (small_lo0bits, (y), __ULong *y) +{ + register int k; + register __ULong x = *y; + + if (x & 7) + { + if (x & 1) + return 0; + if (x & 2) + { + *y = x >> 1; + return 1; + } + *y = x >> 2; + return 2; + } + k = 0; + if (!(x & 0xffff)) + { + k = 16; + x >>= 16; + } + if (!(x & 0xff)) + { + k += 8; + x >>= 8; + } + if (!(x & 0xf)) + { + k += 4; + x >>= 4; + } + if (!(x & 0x3)) + { + k += 2; + x >>= 2; + } + if (!(x & 1)) + { + k++; + x >>= 1; + if (!x & 1) + return 32; + } + *y = x; + return k; +} + + +_Bigint * +_DEFUN (small_i2b, (ptr, i,tab), struct _reent * ptr _AND int i _AND _Bigint tab[]) +{ + _Bigint *b; + + b=&tab[0]; + b->_k=1; + b->_maxwds = 1 << 1; + b->_sign =0; + b->_x[0] = i; + b->_wds = 1; + return b; +} + + + +_Bigint * +_DEFUN (small_mult, (ptr, a, b,tab), struct _reent * ptr _AND _Bigint * a _AND _Bigint * b _AND _Bigint tab[]) +{ + _Bigint *c; + int k, wa, wb, wc; + __ULong carry, y, z; + __ULong *x, *xa, *xae, *xb, *xbe, *xc, *xc0; +#ifdef Pack_32 + __ULong z2; +#endif + + if (a->_wds < b->_wds) + { + c = a; + a = b; + b = c; + } + k = a->_k; + wa = a->_wds; + wb = b->_wds; + wc = wa + wb; + if (wc > a->_maxwds) + k++; + c=&tab[0]; + c->_k=k; + c->_maxwds = 1 << k; + c->_sign= c->_wds =0; + + for (x = c->_x, xa = x + wc; x < xa; x++) + *x = 0; + xa = a->_x; + xae = xa + wa; + xb = b->_x; + xbe = xb + wb; + xc0 = c->_x; +#ifdef Pack_32 + for (; xb < xbe; xb++, xc0++) + { + if ((y = *xb & 0xffff) != 0) + { + x = xa; + xc = xc0; + carry = 0; + do + { + z = (*x & 0xffff) * y + (*xc & 0xffff) + carry; + carry = z >> 16; + z2 = (*x++ >> 16) * y + (*xc >> 16) + carry; + carry = z2 >> 16; + Storeinc (xc, z2, z); + } + while (x < xae); + *xc = carry; + } + if ((y = *xb >> 16) != 0) + { + x = xa; + xc = xc0; + carry = 0; + z2 = *xc; + do + { + z = (*x & 0xffff) * y + (*xc >> 16) + carry; + carry = z >> 16; + Storeinc (xc, z, z2); + z2 = (*x++ >> 16) * y + (*xc & 0xffff) + carry; + carry = z2 >> 16; + } + while (x < xae); + *xc = z2; + } + } +#else + for (; xb < xbe; xc0++) + { + if (y = *xb++) + { + x = xa; + xc = xc0; + carry = 0; + do + { + z = *x++ * y + *xc + carry; + carry = z >> 16; + *xc++ = z & 0xffff; + } + while (x < xae); + *xc = carry; + } + } +#endif + for (xc0 = c->_x, xc = xc0 + wc; wc > 0 && !*--xc; --wc); + c->_wds = wc; + return c; +} + + + +_Bigint * +_DEFUN (small_pow5mult, + (ptr, b, k, tab), struct _reent * ptr _AND _Bigint * b _AND int k _AND _Bigint tab[]) +{ + _Bigint *b1, *p5, *p51; + _Bigint tab_p5[50], tab_p5mult[50]; + _Bigint tab_b2[40], tab_b1[40]; + int i; + int k_sauv; + static _CONST int p05[3] = {5, 25, 125}; + if ((i = k & 3) != 0){ + k_sauv=k; + k_sauv >>= 2; + if (!(k_sauv)){ // we anticipate the case !(k>>=2) with return so as + //to provide the good address &tab[0] + b = small_multadd (ptr, b, p05[i - 1], 0,&tab[0]); + return b; + } + else{ + b = small_multadd (ptr, b, p05[i - 1], 0,&tab_b1[0]); //&tab_b1[0] is an temporary address that + // that we provide to b + } + } + if (!(k>>= 2)){ + return b; + } + if (p5 != tab_p5 ){ /* first time */ + p5 =small_i2b (ptr, 625,tab_p5); + p5->_next = 0; + } + + for (;;) {// We are in a loop for each variable and call of mult we must provide a + // an address which differs from the current address of the variable + // that is why we add a test on the current address + + if (k & 1){ + + k_sauv = k ; + if (!(k_sauv >>= 1) ){ // it is the last passage in the loop + // we must provide the good address + b1 = small_mult (ptr, b, p5,&tab[0]); + b = b1; + break; + } + else { + if (b == &tab_b1[0]){ + b1 = small_mult (ptr, b, p5,&tab_b2[0]); + } + else { + b1 = small_mult (ptr, b, p5,&tab_b1[0]); + } + } + b = b1; + } + if (!(k >>= 1)) + break; + if (!(p51 = p5->_next)) + { + if ( p5 == &tab_p5[0] ){ + p51 = p5->_next = small_mult (ptr, p5, p5,&tab_p5mult[0]); + } + else { + p51 = p5->_next = small_mult (ptr, p5, p5,&tab_p5[0]); + } + p51->_next = 0; + } + p5 = p51; + } + return b; +} + + +_Bigint * +_DEFUN (small_lshift, (ptr, b, k,tab), struct _reent * ptr _AND _Bigint * b _AND int k _AND _Bigint tab[] ) +{ + int i, k1, n, n1; + _Bigint *b1; + __ULong *x, *x1, *xe, z; + +#ifdef Pack_32 + n = k >> 5; +#else + n = k >> 4; +#endif + k1 = b->_k; + n1 = n + b->_wds + 1; + for (i = b->_maxwds; n1 > i; i <<= 1) + k1++; + //b1 = Balloc (ptr, k1); + b1=&tab[0]; + b1->_k=k1; + b1->_maxwds = 1 << k1; + b1->_sign= b1->_wds =0; + x1 = b1->_x; + for (i = 0; i < n; i++) + *x1++ = 0; + x = b->_x; + xe = x + b->_wds; +#ifdef Pack_32 + if (k &= 0x1f) + { + k1 = 32 - k; + z = 0; + do + { + *x1++ = *x << k | z; + z = *x++ >> k1; + } + while (x < xe); + if ((*x1 = z) != 0) + ++n1; + } +#else + if (k &= 0xf) + { + k1 = 16 - k; + z = 0; + do + { + *x1++ = *x << k & 0xffff | z; + z = *x++ >> k1; + } + while (x < xe); + if (*x1 = z) + ++n1; + } +#endif + else + do + *x1++ = *x++; + while (x < xe); + b1->_wds = n1 - 1; + //Bfree (ptr, b); + return b1; +} + +int +_DEFUN (small_cmp, (a, b), _Bigint * a _AND _Bigint * b) +{ + __ULong *xa, *xa0, *xb, *xb0; + int i, j; + + i = a->_wds; + j = b->_wds; +#ifdef DEBUG + if (i > 1 && !a->_x[i - 1]) + Bug ("cmp called with a->_x[a->_wds-1] == 0"); + if (j > 1 && !b->_x[j - 1]) + Bug ("cmp called with b->_x[b->_wds-1] == 0"); +#endif + if (i -= j) + return i; + xa0 = a->_x; + xa = xa0 + j; + xb0 = b->_x; + xb = xb0 + j; + for (;;) + { + if (*--xa != *--xb) + return *xa < *xb ? -1 : 1; + if (xa <= xa0) + break; + } + return 0; +} + + + +_Bigint * +_DEFUN (small_diff, (ptr, a, b,tab), struct _reent * ptr _AND + _Bigint * a _AND _Bigint * b _AND _Bigint tab[]) +{ + _Bigint *c; + int i, wa, wb; + __Long borrow, y; /* We need signed shifts here. */ + __ULong *xa, *xae, *xb, *xbe, *xc; +#ifdef Pack_32 + __Long z; +#endif + + i = small_cmp (a, b); + if (!i) + { + c=&tab[0]; + c->_k = 0; + c->_maxwds = (1 << 0) ; + c->_sign = 0 ; + c->_wds = 1; + c->_x[0] = 0; + return c; + } + if (i < 0) + { + c = a; + a = b; + b = c; + i = 1; + } + else + i = 0; + c=&tab[0]; + c->_k = a->_k; + c->_maxwds = (1 << (a->_k)) ; + c->_wds = 0 ; + c->_sign = i; + wa = a->_wds; + xa = a->_x; + xae = xa + wa; + wb = b->_wds; + xb = b->_x; + xbe = xb + wb; + xc = c->_x; + borrow = 0; +#ifdef Pack_32 + do + { + y = (*xa & 0xffff) - (*xb & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + z = (*xa++ >> 16) - (*xb++ >> 16) + borrow; + borrow = z >> 16; + Sign_Extend (borrow, z); + Storeinc (xc, z, y); + } + while (xb < xbe); + while (xa < xae) + { + y = (*xa & 0xffff) + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + z = (*xa++ >> 16) + borrow; + borrow = z >> 16; + Sign_Extend (borrow, z); + Storeinc (xc, z, y); + } +#else + do + { + y = *xa++ - *xb++ + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + *xc++ = y & 0xffff; + } + while (xb < xbe); + while (xa < xae) + { + y = *xa++ + borrow; + borrow = y >> 16; + Sign_Extend (borrow, y); + *xc++ = y & 0xffff; + } +#endif + while (!*--xc) + wa--; + c->_wds = wa; + return c; +} + +double +_DEFUN (small_ulp, (_x), double _x) +{ + union double_union x, a; + register __Long L; + + x.d = _x; + + L = (word0 (x) & Exp_mask) - (P - 1) * Exp_msk1; +#ifndef Sudden_Underflow + if (L > 0) + { +#endif +#ifdef IBM + L |= Exp_msk1 >> 4; +#endif + word0 (a) = L; +#ifndef _DOUBLE_IS_32BITS + word1 (a) = 0; +#endif + +#ifndef Sudden_Underflow + } + else + { + L = -L >> Exp_shift; + if (L < Exp_shift) + { + word0 (a) = 0x80000 >> L; +#ifndef _DOUBLE_IS_32BITS + word1 (a) = 0; +#endif + } + else + { + word0 (a) = 0; + L -= Exp_shift; +#ifndef _DOUBLE_IS_32BITS + word1 (a) = L >= 31 ? 1 : 1 << (31 - L); +#endif + } + } +#endif + return a.d; +} + +double +_DEFUN (small_b2d, (a, e), + _Bigint * a _AND int *e) +{ + __ULong *xa, *xa0, w, y, z; + int k; + union double_union d; +#ifdef VAX + __ULong d0, d1; +#else +#define d0 word0(d) +#define d1 word1(d) +#endif + + xa0 = a->_x; + xa = xa0 + a->_wds; + y = *--xa; +#ifdef DEBUG + if (!y) + Bug ("zero y in b2d"); +#endif + k = small_hi0bits (y); + *e = 32 - k; +#ifdef Pack_32 + if (k < Ebits) + { + d0 = Exp_1 | y >> (Ebits - k); + w = xa > xa0 ? *--xa : 0; +#ifndef _DOUBLE_IS_32BITS + d1 = y << ((32 - Ebits) + k) | w >> (Ebits - k); +#endif + goto ret_d; + } + z = xa > xa0 ? *--xa : 0; + if (k -= Ebits) + { + d0 = Exp_1 | y << k | z >> (32 - k); + y = xa > xa0 ? *--xa : 0; +#ifndef _DOUBLE_IS_32BITS + d1 = z << k | y >> (32 - k); +#endif + } + else + { + d0 = Exp_1 | y; +#ifndef _DOUBLE_IS_32BITS + d1 = z; +#endif + } +#else + if (k < Ebits + 16) + { + z = xa > xa0 ? *--xa : 0; + d0 = Exp_1 | y << k - Ebits | z >> Ebits + 16 - k; + w = xa > xa0 ? *--xa : 0; + y = xa > xa0 ? *--xa : 0; + d1 = z << k + 16 - Ebits | w << k - Ebits | y >> 16 + Ebits - k; + goto ret_d; + } + z = xa > xa0 ? *--xa : 0; + w = xa > xa0 ? *--xa : 0; + k -= Ebits + 16; + d0 = Exp_1 | y << k + 16 | z << k | w >> 16 - k; + y = xa > xa0 ? *--xa : 0; + d1 = w << k + 16 | y << k; +#endif +ret_d: +#ifdef VAX + word0 (d) = d0 >> 16 | d0 << 16; + word1 (d) = d1 >> 16 | d1 << 16; +#else +#undef d0 +#undef d1 +#endif + return d.d; +} + + +_Bigint * +_DEFUN (small_d2b, + (ptr, _d, e, bits,tab), + struct _reent * ptr _AND + double _d _AND + int *e _AND + int *bits _AND + _Bigint tab[] + ) + +{ + union double_union d; + _Bigint *b; + + int de, i, k; + __ULong *x, y, z; +#ifdef VAX + __ULong d0, d1; +#endif + d.d = _d; +#ifdef VAX + d0 = word0 (d) >> 16 | word0 (d) << 16; + d1 = word1 (d) >> 16 | word1 (d) << 16; +#else +#define d0 word0(d) +#define d1 word1(d) + d.d = _d; +#endif + +#ifdef Pack_32 + b=&tab[0]; + b->_k = 1; + b->_maxwds = (1 << 1) ; + b->_sign = b->_wds = 0 ; + +#else + b=&tab[0]; + b->_k = 2; + b->_maxwds = (1 << 2) ; + b->_sign = b->_wds = 0 ; +#endif + + + x = b->_x; + + z = d0 & Frac_mask; + d0 &= 0x7fffffff; /* clear sign bit, which we ignore */ +#ifdef Sudden_Underflow + de = (int) (d0 >> Exp_shift); +#ifndef IBM + z |= Exp_msk11; +#endif +#else + if ((de = (int) (d0 >> Exp_shift)) != 0) + z |= Exp_msk1; +#endif +#ifdef Pack_32 +#ifndef _DOUBLE_IS_32BITS + if (d1) + { + y = d1; + k = small_lo0bits (&y); + if (k) + { + x[0] = y | z << (32 - k); + z >>= k; + } + else + x[0] = y; + i = b->_wds = (x[1] = z) ? 2 : 1; + } + else +#endif + { +#ifdef DEBUG + if (!z) + Bug ("Zero passed to d2b"); +#endif + k = small_lo0bits (&z); + x[0] = z; + i = b->_wds = 1; +#ifndef _DOUBLE_IS_32BITS + k += 32; +#endif + } +#else + if (d1) + { + y = d1; + k = small_lo0bits (&y); + if (k) + if (k >= 16) + { + x[0] = y | z << 32 - k & 0xffff; + x[1] = z >> k - 16 & 0xffff; + x[2] = z >> k; + i = 2; + } + else + { + x[0] = y & 0xffff; + x[1] = y >> 16 | z << 16 - k & 0xffff; + x[2] = z >> k & 0xffff; + x[3] = z >> k + 16; + i = 3; + } + else + { + x[0] = y & 0xffff; + x[1] = y >> 16; + x[2] = z & 0xffff; + x[3] = z >> 16; + i = 3; + } + } + else + { +#ifdef DEBUG + if (!z) + Bug ("Zero passed to d2b"); +#endif + k = lo0bits (&z); + if (k >= 16) + { + x[0] = z; + i = 0; + } + else + { + x[0] = z & 0xffff; + x[1] = z >> 16; + i = 1; + } + k += 32; + } + while (!x[i]) + --i; + b->_wds = i + 1; +#endif +#ifndef Sudden_Underflow + if (de) + { +#endif +#ifdef IBM + *e = (de - Bias - (P - 1) << 2) + k; + *bits = 4 * P + 8 - k - small_hi0bits (word0 (d) & Frac_mask); +#else + *e = de - Bias - (P - 1) + k; + *bits = P - k; +#endif +#ifndef Sudden_Underflow + } + else + { + *e = de - Bias - (P - 1) + 1 + k; +#ifdef Pack_32 + *bits = 32 * i - small_hi0bits (x[i - 1]); +#else + *bits = (i + 2) * 16 - small_hi0bits (x[i]); +#endif + } +#endif + return b; +} +#undef d0 +#undef d1 + +double +_DEFUN (small_ratio, (a, b), _Bigint * a _AND _Bigint * b) + +{ + union double_union da, db; + int k, ka, kb; + + da.d = small_b2d (a, &ka); + db.d = small_b2d (b, &kb); +#ifdef Pack_32 + k = ka - kb + 32 * (a->_wds - b->_wds); +#else + k = ka - kb + 16 * (a->_wds - b->_wds); +#endif +#ifdef IBM + if (k > 0) + { + word0 (da) += (k >> 2) * Exp_msk1; + if (k &= 3) + da.d *= 1 << k; + } + else + { + k = -k; + word0 (db) += (k >> 2) * Exp_msk1; + if (k &= 3) + db.d *= 1 << k; + } +#else + if (k > 0) + word0 (da) += k * Exp_msk1; + else + { + k = -k; + word0 (db) += k * Exp_msk1; + } +#endif + return da.d / db.d; +} + + +_CONST double + small_tens[] = +{ + 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, + 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, 1e16, 1e17, 1e18, 1e19, + 1e20, 1e21, 1e22, 1e23, 1e24 + +}; + +#if !defined(_DOUBLE_IS_32BITS) && !defined(__v800) +_CONST double small_bigtens[] = +{1e16, 1e32, 1e64, 1e128, 1e256}; + +_CONST double small_tinytens[] = +{1e-16, 1e-32, 1e-64, 1e-128, 1e-256}; +#else +_CONST double small_bigtens[] = +{1e16, 1e32}; + +_CONST double small_tinytens[] = +{1e-16, 1e-32}; +#endif + + + + +double +_DEFUN (small__mprec_log10, (dig), + int dig) +{ + double v = 1.0; + if (dig < 24) + return small_tens[dig]; + while (dig > 0) + { + v *= 10; + dig--; + } + return v; +} + +#endif // SMALL_PRINTF + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.h new file mode 100644 index 000000000..ec04e3ff2 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_mprec.h @@ -0,0 +1,383 @@ +/**************************************************************** + * + * The author of this software is David M. Gay. + * + * Copyright (c) 1991 by AT&T. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose without fee is hereby granted, provided that this entire notice + * is included in all copies of any software which is or includes a copy + * or modification of this software and in all copies of the supporting + * documentation for such software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY + * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + * + ***************************************************************/ + +/* Please send bug reports to + David M. Gay + AT&T Bell Laboratories, Room 2C-463 + 600 Mountain Avenue + Murray Hill, NJ 07974-2070 + U.S.A. + dmg@research.att.com or research!dmg + */ + + +#include +#include +#include +#include +#include +#include + +#ifdef __IEEE_LITTLE_ENDIAN +#define IEEE_8087 +#endif + +#ifdef __IEEE_BIG_ENDIAN +#define IEEE_MC68k +#endif + +#ifdef __Z8000__ +#define Just_16 +#endif + +#ifdef DEBUG +#include "stdio.h" +#define Bug(x) {fprintf(stderr, "%s\n", x); exit(1);} +#endif + +#ifdef Unsigned_Shifts +#define Sign_Extend(a,b) if (b < 0) a |= (__uint32_t)0xffff0000; +#else +#define Sign_Extend(a,b) /*no-op*/ +#endif + +#if defined(IEEE_8087) + defined(IEEE_MC68k) + defined(VAX) + defined(IBM) != 1 +Exactly one of IEEE_8087, IEEE_MC68k, VAX, or IBM should be defined. +#endif + +/* If we are going to examine or modify specific bits in a double using + the word0 and/or word1 macros, then we must wrap the double inside + a union. This is necessary to avoid undefined behavior according to + the ANSI C spec. */ +union double_union +{ + double d; + __uint32_t i[2]; +}; + +#ifdef IEEE_8087 +#define word0(x) (x.i[1]) +#define word1(x) (x.i[0]) +#else +#define word0(x) (x.i[0]) +#define word1(x) (x.i[1]) +#endif + +/* The following definition of Storeinc is appropriate for MIPS processors. + * An alternative that might be better on some machines is + * #define Storeinc(a,b,c) (*a++ = b << 16 | c & 0xffff) + */ +#if defined (__IEEE_BYTES_LITTLE_ENDIAN) + defined (IEEE_8087) + defined (VAX) +#define Storeinc(a,b,c) (((unsigned short *)a)[1] = (unsigned short)b, \ +((unsigned short *)a)[0] = (unsigned short)c, a++) +#else +#define Storeinc(a,b,c) (((unsigned short *)a)[0] = (unsigned short)b, \ +((unsigned short *)a)[1] = (unsigned short)c, a++) +#endif + +/* #define P DBL_MANT_DIG */ +/* Ten_pmax = floor(P*log(2)/log(5)) */ +/* Bletch = (highest power of 2 < DBL_MAX_10_EXP) / 16 */ +/* Quick_max = floor((P-1)*log(FLT_RADIX)/log(10) - 1) */ +/* Int_max = floor(P*log(FLT_RADIX)/log(10) - 1) */ + +#if defined(IEEE_8087) + defined(IEEE_MC68k) +#if defined (_DOUBLE_IS_32BITS) +#define Exp_shift 23 +#define Exp_shift1 23 +#define Exp_msk1 ((__uint32_t)0x00800000L) +#define Exp_msk11 ((__uint32_t)0x00800000L) +#define Exp_mask ((__uint32_t)0x7f800000L) +#define P 24 +#define Bias 127 +#if 0 +#define IEEE_Arith /* it is, but the code doesn't handle IEEE singles yet */ +#endif +#define Emin (-126) +#define Exp_1 ((__uint32_t)0x3f800000L) +#define Exp_11 ((__uint32_t)0x3f800000L) +#define Ebits 8 +#define Frac_mask ((__uint32_t)0x007fffffL) +#define Frac_mask1 ((__uint32_t)0x007fffffL) +#define Ten_pmax 10 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Ten_pmax 10 +#define Bletch 2 +#define Bndry_mask ((__uint32_t)0x007fffffL) +#define Bndry_mask1 ((__uint32_t)0x007fffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 1 +#define Tiny0 0 +#define Tiny1 1 +#define Quick_max 5 +#define Int_max 6 +#define Infinite(x) (word0(x) == ((__uint32_t)0x7f800000L)) +#undef word0 +#undef word1 + +#define word0(x) (x.i[0]) +#define word1(x) 0 +#else + +#define Exp_shift 20 +#define Exp_shift1 20 +#define Exp_msk1 ((__uint32_t)0x100000L) +#define Exp_msk11 ((__uint32_t)0x100000L) +#define Exp_mask ((__uint32_t)0x7ff00000L) +#define P 53 +#define Bias 1023 +#define IEEE_Arith +#define Emin (-1022) +#define Exp_1 ((__uint32_t)0x3ff00000L) +#define Exp_11 ((__uint32_t)0x3ff00000L) +#define Ebits 11 +#define Frac_mask ((__uint32_t)0xfffffL) +#define Frac_mask1 ((__uint32_t)0xfffffL) +#define Ten_pmax 22 +#define Bletch 0x10 +#define Bndry_mask ((__uint32_t)0xfffffL) +#define Bndry_mask1 ((__uint32_t)0xfffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 1 +#define Tiny0 0 +#define Tiny1 1 +#define Quick_max 14 +#define Int_max 14 +#define Infinite(x) (word0(x) == ((__uint32_t)0x7ff00000L)) /* sufficient test for here */ +#endif + +#else +#undef Sudden_Underflow +#define Sudden_Underflow +#ifdef IBM +#define Exp_shift 24 +#define Exp_shift1 24 +#define Exp_msk1 ((__uint32_t)0x1000000L) +#define Exp_msk11 ((__uint32_t)0x1000000L) +#define Exp_mask ((__uint32_t)0x7f000000L) +#define P 14 +#define Bias 65 +#define Exp_1 ((__uint32_t)0x41000000L) +#define Exp_11 ((__uint32_t)0x41000000L) +#define Ebits 8 /* exponent has 7 bits, but 8 is the right value in b2d */ +#define Frac_mask ((__uint32_t)0xffffffL) +#define Frac_mask1 ((__uint32_t)0xffffffL) +#define Bletch 4 +#define Ten_pmax 22 +#define Bndry_mask ((__uint32_t)0xefffffL) +#define Bndry_mask1 ((__uint32_t)0xffffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 4 +#define Tiny0 ((__uint32_t)0x100000L) +#define Tiny1 0 +#define Quick_max 14 +#define Int_max 15 +#else /* VAX */ +#define Exp_shift 23 +#define Exp_shift1 7 +#define Exp_msk1 0x80 +#define Exp_msk11 ((__uint32_t)0x800000L) +#define Exp_mask ((__uint32_t)0x7f80L) +#define P 56 +#define Bias 129 +#define Exp_1 ((__uint32_t)0x40800000L) +#define Exp_11 ((__uint32_t)0x4080L) +#define Ebits 8 +#define Frac_mask ((__uint32_t)0x7fffffL) +#define Frac_mask1 ((__uint32_t)0xffff007fL) +#define Ten_pmax 24 +#define Bletch 2 +#define Bndry_mask ((__uint32_t)0xffff007fL) +#define Bndry_mask1 ((__uint32_t)0xffff007fL) +#define LSB ((__uint32_t)0x10000L) +#define Sign_bit ((__uint32_t)0x8000L) +#define Log2P 1 +#define Tiny0 0x80 +#define Tiny1 0 +#define Quick_max 15 +#define Int_max 15 +#endif +#endif + +#ifndef IEEE_Arith +#define ROUND_BIASED +#endif + +#ifdef RND_PRODQUOT +#define rounded_product(a,b) a = rnd_prod(a, b) +#define rounded_quotient(a,b) a = rnd_quot(a, b) +#ifdef KR_headers +extern double rnd_prod(), rnd_quot(); +#else +extern double rnd_prod(double, double), rnd_quot(double, double); +#endif +#else +#define rounded_product(a,b) a *= b +#define rounded_quotient(a,b) a /= b +#endif + +#define Big0 (Frac_mask1 | Exp_msk1*(DBL_MAX_EXP+Bias-1)) +#define Big1 ((__uint32_t)0xffffffffL) + +#ifndef Just_16 +/* When Pack_32 is not defined, we store 16 bits per 32-bit long. + * This makes some inner loops simpler and sometimes saves work + * during multiplications, but it often seems to make things slightly + * slower. Hence the default is now to store 32 bits per long. + */ + +#ifndef Pack_32 +#define Pack_32 +#endif +#endif + + +#ifdef __cplusplus +extern "C" double strtod(const char *s00, char **se); +extern "C" char *dtoa(double d, int mode, int ndigits, + int *decpt, int *sign, char **rve); +#endif + + +typedef struct _Bigint _Bigint; + +#if (defined (_SMALL_PRINTF) || defined(SMALL_SCANF) ) +#define SMALL_LIB +#endif + +#ifdef SMALL_LIB + + + + +#define small_Balloc _small_Balloc +#define small_Bfree _small_Bfree +#define small_multadd _small_multadd +#define small_s2b _small_s2b +#define small_lo0bits _small_lo0bits +#define small_hi0bits _small_hi0bits +#define small_i2b _small_i2b +#define small_mult _small_multiply +#define small_pow5mult _small_pow5mult +#define small_lshift _small_lshift +#define small_cmp __small_mcmp +#define small_diff __small_mdiff +#define small_ulp _small_ulp +#define small_b2d _small_b2d +#define small_d2b _small_d2b +#define small_ratio _small_ratio + +#define small_tens __small_mprec_tens +#define small_bigtens __small_mprec_bigtens +#define small_tinytens __small_mprec_tinytens + +struct _reent ; +double _EXFUN(small_ulp,(double x)); +double _EXFUN(small_b2d,(_Bigint *a , int *e)); +_Bigint * _EXFUN(small_multadd,(struct _reent *p, _Bigint *, int, int,_Bigint tab[])); +_Bigint * _EXFUN(small_s2b,(struct _reent *, const char*, int, int, __ULong,_Bigint tab[])); +_Bigint * _EXFUN(small_i2b,(struct _reent *,int,_Bigint tab[])); +_Bigint * _EXFUN(small_mult, (struct _reent *, _Bigint *, _Bigint *,_Bigint tab[])); +_Bigint * _EXFUN(small_pow5mult, (struct _reent *, _Bigint *, int k,_Bigint tab[])); +int _EXFUN(small_hi0bits,(__ULong)); +int _EXFUN(small_lo0bits,(__ULong *)); +_Bigint * _EXFUN(small_d2b,(struct _reent *p, double d, int *e, int *bits,_Bigint tab[])); +_Bigint * _EXFUN(small_lshift,(struct _reent *p, _Bigint *b, int k,_Bigint tab[])); +_Bigint * _EXFUN(small_diff,(struct _reent *p, _Bigint *a, _Bigint *b,_Bigint tab[])); +int _EXFUN(small_cmp,(_Bigint *a, _Bigint *b)); + +double _EXFUN(small_ratio,(_Bigint *a, _Bigint *b)); +#define Bcopy(x,y) memcpy((char *)&x->_sign, (char *)&y->_sign, y->_wds*sizeof(__Long) + 2*sizeof(int)) + +#if defined(_DOUBLE_IS_32BITS) && defined(__v800) +#define n_bigtens 2 +#else +#define n_bigtens 5 +#endif + +extern _CONST double small_tinytens[]; +extern _CONST double small_bigtens[]; +extern _CONST double small_tens[]; + + +double _EXFUN(_small_mprec_log10,(int)); + + +#else // NO SMALL_LIB + + + +#define Balloc _Balloc +#define Bfree _Bfree +#define multadd _multadd +#define s2b _s2b +#define lo0bits _lo0bits +#define hi0bits _hi0bits +#define i2b _i2b +#define mult _multiply +#define pow5mult _pow5mult +#define lshift _lshift +#define cmp __mcmp +#define diff __mdiff +#define ulp _ulp +#define b2d _b2d +#define d2b _d2b +#define ratio _ratio + +#define tens __mprec_tens +#define bigtens __mprec_bigtens +#define tinytens __mprec_tinytens + +struct _reent ; +double _EXFUN(ulp,(double x)); +double _EXFUN(b2d,(_Bigint *a , int *e)); +_Bigint * _EXFUN(Balloc,(struct _reent *p, int k)); +void _EXFUN(Bfree,(struct _reent *p, _Bigint *v)); +_Bigint * _EXFUN(multadd,(struct _reent *p, _Bigint *, int, int)); +_Bigint * _EXFUN(s2b,(struct _reent *, const char*, int, int, __ULong)); +_Bigint * _EXFUN(i2b,(struct _reent *,int)); +_Bigint * _EXFUN(mult, (struct _reent *, _Bigint *, _Bigint *)); +_Bigint * _EXFUN(pow5mult, (struct _reent *, _Bigint *, int k)); +int _EXFUN(hi0bits,(__ULong)); +int _EXFUN(lo0bits,(__ULong *)); +_Bigint * _EXFUN(d2b,(struct _reent *p, double d, int *e, int *bits)); +_Bigint * _EXFUN(lshift,(struct _reent *p, _Bigint *b, int k)); +_Bigint * _EXFUN(diff,(struct _reent *p, _Bigint *a, _Bigint *b)); +int _EXFUN(cmp,(_Bigint *a, _Bigint *b)); + +double _EXFUN(ratio,(_Bigint *a, _Bigint *b)); +#define Bcopy(x,y) memcpy((char *)&x->_sign, (char *)&y->_sign, y->_wds*sizeof(__Long) + 2*sizeof(int)) + +#if defined(_DOUBLE_IS_32BITS) && defined(__v800) +#define n_bigtens 2 +#else +#define n_bigtens 5 +#endif + +extern _CONST double tinytens[]; +extern _CONST double bigtens[]; +extern _CONST double tens[]; + + +double _EXFUN(_mprec_log10,(int)); + +#endif diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_strtod.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_strtod.c new file mode 100644 index 000000000..f415da126 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_strtod.c @@ -0,0 +1,936 @@ +/* +FUNCTON + <>, <>---string to double or float + +INDEX + strtod +INDEX + _strtod_r +INDEX + strtof + +ANSI_SYNOPSIS + #include + double strtod(const char *<[str]>, char **<[tail]>); + float strtof(const char *<[str]>, char **<[tail]>); + + double _strtod_r(void *<[reent]>, + const char *<[str]>, char **<[tail]>); + +TRAD_SYNOPSIS + #include + double strtod(<[str]>,<[tail]>) + char *<[str]>; + char **<[tail]>; + + float strtof(<[str]>,<[tail]>) + char *<[str]>; + char **<[tail]>; + + double _strtod_r(<[reent]>,<[str]>,<[tail]>) + char *<[reent]>; + char *<[str]>; + char **<[tail]>; + +DESCRIPTION + The function <> parses the character string <[str]>, + producing a substring which can be converted to a double + value. The substring converted is the longest initial + subsequence of <[str]>, beginning with the first + non-whitespace character, that has the format: + .[+|-]<[digits]>[.][<[digits]>][(e|E)[+|-]<[digits]>] + The substring contains no characters if <[str]> is empty, consists + entirely of whitespace, or if the first non-whitespace + character is something other than <<+>>, <<->>, <<.>>, or a + digit. If the substring is empty, no conversion is done, and + the value of <[str]> is stored in <<*<[tail]>>>. Otherwise, + the substring is converted, and a pointer to the final string + (which will contain at least the terminating null character of + <[str]>) is stored in <<*<[tail]>>>. If you want no + assignment to <<*<[tail]>>>, pass a null pointer as <[tail]>. + <> is identical to <> except for its return type. + + This implementation returns the nearest machine number to the + input decimal string. Ties are broken by using the IEEE + round-even rule. + + The alternate function <<_strtod_r>> is a reentrant version. + The extra argument <[reent]> is a pointer to a reentrancy structure. + +RETURNS + <> returns the converted substring value, if any. If + no conversion could be performed, 0 is returned. If the + correct value is out of the range of representable values, + plus or minus <> is returned, and <> is + stored in errno. If the correct value would cause underflow, 0 + is returned and <> is stored in errno. + +Supporting OS subroutines required: <>, <>, <>, +<>, <>, <>, <>. +*/ + +/**************************************************************** + * + * The author of this software is David M. Gay. + * + * Copyright (c) 1991 by AT&T. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose without fee is hereby granted, provided that this entire notice + * is included in all copies of any software which is or includes a copy + * or modification of this software and in all copies of the supporting + * documentation for such software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY + * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + * + ***************************************************************/ + +/* Please send bug reports to + David M. Gay + AT&T Bell Laboratories, Room 2C-463 + 600 Mountain Avenue + Murray Hill, NJ 07974-2070 + U.S.A. + dmg@research.att.com or research!dmg + */ + + +/* Scanf and printf call both the small_mprec.c file if small_scanf + * has not been specfied optimizations concerning small_mprec.c and + * call of balloc will be performed anyway for scanf. + */ + +#ifdef _SMALL_PRINTF +#ifndef SMALL_SCANF +#define SMALL_SCANF +#endif +#endif + + +#include <_ansi.h> +#include +#include +#include "small_mprec.h" + +double +_DEFUN (_strtod_r, (ptr, s00, se), + struct _reent *ptr _AND + _CONST char *s00 _AND + char **se) +{ + int bb2, bb5, bbe, bd2, bd5, bbbits, bs2, c, dsign, e1, esign, i, j, + k, nd, nd0, nf, nz, nz0, sign; + long e; + _CONST char *s, *s0, *s1; + double aadj, aadj1, adj; + long L; + unsigned long z; + __ULong y; + union double_union rv, rv0; + + _Bigint *bb, *bb1, *bd, *bd0, *bs, *delta; + + #ifdef SMALL_SCANF + + /* + * For the SMALL_SCANF implementation for floating points numbers : + * - To avoid the call of allocator we defined a buffer for each variable : instead of taking the adress + * provided by Balloc variables are initialized to the beginning of the array. + * - For some variables many buffers have been declared, in fact for each call of small_lshift we used a + * buffer that has not been used at the moment + * - This buffers are used in the call of function declared in small_mprec.h + * To have more informations look at small_mprec.c + */ + + + + #define BUF_SIZE 32 + #define BUF_LSHIFT_SIZE 40 + + _Bigint tab_bb[BUF_LSHIFT_SIZE],tab_bb1[BUF_SIZE],tab_bd[BUF_SIZE],tab_bd0[BUF_SIZE],tab_bs[BUF_LSHIFT_SIZE], tab_delta[BUF_LSHIFT_SIZE]; + _Bigint tab_bblshift[BUF_LSHIFT_SIZE],tab_bslshift[BUF_LSHIFT_SIZE], tab_deltalshift[BUF_LSHIFT_SIZE],tab_bdlshift[BUF_LSHIFT_SIZE]; + #endif + + sign = nz0 = nz = 0; + rv.d = 0.; + for (s = s00;; s++) + switch (*s) + { + case '-': + sign = 1; + /* no break */ + case '+': + if (*++s) + goto break2; + /* no break */ + case 0: + s = s00; + goto ret; + case '\t': + case '\n': + case '\v': + case '\f': + case '\r': + case ' ': + continue; + default: + goto break2; + } +break2: + if (*s == '0') + { + nz0 = 1; + while (*++s == '0'); + if (!*s) + goto ret; + } + s0 = s; + y = z = 0; + for (nd = nf = 0; (c = *s) >= '0' && c <= '9'; nd++, s++) + if (nd < 9) + y = 10 * y + c - '0'; + else if (nd < 16) + z = 10 * z + c - '0'; + nd0 = nd; + if (c == '.') + { + c = *++s; + if (!nd) + { + for (; c == '0'; c = *++s) + nz++; + if (c > '0' && c <= '9') + { + s0 = s; + nf += nz; + nz = 0; + goto have_dig; + } + goto dig_done; + } + for (; c >= '0' && c <= '9'; c = *++s) + { + have_dig: + nz++; + if (c -= '0') + { + nf += nz; + for (i = 1; i < nz; i++) + if (nd++ < 9) + y *= 10; + else if (nd <= DBL_DIG + 1) + z *= 10; + if (nd++ < 9) + y = 10 * y + c; + else if (nd <= DBL_DIG + 1) + z = 10 * z + c; + nz = 0; + } + } + } +dig_done: + e = 0; + if (c == 'e' || c == 'E') + { + if (!nd && !nz && !nz0) + { + s = s00; + goto ret; + } + s00 = s; + esign = 0; + switch (c = *++s) + { + case '-': + esign = 1; + case '+': + c = *++s; + } + if (c >= '0' && c <= '9') + { + while (c == '0') + c = *++s; + if (c > '0' && c <= '9') + { + e = c - '0'; + s1 = s; + while ((c = *++s) >= '0' && c <= '9') + e = 10 * e + c - '0'; + if (s - s1 > 8) + /* Avoid confusion from exponents + * so large that e might overflow. + */ + e = 9999999L; + if (esign) + e = -e; + } + else + e = 0; + } + else + s = s00; + } + if (!nd) + { + if (!nz && !nz0) + s = s00; + goto ret; + } + e1 = e -= nf; + + /* Now we have nd0 digits, starting at s0, followed by a + * decimal point, followed by nd-nd0 digits. The number we're + * after is the integer represented by those digits times + * 10**e */ + + if (!nd0) + nd0 = nd; + k = nd < DBL_DIG + 1 ? nd : DBL_DIG + 1; + rv.d = y; + if (k > 9) + #ifndef SMALL_SCANF + rv.d = tens[k - 9] * rv.d + z; + #else + rv.d = small_tens[k - 9] * rv.d + z; + #endif + bd0 = 0; + if (nd <= DBL_DIG +#ifndef RND_PRODQUOT + && FLT_ROUNDS == 1 +#endif + ) + { + if (!e) + goto ret; + if (e > 0) + { + if (e <= Ten_pmax) + { +#ifdef VAX + goto vax_ovfl_check; +#else + #ifndef SMALL_SCANF + /* rv.d = */ rounded_product (rv.d, tens[e]); + #else + rounded_product (rv.d, small_tens[e]); + #endif + goto ret; +#endif + } + i = DBL_DIG - nd; + if (e <= Ten_pmax + i) + { + /* A fancier test would sometimes let us do + * this for larger i values. + */ + e -= i; + #ifndef SMALL_SCANF + rv.d *= tens[i]; + #else + rv.d *= small_tens[i]; + #endif +#ifdef VAX + /* VAX exponent range is so narrow we must + * worry about overflow here... + */ + vax_ovfl_check: + word0 (rv) -= P * Exp_msk1; + #ifndef SMALL_SCANF + /* rv.d = */ rounded_product (rv.d, tens[e]); + #else + /* rv.d = */ rounded_product (rv.d, small_tens[e]); + #endif + if ((word0 (rv) & Exp_mask) + > Exp_msk1 * (DBL_MAX_EXP + Bias - 1 - P)) + goto ovfl; + word0 (rv) += P * Exp_msk1; +#else + #ifndef SMALL_SCANF + /* rv.d = */ rounded_product (rv.d, tens[e]); + #else + /* rv.d = */ rounded_product (rv.d, small_tens[e]); + #endif +#endif + goto ret; + } + } +#ifndef Inaccurate_Divide + else if (e >= -Ten_pmax) + { + #ifndef SMALL_SCANF + /* rv.d = */ rounded_quotient (rv.d, tens[-e]); + #else + /* rv.d = */ rounded_quotient (rv.d, small_tens[-e]); + #endif + goto ret; + } +#endif + } + e1 += nd - k; + + /* Get starting approximation = rv.d * 10**e1 */ + + if (e1 > 0) + { + if ((i = e1 & 15) != 0) + #ifndef SMALL_SCANF + rv.d *= tens[i]; + #else + rv.d *= small_tens[i]; + #endif + if (e1 &= ~15) + { + if (e1 > DBL_MAX_10_EXP) + { + ovfl: + ptr->_errno = ERANGE; +#ifdef _HAVE_STDC + rv.d = HUGE_VAL; +#else + /* Can't trust HUGE_VAL */ +#ifdef IEEE_Arith + word0 (rv) = Exp_mask; +#ifndef _DOUBLE_IS_32BITS + word1 (rv) = 0; +#endif +#else + word0 (rv) = Big0; +#ifndef _DOUBLE_IS_32BITS + word1 (rv) = Big1; +#endif +#endif +#endif + if (bd0) + goto retfree; + goto ret; + } + if (e1 >>= 4) + { + for (j = 0; e1 > 1; j++, e1 >>= 1) + if (e1 & 1) + #ifndef SMALL_SCANF + rv.d *= bigtens[j]; + #else + rv.d *= small_bigtens[j]; + #endif + + /* The last multiplication could overflow. */ + word0 (rv) -= P * Exp_msk1; + #ifndef SMALL_SCANF + rv.d *= bigtens[j]; + #else + rv.d *= small_bigtens[j]; + #endif + + if ((z = word0 (rv) & Exp_mask) + > Exp_msk1 * (DBL_MAX_EXP + Bias - P)) + goto ovfl; + if (z > Exp_msk1 * (DBL_MAX_EXP + Bias - 1 - P)) + { + /* set to largest number */ + /* (Can't trust DBL_MAX) */ + word0 (rv) = Big0; +#ifndef _DOUBLE_IS_32BITS + word1 (rv) = Big1; +#endif + } + else + word0 (rv) += P * Exp_msk1; + } + + } + } + else if (e1 < 0) + { + e1 = -e1; + if ((i = e1 & 15) != 0) + #ifndef SMALL_SCANF + rv.d /= tens[i]; + #else + rv.d /= small_tens[i]; + #endif + if (e1 &= ~15) + { + e1 >>= 4; + if (e1 >= 1 << n_bigtens) + goto undfl; + for (j = 0; e1 > 1; j++, e1 >>= 1) + if (e1 & 1) + #ifndef SMALL_SCANF + rv.d *= tinytens[j]; + /* The last multiplication could underflow. */ + rv0.d = rv.d; + rv.d *=tinytens[j]; + #else + rv.d *= small_tinytens[j]; + /* The last multiplication could underflow. */ + rv0.d = rv.d; + rv.d *= small_tinytens[j]; + #endif + if (!rv.d) + { + rv.d = 2. * rv0.d; + #ifndef SMALL_SCANF + rv.d *= tinytens[j]; + #else + rv.d *= small_tinytens[j]; + #endif + if (!rv.d) + { + undfl: + rv.d = 0.; + ptr->_errno = ERANGE; + if (bd0) + goto retfree; + goto ret; + } +#ifndef _DOUBLE_IS_32BITS + word0 (rv) = Tiny0; + word1 (rv) = Tiny1; +#else + word0 (rv) = Tiny1; +#endif + /* The refinement below will clean + * this approximation up. + */ + } + } + } + + /* Now the hard part -- adjusting rv to the correct value.*/ + + /* Put digits into bd: true value = bd * 10^e */ + #ifndef SMALL_SCANF + bd0 = s2b (ptr, s0, nd0, nd, y); + #else + bd0 = small_s2b(ptr,s0, nd0, nd, y, &tab_bd0[0]); + #endif + + for (;;) + { + #ifndef SMALL_SCANF + bd = Balloc (ptr, bd0->_k); + #else + bd = &tab_bd[0]; + bd->_k = bd0->_k; + bd->_maxwds = 1 << (bd0->_k); + bd->_sign = bd->_wds =0; + + #endif + Bcopy (bd, bd0); + #ifndef SMALL_SCANF + bb = d2b (ptr, rv.d, &bbe, &bbbits); /* rv.d = bb * 2^bbe */ + bs = i2b (ptr, 1); + #else + bb = small_d2b (ptr, rv.d, &bbe, &bbbits, &tab_bb[0]); /* rv.d = bb * 2^bbe */ + bs = small_i2b (ptr, 1, &tab_bs[0]); + #endif + if (e >= 0) + { + bb2 = bb5 = 0; + bd2 = bd5 = e; + } + else + { + bb2 = bb5 = -e; + bd2 = bd5 = 0; + } + if (bbe >= 0) + bb2 += bbe; + else + bd2 -= bbe; + bs2 = bb2; +#ifdef Sudden_Underflow +#ifdef IBM + j = 1 + 4 * P - 3 - bbbits + ((bbe + bbbits - 1) & 3); +#else + j = P + 1 - bbbits; +#endif +#else + i = bbe + bbbits - 1; /* logb(rv.d) */ + if (i < Emin) /* denormal */ + j = bbe + (P - Emin); + else + j = P + 1 - bbbits; +#endif + bb2 += j; + bd2 += j; + i = bb2 < bd2 ? bb2 : bd2; + if (i > bs2) + i = bs2; + if (i > 0) + { + bb2 -= i; + bd2 -= i; + bs2 -= i; + } + if (bb5 > 0) + { + #ifndef SMALL_SCANF + bs = pow5mult (ptr, bs, bb5); + bb1 = mult (ptr, bs, bb); + Bfree (ptr, bb); + bb = bb1; + #else + if (bs == &tab_bs[0]){ + bs = small_pow5mult (ptr, bs, bb5,&tab_bslshift[0]); + } + else{ + bs = small_pow5mult (ptr, bs, bb5,&tab_bs[0]); + } + bb1 = small_mult (ptr, bs, bb,&tab_bb1[0]); + bb = bb1; + #endif + + } + + #ifndef SMALL_SCANF + if (bb2 > 0) + bb = lshift (ptr, bb, bb2); + if (bd5 > 0) + bd = pow5mult (ptr, bd, bd5); + if (bd2 > 0) + bd = lshift (ptr, bd, bd2); + if (bs2 > 0) + bs = lshift (ptr, bs, bs2); + delta = diff (ptr, bb, bd); + dsign = delta->_sign; + delta->_sign = 0; + i = cmp (delta, bs); + #else + if (bb2 > 0){ + if (bb == &tab_bb[0] ){ + bb = small_lshift (ptr, bb, bb2,&tab_bblshift[0]); + } + else { + bb = small_lshift (ptr, bb, bb2,&tab_bblshift[0]); + } + } + if (bd5 > 0){ + if (bd == &tab_bd[0]){ + bd = small_pow5mult (ptr, bd, bd5, &tab_bdlshift[0]); + } + else{ + bd = small_pow5mult (ptr, bd, bd5, &tab_bd[0]); + } + } + if (bd2 > 0){ + if (bd == &tab_bd[0] ){ + bd = small_lshift (ptr, bb, bd2,&tab_bdlshift[0]); + } + else { + bd = small_lshift (ptr, bd, bd2,&tab_bd[0]); + } + } + if (bs2 > 0){ + if ( bs == &tab_bs[0] ){ + bs = small_lshift (ptr, bs, bs2,&tab_bslshift[0]); + } + else{ + bs = small_lshift (ptr, bs, bs2,&tab_bs[0]); + } + } + + delta = small_diff (ptr, bb, bd,&tab_delta[0]); + dsign = delta->_sign; + delta->_sign = 0; + i = small_cmp (delta, bs); + + #endif + if (i < 0) + { + /* Error is less than half an ulp -- check for + * special case of mantissa a power of two. + */ + if (dsign || word1 (rv) || word0 (rv) & Bndry_mask) + break; + + #ifndef SMALL_SCANF + delta = lshift (ptr, delta, Log2P); + if (cmp (delta, bs) > 0) + goto drop_down; + #else + if (delta == &tab_delta[0]){ + delta = small_lshift (ptr, delta, Log2P,&tab_deltalshift[0]); + } + else{ + delta = small_lshift (ptr, delta, Log2P,&tab_delta[0]); + } + if (small_cmp (delta, bs) > 0) + goto drop_down; + #endif + break; + } + if (i == 0) + { + /* exactly half-way between */ + if (dsign) + { + if ((word0 (rv) & Bndry_mask1) == Bndry_mask1 + && word1 (rv) == 0xffffffff) + { + /*boundary case -- increment exponent*/ + word0 (rv) = (word0 (rv) & Exp_mask) + + Exp_msk1 +#ifdef IBM + | Exp_msk1 >> 4 +#endif + ; +#ifndef _DOUBLE_IS_32BITS + word1 (rv) = 0; +#endif + break; + } + } + else if (!(word0 (rv) & Bndry_mask) && !word1 (rv)) + { + drop_down: + /* boundary case -- decrement exponent */ +#ifdef Sudden_Underflow + L = word0 (rv) & Exp_mask; +#ifdef IBM + if (L < Exp_msk1) +#else + if (L <= Exp_msk1) +#endif + goto undfl; + L -= Exp_msk1; +#else + L = (word0 (rv) & Exp_mask) - Exp_msk1; +#endif + word0 (rv) = L | Bndry_mask1; +#ifndef _DOUBLE_IS_32BITS + word1 (rv) = 0xffffffff; +#endif +#ifdef IBM + goto cont; +#else + break; +#endif + } +#ifndef ROUND_BIASED + if (!(word1 (rv) & LSB)) + break; +#endif + if (dsign) + #ifndef SMALL_SCANF + rv.d += ulp (rv.d); + #else + rv.d += small_ulp (rv.d); + #endif +#ifndef ROUND_BIASED + else + { + #ifndef SMALL_SCANF + rv.d -= ulp (rv.d); + #else + rv.d -= small_ulp (rv.d); + #endif +#ifndef Sudden_Underflow + if (!rv.d) + goto undfl; +#endif + } +#endif + break; + } + + #ifndef SMALL_SCANF + if ((aadj = ratio (delta, bs)) <= 2.) + { + #else + if ((aadj = small_ratio (delta, bs)) <= 2.) + { + #endif + if (dsign) + aadj = aadj1 = 1.; + else if (word1 (rv) || word0 (rv) & Bndry_mask) + { +#ifndef Sudden_Underflow + if (word1 (rv) == Tiny1 && !word0 (rv)) + goto undfl; +#endif + aadj = 1.; + aadj1 = -1.; + } + else + { + /* special case -- power of FLT_RADIX to be */ + /* rounded down... */ + + if (aadj < 2. / FLT_RADIX) + aadj = 1. / FLT_RADIX; + else + aadj *= 0.5; + aadj1 = -aadj; + } + } + else + { + aadj *= 0.5; + aadj1 = dsign ? aadj : -aadj; +#ifdef Check_FLT_ROUNDS + switch (FLT_ROUNDS) + { + case 2: /* towards +infinity */ + aadj1 -= 0.5; + break; + case 0: /* towards 0 */ + case 3: /* towards -infinity */ + aadj1 += 0.5; + } +#else + if (FLT_ROUNDS == 0) + aadj1 += 0.5; +#endif + } + y = word0 (rv) & Exp_mask; + + /* Check for overflow */ + + if (y == Exp_msk1 * (DBL_MAX_EXP + Bias - 1)) + { + rv0.d = rv.d; + word0 (rv) -= P * Exp_msk1; + #ifndef SMALL_SCANF + adj = aadj1 * ulp (rv.d); + #else + adj = aadj1 * small_ulp (rv.d); + #endif + rv.d += adj; + if ((word0 (rv) & Exp_mask) >= + Exp_msk1 * (DBL_MAX_EXP + Bias - P)) + { + if (word0 (rv0) == Big0 && word1 (rv0) == Big1) + goto ovfl; +#ifdef _DOUBLE_IS_32BITS + word0 (rv) = Big1; +#else + word0 (rv) = Big0; + word1 (rv) = Big1; +#endif + goto cont; + } + else + word0 (rv) += P * Exp_msk1; + } + else + { +#ifdef Sudden_Underflow + if ((word0 (rv) & Exp_mask) <= P * Exp_msk1) + { + rv0.d = rv.d; + word0 (rv) += P * Exp_msk1; + #ifndef SMALL_SCANF + adj = aadj1 * ulp (rv.d); + #else + adj = aadj1 * small_ulp (rv.d); + #endif + rv.d += adj; + #ifdef IBM + if ((word0 (rv) & Exp_mask) < P * Exp_msk1) + #else + if ((word0 (rv) & Exp_mask) <= P * Exp_msk1) + #endif + { + if (word0 (rv0) == Tiny0 + && word1 (rv0) == Tiny1) + goto undfl; + word0 (rv) = Tiny0; + word1 (rv) = Tiny1; + goto cont; + } + else + word0 (rv) -= P * Exp_msk1; + } + else + { + #ifndef SMALL_SCANF + adj = aadj1 * ulp (rv.d); + #else + adj = aadj1 * small_ulp (rv.d); + #endif + rv.d += adj; + } +#else + /* Compute adj so that the IEEE rounding rules will + * correctly round rv.d + adj in some half-way cases. + * If rv.d * ulp(rv.d) is denormalized (i.e., + * y <= (P-1)*Exp_msk1), we must adjust aadj to avoid + * trouble from bits lost to denormalization; + * example: 1.2e-307 . + */ + if (y <= (P - 1) * Exp_msk1 && aadj >= 1.) + { + aadj1 = (double) (int) (aadj + 0.5); + if (!dsign) + aadj1 = -aadj1; + } + #ifndef SMALL_SCANF + adj = aadj1 * ulp (rv.d); + #else + adj = aadj1 * small_ulp (rv.d); + rv.d += adj; + #endif +#endif + } + z = word0 (rv) & Exp_mask; + if (y == z) + { + /* Can we stop now? */ + L = aadj; + aadj -= L; + /* The tolerances below are conservative. */ + if (dsign || word1 (rv) || word0 (rv) & Bndry_mask) + { + if (aadj < .4999999 || aadj > .5000001) + break; + } + else if (aadj < .4999999 / FLT_RADIX) + break; + } + cont: + #ifndef SMALL_SCANF + Bfree (ptr, bb); + Bfree (ptr, bd); + Bfree (ptr, bs); + Bfree (ptr, delta); + #else + ; + #endif + } +retfree: + #ifndef SMALL_SCANF + Bfree (ptr, bb); + Bfree (ptr, bd); + Bfree (ptr, bs); + Bfree (ptr, bd0); + Bfree (ptr, delta); + #endif +ret: + if (se) + *se = (char *) s; + return sign ? -rv.d : rv.d; +} + +#ifndef NO_REENT + +double +_DEFUN (strtod, (s00, se), + _CONST char *s00 _AND char **se) +{ + return _strtod_r (_REENT, s00, se); +} + +float +_DEFUN (strtof, (s00, se), + _CONST char *s00 _AND + char **se) +{ + return (float)_strtod_r (_REENT, s00, se); +} + +#endif diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_vfsscanf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_vfsscanf.c new file mode 100644 index 000000000..e248c3bf7 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_vfsscanf.c @@ -0,0 +1,1481 @@ +/* +FUNCTION +<>, <>, <>---format argument list + +INDEX + vscanf +INDEX + vfscanf +INDEX + vsscanf + +ANSI_SYNOPSIS + #include + #include + int vscanf(const char *<[fmt]>, va_list <[list]>); + int vfscanf(FILE *<[fp]>, const char *<[fmt]>, va_list <[list]>); + int vsscanf(const char *<[str]>, const char *<[fmt]>, va_list <[list]>); + + int _vscanf_r(void *<[reent]>, const char *<[fmt]>, + va_list <[list]>); + int _vfscanf_r(void *<[reent]>, FILE *<[fp]>, const char *<[fmt]>, + va_list <[list]>); + int _vsscanf_r(void *<[reent]>, const char *<[str]>, const char *<[fmt]>, + va_list <[list]>); + +TRAD_SYNOPSIS + #include + #include + int vscanf( <[fmt]>, <[ist]>) + char *<[fmt]>; + va_list <[list]>; + + int vfscanf( <[fp]>, <[fmt]>, <[list]>) + FILE *<[fp]>; + char *<[fmt]>; + va_list <[list]>; + + int vsscanf( <[str]>, <[fmt]>, <[list]>) + char *<[str]>; + char *<[fmt]>; + va_list <[list]>; + + int _vscanf_r( <[reent]>, <[fmt]>, <[ist]>) + char *<[reent]>; + char *<[fmt]>; + va_list <[list]>; + + int _vfscanf_r( <[reent]>, <[fp]>, <[fmt]>, <[list]>) + char *<[reent]>; + FILE *<[fp]>; + char *<[fmt]>; + va_list <[list]>; + + int _vsscanf_r( <[reent]>, <[str]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[str]>; + char *<[fmt]>; + va_list <[list]>; + +DESCRIPTION +<>, <>, and <> are (respectively) variants +of <>, <>, and <>. They differ only in +allowing their caller to pass the variable argument list as a +<> object (initialized by <>) rather than +directly accepting a variable number of arguments. + +RETURNS +The return values are consistent with the corresponding functions: +<> returns the number of input fields successfully scanned, +converted, and stored; the return value does not include scanned +fields which were not stored. + +If <> attempts to read at end-of-file, the return value +is <>. + +If no fields were stored, the return value is <<0>>. + +The routines <<_vscanf_r>>, <<_vfscanf_f>>, and <<_vsscanf_r>> are +reentrant versions which take an additional first parameter which points to the +reentrancy structure. + +PORTABILITY +These are GNU extensions. + +Supporting OS subroutines required: +*/ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + + +#include <_ansi.h> +//#include +#include +#include +#include +#include +#include +#include + + +#ifdef _HAVE_STDC +#include +#else +#include +#endif + +#ifndef SMALL_SCANF +#include "local.h" +#endif + + +#ifndef NO_FLOATING_POINT +#include +#endif + + + +#ifndef NO_FLOATING_POINT +#define FLOATING_POINT +#endif + +#ifdef FLOATING_POINT +#include + +/* Currently a test is made to see if long double processing is warranted. + This could be changed in the future should the _ldtoa_r code be + preferred over _dtoa_r. */ +#define _NO_LONGDBL +#if defined WANT_IO_LONG_DBL && (LDBL_MANT_DIG > DBL_MANT_DIG) +#undef _NO_LONGDBL +extern _LONG_DOUBLE _strtold _PARAMS((char *s, char **sptr)); +#endif + +#define _NO_LONGLONG +#if defined WANT_PRINTF_LONG_LONG && defined __GNUC__ +# undef _NO_LONGLONG +#endif + +#include "floatio.h" + +#if ((MAXEXP+MAXFRACT+3) > MB_LEN_MAX) +# define BUF (MAXEXP+MAXFRACT+3) /* 3 = sign + decimal point + NUL */ +#else +# define BUF MB_LEN_MAX +#endif + +/* An upper bound for how long a long prints in decimal. 4 / 13 approximates + log (2). Add one char for roundoff compensation and one for the sign. */ +#define MAX_LONG_LEN ((CHAR_BIT * sizeof (long) - 1) * 4 / 13 + 2) +#else +#define BUF 40 +#endif + + +/* + * Flags used during conversion. + */ + +#define LONG 0x01 /* l: long or double */ +#define LONGDBL 0x02 /* L/ll: long double or long long */ +#define SHORT 0x04 /* h: short */ +#define CHAR 0x08 /* hh: 8 bit integer */ +#define SUPPRESS 0x10 /* suppress assignment */ +#define POINTER 0x20 /* weird %p pointer (`fake hex') */ +#define NOSKIP 0x40 /* do not skip blanks */ + +/* + * The following are used in numeric conversions only: + * SIGNOK, NDIGITS, DPTOK, and EXPOK are for floating point; + * SIGNOK, NDIGITS, PFXOK, and NZDIGITS are for integral. + */ + +#define SIGNOK 0x80 /* +/- is (still) legal */ +#define NDIGITS 0x100 /* no digits detected */ + +#define DPTOK 0x200 /* (float) decimal point is still legal */ +#define EXPOK 0x400 /* (float) exponent (e+3, etc) still legal */ + +#define PFXOK 0x200 /* 0x prefix is (still) legal */ +#define NZDIGITS 0x400 /* no zero digits detected */ + +/* + * Conversion types. + */ + +#define CT_CHAR 0 /* %c conversion */ +#define CT_CCL 1 /* %[...] conversion */ +#define CT_STRING 2 /* %s conversion */ +#define CT_INT 3 /* integer, i.e., strtol or strtoul */ +#define CT_FLOAT 4 /* floating, i.e., strtod */ + +#if 0 +#define u_char unsigned char +#endif +#define u_char char +#define u_long unsigned long + +#ifndef _NO_LONGLONG +typedef unsigned long long u_long_long; +#endif + +/*static*/ u_char *__sccl (); + +/* + * vfscanf + */ + +#ifndef SMALL_SCANF +#define BufferEmpty (fp->_r <= 0 && __srefill(fp)) + +#else // SMALL_SCANF + +unsigned char buf_ungetc ; +int flag_buf_ungetc = 0 ; +#define buf_ungetc_empty 0 +#define buf_ungetc_full 1 + + +/* + Redefinition of ungetc : store in a buffer a character + Only ONE ungetc is allowed before a getchar + For each getchar, new_getchar() is called, then the buf is tested: + - if flag_buf_ungetc == 0 : new_getchar call __io_getchar() + - if flag_buf_ungetc == 1 : new_getchar returns character in the buffer + + */ + + + + +int __io_ungetc(int c){ + +if (flag_buf_ungetc == 0){ + flag_buf_ungetc = buf_ungetc_full; //flag to 1 to indicate that a caracter is in the buffer +} +buf_ungetc= (unsigned char)c ; + +return (c); +} + +int new_getchar() { +if (flag_buf_ungetc == 0){ + + return __io_getchar(); + +} +else { + + flag_buf_ungetc = buf_ungetc_empty; + return buf_ungetc; + +} + +} + +#endif // SMALL_SCANF + +#ifndef _REENT_ONLY + +int +_DEFUN (vfscanf, (fp, fmt, ap), + register FILE *fp _AND + _CONST char *fmt _AND + va_list ap) +{ + + #ifndef SMALL_SCANF + CHECK_INIT(fp); + #endif + + return __svfscanf_r (_REENT, fp, fmt, ap); +} + +int +__svfscanf (fp, fmt0, ap) + register FILE *fp; + char _CONST *fmt0; + va_list ap; +{ + return __svfscanf_r (_REENT, fp, fmt0, ap); +} + +#endif /* !_REENT_ONLY */ + +int +_DEFUN (_vfscanf_r, (data, fp, fmt, ap), + struct _reent *data _AND + register FILE *fp _AND + _CONST char *fmt _AND + va_list ap) +{ + return __svfscanf_r (data, fp, fmt, ap); +} + + + +/* + + +For SMALL_SCANF : +The use of files has been removed so as to use directly __io_getchar() +Buffer_empty is not anymore tested since _io_getchar() is blocked until +a character is entered. +Generally each *fp->_p ++ which equal to read a character on the file +has been replaced by a new_getchar() which call __io_getchar(); + + +*/ + +int +__svfscanf_r (rptr, fp, fmt0, ap) + struct _reent *rptr; + register FILE *fp; + char _CONST *fmt0; + va_list ap; +{ + + register char * bufread; + register u_char *fmt = (u_char *) fmt0; + register int c; /* character from format, or conversion */ + register int car; + register size_t width; /* field width, or 0 */ + register char *p; /* points into all kinds of strings */ + register int n; /* handy integer */ + register int flags; /* flags as defined above */ + register char *p0; /* saves original value of p when necessary */ + int nassigned; /* number of fields assigned */ + int nread; /* number of characters consumed from fp */ + int base = 0; /* base argument to strtol/strtoul */ + int nbytes = 1; /* number of bytes read from fmt string */ + wchar_t wc; /* wchar to use to read format string */ + wchar_t *wcp; /* handy wide character pointer */ + size_t mbslen; /* length of converted multibyte sequence */ + mbstate_t state; /* value to keep track of multibyte state */ + + u_long (*ccfn) () = 0; /* conversion function (strtol/strtoul) */ + char ccltab[256]; /* character class table for %[...] */ + char buf[BUF]; /* buffer for numeric conversions */ + char *lptr; /* literal pointer */ + + char *cp; + short *sp; + int *ip; + float *flp; + _LONG_DOUBLE *ldp; + double *dp; + long *lp; +#ifndef _NO_LONGLONG + long long *llp; +#endif + + /* `basefix' is used to avoid `if' tests in the integer scanner */ + static _CONST short basefix[17] = + {10, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + + nassigned = 0; + nread = 0; + for (;;) + { +#ifndef MB_CAPABLE + wc = *fmt; +#else + memset (&state, '\0', sizeof (state)); + nbytes = _mbtowc_r (rptr, &wc, fmt, MB_CUR_MAX, &state); +#endif + fmt += nbytes; + if (wc == 0) + return nassigned; + if (nbytes == 1 && isspace (wc)) + { + for (;;) + { + #ifndef SMALL_SCANF + if (BufferEmpty || !isspace (*fp->_p)) + break; + nread++, fp->_r--, fp->_p++; + + #else + if (!isspace (*fp->_p)) break; + nread++, fp->_r--; + *fp->_p = new_getchar(); + + #endif + } + + continue; + } + if (wc != '%') + goto literal; + width = 0; + flags = 0; + + /* + * switch on the format. continue if done; break once format + * type is derived. + */ + + again: + c = *fmt++; + switch (c) + { + case '%': + literal: + lptr = fmt - nbytes; + for (n = 0; n < nbytes; ++n) + { + #ifndef SMALL_SCANF + if (BufferEmpty) + goto input_failure; + #else + *fp->_p = new_getchar(); + #endif + + if (*fp->_p != *lptr) + goto match_failure; + #ifndef SMALL_SCANF + fp->_r--, fp->_p++; + nread++; + #else + fp->_r--; + *fp->_p = new_getchar(); + nread++; + #endif + ++lptr; + } + continue; + + case '*': + flags |= SUPPRESS; + goto again; + case 'l': + if (*fmt == 'l') /* Check for 'll' = long long (SUSv3) */ + { + ++fmt; + flags |= LONGDBL; + } + else + flags |= LONG; + goto again; + case 'L': + flags |= LONGDBL; + goto again; + case 'h': + if (*fmt == 'h') /* Check for 'hh' = char int (SUSv3) */ + { + ++fmt; + flags |= CHAR; + } + else + flags |= SHORT; + goto again; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + width = width * 10 + c - '0'; + goto again; + + /* + * Conversions. Those marked `compat' are for + * 4.[123]BSD compatibility. + * + * (According to ANSI, E and X formats are supposed to + * the same as e and x. Sorry about that.) + */ + + case 'D': /* compat */ + flags |= LONG; + /* FALLTHROUGH */ + case 'd': + c = CT_INT; + ccfn = (u_long (*)())_strtol_r; + base = 10; + break; + + case 'i': + c = CT_INT; + ccfn = (u_long (*)())_strtol_r; + base = 0; + break; + + case 'O': /* compat */ + flags |= LONG; + /* FALLTHROUGH */ + case 'o': + c = CT_INT; + ccfn = _strtoul_r; + base = 8; + break; + + case 'u': + c = CT_INT; + ccfn = _strtoul_r; + base = 10; + break; + + case 'X': /* compat XXX */ + case 'x': + flags |= PFXOK; /* enable 0x prefixing */ + c = CT_INT; + ccfn = _strtoul_r; + base = 16; + break; + +#ifdef FLOATING_POINT + case 'E': /* compat XXX */ + case 'G': /* compat XXX */ +/* ANSI says that E,G and X behave the same way as e,g,x */ + /* FALLTHROUGH */ + case 'e': + case 'f': + case 'g': + c = CT_FLOAT; + break; +#endif + case 'S': + flags |= LONG; + /* FALLTHROUGH */ + + case 's': + c = CT_STRING; + break; + + case '[': + fmt = __sccl (ccltab, fmt); + flags |= NOSKIP; + c = CT_CCL; + break; + + case 'C': + flags |= LONG; + /* FALLTHROUGH */ + + case 'c': + flags |= NOSKIP; + c = CT_CHAR; + break; + + case 'p': /* pointer format is like hex */ + flags |= POINTER | PFXOK; + c = CT_INT; + ccfn = _strtoul_r; + base = 16; + break; + + case 'n': + if (flags & SUPPRESS) /* ??? */ + continue; + if (flags & CHAR) + { + cp = va_arg (ap, char *); + *cp = nread; + } + else if (flags & SHORT) + { + sp = va_arg (ap, short *); + *sp = nread; + } + else if (flags & LONG) + { + lp = va_arg (ap, long *); + *lp = nread; + } +#ifndef _NO_LONGLONG + else if (flags & LONGDBL) + { + llp = va_arg (ap, long long*); + *llp = nread; + } +#endif + else + { + ip = va_arg (ap, int *); + *ip = nread; + } + continue; + + /* + * Disgusting backwards compatibility hacks. XXX + */ + case '\0': /* compat */ + return EOF; + + default: /* compat */ + if (isupper (c)) + flags |= LONG; + c = CT_INT; + ccfn = (u_long (*)())_strtol_r; + base = 10; + break; + } + + /* + * We have a conversion that requires input. + */ + #ifndef SMALL_SCANF + if (BufferEmpty) + goto input_failure; + #else + *fp->_p = new_getchar(); + #endif + + /* + * Consume leading white space, except for formats that + * suppress this. + */ + + if ((flags & NOSKIP) == 0) + { + while (isspace (*fp->_p)) + { + #ifndef SMALL_SCANF + nread++; + if (--fp->_r > 0) + fp->_p++; + else + if (__srefill (fp)) + goto input_failure; + #else + *fp->_p = new_getchar(); + #endif + } + /* + * Note that there is at least one character in the + * buffer, so conversions that do not set NOSKIP ca + * no longer result in an input failure. + */ + } + + /* + * Do the conversion. + */ + switch (c) + { + + case CT_CHAR: + /* scan arbitrary characters (sets NOSKIP) */ + if (width == 0) + width = 1; + if (flags & LONG) + { + if ((flags & SUPPRESS) == 0) + wcp = va_arg(ap, wchar_t *); + else + wcp = NULL; + n = 0; + while (width != 0) + { + + if (n == MB_CUR_MAX) + goto input_failure; + #ifndef SMALL_SCANF + buf[n++] = *fp->_p; + fp->_r -= 1; + fp->_p += 1; + memset((void *)&state, '\0', sizeof(mbstate_t)); + if ((mbslen = _mbrtowc_r(rptr, wcp, buf, n, &state)) + == (size_t)-1) + goto input_failure; /* Invalid sequence */ + #else + buf[n++] = *fp->_p; + *fp->_p = new_getchar(); + + #endif + + if (mbslen == 0 && !(flags & SUPPRESS)) + *wcp = L'\0'; + if (mbslen != (size_t)-2) /* Incomplete sequence */ + { + nread += n; + width -= 1; + if (!(flags & SUPPRESS)) + wcp += 1; + n = 0; + } + #ifndef SMALL_SCANF + if (BufferEmpty) + { + if (n != 0) + goto input_failure; + break; + } + #endif + } + if (!(flags & SUPPRESS)) + nassigned++; + } + else if (flags & SUPPRESS) + { + size_t sum = 0; + for (;;) + { + if ((n = fp->_r) < (int)width) + { + sum += n; + width -= n; + #ifndef SMALL_SCANF + fp->_p += n; + if (__srefill (fp)) + { + if (sum == 0) + goto input_failure; + break; + } + #else + *fp->_p = new_getchar(); + #endif + + } + else + { + sum += width; + fp->_r -= width; + #ifndef SMALL_SCANF + fp->_p += width; + #else + *fp->_p = new_getchar(); + #endif + + break; + } + } + nread += sum; + } + else + { + + #ifndef SMALL_SCANF + size_t r = fread ((_PTR) va_arg (ap, char *), 1, width, fp); + if (r == 0) + goto input_failure; + nread += r; + nassigned++; + + #else + bufread=(_PTR)va_arg(ap,char *); + int r; + for (r=0;r_p; + if ( r+1 < width){ + *fp->_p = new_getchar(); + } + } + #endif + } + break; + + case CT_CCL: + /* scan a (nonempty) character class (sets NOSKIP) */ + if (width == 0) + width = ~0; /* `infinity' */ + /* take only those things in the class */ + if (flags & SUPPRESS) + { + n = 0; + while (ccltab[*fp->_p]) + { + #ifndef SMALL_SCANF + n++, fp->_r--, fp->_p++; + if (--width == 0) + break; + if (BufferEmpty) + { + if (n == 0) + goto input_failure; + break; + } + #else + n++; + fp->_r++; + *fp->_p = new_getchar(); + #endif + + } + if (n == 0) + goto match_failure; + } + else + { + p0 = p = va_arg (ap, char *); + while (ccltab[*fp->_p]) + { + fp->_r--; + #ifndef SMALL_SCANF + *p++ = *fp->_p++; + if (--width == 0) + break; + if (BufferEmpty) + { + if (p == p0) + goto input_failure; + break; + } + #else + *p++ = *fp->_p; + *fp->_p= new_getchar(); + if (--width == 0) + break; + #endif + + } + n = p - p0; + if (n == 0) + goto match_failure; + *p = 0; + nassigned++; + } + nread += n; + break; + + case CT_STRING: + /* like CCL, but zero-length string OK, & no NOSKIP */ + + if (width == 0) + width = (size_t)~0; + if (flags & LONG) + { + /* Process %S and %ls placeholders */ + if ((flags & SUPPRESS) == 0) + wcp = va_arg(ap, wchar_t *); + else + wcp = &wc; + n = 0; + while (!isspace(*fp->_p) && width != 0) + { + if (n == MB_CUR_MAX) + goto input_failure; + buf[n++] = *fp->_p; + fp->_r -= 1; + #ifndef SMALL_SCANF + fp->_p += 1; + memset((void *)&state, '\0', sizeof(mbstate_t)); + if ((mbslen = _mbrtowc_r(rptr, wcp, buf, n, &state)) + == (size_t)-1) + goto input_failure; + #else + *fp->_p = new_getchar(); + #endif + + if (mbslen == 0) + *wcp = L'\0'; + + if (mbslen != (size_t)-2) /* Incomplete sequence */ + { + if (iswspace(*wcp)) + { + + while (n != 0) + #ifndef SMALL_SCANF + ungetc(buf[--n], fp); + #else + __io_ungetc(buf[--n]); + #endif + break; + + } + + nread += n; + width -= 1; + if ((flags & SUPPRESS) == 0) + wcp += 1; + n = 0; + } + #ifndef SMALL_SCANF + if (BufferEmpty) + { + if (n != 0) + goto input_failure; + break; + } + #endif + + } + if (!(flags & SUPPRESS)) + { + *wcp = L'\0'; + nassigned++; + } + } + else if (flags & SUPPRESS) + { + n = 0; + while (!isspace (*fp->_p)) + { + #ifndef SMALL_SCANF + n++, fp->_r--, fp->_p++; + if (--width == 0) + break; + if (BufferEmpty) + break; + #else + n++; + *fp->_p = new_getchar(); + if (*fp->_p == '\0') break; + #endif + + } + nread += n; + } + else + { + p0 = p = va_arg (ap, char *); + while (!isspace (*fp->_p)) + { + #ifndef SMALL_SCANF + fp->_r--; + *p++ = *fp->_p++; + if (--width == 0) + break; + if (BufferEmpty) + break; + #else + *p++=*fp->_p; + *fp->_p = new_getchar(); + if (*fp->_p == '\0') break; + #endif + + + } + *p = 0; + nread += p - p0; + nassigned++; + } + continue; + + case CT_INT: + /* scan an integer as if by strtol/strtoul */ +#ifdef hardway + if (width == 0 || width > sizeof (buf) - 1) + width = sizeof (buf) - 1; +#else + /* size_t is unsigned, hence this optimisation */ + if (--width > sizeof (buf) - 2) + width = sizeof (buf) - 2; + width++; +#endif + flags |= SIGNOK | NDIGITS | NZDIGITS; + for (p = buf; width; width--) + { + c = *fp->_p; + /* + * Switch on the character; `goto ok' if we + * accept it as a part of number. + */ + switch (c) + { + /* + * The digit 0 is always legal, but is special. + * For %i conversions, if no digits (zero or nonzero) + * have been scanned (only signs), we will have base==0. + * In that case, we should set it to 8 and enable 0x + * prefixing. Also, if we have not scanned zero digits + * before this, do not turn off prefixing (someone else + * will turn it off if we have scanned any nonzero digits). + */ + case '0': + if (base == 0) + { + base = 8; + flags |= PFXOK; + } + if (flags & NZDIGITS) + flags &= ~(SIGNOK | NZDIGITS | NDIGITS); + else + flags &= ~(SIGNOK | PFXOK | NDIGITS); + goto ok; + + /* 1 through 7 always legal */ + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + base = basefix[base]; + flags &= ~(SIGNOK | PFXOK | NDIGITS); + goto ok; + + /* digits 8 and 9 ok iff decimal or hex */ + case '8': + case '9': + base = basefix[base]; + if (base <= 8) + break; /* not legal here */ + flags &= ~(SIGNOK | PFXOK | NDIGITS); + goto ok; + + /* letters ok iff hex */ + case 'A': + case 'B': + case 'C': + case 'D': + case 'E': + case 'F': + case 'a': + case 'b': + case 'c': + case 'd': + case 'e': + case 'f': + /* no need to fix base here */ + if (base <= 10) + break; /* not legal here */ + flags &= ~(SIGNOK | PFXOK | NDIGITS); + goto ok; + + /* sign ok only as first character */ + case '+': + case '-': + if (flags & SIGNOK) + { + flags &= ~SIGNOK; + goto ok; + } + break; + + /* x ok iff flag still set & 2nd char */ + case 'x': + case 'X': + if (flags & PFXOK && p == buf + 1) + { + base = 16;/* if %i */ + flags &= ~PFXOK; + goto ok; + } + break; + } + /* + * If we got here, c is not a legal character + * for a number. Stop accumulating digits. + */ + + break; + ok: + /* + * c is legal: store it and look at the next. + */ + *p++ = c; + #ifndef SMALL_SCANF + if (--fp->_r > 0) + fp->_p++; + else + if (__srefill (fp)) + break; /* EOF */ + #else + + *fp->_p = new_getchar(); + + #endif + + } + /* + * If we had only a sign, it is no good; push back the sign. + * If the number ends in `x', it was [sign] '0' 'x', so push back + * the x and treat it as [sign] '0'. + */ + + if (flags & NDIGITS) + { + if (p > buf) + #ifndef SMALL_SCANF + _CAST_VOID ungetc (*(u_char *)-- p, fp); + #else + _CAST_VOID __io_ungetc (*(u_char *)-- p); + #endif + goto match_failure; + + } + + c = ((u_char *) p)[-1]; + if (c == 'x' || c == 'X') + { + --p; + #ifndef SMALL_SCANF + /*(void)*/ ungetc (c, fp); + #else + __io_ungetc (c); + #endif + + } + if ((flags & SUPPRESS) == 0) + { + u_long res; + + *p = 0; + res = (*ccfn) (rptr, buf, (char **) NULL, base); + if (flags & POINTER) + *(va_arg (ap, _PTR *)) = (_PTR) (unsigned _POINTER_INT) res; + else if (flags & CHAR) + { + cp = va_arg (ap, char *); + *cp = res; + } + else if (flags & SHORT) + { + sp = va_arg (ap, short *); + *sp = res; + } + else if (flags & LONG) + { + lp = va_arg (ap, long *); + *lp = res; + } +#ifndef _NO_LONGLONG + else if (flags & LONGDBL) + { + u_long_long resll; + if (ccfn == _strtoul_r) + resll = _strtoull_r (rptr, buf, (char **) NULL, base); + else + resll = _strtoll_r (rptr, buf, (char **) NULL, base); + llp = va_arg (ap, long long*); + *llp = resll; + } +#endif + else + { + ip = va_arg (ap, int *); + *ip = res; + } + nassigned++; + } + nread += p - buf; + break; + +#ifdef FLOATING_POINT + case CT_FLOAT: + { + /* scan a floating point number as if by strtod */ + /* This code used to assume that the number of digits is reasonable. + However, ANSI / ISO C makes no such stipulation; we have to get + exact results even when there is an unreasonable amount of + leading zeroes. */ + long leading_zeroes = 0; + long zeroes, exp_adjust; + char *exp_start = NULL; +#ifdef hardway + if (width == 0 || width > sizeof (buf) - 1) + width = sizeof (buf) - 1; +#else + /* size_t is unsigned, hence this optimisation */ + if (--width > sizeof (buf) - 2) + width = sizeof (buf) - 2; + width++; +#endif + flags |= SIGNOK | NDIGITS | DPTOK | EXPOK; + zeroes = 0; + exp_adjust = 0; + for (p = buf; width; ) + { + c = *fp->_p; + /* + * This code mimicks the integer conversion + * code, but is much simpler. + */ + switch (c) + { + + case '0': + if (flags & NDIGITS) + { + flags &= ~SIGNOK; + zeroes++; + goto fskip; + } + /* Fall through. */ + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + flags &= ~(SIGNOK | NDIGITS); + goto fok; + + case '+': + case '-': + if (flags & SIGNOK) + { + flags &= ~SIGNOK; + goto fok; + } + break; + case '.': + if (flags & DPTOK) + { + flags &= ~(SIGNOK | DPTOK); + leading_zeroes = zeroes; + goto fok; + } + break; + case 'e': + case 'E': + /* no exponent without some digits */ + if ((flags & (NDIGITS | EXPOK)) == EXPOK + || ((flags & EXPOK) && zeroes)) + { + if (! (flags & DPTOK)) + { + exp_adjust = zeroes - leading_zeroes; + exp_start = p; + } + flags = + (flags & ~(EXPOK | DPTOK)) | + SIGNOK | NDIGITS; + zeroes = 0; + goto fok; + } + break; + } + break; + fok: + *p++ = c; + fskip: + width--; + ++nread; + #ifndef SMALL_SCANF + if (--fp->_r > 0) + fp->_p++; + else + if (__srefill (fp)) + break; /* EOF */ + #else + *fp->_p = new_getchar(); + if ( (47<*fp->_p<58) && (64<*fp->_p < 71) && (96<*fp->_p<103) ){ + ; + } + else + { + break; + } + #endif + } + if (zeroes) + flags &= ~NDIGITS; + /* + * If no digits, might be missing exponent digits + * (just give back the exponent) or might be missing + * regular digits, but had sign and/or decimal point. + */ + if (flags & NDIGITS) + { + if (flags & EXPOK) + { + /* no digits at all */ + + while (p > buf) + { + #ifndef SMALL_SCANF + ungetc (*(u_char *)-- p, fp); + #else + __io_ungetc(*(u_char *)-- p); + #endif + --nread; + } + + goto match_failure; + + } + + /* just a bad exponent (e and maybe sign) */ + c = *(u_char *)-- p; + --nread; + if (c != 'e' && c != 'E') + { + #ifndef SMALL_SCANF + _CAST_VOID ungetc (c, fp); /* sign */ + #else + _CAST_VOID __io_ungetc (c); + #endif + c = *(u_char *)-- p; + --nread; + } + #ifndef SMALL_SCANF + _CAST_VOID ungetc (c, fp); + #else + _CAST_VOID __io_ungetc (c); + #endif + + } + if ((flags & SUPPRESS) == 0) + { + double res = 0; +#ifdef _NO_LONGDBL +#define QUAD_RES res; +#else /* !_NO_LONG_DBL */ + long double qres = 0; +#define QUAD_RES qres; +#endif /* !_NO_LONG_DBL */ + long new_exp = 0; + + *p = 0; + if ((flags & (DPTOK | EXPOK)) == EXPOK) + { + exp_adjust = zeroes - leading_zeroes; + new_exp = -exp_adjust; + exp_start = p; + } + else if (exp_adjust) + new_exp = _strtol_r (rptr, (exp_start + 1), NULL, 10) - exp_adjust; + if (exp_adjust) + { + + /* If there might not be enough space for the new exponent, + truncate some trailing digits to make room. */ + if (exp_start >= buf + sizeof (buf) - MAX_LONG_LEN) + exp_start = buf + sizeof (buf) - MAX_LONG_LEN - 1; + sprintf (exp_start, "e%ld", new_exp); + } + + /* Current _strtold routine is markedly slower than + _strtod_r. Only use it if we have a long double + result. */ +#ifndef _NO_LONGDBL /* !_NO_LONGDBL */ + if (flags & LONGDBL) + qres = _strtold (buf, NULL); + else +#endif + res = _strtod_r (rptr, buf, NULL); + if (flags & LONG) + { + dp = va_arg (ap, double *); + *dp = res; + } + else if (flags & LONGDBL) + { + ldp = va_arg (ap, _LONG_DOUBLE *); + *ldp = QUAD_RES; + } + else + { + flp = va_arg (ap, float *); + *flp = res; + } + nassigned++; + } + break; + } +#endif /* FLOATING_POINT */ + + } + } +input_failure: + return nassigned ? nassigned : -1; +match_failure: + return nassigned; +} + +/* + * Fill in the given table from the scanset at the given format + * (just after `['). Return a pointer to the character past the + * closing `]'. The table has a 1 wherever characters should be + * considered part of the scanset. + */ + +/*static*/ +u_char * +__sccl (tab, fmt) + register char *tab; + register u_char *fmt; +{ + register int c, n, v; + + /* first `clear' the whole table */ + c = *fmt++; /* first char hat => negated scanset */ + if (c == '^') + { + v = 1; /* default => accept */ + c = *fmt++; /* get new first char */ + } + else + v = 0; /* default => reject */ + /* should probably use memset here */ + for (n = 0; n < 256; n++) + tab[n] = v; + if (c == 0) + return fmt - 1; /* format ended before closing ] */ + + /* + * Now set the entries corresponding to the actual scanset to the + * opposite of the above. + * + * The first character may be ']' (or '-') without being special; the + * last character may be '-'. + */ + + v = 1 - v; + for (;;) + { + tab[c] = v; /* take character c */ + doswitch: + n = *fmt++; /* and examine the next */ + switch (n) + { + + case 0: /* format ended too soon */ + return fmt - 1; + + case '-': + /* + * A scanset of the form [01+-] is defined as `the digit 0, the + * digit 1, the character +, the character -', but the effect of a + * scanset such as [a-zA-Z0-9] is implementation defined. The V7 + * Unix scanf treats `a-z' as `the letters a through z', but treats + * `a-a' as `the letter a, the character -, and the letter a'. + * + * For compatibility, the `-' is not considerd to define a range if + * the character following it is either a close bracket (required by + * ANSI) or is not numerically greater than the character we just + * stored in the table (c). + */ + n = *fmt; + if (n == ']' || n < c) + { + c = '-'; + break; /* resume the for(;;) */ + } + fmt++; + do + { /* fill in the range */ + tab[++c] = v; + } + while (c < n); +#if 1 /* XXX another disgusting compatibility hack */ + /* + * Alas, the V7 Unix scanf also treats formats such + * as [a-c-e] as `the letters a through e'. This too + * is permitted by the standard.... + */ + goto doswitch; +#else + c = *fmt++; + if (c == 0) + return fmt - 1; + if (c == ']') + return fmt; +#endif + + break; + + + case ']': /* end of scanset */ + return fmt; + + default: /* just another character */ + c = n; + break; + } + } + /* NOTREACHED */ +} + + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcrtomb.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcrtomb.c new file mode 100644 index 000000000..81087563e --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcrtomb.c @@ -0,0 +1,59 @@ +#include +#include +#include +#include +#include + +#if defined( _SMALL_PRINTF ) || defined(SMALL_SCANF) +#define _ASCII_CAR +#endif + +size_t +_DEFUN (_wcrtomb_r, (ptr, s, wc, ps), + struct _reent *ptr _AND + char *s _AND + wchar_t wc _AND + mbstate_t *ps) +{ + +#ifndef _ASCII_CAR + int retval = 0; + char buf[10]; + + +#ifdef MB_CAPABLE + if (ps == NULL) + { + _REENT_CHECK_MISC(ptr); + ps = &(_REENT_WCRTOMB_STATE(ptr)); + } +#endif + + if (s == NULL) + retval = _wctomb_r (ptr, buf, L'\0', ps); + else + retval = _wctomb_r (ptr, s, wc, ps); + + if (retval == -1) + { + ps->__count = 0; + ptr->_errno = EILSEQ; + return (size_t)(-1); + } + else + return (size_t)retval; +#endif + int retval = 1 ; + return (size_t)retval; +} + +#ifndef _REENT_ONLY +size_t +_DEFUN (wcrtomb, (s, wc, ps), + char *s _AND + wchar_t wc _AND + mbstate_t *ps) +{ + return _wcrtomb_r (_REENT, s, wc, ps); +} +#endif /* !_REENT_ONLY */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcsrtombs.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcsrtombs.c new file mode 100644 index 000000000..5d7365350 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wcsrtombs.c @@ -0,0 +1,97 @@ +#include +#include +#include +#include +#include + +#if defined( _SMALL_PRINTF ) || defined(SMALL_SCANF) + #define _ASCII_CAR + #endif + +size_t +_DEFUN (_wcsrtombs_r, (r, dst, src, len, ps), + struct _reent *r _AND + char *dst _AND + const wchar_t **src _AND + size_t len _AND + mbstate_t *ps) +{ + + + char *ptr = dst; + char buff[10]; + wchar_t *pwcs; + size_t n; + int i; + +#ifdef MB_CAPABLE + if (ps == NULL) + { + _REENT_CHECK_MISC(r); + ps = &(_REENT_WCSRTOMBS_STATE(r)); + } +#endif + + /* If no dst pointer, treat len as maximum possible value. */ + if (dst == NULL) + len = (size_t)-1; + + n = 0; + pwcs = (wchar_t *)(*src); + + while (n < len) + { + int count = ps->__count; + wint_t wch = ps->__value.__wch; + #ifndef _ASCII_CAR + int bytes = _wcrtomb_r (r, buff, *pwcs, ps); + if (bytes == -1) + { + r->_errno = EILSEQ; + ps->__count = 0; + return (size_t)-1; + } + #else + int bytes = 1 ; + #endif + + if (n <= len - bytes && bytes < len) + { + n += bytes; + if (dst) + { + for (i = 0; i < bytes; ++i) + *ptr++ = buff[i]; + ++(*src); + } + if (*pwcs++ == 0x00) + { + if (dst) + *src = NULL; + ps->__count = 0; + return n - 1; + } + } + else + { + /* not enough room, we must back up state to before _wctomb_r call */ + ps->__count = count; + ps->__value.__wch = wch; + len = 0; + } + } + + return n; +} + +#ifndef _REENT_ONLY +size_t +_DEFUN (wcsrtombs, (dst, src, len, ps), + char *dst _AND + const wchar_t **src _AND + size_t len _AND + mbstate_t *ps) +{ + return _wcsrtombs_r (_REENT, dst, src, len, ps); +} +#endif /* !_REENT_ONLY */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wctomb_r.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wctomb_r.c new file mode 100644 index 000000000..5e9883a5f --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/small_wctomb_r.c @@ -0,0 +1,188 @@ +#include +#include +#include +#include +#include "mbctype.h" + +/* The following function concerns caracter coded in more than 0ne byte. For our small_printf we considered only + caracters coded in ASCII and therefore all our caracters are coded in 8 bits (One byte) + If you need the following treatment because caracter that you use are coded in more than one byte + comment the three following lines */ + +#if defined( _SMALL_PRINTF ) || defined(SMALL_SCANF) +#define _ASCII_CAR +#endif + + +/* for some conversions, we use the __count field as a place to store a state value */ +#define __state __count + +#ifndef _ASCII_CAR +extern char __lc_ctype[12]; +#endif +int +_DEFUN (_wctomb_r, (r, s, wchar, state), + struct _reent *r _AND + char *s _AND + wchar_t wchar _AND + mbstate_t *state) +{ + +#ifndef _ASCII_CAR + + if (strlen (__lc_ctype) <= 1) + { /* fall-through */ } + else if (!strcmp (__lc_ctype, "C-UTF-8")) + { + if (s == NULL) + return 0; /* UTF-8 encoding is not state-dependent */ + + if (wchar <= 0x7f) + { + *s = wchar; + return 1; + } + else if (wchar >= 0x80 && wchar <= 0x7ff) + { + *s++ = 0xc0 | ((wchar & 0x7c0) >> 6); + *s = 0x80 | (wchar & 0x3f); + return 2; + } + else if (wchar >= 0x800 && wchar <= 0xffff) + { + /* UTF-16 surrogates -- must not occur in normal UCS-4 data */ + if (wchar >= 0xd800 && wchar <= 0xdfff) + return -1; + + *s++ = 0xe0 | ((wchar & 0xf000) >> 12); + *s++ = 0x80 | ((wchar & 0xfc0) >> 6); + *s = 0x80 | (wchar & 0x3f); + return 3; + } + else if (wchar >= 0x10000 && wchar <= 0x1fffff) + { + *s++ = 0xf0 | ((wchar & 0x1c0000) >> 18); + *s++ = 0x80 | ((wchar & 0x3f000) >> 12); + *s++ = 0x80 | ((wchar & 0xfc0) >> 6); + *s = 0x80 | (wchar & 0x3f); + return 4; + } + else if (wchar >= 0x200000 && wchar <= 0x3ffffff) + { + *s++ = 0xf8 | ((wchar & 0x3000000) >> 24); + *s++ = 0x80 | ((wchar & 0xfc0000) >> 18); + *s++ = 0x80 | ((wchar & 0x3f000) >> 12); + *s++ = 0x80 | ((wchar & 0xfc0) >> 6); + *s = 0x80 | (wchar & 0x3f); + return 5; + } + else if (wchar >= 0x4000000 && wchar <= 0x7fffffff) + { + *s++ = 0xfc | ((wchar & 0x40000000) >> 30); + *s++ = 0x80 | ((wchar & 0x3f000000) >> 24); + *s++ = 0x80 | ((wchar & 0xfc0000) >> 18); + *s++ = 0x80 | ((wchar & 0x3f000) >> 12); + *s++ = 0x80 | ((wchar & 0xfc0) >> 6); + *s = 0x80 | (wchar & 0x3f); + return 6; + } + else + return -1; + } + else if (!strcmp (__lc_ctype, "C-SJIS")) + { + unsigned char char2 = (unsigned char)wchar; + unsigned char char1 = (unsigned char)(wchar >> 8); + + if (s == NULL) + return 0; /* not state-dependent */ + + if (char1 != 0x00) + { + /* first byte is non-zero..validate multi-byte char */ + if (_issjis1(char1) && _issjis2(char2)) + { + *s++ = (char)char1; + *s = (char)char2; + return 2; + } + else + return -1; + } + } + else if (!strcmp (__lc_ctype, "C-EUCJP")) + { + unsigned char char2 = (unsigned char)wchar; + unsigned char char1 = (unsigned char)(wchar >> 8); + + if (s == NULL) + return 0; /* not state-dependent */ + + if (char1 != 0x00) + { + /* first byte is non-zero..validate multi-byte char */ + if (_iseucjp (char1) && _iseucjp (char2)) + { + *s++ = (char)char1; + *s = (char)char2; + return 2; + } + else + return -1; + } + } + else if (!strcmp (__lc_ctype, "C-JIS")) + { + int cnt = 0; + unsigned char char2 = (unsigned char)wchar; + unsigned char char1 = (unsigned char)(wchar >> 8); + + if (s == NULL) + return 1; /* state-dependent */ + + if (char1 != 0x00) + { + /* first byte is non-zero..validate multi-byte char */ + if (_isjis (char1) && _isjis (char2)) + { + if (state->__state == 0) + { + /* must switch from ASCII to JIS state */ + state->__state = 1; + *s++ = ESC_CHAR; + *s++ = '$'; + *s++ = 'B'; + cnt = 3; + } + *s++ = (char)char1; + *s = (char)char2; + return cnt + 2; + } + else + return -1; + } + else + { + if (state->__state != 0) + { + /* must switch from JIS to ASCII state */ + state->__state = 0; + *s++ = ESC_CHAR; + *s++ = '('; + *s++ = 'B'; + cnt = 3; + } + *s = (char)char2; + return cnt + 1; + } + } + + if (s == NULL) + return 0; + #endif + /* otherwise we are dealing with a single byte character */ + *s = (char) wchar; + return 1; +} + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/sscanf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/sscanf.c new file mode 100644 index 000000000..ca80c0e71 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/sscanf.c @@ -0,0 +1,453 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + +FUNCTION + <>, <>, <>---scan and format input + +INDEX + scanf +INDEX + fscanf +INDEX + sscanf + +ANSI_SYNOPSIS + #include + + int scanf(const char *<[format]> [, <[arg]>, ...]); + int fscanf(FILE *<[fd]>, const char *<[format]> [, <[arg]>, ...]); + int sscanf(const char *<[str]>, const char *<[format]> + [, <[arg]>, ...]); + + int _scanf_r(struct _reent *<[ptr]>, const char *<[format]> [, <[arg]>, ...]); + int _fscanf_r(struct _reent *<[ptr]>, FILE *<[fd]>, const char *<[format]> [, <[arg]>, ...]); + int _sscanf_r(struct _reent *<[ptr]>, const char *<[str]>, const char *<[format]> + [, <[arg]>, ...]); + + +TRAD_SYNOPSIS + #include + + int scanf(<[format]> [, <[arg]>, ...]) + char *<[format]>; + + int fscanf(<[fd]>, <[format]> [, <[arg]>, ...]); + FILE *<[fd]>; + char *<[format]>; + + int sscanf(<[str]>, <[format]> [, <[arg]>, ...]); + char *<[str]>; + char *<[format]>; + + int _scanf_r(<[ptr]>, <[format]> [, <[arg]>, ...]) + struct _reent *<[ptr]>; + char *<[format]>; + + int _fscanf_r(<[ptr]>, <[fd]>, <[format]> [, <[arg]>, ...]); + struct _reent *<[ptr]>; + FILE *<[fd]>; + char *<[format]>; + + int _sscanf_r(<[ptr]>, <[str]>, <[format]> [, <[arg]>, ...]); + struct _reent *<[ptr]>; + char *<[str]>; + char *<[format]>; + + +DESCRIPTION + <> scans a series of input fields from standard input, + one character at a time. Each field is interpreted according to + a format specifier passed to <> in the format string at + <<*<[format]>>>. <> stores the interpreted input from + each field at the address passed to it as the corresponding argument + following <[format]>. You must supply the same number of + format specifiers and address arguments as there are input fields. + + There must be sufficient address arguments for the given format + specifiers; if not the results are unpredictable and likely + disasterous. Excess address arguments are merely ignored. + + <> often produces unexpected results if the input diverges from + an expected pattern. Since the combination of <> or <> + followed by <> is safe and easy, that is the preferred way + to be certain that a program is synchronized with input at the end + of a line. + + <> and <> are identical to <>, other than the + source of input: <> reads from a file, and <> + from a string. + + The routines <<_scanf_r>>, <<_fscanf_r>>, and <<_sscanf_r>> are reentrant + versions of <>, <>, and <> that take an additional + first argument pointing to a reentrancy structure. + + The string at <<*<[format]>>> is a character sequence composed + of zero or more directives. Directives are composed of + one or more whitespace characters, non-whitespace characters, + and format specifications. + + Whitespace characters are blank (<< >>), tab (<<\t>>), or + newline (<<\n>>). + When <> encounters a whitespace character in the format string + it will read (but not store) all consecutive whitespace characters + up to the next non-whitespace character in the input. + + Non-whitespace characters are all other ASCII characters except the + percent sign (<<%>>). When <> encounters a non-whitespace + character in the format string it will read, but not store + a matching non-whitespace character. + + Format specifications tell <> to read and convert characters + from the input field into specific types of values, and store then + in the locations specified by the address arguments. + + Trailing whitespace is left unread unless explicitly + matched in the format string. + + The format specifiers must begin with a percent sign (<<%>>) + and have the following form: + +. %[*][<[width]>][<[size]>]<[type]> + + Each format specification begins with the percent character (<<%>>). + The other fields are: + o+ + o * + an optional marker; if present, it suppresses interpretation and + assignment of this input field. + + o <[width]> + an optional maximum field width: a decimal integer, + which controls the maximum number of characters that + will be read before converting the current input field. If the + input field has fewer than <[width]> characters, <> + reads all the characters in the field, and then + proceeds with the next field and its format specification. + + If a whitespace or a non-convertable character occurs + before <[width]> character are read, the characters up + to that character are read, converted, and stored. + Then <> proceeds to the next format specification. + + o size + <>, <>, and <> are optional size characters which + override the default way that <> interprets the + data type of the corresponding argument. + + +.Modifier Type(s) +. hh d, i, o, u, x, n convert input to char, +. store in char object +. +. h d, i, o, u, x, n convert input to short, +. store in short object +. +. h D, I, O, U, X no effect +. e, f, c, s, p +. +. l d, i, o, u, x, n convert input to long, +. store in long object +. +. l e, f, g convert input to double +. store in a double object +. +. l D, I, O, U, X no effect +. c, s, p +. +. ll d, i, o, u, x, n convert to long long, +. store in long long +. +. L d, i, o, u, x, n convert to long long, +. store in long long +. +. L e, f, g, E, G convert to long double, +. store in long double +. +. L all others no effect + + + o <[type]> + + A character to specify what kind of conversion + <> performs. Here is a table of the conversion + characters: + + o+ + o % + No conversion is done; the percent character (<<%>>) is stored. + + o c + Scans one character. Corresponding <[arg]>: <<(char *arg)>>. + + o s + Reads a character string into the array supplied. + Corresponding <[arg]>: <<(char arg[])>>. + + o [<[pattern]>] + Reads a non-empty character string into memory + starting at <[arg]>. This area must be large + enough to accept the sequence and a + terminating null character which will be added + automatically. (<[pattern]> is discussed in the paragraph following + this table). Corresponding <[arg]>: <<(char *arg)>>. + + o d + Reads a decimal integer into the corresponding <[arg]>: <<(int *arg)>>. + + o D + Reads a decimal integer into the corresponding + <[arg]>: <<(long *arg)>>. + + o o + Reads an octal integer into the corresponding <[arg]>: <<(int *arg)>>. + + o O + Reads an octal integer into the corresponding <[arg]>: <<(long *arg)>>. + + o u + Reads an unsigned decimal integer into the corresponding + <[arg]>: <<(unsigned int *arg)>>. + + + o U + Reads an unsigned decimal integer into the corresponding <[arg]>: + <<(unsigned long *arg)>>. + + o x,X + Read a hexadecimal integer into the corresponding <[arg]>: + <<(int *arg)>>. + + o e, f, g + Read a floating-point number into the corresponding <[arg]>: + <<(float *arg)>>. + + o E, F, G + Read a floating-point number into the corresponding <[arg]>: + <<(double *arg)>>. + + o i + Reads a decimal, octal or hexadecimal integer into the + corresponding <[arg]>: <<(int *arg)>>. + + o I + Reads a decimal, octal or hexadecimal integer into the + corresponding <[arg]>: <<(long *arg)>>. + + o n + Stores the number of characters read in the corresponding + <[arg]>: <<(int *arg)>>. + + o p + Stores a scanned pointer. ANSI C leaves the details + to each implementation; this implementation treats + <<%p>> exactly the same as <<%U>>. Corresponding + <[arg]>: <<(void **arg)>>. + o- + + A <[pattern]> of characters surrounded by square brackets can be used + instead of the <> type character. <[pattern]> is a set of + characters which define a search set of possible characters making up + the <> input field. If the first character in the brackets is a + caret (<<^>>), the search set is inverted to include all ASCII characters + except those between the brackets. There is also a range facility + which you can use as a shortcut. <<%[0-9] >> matches all decimal digits. + The hyphen must not be the first or last character in the set. + The character prior to the hyphen must be lexically less than the + character after it. + + Here are some <[pattern]> examples: + o+ + o %[abcd] + matches strings containing only <>, <>, <>, and <>. + + o %[^abcd] + matches strings containing any characters except <>, <>, + <>, or <> + + o %[A-DW-Z] + matches strings containing <>, <>, <>, <>, <>, + <>, <>, <> + + o %[z-a] + matches the characters <>, <<->>, and <> + o- + + Floating point numbers (for field types <>, <>, <>, <>, + <>, <>) must correspond to the following general form: + +. [+/-] ddddd[.]ddd [E|e[+|-]ddd] + + where objects inclosed in square brackets are optional, and <> + represents decimal, octal, or hexadecimal digits. + o- + +RETURNS + <> returns the number of input fields successfully + scanned, converted and stored; the return value does + not include scanned fields which were not stored. + + If <> attempts to read at end-of-file, the return + value is <>. + + If no fields were stored, the return value is <<0>>. + + <> might stop scanning a particular field before + reaching the normal field end character, or may + terminate entirely. + + <> stops scanning and storing the current field + and moves to the next input field (if any) + in any of the following situations: + + O+ + o The assignment suppressing character (<<*>>) appears + after the <<%>> in the format specification; the current + input field is scanned but not stored. + + o <[width]> characters have been read (<[width]> is a + width specification, a positive decimal integer). + + o The next character read cannot be converted + under the the current format (for example, + if a <> is read when the format is decimal). + + o The next character in the input field does not appear + in the search set (or does appear in the inverted search set). + O- + + When <> stops scanning the current input field for one of + these reasons, the next character is considered unread and + used as the first character of the following input field, or the + first character in a subsequent read operation on the input. + + <> will terminate under the following circumstances: + + O+ + o The next character in the input field conflicts + with a corresponding non-whitespace character in the + format string. + + o The next character in the input field is <>. + + o The format string has been exhausted. + O- + + When the format string contains a character sequence that is + not part of a format specification, the same character + sequence must appear in the input; <> will + scan but not store the matched characters. If a + conflict occurs, the first conflicting character remains in the input + as if it had never been read. + +PORTABILITY +<> is ANSI C. + +Supporting OS subroutines required: <>, <>, <>, +<>, <>, <>, <>. +*/ + +#include <_ansi.h> +#include +#include +#include +#ifdef _HAVE_STDC +#include +#else +#include +#endif +#include "local.h" + +/* | ARGSUSED */ +/*SUPPRESS 590*/ +static +_READ_WRITE_RETURN_TYPE +eofread (cookie, buf, len) + _PTR cookie; + char *buf; + int len; +{ + return 0; +} + +#ifndef _REENT_ONLY + +#ifdef _HAVE_STDC +int +_DEFUN (sscanf, (str, fmt), _CONST char *str _AND _CONST char *fmt _DOTS) +#else +int +sscanf (str, fmt, va_alist) + _CONST char *str; + _CONST char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + FILE f; + + f._flags = __SRD; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._r = strlen (str); + f._read = eofread; + f._ub._base = NULL; + f._lb._base = NULL; +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = __svfscanf_r (_REENT, &f, fmt, ap); + va_end (ap); + return ret; +} + +#endif /* !_REENT_ONLY */ + +#ifdef _HAVE_STDC +int +_DEFUN (_sscanf_r, (ptr, str, fmt), struct _reent *ptr _AND _CONST char *str _AND _CONST char *fmt _DOTS) +#else +int +_sscanf_r (ptr, str, fmt, va_alist) + struct _reent *ptr; + _CONST char *str; + _CONST char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + FILE f; + + f._flags = __SRD; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._r = strlen (str); + f._read = eofread; + f._ub._base = NULL; + f._lb._base = NULL; +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = __svfscanf_r (ptr, &f, fmt, ap); + va_end (ap); + return ret; +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/swi.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/swi.h new file mode 100644 index 000000000..15c3866a1 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/swi.h @@ -0,0 +1,60 @@ +/* SWI numbers for RDP (Demon) monitor. */ +#define SWI_WriteC 0x0 +#define SWI_Write0 0x2 +#define SWI_ReadC 0x4 +#define SWI_CLI 0x5 +#define SWI_GetEnv 0x10 +#define SWI_Exit 0x11 +#define SWI_EnterOS 0x16 + +#define SWI_GetErrno 0x60 +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Open 0x66 + +#define SWI_Close 0x68 +#define SWI_Write 0x69 +#define SWI_Read 0x6a +#define SWI_Seek 0x6b +#define SWI_Flen 0x6c + +#define SWI_IsTTY 0x6e +#define SWI_TmpNam 0x6f +#define SWI_InstallHandler 0x70 +#define SWI_GenerateError 0x71 + + +/* Now the SWI numbers and reason codes for RDI (Angel) monitors. */ +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif + +/* The reason codes: */ +#define AngelSWI_Reason_Open 0x01 +#define AngelSWI_Reason_Close 0x02 +#define AngelSWI_Reason_WriteC 0x03 +#define AngelSWI_Reason_Write0 0x04 +#define AngelSWI_Reason_Write 0x05 +#define AngelSWI_Reason_Read 0x06 +#define AngelSWI_Reason_ReadC 0x07 +#define AngelSWI_Reason_IsTTY 0x09 +#define AngelSWI_Reason_Seek 0x0A +#define AngelSWI_Reason_FLen 0x0C +#define AngelSWI_Reason_TmpNam 0x0D +#define AngelSWI_Reason_Remove 0x0E +#define AngelSWI_Reason_Rename 0x0F +#define AngelSWI_Reason_Clock 0x10 +#define AngelSWI_Reason_Time 0x11 +#define AngelSWI_Reason_System 0x12 +#define AngelSWI_Reason_Errno 0x13 +#define AngelSWI_Reason_GetCmdLine 0x15 +#define AngelSWI_Reason_HeapInfo 0x16 +#define AngelSWI_Reason_EnterSVC 0x17 +#define AngelSWI_Reason_ReportException 0x18 +#define ADP_Stopped_ApplicationExit ((2 << 16) + 38) +#define ADP_Stopped_RunTimeError ((2 << 16) + 35) diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/syscalls.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/syscalls.c new file mode 100644 index 000000000..4633afcd8 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/syscalls.c @@ -0,0 +1,403 @@ +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + + +#if 0 + +/*You can comment this three lines if you want to use _gettimeofday and _times*/ + + +#if defined(_SMALL_PRINTF) || defined(SMALL_SCANF) +#define NO_TIME +#endif + +#include <_ansi.h> +#include +#include +#include +#include + +#ifndef NO_TIME + +#include +#include +#include + +#endif + +#include +#include +#include +#include "swi.h" + +/* Forward prototypes. */ + +int _system _PARAMS ((const char *)); + + + +int _rename _PARAMS ((const char *, const char *)); +int isatty _PARAMS ((int)); + +#ifndef NO_TIME +clock_t _times _PARAMS ((struct tms *)); +int _gettimeofday _PARAMS ((struct timeval *, struct timezone *)); +#endif + + +void _raise _PARAMS ((void)); + +int _unlink _PARAMS ((void)); +int _link _PARAMS ((void)); + +int _stat _PARAMS ((const char *, struct stat *)); + +int _fstat _PARAMS ((int, struct stat *)); + +//caddr_t _sbrk _PARAMS ((int)); +int _getpid _PARAMS ((int)); + +int _kill _PARAMS ((int, int)); +void _exit _PARAMS ((int)); +int _close _PARAMS ((int)); + +int _swiclose _PARAMS ((int)); +int _open _PARAMS ((const char *, int, ...)); +int _swiopen _PARAMS ((const char *, int)); +int _write _PARAMS ((int, char *, int)); +int _swiwrite _PARAMS ((int, char *, int)); +int _lseek _PARAMS ((int, int, int)); +int _swilseek _PARAMS ((int, int, int)); +int _read _PARAMS ((int, char *, int)); +int _swiread _PARAMS ((int, char *, int)); +void initialise_monitor_handles _PARAMS ((void)); + +static int wrap _PARAMS ((int)); +static int error _PARAMS ((int)); +static int get_errno _PARAMS ((void)); +static int remap_handle _PARAMS ((int)); +static int findslot _PARAMS ((int)); + +/* Register name faking - works in collusion with the linker. */ +register char * stack_ptr asm ("sp"); + + +/* following is copied from libc/stdio/local.h to check std streams */ +extern void _EXFUN(__sinit,(struct _reent *)); + +#ifndef _SMALL_PRINTF +#define CHECK_INIT(fp) \ + do \ + { \ + if ((fp)->_data == 0) \ + (fp)->_data = _REENT; \ + if (!(fp)->_data->__sdidinit) \ + __sinit ((fp)->_data); \ + } \ + while (0) +#endif +/* Adjust our internal handles to stay away from std* handles. */ +#define FILE_HANDLE_OFFSET (0x20) + +static int std_files_checked; +static int monitor_stdin; +static int monitor_stdout; +static int monitor_stderr; + +/* Struct used to keep track of the file position, just so we + can implement fseek(fh,x,SEEK_CUR). */ +typedef struct +{ + int handle; + int pos; +} +poslog; + +#define MAX_OPEN_FILES 20 +static poslog openfiles [MAX_OPEN_FILES]; +/* +static int findslot (int fh) +{ + int i; + for (i = 0; i < MAX_OPEN_FILES; i ++) + if (openfiles[i].handle == fh) + break; + return i; +} +*/ + +/* Function to convert std(in|out|err) handles to internal versions. */ +/* +static int remap_handle (int fh) +{ + if (!std_files_checked) + { + CHECK_INIT(stdin); + CHECK_INIT(stdout); + CHECK_INIT(stderr); + std_files_checked = 1; + } + if (fh == STDIN_FILENO) + return monitor_stdin; + if (fh == STDOUT_FILENO) + return monitor_stdout; + if (fh == STDERR_FILENO) + return monitor_stderr; + + return fh - FILE_HANDLE_OFFSET; +} +*/ + +/* +void +initialise_monitor_handles (void) +{ + int i; + + int fh; + const char * name; + + name = ":tt"; + asm ("mov r0,%2; mov r1, #0; swi %a1; mov %0, r0" + : "=r"(fh) + : "i" (SWI_Open),"r"(name) + : "r0","r1"); + monitor_stdin = fh; + + name = ":tt"; + asm ("mov r0,%2; mov r1, #4; swi %a1; mov %0, r0" + : "=r"(fh) + : "i" (SWI_Open),"r"(name) + : "r0","r1"); + monitor_stdout = monitor_stderr = fh; + + for (i = 0; i < MAX_OPEN_FILES; i ++) + openfiles[i].handle = -1; + + openfiles[0].handle = monitor_stdin; + openfiles[0].pos = 0; + openfiles[1].handle = monitor_stdout; + openfiles[1].pos = 0; +} +*/ + + + + +static int get_errno (void) +{ + asm ("swi %a0" :: "i" (SWI_GetErrno)); +} + +static int error (int result) +{ + errno = get_errno (); + return result; +} + + + +static int wrap (int result) +{ + if (result == -1) + return error (-1); + return result; +} + +#ifndef NO_FILE +int _read (int file, + char * ptr, + int len) +{ + return 0; +} + +int _lseek (int file, + int ptr, + int dir) +{ + return 0; +} + +extern void __io_putchar( char c ); + +int _write (int file, + char * ptr, + int len) +{ + int todo; + + for (todo = 0; todo < len; todo++) + { + __io_putchar( *ptr++ ); + } + + return len; +} + +int _open (const char * path, + int flags, + ...) +{ + return -1; +} + +int _close (int file) +{ + return -1; +} + +void _exit (int n) +{ + /* FIXME: return code is thrown away. */ + while(1); +} + + + +int _kill (int n, int m) +{ + return -1; +} + + +#if 0 //VC090825: moved to independent lib std_sbrk.lib +caddr_t _sbrk (int incr) +{ + extern char end; /* Defined by the linker */ + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) { + heap_end = &end; + } + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) + { + _write (1, "Heap and stack collision\n", 25); + abort (); + } + + heap_end += incr; + return (caddr_t) prev_heap_end; +} +#endif //if 0 //VC090825: moved to independent lib std_sbrk.lib + +#endif + +#include + +#ifndef NO_FILE +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + + +#endif + +int _stat (const char *fname, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + + +#ifndef NO_FILE +int _link (void) +{ + return -1; +} + +int _unlink (void) +{ + return -1; +} +#endif + +void _raise (void) +{ + return; +} + +#ifndef NO_TIME + +int _gettimeofday (struct timeval * tp, struct timezone * tzp) +{ + + if (tp) + { + /* Ask the host for the seconds since the Unix epoch. */ + { + int value; + asm ("swi %a1; mov %0, r0" : "=r" (value): "i" (SWI_Time) : "r0"); + tp->tv_sec = value; + } + tp->tv_usec = 0; + } + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + + + +/* Return a clock that ticks at 100Hz. */ +clock_t _times (struct tms * tp) +{ + clock_t timeval; + + asm ("swi %a1; mov %0, r0" : "=r" (timeval): "i" (SWI_Clock) : "r0"); + + if (tp) + { + tp->tms_utime = timeval; /* user time */ + tp->tms_stime = 0; /* system time */ + tp->tms_cutime = 0; /* user time, children */ + tp->tms_cstime = 0; /* system time, children */ + } + + return timeval; +}; + +#endif + + +int isatty (int fd) +{ + return 1; + fd = fd; +} + + + +int _system (const char *s) +{ + if (s == NULL) + return 0; + errno = ENOSYS; + return -1; +} + + +#ifndef NO_FILE + +int _rename (const char * oldpath, const char * newpath) +{ + errno = ENOSYS; + return -1; +} + +#endif + +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test.c new file mode 100644 index 000000000..d43ea6839 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test.c @@ -0,0 +1,254 @@ + +#include "UART0_stdio.h" + +int main() { + +char ent_char ; +int ent_dec_pos ; +int ent_dec_neg ; +int ent_hex ; +int ent_oct ; +int ent_oct_hex ; +long ent_slong ; +unsigned short ent_ushort ; +unsigned long ent_ulong ; +char tab_char[3] ; + + +char nom [50] ; +char mois[50] ; +int jour ; +int annee ; +int *ptr ; +char tab[3] ; +long double fld ; +float flottant ; +double f ; +double f4 ; +long double f1 ; +float f2, f3 ; + + + printf("Entrez un char:"); + scanf("%c" , &ent_char); + printf("%c\n", ent_char); + + + + printf("Entrez trois caracteres:\n"); + scanf("%3c" , tab_char); + printf("1er char :%c\n", tab_char[0]); + printf("2eme char :%c\n", tab_char[1]); + printf("3eme char :%c\n", tab_char[2]); + + printf("Entrez un nombre decimal positif: "); + scanf("%d" , &ent_dec_pos); + printf("%d\n", ent_dec_pos); + + printf("Entrez un nombre decimal negatif: "); + scanf("%d" , &ent_dec_neg); + printf("%d\n", ent_dec_neg); + + printf("Entrez un nombre decimal long: "); + scanf("%ld" , &ent_slong); + printf("%ld\n", ent_slong); + + printf("Entrez un nombre decimal unsigned long: "); + scanf("%lu" , &ent_ulong); + printf("valeur entree: %lu\n", ent_ulong); + + printf("Entrez un nombre decimal unsigned short: "); + scanf("%hu" , &ent_ushort); + printf("valeur entree: %lu\n", ent_ushort); + + + printf("Entrez un nombre en hexa: "); + scanf("%x" , &ent_hex); + printf("%x\n", ent_hex); + + printf("Entrez un nombre en octal: "); + scanf("%o" , &ent_oct); + printf("%o \n", ent_oct); + + printf("Entrez un nombre en octal ou hexa (preceder de 0 pour octal et de 0x ou 0X pour hexa), "); + scanf("%i" , &ent_oct_hex); + printf("valeur entree en decimal : %i \n", ent_oct_hex); + + printf("Entrez une chaine de caracteres: "); + scanf("%s" , nom); + printf("%s \n", nom); + + printf("Entrez le jour,le mois et l'annee:\n"); + + scanf("%d%s%d", &jour, mois, &annee); + printf("\njour:%d \n",jour); + printf("mois:%s \n",mois); + printf("annee:%d \n",annee); + + + + // Dans le cas du format %[...] : le scanf se termine lorsqu'un caractere n'appartenant pas a + // l'ensemble est detecte, inversement si on specifie %[^...] le scanf s'arrete lorsque'un + //caractere de l'ensembles a ete lu + + printf("Entrez une chaine de caracteres en majuscules: "); + scanf("%[A-Z]" , nom); + printf("%s \n", nom); + + printf("Entrez une chaine de caracteres sans majuscules pour terminer le scanf entrez une majuscule: "); + scanf("%[^A-Z]" , nom); + printf("%s \n", nom); + + printf("Entrez une adresse memoire quelconque \n"); + scanf("%p",&ptr); + printf("L'adresse %p contient la valeur %d ",ptr,*ptr); + +/* printf("Entrez un caractere: "); + scanf("%c" , &ent_char); + __io_ungetc(ent_char); + scanf("%c" , &ent_char); + printf("Apres un scanf suivi d'un ungetc et d'un scanf on a : %c \n", ent_char); + + printf("Entrez une chaine de 2 caracteres\n "); + scanf("%s" , nom); + printf("la chaine entree est %s \n",nom); + ent_char = __io_ungetc(nom[0]); + scanf("%c" , nom[0]) ; + printf("Apres un ungetc et d'un scanf on a : %s \n", nom); + */ + + printf("Entrer un float:\n"); + scanf("%f",&flottant); + printf("Le float entre est %f",flottant); + + printf("Entrer un double float:\n"); + scanf("%Lf",&f); + printf("Le float entre est %Lf\n",f); + + + printf("Entrer un nombre avec exposant :\n"); + scanf("%le",&f); + printf("Le float entre est %le\n",f); + + // Note : le format %g choisit en fonction de la valeur entree le format le plus + // appropriée entre %e et %f + + + printf("Entrer un nombre avec exposant :\n"); + scanf("%lg",&f); + printf("Le float entre est %lg\n",f); + + printf("Entrer un nombre avec exposant :\n"); + scanf("%Lg",&fld); + printf("Le float entre est %Lg\n",fld); + + +f1 = 48656568.256479123456789123456789; +f = 48656568.256479123456789123456789; +f2 = 456.45366; +f3 = 456.45362; +printf("Test for Floating points numbers printf\n"); + +/*Simple test of %f format */ + printf("double :%lf\n",f); + +/* Test with format specifying first number is equal to minimal number + of caracter to be print the second one is number of digits */ + +printf("LONG DOUBLE :%Lf - %20.10Lf - %20.15Lf - %20.20Lf - %30.30Lf\n", f1, f1, f1, f1, f1); +printf("float2 :%4.2f %+.0e %E \n", 3.1416, 3.1416, 3.1416); + +/*Note: the output should be float2: 3.14 +3e+000 3.141600E+000*/ + + printf("float3 :%7.3f\n", 1.2345); + printf("float3bis :%7.3lf\n",4865.256479 ); + printf("float4 :%10.3f\n", 1.2345e3); + printf("float5 :%10.3f\n", 1.2345e7); + printf("float6 :%12.4e\n", 1.2345); + printf("float7 :%12.4e\n", 123.456789e8); + printf("float8 :%15.5lf\n",48656568.256479 ); + printf("float9 :%15.6lf\n",48656568.256479 - 48656568.256478 ); + printf("float9bis :%-15.6lf%7.4f\n",48656568.256479 - 48656568.256478,1.2345 ); + printf("float9ter :%15.2lf\n",f2*f3 ); + +/*Note : the outputs shoud be +for 1.2345, ^^1.235 +for 1.2345e5, ^^1234.500 +for 1.2345e7, 12345000.000 +for 1.2345, ^^1.2345e+00 +for 123.456789e8, ^^1.2346e+10 + +for float 9: 48656568.256479 - 48656568.2563,^^^^^^^^0.00001 +for float 9bis: 48656568.256479 - 48656568.2563,0.00001^^^^^^^^1.2345 +for f2*f3 ,^^^^^^208349,92 +^ is equal to a space */ + + + printf("float10 :01234567 \n" ); + printf("float11 :%8g|\n", 12.34 ); + printf("float12 :%8g|\n", 1234.5678 ); + printf("float13 :%8g|\n", 0.0478 ); + printf("float14 :%8g|\n", 422121.0 ); + printf("float15 :%8g|\n", 422121234.345345 ); + +/*Note : outputs should be +01234567 + 12.34| + 1234.57| + 0.0478| + 422121| +4.22121e+08| +*/ + + +printf("float16 :%.0f|\n", 1000.123456789123456789 ); +printf("float17 :%.1f|\n", 2000.123456789123456789 ); +printf("float18 :%.2f|\n", 3000.123456789123456789 ); +printf("float19 :%.10f|\n", 4000.123456789123456789 ); +printf("float20 :%.30f|\n", 5000.123456789123456789 ); +printf("float21 :%f|\n", 6000.123456789123456789 ); +printf("float22 :%.f|\n", 7000.123456789123456789 ); + +/*Note : outputs should be +1000| +2000.1| +3000.12| +4000.1234567891| +5000.12345678912333823973312939761| +6000.123457| +7000| +*/ + +int a ; +char c ; +float ft ; +int hex ; +double db ; +char stg[50]="chaine" ; + +a=1; +// Test du printf avec une suite de parametres int +printf("Test suite de int: \n a=%d\na+1=%d\na+2=%d\na+3=%d\na+4=%d\na+5=%d\na+6=%d\na+7=%d\na+8=%d\na=%d\n",a,a+1,a+2,a+3,a+4,a+5,a+6,a+7,a+8,a); + +//Test du printf avec une suite de floats + ft=1.589634 ; + printf("Test suite de floats: \nft=%f\nft+0.1=%f\nft+0.01=%f\nft+0.001=%f\nft+0.0001=%f\nft+0.00001=%f\n",ft,ft+0.1,ft+0.01,ft+0.001,ft+0.0001,ft+0.00001); + +// Test du printf avec un melange de formats + +a = 1 ; +c ='c' ; +ft = 1.963214 ; +db = 1.589e+15; +hex = 0x0FA ; + + printf("Test avec plusieurs formats:\na=%d\nc=%c\nstg=%s\nft=%6.5f\ndb=%10.2e\nhex=%x\n",a,c,stg,ft,db,hex); + printf("Entrez dans l'ordre un int\n un char\n une chaine\nun float\nun float avec exposant\nun hexa \n"); + scanf("%d%c%s%f%le%x",&a,&c,stg,&ft,&db,&hex); + printf("Test avec plusieurs formats apres un scanf:\n a=%d\nc=%c\nstg=%s\nft=%6.5f\ndb=%10.2le\nhex=0x%x\n",a,c,stg,ft,db,hex); + + return 0; + + } + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_mes.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_mes.c new file mode 100644 index 000000000..ff24c0188 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_mes.c @@ -0,0 +1,44 @@ + +#define FLOATING +#define PRINT +#define SCANF + + +int main() { + +char ent_char ; +float flottant ; + +#ifndef FLOATING +#ifdef PRINT + ent_char='a'; +#endif + +#ifdef SCANF + scanf("%c" , &ent_char); +#endif + +#ifdef PRINT + printf("%c\n", ent_char); +#endif + + + +#else + #ifdef PRINT + flottant = 1.456789; +#endif + +#ifdef SCANF + scanf("%f" , &flottant); +#endif + +#ifdef PRINT + printf("%f\n", flottant); +#endif + +#endif + return 0; + + } + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_printf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_printf.c new file mode 100644 index 000000000..6bdbe5768 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_printf.c @@ -0,0 +1,87 @@ + +int main (){ +double f; + +/*double f4; +long double f1; +float f2, f3; +float flottant;*/ + + f = 48656568.256479123456789123456789; +/* +f1= 48656568.256479123456789123456789; +f2 = 456.45366; +f3 = 456.45362; */ +//printf("Test du printf"); + +/*Simple test of %f format */ +printf("double :%lf\n",f); + +/* Test with format specifying first number is equal to minimal number + of caracter to be print the second one is number of digits */ +/* +printf("LONG DOUBLE :%Lf - %20.10Lf - %20.15Lf - %20.20Lf - %30.30Lf\n", f1, f1, f1, f1, f1); +printf("float2 :%4.2f %+.0e %E \n", 3.1416, 3.1416, 3.1416);*/ + +/*Note: the output should be float2: 3.14 +3e+000 3.141600E+000*/ +/* +printf("float3 :%7.3f\n", 1.2345); +printf("float3bis :%7.3lf\n",4865.256479 ); +printf("float4 :%10.3f\n", 1.2345e3); +printf("float5 :%10.3f\n", 1.2345e7); +printf("float6 :%12.4e\n", 1.2345); +printf("float7 :%12.4e\n", 123.456789e8); +printf("float8 :%15.5lf\n",48656568.256479 ); +printf("float9 :%15.6lf\n",48656568.256479 - 48656568.256478 ); +printf("float9bis :%15.2lf\n",f2*f3 );*/ +/*Note : the outputs shoud be +for 1.2345, ^^1.235 +for 1.2345e5, ^^1234.500 +for 1.2345e7, 12345000.000 +for 1.2345, ^^1.2345e+00 +for 123.456789e8, ^^1.2346e+10 +for 48656568.256479 - 48656568.2563,^^^^^^^^0.00001 +for f2*f3 ,^^^^^^208349,92 +^ is equal to a space */ + +/* +printf("float10 :01234567 \n" ); +printf("float11 :%8g|\n", 12.34 ); +printf("float12 :%8g|\n", 1234.5678 ); +printf("float13 :%8g|\n", 0.0478 ); +printf("float14 :%8g|\n", 422121.0 ); +printf("float15 :%8g|\n", 422121234.345345 );*/ +/*Note : outputs should be +01234567 + 12.34| + 1234.57| + 0.0478| + 422121| +4.22121e+08| +*/ +/* + +printf("float16 :%.0f|\n", 1000.123456789123456789 ); +printf("float17 :%.1f|\n", 2000.123456789123456789 ); +printf("float18 :%.2f|\n", 3000.123456789123456789 ); +printf("float19 :%.10f|\n", 4000.123456789123456789 ); +printf("float20 :%.30f|\n", 5000.123456789123456789 ); +printf("float21 :%f|\n", 6000.123456789123456789 ); +printf("float22 :%.f|\n", 7000.123456789123456789 ); +*/ +/*Note : outputs should be +1000| +2000.1| +3000.12| +4000.1234567891| +5000.12345678912333823973312939761| +6000.123457| +7000| +*/ + + +//while(1); + +} + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_scanf.c b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_scanf.c new file mode 100644 index 000000000..1589642bb --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/test_scanf.c @@ -0,0 +1,14 @@ + + + +int main() { + +float flottant ; +// char c; +scanf("%f" , &flottant); +// scanf("%c",&c); + //while(1); + return 0; + + } + diff --git a/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/vfieeefp.h b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/vfieeefp.h new file mode 100644 index 000000000..1b240fcde --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/e_stdio/src/vfieeefp.h @@ -0,0 +1,284 @@ +/**************************************************************** + * + * The author of this software is David M. Gay. + * + * Copyright (c) 1991 by AT&T. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose without fee is hereby granted, provided that this entire notice + * is included in all copies of any software which is or includes a copy + * or modification of this software and in all copies of the supporting + * documentation for such software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY + * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + * + ***************************************************************/ + +/* Please send bug reports to + David M. Gay + AT&T Bell Laboratories, Room 2C-463 + 600 Mountain Avenue + Murray Hill, NJ 07974-2070 + U.S.A. + dmg@research.att.com or research!dmg + */ + +/* This header file is a modification of mprec.h that only contains floating + point union code. */ + +#include +#include +#include +#include +#include + +#ifdef __IEEE_LITTLE_ENDIAN +#define IEEE_8087 +#endif + +#ifdef __IEEE_BIG_ENDIAN +#define IEEE_MC68k +#endif + +#ifdef __Z8000__ +#define Just_16 +#endif + +#ifdef Unsigned_Shifts +#define Sign_Extend(a,b) if (b < 0) a |= (__uint32_t)0xffff0000; +#else +#define Sign_Extend(a,b) /*no-op*/ +#endif + +#if defined(IEEE_8087) + defined(IEEE_MC68k) + defined(VAX) + defined(IBM) != 1 +Exactly one of IEEE_8087, IEEE_MC68k, VAX, or IBM should be defined. +#endif + +#ifdef WANT_IO_LONG_DBL +/* If we are going to examine or modify specific bits in a long double using + the lword0 or lwordx macros, then we must wrap the long double inside + a union. This is necessary to avoid undefined behavior according to + the ANSI C spec. */ + +#ifdef IEEE_8087 +#if LDBL_MANT_DIG == 24 +struct ldieee +{ + unsigned manh:23; + unsigned exp:8; + unsigned sign:1; +}; +#elif LDBL_MANT_DIG == 53 +struct ldieee +{ + unsigned manl:20; + unsigned manh:32; + unsigned exp:11; + unsigned sign:1; +}; +#elif LDBL_MANT_DIG == 64 +struct ldieee +{ + unsigned manl:32; + unsigned manh:32; + unsigned exp:15; + unsigned sign:1; +}; +#elif LDBL_MANT_DIG > 64 +struct ldieee +{ + unsigned manl3:16; + unsigned manl2:32; + unsigned manl:32; + unsigned manh:32; + unsigned exp:15; + unsigned sign:1; +}; +#endif /* LDBL_MANT_DIG */ +#else /* !IEEE_8087 */ +#if LDBL_MANT_DIG == 24 +struct ldieee +{ + unsigned sign:1; + unsigned exp:8; + unsigned manh:23; +}; +#elif LDBL_MANT_DIG == 53 +struct ldieee +{ + unsigned sign:1; + unsigned exp:11; + unsigned manh:32; + unsigned manl:20; +}; +#elif LDBL_MANT_DIG == 64 +struct ldieee +{ + unsigned sign:1; + unsigned exp:15; + unsigned manh:32; + unsigned manl:32; +}; +#elif LDBL_MANT_DIG > 64 +struct ldieee +{ + unsigned sign:1; + unsigned exp:15; + unsigned manh:32; + unsigned manl:32; + unsigned manl2:32; + unsigned manl3;16; +}; +#endif /* LDBL_MANT_DIG */ +#endif /* !IEEE_8087 */ +#endif /* WANT_IO_LONG_DBL */ + +/* If we are going to examine or modify specific bits in a double using + the word0 and/or word1 macros, then we must wrap the double inside + a union. This is necessary to avoid undefined behavior according to + the ANSI C spec. */ +union double_union +{ + double d; + __uint32_t i[2]; +}; + +#ifdef IEEE_8087 +#define word0(x) (x.i[1]) +#define word1(x) (x.i[0]) +#else +#define word0(x) (x.i[0]) +#define word1(x) (x.i[1]) +#endif + +/* #define P DBL_MANT_DIG */ +/* Ten_pmax = floor(P*log(2)/log(5)) */ +/* Bletch = (highest power of 2 < DBL_MAX_10_EXP) / 16 */ +/* Quick_max = floor((P-1)*log(FLT_RADIX)/log(10) - 1) */ +/* Int_max = floor(P*log(FLT_RADIX)/log(10) - 1) */ + +#if defined(IEEE_8087) + defined(IEEE_MC68k) +#if defined (_DOUBLE_IS_32BITS) +#define Exp_shift 23 +#define Exp_shift1 23 +#define Exp_msk1 ((__uint32_t)0x00800000L) +#define Exp_msk11 ((__uint32_t)0x00800000L) +#define Exp_mask ((__uint32_t)0x7f800000L) +#define P 24 +#define Bias 127 +#if 0 +#define IEEE_Arith /* it is, but the code doesn't handle IEEE singles yet */ +#endif +#define Emin (-126) +#define Exp_1 ((__uint32_t)0x3f800000L) +#define Exp_11 ((__uint32_t)0x3f800000L) +#define Ebits 8 +#define Frac_mask ((__uint32_t)0x007fffffL) +#define Frac_mask1 ((__uint32_t)0x007fffffL) +#define Ten_pmax 10 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Ten_pmax 10 +#define Bletch 2 +#define Bndry_mask ((__uint32_t)0x007fffffL) +#define Bndry_mask1 ((__uint32_t)0x007fffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 1 +#define Tiny0 0 +#define Tiny1 1 +#define Quick_max 5 +#define Int_max 6 +#define Infinite(x) (word0(x) == ((__uint32_t)0x7f800000L)) +#undef word0 +#undef word1 + +#define word0(x) (x.i[0]) +#define word1(x) 0 +#else + +#define Exp_shift 20 +#define Exp_shift1 20 +#define Exp_msk1 ((__uint32_t)0x100000L) +#define Exp_msk11 ((__uint32_t)0x100000L) +#define Exp_mask ((__uint32_t)0x7ff00000L) +#define P 53 +#define Bias 1023 +#define IEEE_Arith +#define Emin (-1022) +#define Exp_1 ((__uint32_t)0x3ff00000L) +#define Exp_11 ((__uint32_t)0x3ff00000L) +#define Ebits 11 +#define Frac_mask ((__uint32_t)0xfffffL) +#define Frac_mask1 ((__uint32_t)0xfffffL) +#define Ten_pmax 22 +#define Bletch 0x10 +#define Bndry_mask ((__uint32_t)0xfffffL) +#define Bndry_mask1 ((__uint32_t)0xfffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 1 +#define Tiny0 0 +#define Tiny1 1 +#define Quick_max 14 +#define Int_max 14 +#define Infinite(x) (word0(x) == ((__uint32_t)0x7ff00000L)) /* sufficient test for here */ +#endif + +#else +#undef Sudden_Underflow +#define Sudden_Underflow +#ifdef IBM +#define Exp_shift 24 +#define Exp_shift1 24 +#define Exp_msk1 ((__uint32_t)0x1000000L) +#define Exp_msk11 ((__uint32_t)0x1000000L) +#define Exp_mask ((__uint32_t)0x7f000000L) +#define P 14 +#define Bias 65 +#define Exp_1 ((__uint32_t)0x41000000L) +#define Exp_11 ((__uint32_t)0x41000000L) +#define Ebits 8 /* exponent has 7 bits, but 8 is the right value in b2d */ +#define Frac_mask ((__uint32_t)0xffffffL) +#define Frac_mask1 ((__uint32_t)0xffffffL) +#define Bletch 4 +#define Ten_pmax 22 +#define Bndry_mask ((__uint32_t)0xefffffL) +#define Bndry_mask1 ((__uint32_t)0xffffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 4 +#define Tiny0 ((__uint32_t)0x100000L) +#define Tiny1 0 +#define Quick_max 14 +#define Int_max 15 +#else /* VAX */ +#define Exp_shift 23 +#define Exp_shift1 7 +#define Exp_msk1 0x80 +#define Exp_msk11 ((__uint32_t)0x800000L) +#define Exp_mask ((__uint32_t)0x7f80L) +#define P 56 +#define Bias 129 +#define Exp_1 ((__uint32_t)0x40800000L) +#define Exp_11 ((__uint32_t)0x4080L) +#define Ebits 8 +#define Frac_mask ((__uint32_t)0x7fffffL) +#define Frac_mask1 ((__uint32_t)0xffff007fL) +#define Ten_pmax 24 +#define Bletch 2 +#define Bndry_mask ((__uint32_t)0xffff007fL) +#define Bndry_mask1 ((__uint32_t)0xffff007fL) +#define LSB ((__uint32_t)0x10000L) +#define Sign_bit ((__uint32_t)0x8000L) +#define Log2P 1 +#define Tiny0 0x80 +#define Tiny1 0 +#define Quick_max 15 +#define Int_max 15 +#endif +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/flash.c b/cpu/stm32w108/hal/micro/cortexm3/flash.c new file mode 100644 index 000000000..bf99b1771 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/flash.c @@ -0,0 +1,362 @@ +/** @file hal/micro/cortexm3/flash.c + * @brief Implements the generic flash manipulation routines. + * + * The file 'flash-sw-spec.txt' should provide *all* the information needed + * to understand and work with the FLITF and flash. + * + * + * + */ + +#include PLATFORM_HEADER +#include "error.h" +#include "hal/micro/cortexm3/bootloader/fib-bootloader.h" +#include "hal/micro/cortexm3/mpu.h" +#include "memmap.h" +#include "flash.h" + +// A translation table used to convert FibStatus codes to corresponding +// StStatus values +static const StStatus fibToStStatus[] = { + ST_SUCCESS, // FIB_SUCCESS 0 + ST_BAD_ARGUMENT, // FIB_ERR_UNALIGNED 1 + ST_BAD_ARGUMENT, // FIB_ERR_INVALID_ADDRESS 2 + ST_BAD_ARGUMENT, // FIB_ERR_INVALID_TYPE 3 + ST_ERR_FLASH_PROG_FAIL, // FIB_ERR_WRITE_PROTECTED 4 + ST_ERR_FLASH_PROG_FAIL, // FIB_ERR_WRITE_FAILED 5 + ST_ERR_FLASH_WRITE_INHIBITED, // FIB_ERR_ERASE_REQUIRED 6 + ST_ERR_FLASH_VERIFY_FAILED // FIB_ERR_VERIFY_FAILED 7 +}; + +//The purpose of flashEraseIsActive and halFlashEraseIsActive() is so that +//interrupts can query the flash library to find out of Flash Erase is +//active when their ISR gets invoked. This is useful because Flash Erase +//causes the chip to go ATOMIC for 21ms and this delay will disrupt interrupt +//latency. By having a sinple API that an ISR can query for this state, +//the ISR can appriopriately adjust for a 21ms latency time. +boolean flashEraseIsActive = FALSE; +boolean halFlashEraseIsActive(void) +{ + return flashEraseIsActive; +} + + +// Emulators do not have FIB bootloaders, so need to include a copy of +// these core flash routines. + +#if defined(ST_EMU_TEST) + +static void enableFlitf(void) +{ + //First, unlock the FLITF by writing the two key values to the Flash + //Protection Unlock register + FPEC_KEY = FPEC_KEY1; + FPEC_KEY = FPEC_KEY2; + + //Second, unlock the CIB by writing the two key values to the CIB + //Protection Unlock register + OPT_KEY = FPEC_KEY1; + OPT_KEY = FPEC_KEY2; + + //Turn on the FPEC clock for flash manipulation operations + FPEC_CLKREQ = FPEC_CLKREQ_FIELD; + + //make sure the FPEC clock is running before we proceed + while( (FPEC_CLKSTAT&FPEC_CLKACK) != FPEC_CLKACK) {} + + //just in case, wait until the flash is no longer busy + while( (FLASH_STATUS&FLASH_STATUS_FLA_BSY) == FLASH_STATUS_FLA_BSY ) {} +} + +static void disableFlitf(void) +{ + //make sure the FPEC is completely idle before turning off the clock + while( (FPEC_CLKSTAT&FPEC_CLKBSY) == FPEC_CLKBSY) {} + + //Turn off the FPEC clock now that we're done + FPEC_CLKREQ = FPEC_CLKREQ_RESET; + + //Set LOCK and clear OPTWREN to lock both the FLITF and the CIB. + //NOTE: The PROG bit must also be cleared otherwise Flash can still + // be programmed even with the LOCK bit set. BugzID: 6267 + FLASH_CTRL = FLASH_CTRL_LOCK; //lock the flash from further accesses +} + +static FibStatus fibFlashWrite(int32u address, int8u *data, int32u length, int32u dummy) +{ + int32u i; + int16u *ptr; + FibStatus status = FIB_SUCCESS; + // Address and length must be half-word aligned. + if ((address & 1) || (length & 1)) { + return FIB_ERR_UNALIGNED; + } + // Start and end address must be in MFB or CIB. + if (!((address >= MFB_BOTTOM && address + length <= MFB_TOP + 1) + || (address >= CIB_BOTTOM && address + length <= CIB_TOP + 1))) { + return FIB_ERR_INVALID_ADDRESS; + } + enableFlitf(); + ptr = (int16u *)address; + for (i = 0; i < length; i += 2) { + int16u currentData = *ptr; + int16u newData = HIGH_LOW_TO_INT(data[i + 1], data[i]); + // Only program the data if it makes sense to do so. + if (currentData == newData) { + // If the new data matches the flash, don't bother doing anything. + } else if (currentData == 0xFFFF || newData == 0x0000) { + // If the flash is 0xFFFF we're allowed to write anything. + // If the new data is 0x0000 it doesn't matter what the flash is. + // OPTWREN must stay set to keep CIB unlocked. + if ((CIB_OB_BOTTOM <= (int32u)ptr) && ((int32u)ptr <= CIB_OB_TOP)) { + FLASH_CTRL = (FLASH_CTRL_OPTWREN | FLASH_CTRL_OPTPROG); + } else { + FLASH_CTRL = (FLASH_CTRL_OPTWREN | FLASH_CTRL_PROG); + } + // Assigning data to the address performs the actual write. + (*ptr) = newData; + // Wait for the busy bit to clear, indicating operation is done. + while ((FLASH_STATUS & FLASH_STATUS_FLA_BSY) != 0) {} + // Reset the operation complete flag. + FLASH_STATUS = FLASH_STATUS_EOP; + // Check if any error bits have been tripped, and if so, exit. + // The bit PAGE_PROG_ERR is not relevant in this programming mode. + if (FLASH_STATUS & (FLASH_STATUS_WRP_ERR | FLASH_STATUS_PROG_ERR)) { + if (FLASH_STATUS & FLASH_STATUS_WRP_ERR) { + status = FIB_ERR_WRITE_PROTECTED; + } else { + status = FIB_ERR_WRITE_FAILED; + } + FLASH_STATUS = FLASH_STATUS_WRP_ERR; + FLASH_STATUS = FLASH_STATUS_PROG_ERR; + break; + } + } else { + status = FIB_ERR_ERASE_REQUIRED; + break; + } + ptr++; + } + disableFlitf(); + return status; +} + +static FibStatus fibFlashWriteVerify(int32u address, int8u *data, int32u length) +{ + int32u i; + int8u *ptr = (int8u *)address; + for (i = 0; i < length; i++) { + if (*ptr != data[i]) { + return FIB_ERR_VERIFY_FAILED; + } + ptr++; + } + return FIB_SUCCESS; +} + +static FibStatus fibFlashErase(FibEraseType eraseType, int32u address) +{ + int32u eraseOp; + int32u *ptr; + int32u length; + FibStatus status = FIB_SUCCESS; + if (BYTE_0(eraseType) == MFB_MASS_ERASE) { + eraseOp = FLASH_CTRL_MASSERASE; + ptr = (int32u *)MFB_BOTTOM; + length = MFB_SIZE_W; + } else if (BYTE_0(eraseType) == MFB_PAGE_ERASE) { + if (address < MFB_BOTTOM || address > MFB_TOP) { + return FIB_ERR_INVALID_ADDRESS; + } + eraseOp = FLASH_CTRL_PAGEERASE; + ptr = (int32u *)(address & MFB_PAGE_MASK_B); + length = MFB_PAGE_SIZE_W; + } else if (BYTE_0(eraseType) == CIB_ERASE) { + eraseOp = FLASH_CTRL_OPTWREN | FLASH_CTRL_OPTERASE; + ptr = (int32u *)CIB_BOTTOM; + length = CIB_SIZE_W; + } else { + return FIB_ERR_INVALID_TYPE; + } + if ((eraseType & DO_ERASE) != 0) { + enableFlitf(); + FLASH_CTRL = eraseOp; + if (BYTE_0(eraseType) == MFB_PAGE_ERASE) { + FLASH_ADDR = (address & MFB_PAGE_MASK_B); + } + eraseOp |= FLASH_CTRL_FLA_START; + // Perform the actual erase. + FLASH_CTRL = eraseOp; + // Wait for the busy bit to clear, indicating operation is done. + while ((FLASH_STATUS & FLASH_STATUS_FLA_BSY) != 0) {} + // Reset the operation complete flag. + FLASH_STATUS = FLASH_STATUS_EOP; + // Check for errors; the only relevant one for erasing is write protection. + if (FLASH_STATUS & FLASH_STATUS_WRP_ERR) { + FLASH_STATUS = FLASH_STATUS_WRP_ERR; + status = FIB_ERR_WRITE_PROTECTED; + } + disableFlitf(); + } + if (status == FIB_SUCCESS + && (eraseType & DO_VERIFY) != 0) { + int32u i; + for (i = 0; i < length; i++) { + if (*ptr != 0xFFFFFFFF) { + return FIB_ERR_VERIFY_FAILED; + } + ptr++; + } + } + return status; +} +#endif // ST_EMU_TEST + +static boolean verifyFib(void) +{ + // Ensure that a programmed FIB of a proper version is present + return ( (halFixedAddressTable.baseTable.type == FIXED_ADDRESS_TABLE_TYPE) && + ( ( (halFixedAddressTable.baseTable.version & FAT_MAJOR_VERSION_MASK) + == 0x0000 ) && + (halFixedAddressTable.baseTable.version >= 0x0002) + ) + ); +} + +//The parameter 'eraseType' chooses which erasure will be performed while +//the 'address' parameter chooses the page to be erased during MFB page erase. +StStatus halInternalFlashErase(int8u eraseType, int32u address) +{ + FibStatus status; + + ATOMIC( + BYPASS_MPU( + flashEraseIsActive = TRUE; + #if defined(ST_EMU_TEST) + // Always try to use the FIB bootloader if its present + if(verifyFib()) { + status = halFixedAddressTable.fibFlashErase( + (((int32u)eraseType) | DO_ERASE), + address); + } else { + status = fibFlashErase((((int32u)eraseType) | DO_ERASE), address); + } + #else + + + + assert(verifyFib()); + status = halFixedAddressTable.fibFlashErase( + (((int32u)eraseType) | DO_ERASE), + address); + #endif + ) + ) + //If there are any interrupts pending that could have been delayed for 21ms, + //they will be serviced here since we exit the ATOMIC block. These ISRs + //can query the flash library and find out that erasing is active. After + //this point, we're no longer ATOMIC/disrupting latency so our erase + //active flag should be cleared. + flashEraseIsActive = FALSE; + + if(status!=FIB_SUCCESS) { + return fibToStStatus[status]; + } + + #if defined(ST_EMU_TEST) + // Always try to use the FIB bootloader if its present + if(verifyFib()) { + status = halFixedAddressTable.fibFlashErase( + (((int32u)eraseType) | DO_VERIFY), + address); + } else { + status = fibFlashErase((((int32u)eraseType) | DO_VERIFY), address); + } + #else + status = halFixedAddressTable.fibFlashErase( + (((int32u)eraseType) | DO_VERIFY), + address); + #endif + return fibToStStatus[status]; +} + + +//The parameter 'address' defines the starting address of where the +//programming will occur - this parameter MUST be half-word aligned since all +//programming operations are HW. The parameter 'data' is a pointer to a buffer +//containin the 16bit half-words to be written. Length is the number of 16bit +//half-words contained in 'data' to be written to flash. +//NOTE: This function can NOT write the option bytes and will throw an error +//if that is attempted. +StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length) +{ + FibStatus status; + + length = length * 2; // fib routines specify length in bytes + + ATOMIC( + BYPASS_MPU( + #if defined(ST_EMU_TEST) + // Always try to use the FIB bootloader if its present + if(verifyFib()) { + status = halFixedAddressTable.fibFlashWrite(address, + (int8u *)data, + length, + 0); + } else { + status = fibFlashWrite(address, (int8u *)data, length, 0); + } + #else + + + + // Ensure that a programmed FIB of a proper version is present + assert(verifyFib()); + status = halFixedAddressTable.fibFlashWrite(address, + (int8u *)data, + length, + 0); + #endif + ) + ) + + if(status!=FIB_SUCCESS) { + return fibToStStatus[status]; + } + + #if defined(ST_EMU_TEST) + // Always try to use the FIB bootloader if its present + if(verifyFib()) { + status = halFixedAddressTable.fibFlashWrite(address, + (int8u *)data, + 0, + length); + } else { + status = fibFlashWriteVerify(address, (int8u *)data, length); + } + #else + status = halFixedAddressTable.fibFlashWrite(address, + (int8u *)data, + 0, + length); + #endif + + return fibToStStatus[status]; +} + + +//The parameter 'byte' is the option byte number to be programmed. This +//parameter can have a value of 0 through 7. 'data' is the 8bit value to be +//programmed into the option byte since the hardware will calculate the +//compliment and program the full 16bit option byte. +StStatus halInternalCibOptionByteWrite(int8u byte, int8u data) +{ + int16u dataAndInverse = HIGH_LOW_TO_INT(~data, data); + // There are only 8 option bytes, don't try to program more than that. + if (byte > 7) { + return ST_ERR_FLASH_PROG_FAIL; + } + return halInternalFlashWrite(CIB_OB_BOTTOM + (byte << 1), &dataAndInverse, 1); +} + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/flash.h b/cpu/stm32w108/hal/micro/cortexm3/flash.h new file mode 100644 index 000000000..32899892f --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/flash.h @@ -0,0 +1,126 @@ +/** @file hal/micro/cortexm3/flash.h + * @brief Header for flash for APIs + * + * + */ + +/** @addtogroup flash + * @brief Definition and description of public flash manipulation routines. + * + * @note + * During an erase or a write the flash is not available, + * which means code will not be executable from flash. These routines still + * execute from flash, though, since the bus architecture can support doing so. + * Additonally, this also means all interrupts will be disabled. + * + * Hardware documentation indicates 40us for a write and 21ms for an erase. + * + * See flash.h for source code. + *@{ + */ + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#include "memmap.h" + + +/** @brief Tells the calling code if a Flash Erase operation is active. + * + * This state is import to know because Flash Erasing is ATOMIC for 21ms + * and could disrupt interrupt latency. But if an ISR can know that it wasn't + * serviced immediately due to Flash Erasing, then the ISR has the opportunity + * to correct in whatever manner it needs to. + * + * @return A boolean flag: TRUE if Flash Erase is active, FALSE otherwise. + */ +boolean halFlashEraseIsActive(void); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +//[[ The following eraseType definitions must match the FIB erase types! ]] +/** + * @brief Assign numerical value to the type of erasure requested. + */ +#define MFB_MASS_ERASE 0x01 +#define MFB_PAGE_ERASE 0x02 +#define CIB_ERASE 0x03 + +/** @brief Erases a section of flash back to all 0xFFFF. + * + * @param eraseType Choose one of the three types of erasures to perform. + * - MFB_MASS_ERASE (0x01) Erase the entire main flash block. + * - MFB_PAGE_ERASE (0x02) Erase one hardware page in the main flash block + * chosen by the \c address parameter. + * - CIB_ERASE (0x03) Erase the entire customer information block. + * + * @param address This parameter is only effectual when a MFB_PAGE_ERASE is + * being performed. The hardware page encapsulating the address given in this + * parameter will be erased. A hardware page size depends on the chip + * + * @return An ::StStatus value indicating the success or failure of the + * command: + * - ST_ERR_FATAL if the \c eraseType is not valid + * - ST_ERR_FLASH_ERASE_FAIL if erasing failed due to write protection + * - ST_ERR_FLASH_VERIFY_FAILED if erase verification failed + * - ST_SUCCESS if erasure completed and verified properly + */ +StStatus halInternalFlashErase(int8u eraseType, int32u address); + +/** @brief Writes a block of words to flash. A page is erased + * to 0xFFFF at every address. Only two writes can be performed to the same + * address between erasures and this is enforced by the flash interface + * controller. If the value already in the address being written to is 0xFFFF, + * any value can be written. If the value is not 0xFFFF and not 0x0000, only + * 0x0000 can be written. If the value is 0x0000, nothing can be written. + * + * \b NOTE: This function can NOT write the option bytes and will throw an + * error if that is attempted. + * + * @param address The starting address of where the programming will occur. + * This parameter MUST be half-word aligned since all programming operations + * are half-words. Also, the address parameter is NOT a pointer. This + * routines will cast the address to a pointer for the actual hardware access. + * + * @param data A pointer to a buffer containing the 16bit (half-words) to + * be written. + * + * @param length The number of 16bit (half-words) contained in the data buffer + * to be written to flash. + * + * @return An ::StStatus value indicating the success or failure of the + * command: + * - ST_ERR_FLASH_PROG_FAIL if the address is not half-word aligned, the + * address is inside the option bytes, write protection is enabled, or the + * address is being written to more than twice between erasures. + * - ST_ERR_FLASH_VERIFY_FAILED if write verification failed + * - ST_SUCCESS if writing completed and verified properly + */ +StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length); + +/** @brief Writes an option byte to the customer information block. Only + * two writes can be performed to the same address between erasures and this + * is enforced by the flash interface controller. + * + * @param byte The option byte number, 0 though 7, to be programmed. + * + * @param data The 8 bit value to be programmed into the option byte. The + * hardware is responsible for calculating the compliment and programming + * the full 16bit option byte space. + * + * @return An ::StStatus value indicating the success or failure of the + * command: + * - ST_ERR_FLASH_PROG_FAIL if the byte chosen is greater than 7, write + * protection is enabled, or the byte is being written to more than twice + * between erasures. + * - ST_ERR_FLASH_VERIFY_FAILED if write verification failed + * - ST_SUCCESS if writing completed and verified properly + */ +StStatus halInternalCibOptionByteWrite(int8u byte, int8u data); + +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#endif //__FLASH_H__ + +/** @} END addtogroup */ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/led.c b/cpu/stm32w108/hal/micro/cortexm3/led.c new file mode 100644 index 000000000..9bdb2f0c7 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/led.c @@ -0,0 +1,52 @@ +/** @file hal/micro/cortexm3/led.c + * @brief LED manipulation routines; stack and example APIs + * + * + */ + +#include PLATFORM_HEADER +#include BOARD_HEADER +#include "hal/micro/led.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" + +#define GPIO_PxCLR_BASE (GPIO_PACLR_ADDR) +#define GPIO_PxSET_BASE (GPIO_PASET_ADDR) +#define GPIO_PxOUT_BASE (GPIO_PAOUT_ADDR) +// Each port is offset from the previous port by the same amount +#define GPIO_Px_OFFSET (GPIO_PBCFGL_ADDR-GPIO_PACFGL_ADDR) + +void halInitLed(void) +{ + /* Set GPIO pins for Led D1 and Led D3 */ + halGpioConfig(LED_D1, GPIOCFG_OUT); + halGpioConfig(LED_D3, GPIOCFG_OUT); + /* Switch off Led D1,D3 */ + halClearLed(LED_D1); + halClearLed(LED_D3); +} + +void halSetLed(HalBoardLed led) +{ + if(led/8 < 3) { + *((volatile int32u *)(GPIO_PxCLR_BASE+(GPIO_Px_OFFSET*(led/8)))) = BIT(led&7); + } +} + +void halClearLed(HalBoardLed led) +{ + if(led/8 < 3) { + *((volatile int32u *)(GPIO_PxSET_BASE+(GPIO_Px_OFFSET*(led/8)))) = BIT(led&7); + } +} + +void halToggleLed(HalBoardLed led) +{ + //to avoid contention with other code using the other pins for other + //purposes, we disable interrupts since this is a read-modify-write + ATOMIC( + if(led/8 < 3) { + *((volatile int32u *)(GPIO_PxOUT_BASE+(GPIO_Px_OFFSET*(led/8)))) ^= BIT(led&7); + } + ) +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h b/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h new file mode 100644 index 000000000..845ae67f0 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h @@ -0,0 +1,51 @@ +/** @file hal/micro/cortexm3/memmap-fat.h + * @brief STM32W108 series memory map fixed address table definition + * + * + */ +#ifndef __MEMMAP_FAT_H__ +#define __MEMMAP_FAT_H__ + +#ifndef __MEMMAP_TABLES_H__ + // if we weren't included via memmap-tables.h, define a dummy type for the BAT + typedef void HalBootloaderAddressTableType; +#endif + +#include "hal/micro/cortexm3/bootloader/fib-bootloader.h" + +// **************************************************************************** +// If any of these address table definitions ever need to change, it is highly +// desirable to only add new entries, and only add them on to the end of an +// existing address table... this will provide the best compatibility with +// any existing code which may utilize the tables, and which may not be able to +// be updated to understand a new format (example: bootloader which reads the +// application address table) + + +// Description of the Fixed Address Table (FAT) +typedef struct { + HalBaseAddressTableType baseTable; + void *CustomerInformationBlock; + HalBootloaderAddressTableType *bootloaderAddressTable; + void *startOfUnusedRam; + // ** pointers to shared functions ** + FibStatus (* fibFlashWrite)(int32u address, int8u *data, + int32u writeLength, int32u verifyLength); + FibStatus (* fibFlashErase)(FibEraseType eraseType, int32u address); +} HalFixedAddressTableType; + +extern const HalFixedAddressTableType halFixedAddressTable; + +#define FIXED_ADDRESS_TABLE_TYPE (0x0FA7) + +// The current versions of the address tables. +// Note that the major version should be updated only when a non-backwards +// compatible change is introduced (like removing or rearranging fields) +// adding new fields is usually backwards compatible, and their presence can +// be indicated by incrementing only the minor version +#define FAT_VERSION (0x0003) +#define FAT_MAJOR_VERSION (0x0000) +#define FAT_MAJOR_VERSION_MASK (0xFF00) + + +#endif //__MEMMAP_FAT_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/memmap.h b/cpu/stm32w108/hal/micro/cortexm3/memmap.h new file mode 100644 index 000000000..801cb1290 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/memmap.h @@ -0,0 +1,64 @@ +/** @file hal/micro/cortexm3/memmap.h + * @brief STM32W108 series memory map definitions used by the full hal + * + * + */ +#ifndef __MEMMAP_H__ +#define __MEMMAP_H__ + +// Include the chip specific definitions +#ifndef LOADER + #if defined (CORTEXM3_STM32W108) + #include "hal/micro/cortexm3/stm32w108/memmap.h" + #else + #error no appropriate micro defined + #endif +#endif + +//============================================================================= +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +// Normally the vectorTable below would require entries such as: +// { .topOfStack = x }, +// { .ptrToHandler = y }, +// But since ptrToHandler is defined first in the union, this is the default +// type which means we don't need to use the full, explicit entry. This makes +// the vector table easier to read because it's simply a list of the handler +// functions. topOfStack, though, is the second definition in the union so +// the full entry must be used in the vectorTable. +//============================================================================= +typedef union +{ + void (*ptrToHandler)(void); + void *topOfStack; +} HalVectorTableType; + + +// **************************************************************************** +// If any of these address table definitions ever need to change, it is highly +// desirable to only add new entries, and only add them on to the end of an +// existing address table... this will provide the best compatibility with +// any existing code which may utilize the tables, and which may not be able to +// be updated to understand a new format (example: bootloader which reads the +// application address table) + +// Generic Address table definition which describes leading fields which +// are common to all address table types +typedef struct { + void *topOfStack; + void (*resetVector)(void); + void (*nmiHandler)(void); + void (*hardFaultHandler)(void); + int16u type; + int16u version; + const HalVectorTableType *vectorTable; + // Followed by more fields depending on the specific address table type +} HalBaseAddressTableType; + +// Hal only references the FAT +#include "memmap-fat.h" + +#endif //__MEMMMAP_H__ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/mems.c b/cpu/stm32w108/hal/micro/cortexm3/mems.c new file mode 100644 index 000000000..895134786 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/mems.c @@ -0,0 +1,241 @@ +/** @file mems.c + * @brief MB851 MEMS drivers + * + * + * + */ +#include PLATFORM_HEADER +#include "hal/hal.h" +#include "hal/error.h" +#include "hal/micro/mems.h" + +#define TIMEOUT 20000 + +#define SUCCESS 1 + +#define SEND_BYTE(data) do{ SC2_DATA=(data); SC2_TWICTRL1 |= SC_TWISEND; }while(0) + +#define WAIT_CMD_FIN() do{}while((SC2_TWISTAT&SC_TWICMDFIN)!=SC_TWICMDFIN) +#define WAIT_TX_FIN() do{}while((SC2_TWISTAT&SC_TWITXFIN)!=SC_TWITXFIN) +#define WAIT_RX_FIN() do{}while((SC2_TWISTAT&SC_TWIRXFIN)!=SC_TWIRXFIN) + +static int8u i2c_MEMS_Init (void); +static int8u i2c_MEMS_Read (t_mems_data *mems_data); +//extern void halInternalResetWatchDog(void); +static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes); +static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes); +int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); +static int8u i2c_MEMS_Init (void); +static int8u i2c_MEMS_Read (t_mems_data *mems_data); + +/* Functions -----------------------------------------------------------------*/ +int8u mems_Init(void) +{ + int8u ret = 0; + + // GPIO assignments + // PA1: SC2SDA (Serial Data) + // PA2: SC2SCL (Serial Clock) + + //-----SC2 I2C Master GPIO configuration + + TIM2_CCER &= 0xFFFFEEEE; + SC2_MODE = SC2_MODE_I2C; + GPIO_PACFGL &= 0xFFFFF00F; + GPIO_PACFGL |= 0x00000DD0; + + SC2_RATELIN = 14; // generates standard 100kbps or 400kbps + SC2_RATEEXP = 1; // 3 yields 100kbps; 1 yields 400kbps + SC2_TWICTRL1 = 0; // start from a clean state + SC2_TWICTRL2 = 0; // start from a clean state + + ret = i2c_MEMS_Init(); + +//Add later if really needed +#ifdef ST_DBG + if (!ret) + i2c_DeInit(MEMS_I2C); +#endif + + return ret; +}/* end mems_Init */ + +int8u mems_GetValue(t_mems_data *mems_data) +{ + int8u i; + i = i2c_MEMS_Read(mems_data); + return i; +}/* end mems_GetValue() */ + + +/* Private Functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : i2c_Send_Frame +* Description : It sends I2C frame +* Input : DeviceAddress is the destination device address +* pBUffer is the buffer data +* NoOfBytes is the number of bytes +* Output : None +* Return : status +*******************************************************************************/ +static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes) +{ + int8u i, data; + + SC2_TWICTRL1 |= SC_TWISTART; // send start + WAIT_CMD_FIN(); + + SEND_BYTE(DeviceAddress); // send the address low byte + WAIT_TX_FIN(); + + // loop sending the data + for (i=0; i 1) + addr += REPETIR; + + SC2_TWICTRL1 |= SC_TWISTART; // send start + WAIT_CMD_FIN(); + + SEND_BYTE(slave_addr | 0x00); // send the address low byte + WAIT_TX_FIN(); + + SEND_BYTE(addr); + WAIT_TX_FIN(); + + SC2_TWICTRL1 |= SC_TWISTART; // send start + WAIT_CMD_FIN(); + + SEND_BYTE(slave_addr | 0x01); // send the address low byte + WAIT_TX_FIN(); + + // loop receiving the data + for (i=0;ioutx_h = i2c_buffer[0]; + mems_data->outx_l = i2c_buffer[1]; + mems_data->outy_h = i2c_buffer[2]; + mems_data->outy_l = i2c_buffer[3]; + mems_data->outz_h = i2c_buffer[4]; + mems_data->outz_l = i2c_buffer[5]; + + return i; +}/* end i2c_MEMS_Read() */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c b/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c new file mode 100644 index 000000000..537a4ac34 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c @@ -0,0 +1,104 @@ +/** @file hal/micro/cortexm3/mfg-token.c + * @brief Cortex-M3 Manufacturing-Token system + * + * + */ +#include PLATFORM_HEADER +#include "error.h" +#include "hal/micro/cortexm3/flash.h" +#include "mfg-token.h" + + + + +#define DEFINETOKENS +#define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ + const int16u TOKEN_##name = TOKEN_##name##_ADDRESS; + #include "hal/micro/cortexm3/token-manufacturing.h" +#undef TOKEN_DEF +#undef TOKEN_MFG +#undef DEFINETOKENS + + + + + + + + +static const int8u nullEui[] = { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF }; + + +void halInternalGetMfgTokenData(void *data, int16u ID, int8u index, int8u len) +{ + int8u *ram = (int8u*)data; + + //0x7F is a non-indexed token. Remap to 0 for the address calculation + index = (index==0x7F) ? 0 : index; + + if(ID == MFG_EUI_64_LOCATION) { + //There are two EUI64's stored in the Info Blocks, St and Custom. + //0x0A00 is the address used by the generic EUI64 token, and it is + //token.c's responbility to pick the returned EUI64 from either St + //or Custom. Return the Custom EUI64 if it is not all FF's, otherwise + //return the St EUI64. + tokTypeMfgEui64 eui64; + halCommonGetMfgToken(&eui64, TOKEN_MFG_CUSTOM_EUI_64); + if(MEMCOMPARE(eui64,nullEui, 8 /*EUI64_SIZE*/) == 0) { + halCommonGetMfgToken(&eui64, TOKEN_MFG_ST_EUI_64); + } + MEMCOPY(ram, eui64, 8 /*EUI64_SIZE*/); + } else { + //read from the Information Blocks. The token ID is only the + //bottom 16bits of the token's actual address. Since the info blocks + //exist in the range DATA_BIG_INFO_BASE-DATA_BIG_INFO_END, we need + //to OR the ID with DATA_BIG_INFO_BASE to get the real address. + int32u realAddress = (DATA_BIG_INFO_BASE|ID) + (len*index); + int8u *flash = (int8u *)realAddress; + + + + + + + + + + + + + + + MEMCOPY(ram, flash, len); + } +} + + +void halInternalSetMfgTokenData(int16u token, void *data, int8u len) +{ + StStatus flashStatus; + int32u realAddress = (DATA_BIG_INFO_BASE|token); + int8u * flash = (int8u *)realAddress; + int32u i; + + //The flash library (and hardware) requires the address and length to both + //be multiples of 16bits. Since this API is only valid for writing to + //the CIB, verify that the token+len falls within the CIB. + assert((token&1) != 1); + assert((len&1) != 1); + assert((realAddress>=CIB_BOTTOM) && ((realAddress+len-1)<=CIB_TOP)); + + //CIB manufacturing tokens can only be written by on-chip code if the token + //is currently unprogrammed. Verify the entire token is unwritten. The + //flash library performs a similar check, but verifying here ensures that + //the entire token is unprogrammed and will prevent partial writes. + for(i=0;i + */ + +#ifndef __MFG_TOKEN_H__ +#define __MFG_TOKEN_H__ + + +// The manufacturing tokens live in the Info Blocks, while all other tokens +// live in the Simulated EEPROM. This requires the token names to be defined +// as different data (mfg tokens are memory address, all others are an enum). + + +#define DEFINETOKENS + +/** + * @description Macro for translating token defs into address variables + * that point to the correct location in the Info Blocks. (This is the + * extern, the actual definition is found in hal/micro/cortexm3/token.c) + * + * @param name: The name of the token. + * + * @param TOKEN_##name##_ADDRESS: The address in EEPROM at which the token + * will be stored. This parameter is generated with a macro above. + */ +#define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ + extern const int16u TOKEN_##name; + #include "hal/micro/cortexm3/token-manufacturing.h" +#undef TOKEN_MFG + +/** + * @description Macro for translating token definitions into size variables. + * This provides a convenience for abstracting the 'sizeof(type)' anywhere. + * + * @param name: The name of the token. + * + * @param type: The token type. The types are found in token-stack.h. + */ +#define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ + TOKEN_##name##_SIZE = sizeof(type), + enum { + #include "hal/micro/cortexm3/token-manufacturing.h" + }; +#undef TOKEN_MFG +#undef TOKEN_DEF + +/** + * @description Macro for typedef'ing the CamelCase token type found in + * token-stack.h to a capitalized TOKEN style name that ends in _TYPE. + * This macro allows other macros below to use 'token##_TYPE' to declare + * a local copy of that token. + * + * @param name: The name of the token. + * + * @param type: The token type. The types are found in token-stack.h. + */ +#define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ + typedef type TOKEN_##name##_TYPE; + #include "hal/micro/cortexm3/token-manufacturing.h" +#undef TOKEN_MFG + +#undef TOKEN_NEXT_ADDRESS + +#define DEFINEADDRESSES +/** + * @description Macro for creating a 'region' element in the enum below. This + * creates an element in the enum that provides a starting point (address) for + * subsequent tokens to align against. ( See hal/micro/cortexm3/token.c for + * the instances of TOKEN_NEXT_ADDRESS() ); + * + * @param region: The name to give to the element in the address enum.. + * + * @param address: The address in EEPROM where the region begins. + */ +#define TOKEN_NEXT_ADDRESS(region, address) \ + TOKEN_##region##_NEXT_ADDRESS = ((address) - 1), + +/** + * @description Macro for creating ADDRESS and END elements for each token in + * the enum below. The ADDRESS element is linked to from the the normal + * TOKEN_##name macro and provides the value passed into the internal token + * system calls. The END element is a placeholder providing the starting + * point for the ADDRESS of the next dynamically positioned token. + * + * @param name: The name of the token. + * + * @param arraysize: The number of elements in an indexed token (arraysize=1 + * for scalar tokens). + */ +#define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ + TOKEN_##name##_ADDRESS, \ + TOKEN_##name##_END = TOKEN_##name##_ADDRESS + \ + (TOKEN_##name##_SIZE * arraysize) - 1, + +/** + * @description The enum that operates on the two macros above. Also provides + * an indentifier so the address of the top of the token system can be known. + */ +enum { + #include "hal/micro/cortexm3/token-manufacturing.h" +}; +#undef TOKEN_MFG +#undef DEFINEADDRESSES + +#undef DEFINETOKENS + + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * @description Copies the token value from non-volatile storage into a RAM + * location. This is the internal function that the exposed API + * (halCommonGetMfgToken) expands out to. The + * API simplifies the access into this function by hiding the size parameter. + * + * @param data: A pointer to where the data being read should be placed. + * + * @param token: The name of the token to get data from. On this platform + * that name is defined as an address. + * + * @param index: The index to access. If the token being accessed is not an + * indexed token, this parameter is set by the API to be 0x7F. + * + * @param len: The length of the token being worked on. This value is + * automatically set by the API to be the size of the token. + */ +void halInternalGetMfgTokenData(void *data, int16u token, int8u index, int8u len); + +/** + * @description Sets the value of a token in non-volatile storage. This is + * the internal function that the exposed API (halCommonSetMfgToken) + * expands out to. The API simplifies the access into this function + * by hiding the size parameter. + * + * NOTE: CIB manufacturing tokens can only be written by on-chip + * code if the token is currently unprogrammed. + * + * REMEMBER: The flash hardware requires writing to 16bit aligned + * addresses with a length that is multiples of 16bits. + * + * @param token: The name of the token to get data from. On this platform + * that name is defined as an address. + * + * @param data: A pointer to the data being written. + * + * @param len: The length of the token being worked on. This value is + * automatically set by the API to be the size of the token. + */ +void halInternalSetMfgTokenData(int16u token, void *data, int8u len); + +#define halCommonGetMfgToken( data, token ) \ + halInternalGetMfgTokenData(data, token, 0x7F, token##_SIZE) + +#define halCommonGetIndexedMfgToken( data, token, index ) \ + halInternalGetMfgTokenData(data, token, index, token##_SIZE) + +#define halCommonSetMfgToken( token, data ) \ + halInternalSetMfgTokenData(token, data, token##_SIZE) + +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#endif //__MFG_TOKEN_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c b/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c new file mode 100644 index 000000000..a0d0537f4 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c @@ -0,0 +1,294 @@ +/* + * File: micro-common-internal.c + * Description: STM32W108 internal, micro specific HAL functions. + * This file is provided for completeness and it should not be modified + * by customers as it comtains code very tightly linked to undocumented + * device features + * + * + */ + +#include PLATFORM_HEADER +#include "error.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" +#include "hal/micro/cortexm3/mfg-token.h" + +#define HAL_STANDALONE +#ifdef HAL_STANDALONE + +#define AUXADC_REG (0xC0u) +#define DUMMY 0 + +#define ADC_6MHZ_CLOCK 0 +#define ADC_1MHZ_CLOCK 1 + +#define ADC_SAMPLE_CLOCKS_32 0 +#define ADC_SAMPLE_CLOCKS_64 1 +#define ADC_SAMPLE_CLOCKS_128 2 +#define ADC_SAMPLE_CLOCKS_256 3 +#define ADC_SAMPLE_CLOCKS_512 4 +#define ADC_SAMPLE_CLOCKS_1024 5 +#define ADC_SAMPLE_CLOCKS_2048 6 +#define ADC_SAMPLE_CLOCKS_4096 7 + +#define CAL_ADC_CHANNEL_VDD_4 0x00 //VDD_PADS/4 +#define CAL_ADC_CHANNEL_VREG_2 0x01 //VREG_OUT/2 +#define CAL_ADC_CHANNEL_TEMP 0x02 +#define CAL_ADC_CHANNEL_GND 0x03 +#define CAL_ADC_CHANNEL_VREF 0x04 +#define CAL_ADC_CHANNEL_I 0x06 +#define CAL_ADC_CHANNEL_Q 0x07 +#define CAL_ADC_CHANNEL_ATEST_A 0x09 + +void stCalibrateVref(void) +{ + // Calibrate Vref by measuring a known voltage, Vdd/2. + // + // FIXME: add support for calibration if done in boost mode. + extern int16u stmRadioTxPowerMode; + tokTypeMfgAnalogueTrimBoth biasTrim; + + halCommonGetMfgToken(&biasTrim, TOKEN_MFG_ANALOG_TRIM_BOTH); + + if(biasTrim.auxadc == 0xFFFF) { + assert(FALSE); + } else { + //The bias trim token is set, so use the trim directly + int16u temp_value; + int16u mask = 0xFFFF; + + // halClearLed(BOARDLED3); + + while (SCR_BUSY_REG) ; + + SCR_ADDR_REG = AUXADC_REG ; // prepare the address to write to + + // initiate read (starts on falling edge of SCR_CTRL_SCR_READ) + SCR_CTRL_REG = SCR_CTRL_SCR_READ_MASK; + SCR_CTRL_REG = 0; + + // wait for read to complete + while (SCR_BUSY_REG) ; + + temp_value = SCR_READ_REG & ~mask; + temp_value |= biasTrim.auxadc & mask; + + SCR_WRITE_REG = temp_value; + + // initiate write (starts on falling edge of SCR_CTRL_SCR_WRITE_MASK) + SCR_CTRL_REG = SCR_CTRL_SCR_WRITE_MASK; + SCR_CTRL_REG = 0; + + while (SCR_BUSY_REG) ; + + } +} + + +void calDisableAdc(void) { + // Disable the Calibration ADC to save current. + CAL_ADC_CONFIG &= ~CAL_ADC_CONFIG_CAL_ADC_EN; +} + + + +// These routines maintain the same signature as their hal- counterparts to +// facilitate simple support between phys. +// It is assumed (hoped?) that the compiler will optimize out unused arguments. +StStatus calStartAdcConversion(int8u dummy1, // Not used. + int8u dummy2, // Not used. + int8u channel, + int8u rate, + int8u clock) { + // Disable the Calibration ADC interrupt so that we can poll it. + INT_MGMTCFG &= ~INT_MGMTCALADC; + + ATOMIC( + // Enable the Calibration ADC, choose source, set rate, and choose clock. + CAL_ADC_CONFIG =((CAL_ADC_CONFIG_CAL_ADC_EN) | + (channel << CAL_ADC_CONFIG_CAL_ADC_MUX_BIT) | + (rate << CAL_ADC_CONFIG_CAL_ADC_RATE_BIT) | + (clock << CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT) ); + // Clear any pending Calibration ADC interrupt. Since we're atomic, the + // one we're interested in hasn't happened yet (will take ~10us at minimum). + // We're only clearing stale info. + INT_MGMTFLAG = INT_MGMTCALADC; + ) + return ST_SUCCESS; +} + + +StStatus calReadAdcBlocking(int8u dummy, + int16u *value) { + // Wait for conversion to complete. + while ( ! (INT_MGMTFLAG & INT_MGMTCALADC) ); + // Clear the interrupt for this conversion. + INT_MGMTFLAG = INT_MGMTCALADC; + // Get the result. + *value = (int16u)CAL_ADC_DATA; + return ST_SUCCESS; +} + + + + +//Using 6MHz clock reduces resolution but greatly increases conversion speed. +//The sample clocks were chosen based upon empirical evidence and provided +//the fastest conversions with the greatest reasonable accuracy. Variation +//across successive conversions appears to be +/-20mv of the average +//conversion. Overall function time is <150us. +int16u stMeasureVddFast(void) +{ + int16u value; + int32u Ngnd; + int32u Nreg; + int32u Nvdd; + tokTypeMfgRegVoltage1V8 vregOutTok; + halCommonGetMfgToken(&vregOutTok, TOKEN_MFG_1V8_REG_VOLTAGE); + + //Measure GND + calStartAdcConversion(DUMMY, + DUMMY, + CAL_ADC_CHANNEL_GND, + ADC_SAMPLE_CLOCKS_128, + ADC_6MHZ_CLOCK); + calReadAdcBlocking(DUMMY, &value); + Ngnd = (int32u)value; + + //Measure VREG_OUT/2 + calStartAdcConversion(DUMMY, + DUMMY, + CAL_ADC_CHANNEL_VREG_2, + ADC_SAMPLE_CLOCKS_128, + ADC_6MHZ_CLOCK); + calReadAdcBlocking(DUMMY, &value); + Nreg = (int32u)value; + + //Measure VDD_PADS/4 + calStartAdcConversion(DUMMY, + DUMMY, + CAL_ADC_CHANNEL_VDD_4, + ADC_SAMPLE_CLOCKS_128, + ADC_6MHZ_CLOCK); + calReadAdcBlocking(DUMMY, &value); + Nvdd = (int32u)value; + + calDisableAdc(); + + //Convert the value into mV. VREG_OUT is ideally 1.8V, but it wont be + //exactly 1.8V. The actual value is stored in the manufacturing token + //TOKEN_MFG_1V8_REG_VOLTAGE. The token stores the value in 10^-4, but we + //need 10^-3 so divide by 10. If this token is not set (0xFFFF), then + //assume 1800mV. + if(vregOutTok == 0xFFFF) { + vregOutTok = 1800; + } else { + vregOutTok /= 10; + } + return ((((((Nvdd-Ngnd)<<16)/(Nreg-Ngnd))*vregOutTok)*2)>>16); +} +#endif + +void halCommonCalibratePads(void) +{ + if(stMeasureVddFast() < 2700) { + GPIO_DBGCFG |= GPIO_DBGCFGRSVD; + } else { + GPIO_DBGCFG &= ~GPIO_DBGCFGRSVD; + } +} + + +void halInternalSetRegTrim(boolean boostMode) +{ + tokTypeMfgRegTrim regTrim; + int8u trim1V2; + int8u trim1V8; + + halCommonGetMfgToken(®Trim, TOKEN_MFG_REG_TRIM); + // The compiler can optimize this function a bit more and keep the + // values in processor registers if we use separate local vars instead + // of just accessing via the structure fields + trim1V8 = regTrim.regTrim1V8; + trim1V2 = regTrim.regTrim1V2; + + //If tokens are erased, default to reasonable values, otherwise use the + //token values. + if((trim1V2 == 0xFF) && (trim1V8 == 0xFF)) { + trim1V8 = 4; + trim1V2 = 0; + } + + //When the radio is in boost mode, we have to increase the 1.8V trim. + if(boostMode) { + trim1V8 += 2; + } + + //Clamp at 7 to ensure we don't exceed max values, accidentally set + //other bits, or wrap values. + if(trim1V8>7) { + trim1V8 = 7; + } + if(trim1V2>7) { + trim1V2 = 7; + } + + VREG_REG = ( (trim1V8<>= 1; + } + + //we have about 2us of overhead in the calculations + if(us<=2) { + return; + } + + // MAC Timer is enabled in stmRadioInit, which may not have been called yet. + // This algorithm needs the MAC Timer so we enable it here. + MAC_TIMER_CTRL |= MAC_TIMER_CTRL_MAC_TIMER_EN; + + // since our max delay (65535<<1) is less than half the size of the + // 20 bit mac timer, we can easily just handle the potential for + // mac timer wrapping by subtracting the time delta and masking out + // the extra bits + while( ((MAC_TIMER-beginTime)&MAC_TIMER_MAC_TIMER_MASK) < us ) { + ; // spin + } +} + + +//Burning cycles for milliseconds is generally a bad idea, but it is +//necessary in some situations. If you have to burn more than 65ms of time, +//the halCommonDelayMicroseconds function becomes cumbersome, so this +//function gives you millisecond granularity. +void halCommonDelayMilliseconds(int16u ms) +{ + if(ms==0) { + return; + } + + while(ms-->0) { + halCommonDelayMicroseconds(1000); + } +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro-common.c b/cpu/stm32w108/hal/micro/cortexm3/micro-common.c new file mode 100644 index 000000000..1afd82c41 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/micro-common.c @@ -0,0 +1,115 @@ +/** @file micro-common.c + * @brief STM32W108 micro specific HAL functions common to + * full and minimal hal + * + * + * + */ + + + +#include PLATFORM_HEADER +#include "error.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" + +void halInternalEnableWatchDog(void) +{ + //Just to be on the safe side, restart the watchdog before enabling it + WDOG_RESET = 1; + WDOG_KEY = 0xEABE; + WDOG_CFG = WDOG_ENABLE; +} + +void halInternalResetWatchDog(void) +{ + //Writing any value will restart the watchdog + WDOG_RESET = 1; +} + +void halInternalDisableWatchDog(int8u magicKey) +{ + if (magicKey == MICRO_DISABLE_WATCH_DOG_KEY) { + WDOG_KEY = 0xDEAD; + WDOG_CFG = WDOG_DISABLE; + } +} + +boolean halInternalWatchDogEnabled(void) +{ + if(WDOG_CFG&WDOG_ENABLE) { + return TRUE; + } else { + return FALSE; + } +} + +void halGpioConfig(int32u io, int32u config) +{ + static volatile int32u *const configRegs[] = + { (volatile int32u *)GPIO_PACFGL_ADDR, + (volatile int32u *)GPIO_PACFGH_ADDR, + (volatile int32u *)GPIO_PBCFGL_ADDR, + (volatile int32u *)GPIO_PBCFGH_ADDR, + (volatile int32u *)GPIO_PCCFGL_ADDR, + (volatile int32u *)GPIO_PCCFGH_ADDR }; + int32u portcfg; + portcfg = *configRegs[io/4]; // get current config + portcfg = portcfg & ~((0xF)<<((io&3)*4)); // mask out config of this pin + *configRegs[io/4] = portcfg | (config <<((io&3)*4)); +} + + + + + + + +int16u halInternalStartSystemTimer(void) +{ + //Since the SleepTMR is the only timer maintained during deep sleep, it is + //used as the System Timer (RTC). We maintain a 32 bit hardware timer + //configured for a tick value time of 1024 ticks/second (0.9765625 ms/tick) + //using either the 10 kHz internal SlowRC clock divided and calibrated to + //1024 Hz or the external 32.768 kHz crystal divided to 1024 Hz. + //With a tick time of ~1ms, this 32bit timer will wrap after ~48.5 days. + + //disable top-level interrupt while configuring + INT_CFGCLR = INT_SLEEPTMR; + + #ifdef ENABLE_OSC32K + #ifdef DIGITAL_OSC32_EXT + //Disable both OSC32K and SLOWRC if using external digital clock input + SLEEPTMR_CLKEN = 0; + #else//!DIGITAL_OSC32_EXT + //Enable the 32kHz XTAL (and disable SlowRC since it is not needed) + SLEEPTMR_CLKEN = SLEEPTMR_CLK32KEN; + #endif + //Sleep timer configuration is the same for crystal and external clock + SLEEPTMR_CFG = (SLEEPTMR_ENABLE | //enable TMR + (0 << SLEEPTMR_DBGPAUSE_BIT)| //TMR paused when halted + (5 << SLEEPTMR_CLKDIV_BIT) | //divide down to 1024Hz + (1 << SLEEPTMR_CLKSEL_BIT)) ; //select XTAL + #else //!ENABLE_OSC32K + //Enable the SlowRC (and disable 32kHz XTAL since it is not needed) + SLEEPTMR_CLKEN = SLEEPTMR_CLK10KEN; + SLEEPTMR_CFG = (SLEEPTMR_ENABLE | //enable TMR + (0 << SLEEPTMR_DBGPAUSE_BIT)| //TMR paused when halted + (0 << SLEEPTMR_CLKDIV_BIT) | //already 1024Hz + (0 << SLEEPTMR_CLKSEL_BIT)) ; //select SlowRC + #ifndef DISABLE_RC_CALIBRATION + halInternalCalibrateSlowRc(); //calibrate SlowRC to 1024Hz + #endif//DISABLE_RC_CALIBRATION + #endif//ENABLE_OSC32K + + //clear out any stale interrupts + INT_SLEEPTMRFLAG = (INT_SLEEPTMRWRAP | INT_SLEEPTMRCMPA | INT_SLEEPTMRCMPB); + //turn off second level interrupts. they will be enabled elsewhere as needed + INT_SLEEPTMRCFG = INT_SLEEPTMRCFG_RESET; + //enable top-level interrupt + INT_CFGSET = INT_SLEEPTMR; + + return 0; +} + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro-common.h b/cpu/stm32w108/hal/micro/cortexm3/micro-common.h new file mode 100644 index 000000000..1a146df6e --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/micro-common.h @@ -0,0 +1,271 @@ +/** @file hal/micro/cortexm3/micro-common.h + * @brief Utility and convenience functions for STM32W108 microcontroller, + * common to both the full and minimal hal. + * See @ref micro for documentation. + * + * + */ + +/** @addtogroup micro + * See also hal/micro/cortexm3/micro.h for source code. + *@{ + */ + +#ifndef __STM32W108XX_MICRO_COMMON_H__ +#define __STM32W108XX_MICRO_COMMON_H__ + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +#ifndef __STSTATUS_TYPE__ +#define __STSTATUS_TYPE__ + //This is necessary here because halSleepForQsWithOptions returns an + //StStatus and not adding this typedef to this file breaks a + //whole lot of builds. + typedef int8u StStatus; +#endif //__STSTATUS_TYPE__ +#endif // DOXYGEN_SHOULD_SKIP_THIS + +/** + * @brief Some registers and variables require indentifying GPIO by + * a single number instead of the port and pin. This macro converts + * Port A pins into a single number. + */ +#define PORTA_PIN(y) ((0<<3)|y) +/** + * @brief Some registers and variables require indentifying GPIO by + * a single number instead of the port and pin. This macro converts + * Port B pins into a single number. + */ +#define PORTB_PIN(y) ((1<<3)|y) +/** + * @brief Some registers and variables require indentifying GPIO by + * a single number instead of the port and pin. This macro converts + * Port C pins into a single number. + */ +#define PORTC_PIN(y) ((2<<3)|y) + +/** + * @brief Resets the watchdog timer. This function is pointed + * to by the macro ::halResetWatchdog(). + * @warning Be very careful when using this as you can easily get into an + * infinite loop. + */ +void halInternalResetWatchDog( void ); + + +/** + * @brief Configure an IO pin's operating mode + * + * @param io The io pin to use, can be specified with the convenience macros + * PORTA_PIN(), PORTB_PIN(), PORTC_PIN() + * @param config The configuration mode to use. + * + */ +void halGpioConfig(int32u io, int32u config); + + +/** + * @brief Calibrates the internal SlowRC to generate a 1024 Hz (1kHz) clock. + */ +void halInternalCalibrateSlowRc( void ); + +/** + * @brief Calibrates the internal FastRC to generate a 12Mhz clock. + */ +void halInternalCalibrateFastRc(void); + + +/** + * @brief Sets the trim values for the 1.8V and 1.2V regulators based upon + * manufacturing configuration. + * + * @param boostMode Alter the regulator trim based upon the state + * of boost mode. TRUE if boost mode is active, FALSE otherwise. + */ +void halInternalSetRegTrim(boolean boostMode); + +/** @brief Takes a slow ADC measurement of VDD_PADS in millivolts. Due to + * the conversions performed, this function takes slightly under 3.2ms with a + * variation across successive conversions approximately +/-2mv of the average + * conversion. + * + * @return A slow measurement of VDD_PADS in millivolts. + */ +int16u stMeasureVddSlow(void); + + +/** @brief Takes a fast ADC measurement of VDD_PADS in millivolts. + * Due to the conversions performed, this function takes slightly under 150us + * with a variation across successive conversions approximately +/-20mv of + * the average conversion. + * + * @return A fast measurement of VDD_PADS in millivolts. + */ +int16u stMeasureVddFast(void); + + +/** + * @brief Calibrates the GPIO pads. This function is called from within + * the stack and HAL at appropriate times. + */ +void halCommonCalibratePads(void); + +/** + * @brief This function is intended to be called periodically, from the + * stack and application, to check the XTAL bias trim is within + * appropriate levels and adjust if not. This function is *not* designed + * to be used before halInternalSwitchToXtal() has been called. + */ +void halCommonCheckXtalBiasTrim(void); + +/** + * @brief Switches to running off of the 24MHz crystal, including changing + * the CPU to be 24MHz (FCLK sourced from SYSCLK). The switch function + * will respect the BIASTRIM HI and LO flags and adjust bias trim until + * appropriate crystal biasing is used. This function is called from + * within the stack and HAL at appropriate times. + */ +void halInternalSwitchToXtal(void); + +/** + * @brief Search for optimal 24MHz crystal bias trim, assuming no valid + * prior value. This function is typically called during initialization + * of the microcontroller. + */ +void halInternalSearchForBiasTrim(void); + +/** @brief Blocks the current thread of execution for the specified + * amount of time, in milliseconds. + * + * The function is implemented with cycle-counted busy loops + * and is intended to create the short delays required when interfacing with + * hardware peripherals. This function works by simply adding another + * layer on top of halCommonDelayMicroseconds(). + * + * @param ms The specified time, in milliseconds. + */ +void halCommonDelayMilliseconds(int16u ms); + + +/** @brief Puts the microcontroller to sleep in a specified mode, allows + * the GPIO wake sources to be determined at runtime. This function + * requires the GPIO wake sources to be defined at compile time in the board + * file. + * + * @note This routine always enables interrupts. + * + * @param sleepMode A microcontroller sleep mode. + * + * @param gpioWakeBitMask A bit mask of the GPIO that are allowed to wake + * the chip from deep sleep. A high bit in the mask will enable waking + * the chip if the corresponding GPIO changes state. bit0 is PA0, bit1 is + * PA1, bit8 is PB0, bit16 is PCO, bit23 is PC7, bits[31:24] are ignored. + * + * @sa ::SleepModes + */ +void halSleepWithOptions(SleepModes sleepMode, int32u gpioWakeBitMask); + + +/** + * @brief Uses the system timer to enter ::SLEEPMODE_WAKETIMER for + * approximately the specified amount of time (provided in quarter seconds), + * the GPIO wake sources can be provided at runtime. + * + * This function returns ::ST_SUCCESS and the duration parameter is + * decremented to 0 after sleeping for the specified amount of time. If an + * interrupt occurs that brings the chip out of sleep, the function returns + * ::ST_SLEEP_INTERRUPTED and the duration parameter reports the amount of + * time remaining out of the original request. + * + * @note This routine always enables interrupts. + * + * @note The maximum sleep time of the hardware is limited on STM32W108 platforms + * to 48.5 days. Any sleep duration greater than this limit will wake up + * briefly (e.g. 16 microseconds) to reenable another sleep cycle. + * + * @nostackusage + * + * @param duration The amount of time, expressed in quarter seconds, that the + * micro should be placed into ::SLEEPMODE_WAKETIMER. When the function returns, + * this parameter provides the amount of time remaining out of the original + * sleep time request (normally the return value will be 0). + * + * @param gpioWakeBitMask A bit mask of the GPIO that are allowed to wake + * the chip from deep sleep. A high bit in the mask will enable waking + * the chip if the corresponding GPIO changes state. bit0 is PA0, bit1 is + * PA1, bit8 is PB0, bit16 is PCO, bit23 is PC7, bits[31:24] are ignored. + * + * @return An StStatus value indicating the success or + * failure of the command. + */ +StStatus halSleepForQsWithOptions(int32u *duration, int32u gpioWakeBitMask); + +/** + * @brief Provides access to assembly code which triggers idle sleep. + */ +void halInternalIdleSleep(void); + +/** @brief Puts the microcontroller to sleep in a specified mode. This + * internal function performs the actual sleep operation. This function + * assumes all of the wake source registers are configured properly. + * + * @note This routine always enables interrupts. + * + * @param sleepMode A microcontroller sleep mode + */ +void halInternalSleep(SleepModes sleepMode); + + +/** + * @brief Obtains the events that caused the last wake from sleep. The + * meaning of each bit is as follows: + * - [31] = WakeInfoValid + * - [30] = SleepSkipped + * - [29] = CSYSPWRUPREQ + * - [28] = CDBGPWRUPREQ + * - [27] = PWRUP_WAKECORE + * - [26] = PWRUP_SLEEPTMRWRAP + * - [25] = PWRUP_SLEEPTMRCOMPB + * - [24] = PWRUP_SLEEPTMRCOMPA + * - [23:0] = corresponding GPIO activity + * + * WakeInfoValid means that ::halSleepWithOptions (::halInternalSleep) has been called + * at least once. Since the power on state clears the wake event info, + * this bit says the sleep code has been called since power on. + * + * SleepSkipped means that the chip never left the running state. Sleep can + * be skipped if any wake event occurs between going ::ATOMIC and transferring + * control from the CPU to the power management state machine. Sleep can + * also be skipped if the debugger is connected (JTAG/SerialWire CSYSPWRUPREQ + * signal is set). The net affect of skipping sleep is the Low Voltage + * domain never goes through a power/reset cycle. + * + * @return The events that caused the last wake from sleep. + */ +int32u halGetWakeInfo(void); + + +/** @brief Seeds the ::halCommonGetRandom() pseudorandom number + * generator. + * + * It should be called by the application during initialization with a seed + * from the radio randon number generator. + * + * @param seed A seed for the pseudorandom number generator. + */ +void halCommonSeedRandom(int32u seed); + +/** @brief Runs a standard LFSR to generate pseudorandom numbers. + * + * Called by the MAC in the stack to choose random backoff slots. + * + * Complicated implementations may improve the MAC's + * ability to avoid collisions in large networks, but it is \b critical to + * implement this function to return quickly. + */ +int16u halCommonGetRandom(void); + +#endif //__STM32W108XX_MICRO_COMMON_H__ + +/**@} // END micro group + */ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro.c b/cpu/stm32w108/hal/micro/cortexm3/micro.c new file mode 100644 index 000000000..b464ce0ce --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/micro.c @@ -0,0 +1,108 @@ +/** @file micro.c + * @brief STM32W108 micro specific minimal HAL functions + * + * + * + */ + +#include PLATFORM_HEADER +#include "error.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" +#include "micro/system-timer.h" +#include "micro/adc.h" + +#include +#include + + +void halInit(void) +{ + //Disable the REG_EN external regulator enable signal. Out of reset this + //signal overrides PA7. By disabling it early, PA7 is reclaimed as a GPIO. + //If an external regulator is required, the following line of code should + //be deleted. + GPIO_DBGCFG &= ~GPIO_EXTREGEN; + halInternalSetRegTrim(FALSE); + halPowerUp(); + halInternalCalibrateFastRc(); + + #ifndef DISABLE_WATCHDOG + halInternalEnableWatchDog(); + #endif + + halInternalStartSystemTimer(); +} + + +void halReboot(void) +{ + INTERRUPTS_OFF(); + + + //FCLK must be 6MHz to allow the SYSRESETREQ signal to cleanly + //propagate and reset the chip. Switch SYSCLK first since we need + //the cycles used by switching FCLK to guarantee the SYSCLK is + //stable and ready for SYSRESETREQ. + OSC24M_CTRL = OSC24M_CTRL_RESET; //Guarantee SYSCLK is sourced from OSCHF + CPU_CLKSEL = CPU_CLKSEL_RESET; //Guarantee FCLK is sourced from PCLK + + SCS_AIRCR = (0x05FA0000 | SCS_AIRCR_SYSRESETREQ); // trigger the reset + //NOTE: SYSRESETREQ is not the same as nRESET. It will not do the debug + //pieces: DWT, ITM, FPB, vector catch, etc +} + +void halPowerDown(void) +{ +} + +void halPowerUp(void) +{ + halInternalInitAdc(); + halCommonCalibratePads(); + halInternalSwitchToXtal(); +} + +static int16u seed0 = 0xbeef; +static int16u seed1 = 0xface; + +void halCommonSeedRandom(int32u seed) +{ + seed0 = (int16u) seed; + if (seed0 == 0) + seed0 = 0xbeef; + seed1 = (int16u) (seed >> 16); + if (seed1 == 0) + seed1 = 0xface; +} + +static int16u shift(int16u *val, int16u taps) +{ + int16u newVal = *val; + + if (newVal & 0x8000) + newVal ^= taps; + *val = newVal << 1; + return newVal; +} + +int16u halCommonGetRandom(void) +{ + return (shift(&seed0, 0x0062) + ^ shift(&seed1, 0x100B)); +} + +void halCommonMemCopy(void *dest, const void *source, int8u bytes) +{ + memcpy(dest, source, bytes); +} + +int8s halCommonMemCompare(const void *source0, const void *source1, int8u bytes) +{ + return memcmp(source0, source1, bytes); +} + +void halCommonMemSet(void *dest, int8u val, int16u bytes) +{ + memset(dest, val, bytes); +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/mpu.h b/cpu/stm32w108/hal/micro/cortexm3/mpu.h new file mode 100644 index 000000000..616270e12 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/mpu.h @@ -0,0 +1,12 @@ +/** @file hal/micro/cortexm3/mpu.h + * + * + */ + + +#ifndef __MPU_H__ +#define __MPU_H__ + +#define BYPASS_MPU(blah) blah + +#endif//__MPU_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/nvm-def.h b/cpu/stm32w108/hal/micro/cortexm3/nvm-def.h new file mode 100644 index 000000000..1bf54d8f7 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/nvm-def.h @@ -0,0 +1,53 @@ +/** @file hal/micro/cortexm3/nvm-def.h + * @brief Data definitions for the Cortex-M3 Non-Volatile Memory data storage + * system. + * See @ref nvm for documentation. + * + * See hal/micro/cortexm3/nvm-def.h for source code. + * + * + */ + +/** @addtogroup nvm + * @brief Data definitions for the Cortex-M3 Non-Volatile Memory data storage + * system. + * + * This header defines all of the data sets in the NVM data storage. Each + * piece of data in NVM storage uses an offset to indicate where the data + * lives and a size to indicate the size of that data. Both the offset + * and size are defined in bytes and must be a mupltiple of 16bits. The + * offset is from the start of an NVM page, defined by NVM_LEFT_PAGE and + * NVM_RIGHT_PAGE. The offset and size must be below the maximum size + * of NVM storage as defined by NVM_DATA_SIZE_B. All NVM data must start + * above NVM_MGMT_SIZE_B, since this is where the management bytes live. + * + * @note This file is not directly used by the nvm.c or nvm.h files. This + * file is intended to be a convenient place to define all data that + * lives in NVM so it can be seen together in one group. nvm.h includes + * this file which means any code that includes nvm.h to call the read + * and write functions also has access to these defines. + *@{ + */ + +#ifndef __NVM_DEF_H__ +#define __NVM_DEF_H__ + +//The bottom 64 bytes of NVM storage is allocated to radio calibration +//values. These 64 bytes *must* exist for the radio to function. +#define NVM_RADIO_CAL_OFFSET (NVM_MGMT_SIZE_B+0x0000) +#define NVM_RADIO_CAL_SIZE_B 64 + +//IMPORTANT: Data storage starts at offset 0x0040. + +//Three example pieces of data: +#define NVM_FOO_OFFSET (NVM_MGMT_SIZE_B+0x0040) +#define NVM_FOO_SIZE_B 2 +#define NVM_HAM_OFFSET (NVM_MGMT_SIZE_B+0x0042) +#define NVM_HAM_SIZE_B 10 +#define NVM_SPAM_OFFSET (NVM_MGMT_SIZE_B+0x004C) +#define NVM_SPAM_SIZE_B 20 + +/** @} END addtogroup */ + +#endif // __NVM_DEF_H__ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/nvm.c b/cpu/stm32w108/hal/micro/cortexm3/nvm.c new file mode 100644 index 000000000..0b14257a5 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/nvm.c @@ -0,0 +1,377 @@ +/** @file hal/micro/cortexm3/nvm.c + * @brief Cortex-M3 Non-Volatile Memory data storage system. + * + * This file implements the NVM data storage system. Refer to nvm.h for + * full documentation of how the NVM data storage system works, is configured, + * and is accessed. + * + * + */ + +#include PLATFORM_HEADER +#include "error.h" +//flash.h gives access to halInternalFlashErase and halInternalFlashWrite. +#include "hal/micro/cortexm3/flash.h" +//nvm.h includes memmap.h. These two headers define the key parameters: +// MFB_PAGE_SIZE_B +// MFB_TOP +// NVM_LEFT_PAGE +// NVM_RIGHT_PAGE +// NVM_DATA_SIZE_B +// NVM_FLASH_PAGE_COUNT +// NVM_MGMT_SIZE_B +#include "hal/micro/cortexm3/nvm.h" + +//Define two variables that hold the actual NVM data storage. LEFT and RIGHT +//are not required to be continuous memory blocks so they can be define +//separately. The linker is responsible for placing these storage containers +//on flash page boundaries. +NO_STRIPPING __no_init VAR_AT_SEGMENT (const int8u nvmStorageLeft[NVM_DATA_SIZE_B], __NVM__); +NO_STRIPPING __no_init VAR_AT_SEGMENT (const int8u nvmStorageRight[NVM_DATA_SIZE_B], __NVM__); + +static int8u determineState(void) +{ + int32u leftMgmt = *(int32u *)NVM_LEFT_PAGE; + int32u rightMgmt = *(int32u *)NVM_RIGHT_PAGE; + int8u state=0; + + if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFFFF)) { + //State 1 and state 4 use identical mgmt words. The function + //determineState() is only called at the start of a NVM read + //or write. During a read, state 1 and 4 both read from the + //LEFT so there is no reason to make a distinction. During + //a write, the system will see the current page as LEFT and + //therefore be transitioning from LEFT to RIGHT so state 4 is + //correct. State 1 is only required to transition from 0 to 2. + state = 4; + } else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFF00FFFF)) { + state = 2; + } else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFF000000)) { + state = 3; + } else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFFFF)) { + state = 4; + } else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFF00)) { + state = 5; + } else if((leftMgmt==0xFF000000) && (rightMgmt==0xFFFFFF00)) { + state = 6; + } else if((leftMgmt==0xFF000000) && (rightMgmt==0xFFFF0000)) { + state = 7; + } else if((leftMgmt==0xFFFFFFFF) && (rightMgmt==0xFFFF0000)) { + state = 8; + } else if((leftMgmt==0xFFFFFF00) && (rightMgmt==0xFFFF0000)) { + state = 9; + } else if((leftMgmt==0xFFFFFF00) && (rightMgmt==0xFF000000)) { + state = 10; + } else { + //State 0 is used to indicate erased or invalid. + state = 0; + } + + return state; +} + + +int8u halCommonReadFromNvm(void *data, int32u offset, int16u length) +{ + int16u i; + int16u *flash; + //Remember: all flash writes are 16bits. + int16u *ram = (int16u*)data; + + //The NVM data storage system cannot function if the LEFT and RIGHT + //storage are not aligned to physical flash pages. + assert((NVM_LEFT_PAGE%MFB_PAGE_SIZE_B)==0); + assert((NVM_RIGHT_PAGE%MFB_PAGE_SIZE_B)==0); + //The offset of the NVM data must be 16bit aligned. + assert((offset&0x1)==0); + //The length of the NVM data must be 16bit aligned. + assert((length&0x1)==0); + + assert(offset+length0;i--) { + address = (page+((i-1)*MFB_PAGE_SIZE_B)); + flash = (int8u *)address; + //Scan the page to determine if it is fully erased already. + //If the flash is not erased, erase it. The purpose of scanning + //first is to save a little time if erasing is not required. + for(k=0;k + */ + +/** @addtogroup nvm + * @brief Cortex-M3 Non-Volatile Memory data storage system. + * + * This header defines the API for NVM data storage. This header also + * describes the algorithm behind the NVM data storage system with notes + * on algorithm behavior. + * + * See hal/micro/cortexm3/nvm.h for source code. + * + * @note The algorithm description uses "page" to indicate an area of memory + * that is a multiple of physical flash pages. There are two pages: LEFT + * and RIGHT. The term "flash page" is used to refer to a page of + * physical flash. + * + * NVM data storage works by alternating between two pages: LEFT and RIGHT. + * The basic algorithm is driven by a call to halCommonSaveToNvm(). It will: + * - erase the inactive page + * - write the new data to the inactive page + * - copy existing data from the active page to the inactive page + * - mark the inactive page as the new active page + * - mark the old active page as the new inactive page + * To accomplish alternating between two pages and knowing which page has the + * valid set of data, the algorithm uses 4 bytes of mgmt data that exists + * at the top of both LEFT and RIGHT (the term "mgmt" is shorthand referring to + * the management data). The management data is comprised of a Valid marker, + * an Active marker, a Dead marker, and a Spare byte. Viewing the + * management data as a single 32 bit quantity yields: + * - Valid is mgmt[0] + * - Active is mgmt[1] + * - Dead is mgmt[2] + * - Spare is mgmt[3] + * The algorithm is based on a simple, circular state machine. The following + * discussion details all of the possible mgmt bytes and the states they + * correspond to. The "Reads from" line indicates which page a call to + * halCommonReadFromNvm() will read from (an 'x' page will stuff the read + * data with 0xFF). The vertical "erase" and "write" words indicate the + * flash altering actions taken between those states. Invalid mgmt bytes + * is equivalent to erased mgmt bytes (state 0) and will trigger an + * erase of both LEFT and RIGHT. State 3 and state 7 are the only exit + * states. When the algorithm is run, regardless of starting state, it + * will advance to the next exit state. This means if the "Read from" + * is LEFT then the state machine will advance until state 7 and then exit. + * If "Read from" is RIGHT, then the state machine will advance until + * state 3 and then exit. + * + * @code + * Starting from erased or invalid mgmt, write to LEFT + * State # 0 0 1 2 3 + * Reads from: x x e w L L L + * Valid xx|xx FF|FF r r 00|FF 00|FF 00|00 + * Active xx|xx FF|FF a i 00|FF 00|FF 00|00 + * Dead xx|xx FF|FF s t FF|FF FF|00 FF|00 + * Spare xx|xx FF|FF e e FF|FF FF|FF FF|FF + * + * + * Starting from LEFT page, transition to RIGHT page: + * State # 3 4 5 6 7 + * Reads from: L e L w R R R + * Valid 00|00 r 00|FF r 00|00 00|00 00|00 + * Active 00|00 a 00|FF i 00|FF 00|FF 00|00 + * Dead FF|00 s FF|FF t FF|FF 00|FF 00|FF + * Spare FF|FF e FF|FF e FF|FF FF|FF FF|FF + * + * + * Starting from RIGHT page, transition to LEFT page: + * State # 7 8 9 10 3 + * Reads from: R e R w L L L + * Valid 00|00 r FF|00 r 00|00 00|00 00|00 + * Active 00|00 a FF|00 i FF|00 FF|00 00|00 + * Dead 00|FF s FF|FF t FF|FF FF|00 FF|00 + * Spare FF|FF e FF|FF e FF|FF FF|FF FF|FF + * @endcode + * + * Based on the 10 possible states, there are 5 valid 32bit mgmt words: + * - 0xFFFFFFFF + * - 0xFFFFFF00 + * - 0xFFFF0000 + * - 0xFF000000 + * - 0xFF00FFFF + * The algorithm determines the current state by using these 5 mgmt words + * with the 10 possible combinations of LEFT mgmt and RIGHT mgmt. + * + * Detailed State Description: + * - State 0: + * In this state the mgmt bytes do not conform to any of the other states + * and therefore the entire NVM system, both the LEFT and RIGHT, is + * invalid. Invalid could be as simple as both LEFT and RIGHT are erased + * or as complex as serious memory corruption or a bug caused bad data to + * be written to the NVM. By using a small set of very strict, precise, + * valid states (versus other management systems such as a simple counter), + * the algorithm/data gains some protection against not only corruption, but + * also executing the NVM algorithm on a chip that previously did not + * have the NVM system running on it. + * - State 1, 4, 8 + * In these states, mgmt is saying that one page is valid and active, while + * the other page is erased. This tells the algorithm which page to read + * from and indicates that the other page has already been erased. + * - State 2 + * This state is only necessary for transitioning from state 0. From state + * 0, the goal is to arrive at state 3. Ideally, the RIGHT mgmt would + * be written with 0xFF000000, but the flash library only permits 16 bit + * writes. If a reset were to occur in the middle of this section of the + * algorithm, we want to ensure that the mgmt is left in a known state, + * state 2, so that the algorithm could continue from where it got + * interrupted. + * - State 5, 9 + * These states indicate that the other page has just become valid because + * the new data has just been written. Once at these states, reading + * from the NVM will now pull data from the other page. + * - State 6, 10 + * These states indicate that the old page is now dead and not in use. + * While the algorithm already knows to read from the new page, the Dead + * mgmt byte is primarily used to indicate that the other page needs to + * be erased. Conceptually, the Dead byte can also be considered a type + * of "garbage collection" flag indicating the old page needs to be + * destroyed and has not yet been erased. + * - State 3, 7 + * These states are the final exit points of the circular state machine. + * Once at these states, the current page is marked Valid and Active and + * the old page is marked as Dead. The algorithm knows which page to + * read from and which page needs to be erased on the next write to the NVM. + * + * + * Notes on algorithm behavior: + * - Refer to nvm-def.h for a list of offset/length that define the data + * stored in NVM storage space. + * - All writes to flash are 16bit granularity and therefore the internal + * flash writes cast the data to int16u. Length is also required to be + * a multiple of 16bits. + * - Flash page erase uses a granularity of a single flash page. The size + * of a flash page depends on the chip and is defined in memmap.h with + * the define MFB_PAGE_SIZE_B. + * - Erasing will only occur when halCommonSaveToNvm() is called. + * - Erasing will always occur when halCommonSaveToNvm() is called unless the + * page intended to be erased is already entirely 0xFFFF. + * - When reading and management is invalid, the read will return 0xFF for data. + * - Calling halCommonSaveToNvm() while in any state is always valid and the + * new data will be written to flash. + * - halCommonSaveToNvm() will always advance the state machine to 3 or 7. + * - When writing and management is invalid, both LEFT and RIGHT will be erased + * and the new data will be written to LEFT. + * - Writing causes the new data being passed into halCommonSaveToNvm() to be + * written to flash. The data already existing in the currently valid page + * will be copied over to the new page. + * - Reading or writing to an offset equal to or greater than NVM_DATA_SIZE_B is + * illegal and will cause an assert. + * - Offset and length must always be multiples of 16bits. If not, both a read + * and a write will trigger an assert. + * - Offset and length must be supplied in bytes. + * - All data in NVM storage must exist above the mgmt bytes, denoted by + * NVM_MGMT_SIZE_B. + * - The bottom 64 bytes of NVM storage are allocated to radio calibration + * values. These 64 bytes *must* exist for the radio to function. + * - There is no error checking beyond checking for 16bit alignment. This + * means it is possible to use data offset and size combinations that + * exceed NVM storage space or overlap with other data. Be careful! + *@{ + */ + + +#ifndef __NVM_H__ +#define __NVM_H__ + +//Pull in the MFB_ definitions. +#include "hal/micro/cortexm3/memmap.h" +//Pull in nvm-def.h so any code including nvm.h has access to the +//offsets and sizes defining the NVM data. +#include "hal/micro/cortexm3/nvm-def.h" +//Necessary to define StStatus and codes. +#include "error.h" + + +/** + * @brief Copy the NVM data from flash into the provided RAM location. + * It is illegal for the offset to be greater than NVM_DATA_SIZE_B. + * + * @param data A (RAM) pointer to where the data should be copied. + * + * @param offset The location from which the data should be copied. Must be + * 16bit aligned. + * + * @param length The length of the data in bytes. Must be 16bit aligned. + * + * @return An StStatus value indicating the success of the function. + * - ST_SUCCESS if the read completed cleanly. + * - ST_ERR_FATAL if the NVM storage management indicated an invalid + * state. The function will return entirely 0xFF in the data parameter. + */ +StStatus halCommonReadFromNvm(void *data, int32u offset, int16u length); + +/** + * @brief Return the address of the token in NVM + * + * @param offset The location offset from which the address should be returned + * + * + * @return The address requested + */ +int16u *halCommonGetAddressFromNvm(int32u offset); + +/** + * @brief Write the NVM data from the provided location RAM into flash. + * It is illegal for the offset to be greater than NVM_DATA_SIZE_B. + * + * @param data A (RAM) pointer from where the data should be taken. + * + * @param offset The location to which the data should be written. Must be + * 16bit aligned. + * + * @param length The length of the data in bytes. Must be 16bit aligned. + * + * @return An StStatus value indicating the success of the function. + * - ST_SUCCESS if the write completed cleanly. + * - Any other status value is an error code generated by the low level + * flash erase and write API. Refer to flash.h for details. + */ +StStatus halCommonWriteToNvm(const void *data, int32u offset, int16u length); + +/** + * @brief Define the number of physical flash pages that comprise a NVM page. + * Since NVM_DATA_SIZE_B must be a multiple of MFB_PAGE_SIZE_B, increasing the + * size of NVM storage should be done by modifying this define. + * + * @note The total flash area consumed by NVM storage is double this value. + * This is due to the fact that there are two NVM pages, LEFT and RIGHT, + * which the algorithm alternates between. + */ +#define NVM_FLASH_PAGE_COUNT (1) + +/** + * @brief Define the total size of a NVM page, in bytes. This must be a + * multiple of the memory map define MFB_PAGE_SIZE_B. Note that 4 bytes of + * the total size of an NVM page are dedicated to page management. + * + * @note DO NOT EDIT THIS DEFINE. Instead, edit NVM_FLASH_PAGE_COUNT. + */ +#define NVM_DATA_SIZE_B (MFB_PAGE_SIZE_B*NVM_FLASH_PAGE_COUNT) +#if ((NVM_DATA_SIZE_B%MFB_PAGE_SIZE_B) != 0) + #error Illegal NVM data storage size. NVM_DATA_SIZE_B must be a multiple of MFB_PAGE_SIZE_B. +#endif + +/** + * @brief Define the absolute address of the LEFT page. LEFT page storage + * is defined by nvmStorageLeft[NVM_DATA_SIZE_B] and placed by the linker + * using the segment "NVM". + */ +#define NVM_LEFT_PAGE ((int32u)nvmStorageLeft) + +/** + * @brief Define the absolute address of the RIGHT page. RIGHT page storage + * is defined by nvmStorageRight[NVM_DATA_SIZE_B] and placed by the linker + * using the segment "NVM". + */ +#define NVM_RIGHT_PAGE ((int32u)nvmStorageRight) + +/** + * @brief Define the number of bytes that comprise the NVM management bytes. + * All data must begin at an offset above the management bytes. + * + * @note This value must not change. + */ +#define NVM_MGMT_SIZE_B (4) + +/** @} END addtogroup */ + +#endif // __NVM_H__ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/sleep.c b/cpu/stm32w108/hal/micro/cortexm3/sleep.c new file mode 100644 index 000000000..4d6dd9f0f --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/sleep.c @@ -0,0 +1,873 @@ +/** @file hal/micro/cortexm3/sleep.c + * + * @brief STM32W108 micro specific sleep functions. + * + * + */ + +#include PLATFORM_HEADER +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//We don't have a real register to hold this composite information. +//Pretend we do so halGetWakeInfo can operate like halGetResetInfo. +//This "register" is only ever set by halInternalSleep. +// [31] = WakeInfoValid +// [30] = SleepSkipped +// [29] = CSYSPWRUPREQ +// [28] = CDBGPWRUPREQ +// [27] = WAKE_CORE +// [26] = TIMER_WAKE_WRAP +// [25] = TIMER_WAKE_COMPB +// [24] = TIMER_WAKE_COMPA +// [23:0] = corresponding GPIO activity +#define WAKEINFOVALID_INTERNAL_WAKE_EVENT_BIT 31 +#define SLEEPSKIPPED_INTERNAL_WAKE_EVENT_BIT 30 +#define CSYSPWRUPREQ_INTERNAL_WAKE_EVENT_BIT 29 +#define CDBGPWRUPREQ_INTERNAL_WAKE_EVENT_BIT 28 +#define WAKE_CORE_INTERNAL_WAKE_EVENT_BIT 27 +#define WRAP_INTERNAL_WAKE_EVENT_BIT 26 +#define CMPB_INTERNAL_WAKE_EVENT_BIT 25 +#define CMPA_INTERNAL_WAKE_EVENT_BIT 24 +//This define shifts events from the PWRUP_EVENT register into the proper +//place in the halInternalWakeEvent variable +#define INTERNAL_WAKE_EVENT_BIT_SHIFT 20 + +static int32u halInternalWakeEvent=0; + +int32u halGetWakeInfo(void) +{ + return halInternalWakeEvent; +} + +void halInternalSleep(SleepModes sleepMode) +{ + //Timer restoring always takes place during the wakeup sequence. We save + //the state here in case SLEEPMODE_NOTIMER is invoked, which would disable + //the clocks. + int32u SLEEPTMR_CLKEN_SAVED = SLEEPTMR_CLKEN; + + //This code assumes all wake source registers are properly configured. + //As such, it should be called from halSleepWithOptions() or from + // halSleepForQsWithOptions() which configues the wake sources. + + //The parameter gpioWakeSel is a bitfield composite of the GPIO wake + //sources derived from the 3 ports, indicating which of the 24 GPIO + //are configured as a wake source. + int32u gpioWakeSel = (GPIO_PAWAKE<<0); + gpioWakeSel |= (GPIO_PBWAKE<<8); + gpioWakeSel |= (GPIO_PCWAKE<<16); + + //PB2 is also WAKE_SC1. Set this wake source if PB2's GPIO wake is set. + if(GPIO_PBWAKE & PB2) { + WAKE_SEL |= WAKE_SC1; + } + + //PA2 is also WAKE_SC2. Set this wake source if PA2's GPIO wake is set. + if(GPIO_PAWAKE & PA2) { + WAKE_SEL |= WAKE_SC2; + } + + //The WAKE_IRQD source can come from any pin based on IRQD's sel register. + if(gpioWakeSel & BIT(GPIO_IRQDSEL)) { + WAKE_SEL |= WAKE_IRQD; + } + + halInternalWakeEvent = 0; //clear old wake events + + switch(sleepMode) + { + case SLEEPMODE_NOTIMER: + //The sleep timer clock sources (both RC and XTAL) are turned off. + //Wakeup is possible from only GPIO. System time is lost. + //NOTE: Timer restoring always takes place during the wakeup sequence. + SLEEPTMR_CLKEN = 0; + goto deepSleepCore; + + case SLEEPMODE_WAKETIMER: + //The sleep timer clock sources remain running. The RC is always + //running and the 32kHz XTAL depends on the board header. Wakeup + //is possible from both GPIO and the sleep timer. System time + //is maintained. The sleep timer is assumed to be configured + //properly for wake events. + //NOTE: This mode assumes the caller has configured the *entire* + // sleep timer properly. + + if(INT_SLEEPTMRCFG&INT_SLEEPTMRWRAP) { + WAKE_SEL |= WAKE_SLEEPTMRWRAP; + } + if(INT_SLEEPTMRCFG&INT_SLEEPTMRCMPB) { + WAKE_SEL |= WAKE_SLEEPTMRCMPB; + } + if(INT_SLEEPTMRCFG&INT_SLEEPTMRCMPA) { + WAKE_SEL |= WAKE_SLEEPTMRCMPA; + } + //fall into SLEEPMODE_MAINTAINTIMER's sleep code: + + case SLEEPMODE_MAINTAINTIMER: + //The sleep timer clock sources remain running. The RC is always + //running and the 32kHz XTAL depends on the board header. Wakeup + //is possible from only GPIO. System time is maintained. + //NOTE: System time is maintained without any sleep timer interrupts + // because the hardware sleep timer counter is large enough + // to hold the entire count value and not need a RAM counter. + + //////////////////////////////////////////////////////////////////////////// + // Core deep sleep code + //////////////////////////////////////////////////////////////////////////// +deepSleepCore: + // Interrupts *must* be/stay disabled for DEEP SLEEP operation + // INTERRUPTS_OFF will use BASEPRI to disable all interrupts except + // fault handlers and PendSV. + INTERRUPTS_OFF(); + // This is the point of no return. From here on out, only the interrupt + // sources available in WAKE_SEL will be captured and propagated across + // deep sleep. + //stick all our saved info onto stack since it's only temporary + { + boolean restoreWatchdog = halInternalWatchDogEnabled(); + boolean skipSleep = FALSE; + + // Only three register blocks keep power across deep sleep: + // CM_HV, GPIO, SLOW_TIMERS + // + // All other register blocks lose their state across deep sleep: + // BASEBAND, MAC, SECURITY, SERIAL, TMR1, TMR2, EVENT, CM_LV, RAM_CTRL, + // AUX_ADC, CAL_ADC, FLASH_CONTROL, ITM, DWT, FPB, NVIC, TPIU + // + // The sleep code will only save and restore registers where it is + // meaningful and necessary to do so. In most cases, there must still + // be a powerup function to restore proper state. + // + // NOTE: halPowerUp() and halPowerDown() will always be called before + // and after this function. halPowerDown and halPowerUp should leave + // the modules in a safe state and then restart the modules. + // (For example, shutting down and restarting Timer1) + // + //----BASEBAND + // reinitialized by stStackPowerUp() + //----MAC + // reinitialized by stStackPowerUp() + //----SECURITY + // reinitialized by stStackPowerUp() + //----SERIAL + // reinitialized by halPowerUp() or similar + //----TMR1 + // reinitialized by halPowerUp() or similar + //----TMR2 + // reinitialized by halPowerUp() or similar + //----EVENT + //SRC or FLAG interrupts are not saved or restored + //MISS interrupts are not saved or restored + //MAC_RX_INT_MASK - reinitialized by stStackPowerUp() + //MAC_TX_INT_MASK - reinitialized by stStackPowerUp() + //MAC_TIMER_INT_MASK - reinitialized by stStackPowerUp() + //BB_INT_MASK - reinitialized by stStackPowerUp() + //SEC_INT_MASK - reinitialized by stStackPowerUp() + int32u INT_SLEEPTMRCFG_SAVED = INT_SLEEPTMRCFG_REG; + int32u INT_MGMTCFG_SAVED = INT_MGMTCFG_REG; + //INT_TIM1CFG - reinitialized by halPowerUp() or similar + //INT_TIM2CFG - reinitialized by halPowerUp() or similar + //INT_SC1CFG - reinitialized by halPowerUp() or similar + //INT_SC2CFG - reinitialized by halPowerUp() or similar + //INT_ADCCFG - reinitialized by halPowerUp() or similar + int32u GPIO_INTCFGA_SAVED = GPIO_INTCFGA_REG; + int32u GPIO_INTCFGB_SAVED = GPIO_INTCFGB_REG; + int32u GPIO_INTCFGC_SAVED = GPIO_INTCFGC_REG; + int32u GPIO_INTCFGD_SAVED = GPIO_INTCFGD_REG; + //SC1_INTMODE - reinitialized by halPowerUp() or similar + //SC2_INTMODE - reinitialized by halPowerUp() or similar + //----CM_LV + int32u OSC24M_BIASTRIM_SAVED = OSC24M_BIASTRIM_REG; + int32u OSCHF_TUNE_SAVED = OSCHF_TUNE_REG; + int32u DITHER_DIS_SAVED = DITHER_DIS_REG; + //OSC24M_CTRL - reinitialized by halPowerUp() or similar + //CPU_CLKSEL - reinitialized by halPowerUp() or similar + //TMR1_CLK_SEL - reinitialized by halPowerUp() or similar + //TMR2_CLK_SEL - reinitialized by halPowerUp() or similar + int32u PCTRACE_SEL_SAVED = PCTRACE_SEL_REG; + //----RAM_CTRL + int32u MEM_PROT_0_SAVED = MEM_PROT_0_REG; + int32u MEM_PROT_1_SAVED = MEM_PROT_1_REG; + int32u MEM_PROT_2_SAVED = MEM_PROT_2_REG; + int32u MEM_PROT_3_SAVED = MEM_PROT_3_REG; + int32u MEM_PROT_4_SAVED = MEM_PROT_4_REG; + int32u MEM_PROT_5_SAVED = MEM_PROT_5_REG; + int32u MEM_PROT_6_SAVED = MEM_PROT_6_REG; + int32u MEM_PROT_7_SAVED = MEM_PROT_7_REG; + int32u MEM_PROT_EN_SAVED = MEM_PROT_EN_REG; + //----AUX_ADC + // reinitialized by halPowerUp() or similar + //----CAL_ADC + // reinitialized by stStackPowerUp() + //----FLASH_CONTROL + // configured on the fly by the flash library + //----ITM + // reinitialized by halPowerUp() or similar + //----DWT + // not used by software on chip + //----FPB + // not used by software on chip + //----NVIC + //ST_CSR - fixed, restored by cstartup when exiting deep sleep + //ST_RVR - fixed, restored by cstartup when exiting deep sleep + int32u INT_CFGSET_SAVED = INT_CFGSET_REG; //mask against wake sources + //INT_PENDSET - used below when overlapping interrupts and wake sources + //NVIC_IPR_3to0 - fixed, restored by cstartup when exiting deep sleep + //NVIC_IPR_7to4 - fixed, restored by cstartup when exiting deep sleep + //NVIC_IPR_11to8 - fixed, restored by cstartup when exiting deep sleep + //NVIC_IPR_15to12 - fixed, restored by cstartup when exiting deep sleep + //NVIC_IPR_19to16 - fixed, restored by cstartup when exiting deep sleep + int32u SCS_VTOR_SAVED = SCS_VTOR_REG; + //SCS_CCR - fixed, restored by cstartup when exiting deep sleep + //SCS_SHPR_7to4 - fixed, restored by cstartup when exiting deep sleep + //SCS_SHPR_11to8 - fixed, restored by cstartup when exiting deep sleep + //SCS_SHPR_15to12 - fixed, restored by cstartup when exiting deep sleep + //SCS_SHCSR - fixed, restored by cstartup when exiting deep sleep + //----TPIU + // reinitialized by halPowerUp() or similar + + //stmDebugPowerDown() should have shutdown the DWT/ITM/TPIU already. + + //freeze input to the GPIO from LV (alternate output functions freeze) + EVENT_CTRL = LV_FREEZE; + //record GPIO state for wake monitoring purposes + //By having a snapshot of GPIO state, we can figure out after waking + //up exactly which GPIO could have woken us up. + //Reading the three IN registers is done separately to avoid warnings + //about undefined order of volatile access. + int32u GPIO_IN_SAVED = GPIO_PAIN; + GPIO_IN_SAVED |= (GPIO_PBIN<<8); + GPIO_IN_SAVED |= (GPIO_PCIN<<16); + //reset the power up events by writing 1 to all bits. + PWRUP_EVENT = 0xFFFFFFFF; + + + + //By clearing the events, the wake up event capturing is activated. + //At this point we can safely check our interrupt flags since event + //capturing is now overlapped. Up to now, interrupts indicate + //activity, after this point, powerup events indicate activity. + //If any of the interrupt flags are set, that means we saw a wake event + //sometime while entering sleep, so we need to skip over sleeping + // + //--possible interrupt sources for waking: + // IRQA, IRQB, IRQC, IRQD + // SleepTMR CMPA, CMPB, Wrap + // WAKE_CORE (DebugIsr) + // + //check for IRQA interrupt and if IRQA (PB0) is wake source + if((INT_PENDSET&INT_IRQA) && + (GPIO_PBWAKE&PB0) && + (WAKE_SEL&GPIO_WAKE)) { + skipSleep = TRUE; + //log IRQA as a wake event + halInternalWakeEvent |= BIT(PORTB_PIN(0)); + + + + } + //check for IRQB interrupt and if IRQB (PB6) is wake source + if((INT_PENDSET&INT_IRQB) && + (GPIO_PBWAKE&PB6) && + (WAKE_SEL&GPIO_WAKE)) { + skipSleep = TRUE; + //log IRQB as a wake event + halInternalWakeEvent |= BIT(PORTB_PIN(6)); + + + + } + //check for IRQC interrupt and if IRQC (GPIO_IRQCSEL) is wake source + if((INT_PENDSET&INT_IRQC) && + (gpioWakeSel&BIT(GPIO_IRQCSEL)) && + (WAKE_SEL&GPIO_WAKE)) { + skipSleep = TRUE; + //log IRQC as a wake event + halInternalWakeEvent |= BIT(GPIO_IRQCSEL); + + + + } + //check for IRQD interrupt and if IRQD (GPIO_IRQDSEL) is wake source + if((INT_PENDSET&INT_IRQD) && + (gpioWakeSel&BIT(GPIO_IRQDSEL)) && + ((WAKE_SEL&GPIO_WAKE) || + (WAKE_SEL&WAKE_IRQD))) { + skipSleep = TRUE; + //log IRQD as a wake event + halInternalWakeEvent |= BIT(GPIO_IRQDSEL); + + + + } + //check for SleepTMR CMPA interrupt and if SleepTMR CMPA is wake source + if((INT_SLEEPTMR&INT_SLEEPTMRCMPA) && (WAKE_SEL&WAKE_SLEEPTMRCMPA)) { + skipSleep = TRUE; + //log SleepTMR CMPA as a wake event + halInternalWakeEvent |= BIT32(CMPA_INTERNAL_WAKE_EVENT_BIT); + + + + } + //check for SleepTMR CMPB interrupt and if SleepTMR CMPB is wake source + if((INT_SLEEPTMR&INT_SLEEPTMRCMPB) && (WAKE_SEL&WAKE_SLEEPTMRCMPB)) { + skipSleep = TRUE; + //log SleepTMR CMPB as a wake event + halInternalWakeEvent |= BIT32(CMPB_INTERNAL_WAKE_EVENT_BIT); + + + + } + //check for SleepTMR WRAP interrupt and if SleepTMR WRAP is wake source + if((INT_SLEEPTMR&INT_SLEEPTMRWRAP) && (WAKE_SEL&WAKE_SLEEPTMRWRAP)) { + skipSleep = TRUE; + //log SleepTMR WRAP as a wake event + halInternalWakeEvent |= BIT32(WRAP_INTERNAL_WAKE_EVENT_BIT); + + + + } + //check for Debug interrupt and if WAKE_CORE is wake source + if((INT_PENDSET&INT_DEBUG) && (WAKE_SEL&WAKE_WAKE_CORE)) { + skipSleep = TRUE; + //log WAKE_CORE as a wake event + halInternalWakeEvent |= BIT32(WAKE_CORE_INTERNAL_WAKE_EVENT_BIT); + + + + } + + //only propagate across deep sleep the interrupts that are both + //enabled and possible wake sources + { + int32u wakeSourceInterruptMask = 0; + + if(GPIO_PBWAKE&PB0) { + wakeSourceInterruptMask |= INT_IRQA; + + + + } + if(GPIO_PBWAKE&PB6) { + wakeSourceInterruptMask |= INT_IRQB; + + + + } + if(gpioWakeSel&BIT(GPIO_IRQCSEL)) { + wakeSourceInterruptMask |= INT_IRQC; + + + + } + if(gpioWakeSel&BIT(GPIO_IRQDSEL)) { + wakeSourceInterruptMask |= INT_IRQD; + + + + } + if( (WAKE_SEL&WAKE_SLEEPTMRCMPA) || + (WAKE_SEL&WAKE_SLEEPTMRCMPB) || + (WAKE_SEL&WAKE_SLEEPTMRWRAP) ) { + wakeSourceInterruptMask |= INT_SLEEPTMR; + + + + } + if(WAKE_SEL&WAKE_WAKE_CORE) { + wakeSourceInterruptMask |= INT_DEBUG; + + + + } + + INT_CFGSET_SAVED &= wakeSourceInterruptMask; + } + + + + + + + + + + + + + + + + + + //disable watchdog while sleeping (since we can't reset it asleep) + halInternalDisableWatchDog(MICRO_DISABLE_WATCH_DOG_KEY); + + //The chip is not allowed to enter a deep sleep mode (which could + //cause a core reset cycle) while CSYSPWRUPREQ is set. CSYSPWRUPREQ + //indicates that the debugger is trying to access sections of the + //chip that would get reset during deep sleep. Therefore, a reset + //cycle could very easily cause the debugger to error and we don't + //want that. While the power management state machine will stall + //if CSYSPWRUPREQ is set (to avoid the situation just described), + //in this stalled state the chip will not be responsive to wake + //events. To be sensitive to wake events, we must handle them in + //software instead. To accomplish this, we request that the + //CSYSPWRUPACK be inhibited (which will indicate the debugger is not + //connected). But, we cannot induce deep sleep until CSYSPWRUPREQ/ACK + //go low and these are under the debuggers control, so we must stall + //and wait here. If there is a wake event during this time, break + //out and wake like normal. If the ACK eventually clears, + //we can proceed into deep sleep. The CSYSPWRUPACK_INHIBIT + //functionality will hold off the debugger (by holding off the ACK) + //until we are safely past and out of deep sleep. The power management + //state machine then becomes responsible for clearing + //CSYSPWRUPACK_INHIBIT and responding to a CSYSPWRUPREQ with a + //CSYSPWRUPACK at the right/safe time. + CSYSPWRUPACK_INHIBIT = CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT; + { + //Use a local copy of WAKE_SEL to avoid warnings from the compiler + //about order of volatile accesses + int32u wakeSel = WAKE_SEL; + //stall until a wake event or CSYSPWRUPREQ/ACK clears + while( (CSYSPWRUPACK_STATUS) && (!(PWRUP_EVENT&wakeSel)) ) {} + //if there was a wake event, allow CSYSPWRUPACK and skip sleep + if(PWRUP_EVENT&wakeSel) { + CSYSPWRUPACK_INHIBIT = CSYSPWRUPACK_INHIBIT_RESET; + skipSleep = TRUE; + } + } + + + + + + if(!skipSleep) { + + + + //FogBugz 7283 states that we must switch to the OSCHF when entering + //deep sleep since using the 24MHz XTAL could result in RAM + //corruption. This switch must occur at least 2*24MHz cycles before + //sleeping. + //FogBugz 8858 states that we cannot go into deep-sleep when the + //chip is clocked with the 24MHz XTAL with a duty cycle as low as + //70/30 since this causes power_down generation timing to fail. + OSC24M_CTRL &= ~OSC24M_CTRL_OSC24M_SEL; + //If DS12 needs to be forced regardless of state, clear + //REGEN_DSLEEP here. This is hugely dangerous and + //should only be done in very controlled chip tests. + SCS_SCR |= SCS_SCR_SLEEPDEEP; //enable deep sleep + extern volatile boolean halPendSvSaveContext; + halPendSvSaveContext = 1; //1 means save context + //The INTERRUPTS_OFF used at the beginning of this function set + //BASEPRI such that the only interrupts that will fire are faults + //and PendSV. Trigger PendSV now to induce a context save. + SCS_ICSR |= SCS_ICSR_PENDSVSET; //pend the context save and Dsleep + //Since the interrupt will not fire immediately it is possible to + //execute a few lines of code. To stay halted in this spot until the + //WFI instruction, spin on the context flag (which will get cleared + //during the startup sequence when restoring context). + while(halPendSvSaveContext) {} + //I AM ASLEEP. WHEN EXECUTION RESUMES, CSTARTUP WILL RESTORE TO HERE + } else { + //Record the fact that we skipped sleep + halInternalWakeEvent |= BIT32(SLEEPSKIPPED_INTERNAL_WAKE_EVENT_BIT); + //If this was a true deep sleep, we would have executed cstartup and + //PRIMASK would be set right now. If we skipped sleep, PRIMASK is not + //set so we explicitely set it to guarantee the powerup sequence + //works cleanly and consistently with respect to interrupt + //dispatching and enabling. + _setPriMask(); + } + + + + + + + + + //Clear the interrupt flags for all wake sources. This + //is necessary because if we don't execute an actual deep sleep cycle + //the interrupt flags will never be cleared. By clearing the flags, + //we always mimick a real deep sleep as closely as possible and + //guard against any accidental interrupt triggering coming out + //of deep sleep. (The interrupt dispatch code coming out of sleep + //is responsible for translating wake events into interrupt events, + //and if we don't clear interrupt flags here it's possible for an + //interrupt to trigger even if it wasn't the true wake event.) + INT_SLEEPTMRFLAG = (INT_SLEEPTMRCMPA | + INT_SLEEPTMRCMPB | + INT_SLEEPTMRWRAP); + INT_GPIOFLAG = (INT_IRQAFLAG | + INT_IRQBFLAG | + INT_IRQCFLAG | + INT_IRQDFLAG); + + //immediately restore the registers we saved before sleeping + //so IRQ and SleepTMR capture can be reenabled as quickly as possible + //this is safe because our global interrupts are still disabled + //other registers will be restored later + + + + + + + + SLEEPTMR_CLKEN_REG = SLEEPTMR_CLKEN_SAVED; + INT_SLEEPTMRCFG_REG = INT_SLEEPTMRCFG_SAVED; + INT_MGMTCFG_REG = INT_MGMTCFG_SAVED; + GPIO_INTCFGA_REG = GPIO_INTCFGA_SAVED; + GPIO_INTCFGB_REG = GPIO_INTCFGB_SAVED; + GPIO_INTCFGC_REG = GPIO_INTCFGC_SAVED; + GPIO_INTCFGD_REG = GPIO_INTCFGD_SAVED; + OSC24M_BIASTRIM_REG = OSC24M_BIASTRIM_SAVED; + OSCHF_TUNE_REG = OSCHF_TUNE_SAVED; + DITHER_DIS_REG = DITHER_DIS_SAVED; + PCTRACE_SEL_REG = PCTRACE_SEL_SAVED; + MEM_PROT_0_REG = MEM_PROT_0_SAVED; + MEM_PROT_1_REG = MEM_PROT_1_SAVED; + MEM_PROT_2_REG = MEM_PROT_2_SAVED; + MEM_PROT_3_REG = MEM_PROT_3_SAVED; + MEM_PROT_4_REG = MEM_PROT_4_SAVED; + MEM_PROT_5_REG = MEM_PROT_5_SAVED; + MEM_PROT_6_REG = MEM_PROT_6_SAVED; + MEM_PROT_7_REG = MEM_PROT_7_SAVED; + MEM_PROT_EN_REG = MEM_PROT_EN_SAVED; + INT_CFGSET_REG = INT_CFGSET_SAVED; + SCS_VTOR_REG = SCS_VTOR_SAVED; + + //WAKE_CORE/INT_DEBUG and INT_IRQx is cleared by INT_PENDCLR below + INT_PENDCLR = 0xFFFFFFFF; + + //Now that we're awake, normal interrupts are operational again + //Take a snapshot of the new GPIO state and the EVENT register to + //record our wake event + int32u GPIO_IN_NEW = GPIO_PAIN; + GPIO_IN_NEW |= (GPIO_PBIN<<8); + GPIO_IN_NEW |= (GPIO_PCIN<<16); + //Only operate on power up events that are also wake events. Power + //up events will always trigger like an interrupt flag, so we have + //to check them against events that are enabled for waking. (This is + //a two step process because we're accessing two volatile values.) + int32u powerUpEvents = PWRUP_EVENT; + powerUpEvents &= WAKE_SEL; + halInternalWakeEvent |= ((GPIO_IN_SAVED^GPIO_IN_NEW)&gpioWakeSel); + //PWRUP_SC1 is PB2 which is bit 10 + halInternalWakeEvent |= (!!(powerUpEvents&PWRUP_SC1))<<((1*8)+2); + //PWRUP_SC2 is PA2 which is bit 2 + halInternalWakeEvent |= (!!(powerUpEvents&PWRUP_SC2))<<((0*8)+2); + //PWRUP_IRQD is chosen by GPIO_IRQDSEL + halInternalWakeEvent |= (!!(powerUpEvents&PWRUP_IRQD))<<(GPIO_IRQDSEL); + halInternalWakeEvent |= ((powerUpEvents & + (PWRUP_CSYSPWRUPREQ_MASK | + PWRUP_CDBGPWRUPREQ_MASK | + PWRUP_WAKECORE_MASK | + PWRUP_SLEEPTMRWRAP_MASK | + PWRUP_SLEEPTMRCOMPB_MASK | + PWRUP_SLEEPTMRCOMPA_MASK )) + <>0)&0xFF; + GPIO_PBWAKE = (gpioWakeBitMask>>8)&0xFF; + GPIO_PCWAKE = (gpioWakeBitMask>>16)&0xFF; + + //use the defines found in the board file to choose our wakeup source(s) + WAKE_SEL = 0; //start with no wake sources + + //if any of the GPIO wakeup monitor bits are set, enable the top level + //GPIO wakeup monitor + if((GPIO_PAWAKE)||(GPIO_PBWAKE)||(GPIO_PCWAKE)) { + WAKE_SEL |= GPIO_WAKE; + } + //always wakeup when the debugger is connected + WAKE_SEL |= WAKE_CDBGPWRUPREQ; + //always wakeup when the debugger attempts to access the chip + WAKE_SEL |= WAKE_CSYSPWRUPREQ; + //always wakeup when the debug channel attempts to access the chip + WAKE_SEL |= WAKE_WAKE_CORE; + //the timer wakeup sources are enabled below in POWERSAVE, if needed + + //wake sources are configured so do the actual sleeping + halInternalSleep(sleepMode); +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/Makefile b/cpu/stm32w108/hal/micro/cortexm3/small_printf/Makefile new file mode 100644 index 000000000..df004dd3a --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/Makefile @@ -0,0 +1,35 @@ + + + +CC = arm-none-eabi-gcc +AR = arm-none-eabi-ar +CFLAGS = -mthumb -mcpu=cortex-m3 -I "." -I "C:/Program\ Files/Raisonance/Ride/Lib/ARM/include" \ + -fsigned-char -D _SMALL_PRINTF -D INTEGER_ONLY -Os -ffunction-sections -mlittle-endian +AROPTS = cq + + +SOURCE_FILES = _SP_printf.c _SP_puts.c _SP_sprintf.c _SP_snprintf.c _SP_vfprintf.c + + +SOURCE_OBJS = ${patsubst %.c,%.o,$(SOURCE_FILES)} + + +LIB = smallprintf_thumb2.a + + + +all: clean $(LIB) + +clean: + rm -f $(LIB) + + +%.a: $(SOURCE_OBJS) + $(AR) $(AROPTS) $@ $^ + + +%.o: %.c + $(CC) $(CFLAGS) -c $< -o $@ + + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_printf.c b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_printf.c new file mode 100644 index 000000000..65386b2af --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_printf.c @@ -0,0 +1,78 @@ +#ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #define _vfprintf _vfiprintf + #define vfprintf vfiprintf +#endif + +#include <_ansi.h> +#include + +#ifndef _SMALL_PRINTF + #include "local.h" +#endif + +#ifdef _HAVE_STDC +#include +#else +#include +#endif + +#ifndef _SMALL_PRINTF + + #ifdef _HAVE_STDC + int + _printf_r (struct _reent *ptr, const char *fmt, ...) + #else + int + _printf_r (ptr, fmt, va_alist) + struct _reent *ptr; + char *fmt; + va_dcl + #endif + { + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdout_r (ptr)); + #ifdef _HAVE_STDC + va_start (ap, fmt); + #else + va_start (ap); + #endif + ret = _vfprintf_r (ptr, _stdout_r (ptr), fmt, ap); + va_end (ap); + return ret; + } +#endif + +#ifndef _REENT_ONLY + +#ifdef _HAVE_STDC +int +printf (const char *fmt, ...) +#else +int +printf (fmt, va_alist) + char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdout_r (_REENT)); +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif +#ifndef _SMALL_PRINTF + ret = vfprintf (_stdout_r (_REENT), fmt, ap); +#else + ret = vfprintf (0, fmt, ap); +#endif + va_end (ap); + return ret; +} + +#endif /* ! _REENT_ONLY */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_puts.c b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_puts.c new file mode 100644 index 000000000..0e6a719f9 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_puts.c @@ -0,0 +1,34 @@ +#include +#include + + +void __io_putchar ( char ); + +void _SMALL_PRINTF_puts(const char *ptr, int len, FILE *fp) + { + if ( fp && ( fp->_file == -1 ) /* No file => sprintf */ + && (fp->_flags & (__SWR | __SSTR) ) ) + { + char *str = fp->_p; + + for ( ; len ; len-- ) + { + *str ++ = *ptr++; + } + fp->_p = str; + } + else /* file => printf */ + { + for ( ; len ; len-- ) + __io_putchar ( *ptr++ ); + } + } + +int puts(const char *str) + { + int len = strlen ( str ); + _SMALL_PRINTF_puts(str, len, 0) ; + __io_putchar ( '\n' ); + return len; + } + diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_snprintf.c b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_snprintf.c new file mode 100644 index 000000000..2dfcd8599 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_snprintf.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +/* doc in _SP_sprintf.c */ +/* This code created by modifying _SP_sprintf.c so copyright inherited. */ + +#include +#ifdef _HAVE_STDC +#include +#else +#include +#endif +#include +#include +#include <_ansi.h> + +#ifndef _SMALL_PRINTF + #include "local.h" +#else + #ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #endif +#endif + + +#ifndef _SMALL_PRINTF + int + #ifdef _HAVE_STDC + _DEFUN (_snprintf_r, (ptr, str, size, fmt), struct _reent *ptr _AND char *str _AND size_t size _AND _CONST char *fmt _DOTS) + #else + _snprintf_r (ptr, str, size, fmt, va_alist) + struct _reent *ptr; + char *str; + size_t size; + _CONST char *fmt; + va_dcl + #endif + { + int ret; + va_list ap; + FILE f; + + if (size > INT_MAX) + { + ptr->_errno = EOVERFLOW; + return EOF; + } + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = (size > 0 ? size - 1 : 0); + f._file = -1; /* No file. */ + #ifdef _HAVE_STDC + va_start (ap, fmt); + #else + va_start (ap); + #endif + ret = _vfprintf_r (ptr, &f, fmt, ap); + va_end (ap); + if (ret < EOF) + ptr->_errno = EOVERFLOW; + if (size > 0) + *f._p = 0; + return (ret); + } +#endif + +#ifndef _REENT_ONLY +int +#ifdef _HAVE_STDC +_DEFUN (snprintf, (str, size, fmt), char *str _AND size_t size _AND _CONST char *fmt _DOTS) +#else +snprintf (str, size, fmt, va_alist) + char *str; + size_t size; + _CONST char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + FILE f; + + struct _reent *ptr = _REENT; + + if (size > INT_MAX) + { + ptr->_errno = EOVERFLOW; + return EOF; + } + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = (size > 0 ? size - 1 : 0); + f._file = -1; /* No file. */ +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = _vfprintf_r (ptr, &f, fmt, ap); + va_end (ap); + if (ret < EOF) + ptr->_errno = EOVERFLOW; + if (size > 0) + *f._p = 0; + return (ret); +} +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_sprintf.c b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_sprintf.c new file mode 100644 index 000000000..b64048c31 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_sprintf.c @@ -0,0 +1,389 @@ +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + +FUNCTION + <>, <>, <>, <>, <>---format output +INDEX + fprintf +INDEX + printf +INDEX + asprintf +INDEX + sprintf +INDEX + snprintf + +ANSI_SYNOPSIS + #include + + int printf(const char *<[format]> [, <[arg]>, ...]); + int fprintf(FILE *<[fd]>, const char *<[format]> [, <[arg]>, ...]); + int sprintf(char *<[str]>, const char *<[format]> [, <[arg]>, ...]); + int asprintf(char **<[strp]>, const char *<[format]> [, <[arg]>, ...]); + int snprintf(char *<[str]>, size_t <[size]>, const char *<[format]> [, <[arg]>, ...]); + +TRAD_SYNOPSIS + #include + + int printf(<[format]> [, <[arg]>, ...]) + char *<[format]>; + + int fprintf(<[fd]>, <[format]> [, <[arg]>, ...]); + FILE *<[fd]>; + char *<[format]>; + + int asprintf(<[strp]>, <[format]> [, <[arg]>, ...]); + char **<[strp]>; + char *<[format]>; + + int sprintf(<[str]>, <[format]> [, <[arg]>, ...]); + char *<[str]>; + char *<[format]>; + + int snprintf(<[str]>, size_t <[size]>, <[format]> [, <[arg]>, ...]); + char *<[str]>; + size_t <[size]>; + char *<[format]>; + +DESCRIPTION + <> accepts a series of arguments, applies to each a + format specifier from <<*<[format]>>>, and writes the + formatted data to <>, terminated with a null character. + The behavior of <> is undefined if there are not enough + arguments for the format. + <> returns when it reaches the end of the format string. + If there are more arguments than the format requires, excess + arguments are ignored. + + <>, <>, <> and <> are identical + to <>, other than the destination of the formatted output: + <> sends the output to a specified file <[fd]>, while + <> stores the output in a dynamically allocated buffer, + while <> stores the output in the specified char array + <[str]> and <> limits number of characters written to + <[str]> to at most <[size]> (including terminating <<0>>). For + <> and <>, the behavior is undefined if the + output <<*<[str]>>> overlaps with one of the arguments. For + <>, <[strp]> points to a pointer to char which is filled + in with the dynamically allocated buffer. <[format]> is a pointer + to a charater string containing two types of objects: ordinary + characters (other than <<%>>), which are copied unchanged to the + output, and conversion specifications, each of which is introduced + by <<%>>. (To include <<%>> in the output, use <<%%>> in the format + string.) A conversion specification has the following form: + +. %[<[flags]>][<[width]>][.<[prec]>][<[size]>][<[type]>] + + The fields of the conversion specification have the following meanings: + + O+ + o <[flags]> + + an optional sequence of characters which control + output justification, numeric signs, decimal points, + trailing zeroes, and octal and hex prefixes. + The flag characters are minus (<<->>), plus (<<+>>), + space ( ), zero (<<0>>), and sharp (<<#>>). They can + appear in any combination. + + o+ + o - + The result of the conversion is left justified, and the right is + padded with blanks. If you do not use this flag, the result is right + justified, and padded on the left. + + o + + The result of a signed conversion (as determined by <[type]>) + will always begin with a plus or minus sign. (If you do not use + this flag, positive values do not begin with a plus sign.) + + o " " (space) + If the first character of a signed conversion specification + is not a sign, or if a signed conversion results in no + characters, the result will begin with a space. If the + space ( ) flag and the plus (<<+>>) flag both appear, + the space flag is ignored. + + o 0 + If the <[type]> character is <>, <>, <>, <>, + <>, <>, <>, <>, <>, <>, or <>: leading zeroes, + are used to pad the field width (following any indication of sign or + base); no spaces are used for padding. If the zero (<<0>>) and + minus (<<->>) flags both appear, the zero (<<0>>) flag will + be ignored. For <>, <>, <>, <>, <>, and <> + conversions, if a precision <[prec]> is specified, the zero (<<0>>) + flag is ignored. + + Note that <<0>> is interpreted as a flag, not as the beginning + of a field width. + + o # + The result is to be converted to an alternative form, according + to the next character: + + o+ + o 0 + increases precision to force the first digit + of the result to be a zero. + + o x + a non-zero result will have a <<0x>> prefix. + + o X + a non-zero result will have a <<0X>> prefix. + + o e, E or f + The result will always contain a decimal point + even if no digits follow the point. + (Normally, a decimal point appears only if a + digit follows it.) Trailing zeroes are removed. + + o g or G + same as <> or <>, but trailing zeroes + are not removed. + + o all others + undefined. + + o- + o- + + o <[width]> + + <[width]> is an optional minimum field width. You can either + specify it directly as a decimal integer, or indirectly by + using instead an asterisk (<<*>>), in which case an <> + argument is used as the field width. Negative field widths + are not supported; if you attempt to specify a negative field + width, it is interpreted as a minus (<<->>) flag followed by a + positive field width. + + o <[prec]> + + an optional field; if present, it is introduced with `<<.>>' + (a period). This field gives the maximum number of + characters to print in a conversion; the minimum number of + digits of an integer to print, for conversions with <[type]> + <>, <>, <>, <>, <>, and <>; the maximum number of + significant digits, for the <> and <> conversions; + or the number of digits to print after the decimal + point, for <>, <>, and <> conversions. You can specify + the precision either directly as a decimal integer or + indirectly by using an asterisk (<<*>>), in which case + an <> argument is used as the precision. Supplying a negative + precision is equivalent to omitting the precision. + If only a period is specified the precision is zero. + If a precision appears with any other conversion <[type]> + than those listed here, the behavior is undefined. + + o <[size]> + + <>, <>, and <> are optional size characters which + override the default way that <> interprets the + data type of the corresponding argument. <> forces + the following <>, <>, <>, <>, <> or <> conversion + <[type]> to apply to a <> or <>. <> also + forces a following <> <[type]> to apply to + a pointer to a <>. Similarily, an + <> forces the following <>, <>, <>, <>, + <> or <> conversion <[type]> to apply to a <> or + <>. <> also forces a following <> <[type]> to + apply to a pointer to a <>. <> with <>, <> is + equivalent to <>, <> respectively. If an <> + or an <> appears with another conversion + specifier, the behavior is undefined. <> forces a + following <>, <>, <>, <> or <> conversion <[type]> to + apply to a <> argument. If <> appears with + any other conversion <[type]>, the behavior is undefined. + + o <[type]> + + <[type]> specifies what kind of conversion <> performs. + Here is a table of these: + + o+ + o % + prints the percent character (<<%>>) + + o c + prints <[arg]> as single character + + o C + prints wchar_t <[arg]> as single multibyte character + + o s + prints characters until precision is reached or a null terminator + is encountered; takes a string pointer + + o S + converts wchar_t characters to multibyte output characters until + precision is reached or a null wchar_t terminator + is encountered; takes a wchar_t pointer + + o d + prints a signed decimal integer; takes an <> (same as <>) + + o i + prints a signed decimal integer; takes an <> (same as <>) + + o o + prints a signed octal integer; takes an <> + + o u + prints an unsigned decimal integer; takes an <> + + o x + prints an unsigned hexadecimal integer (using <> as + digits beyond <<9>>); takes an <> + + o X + prints an unsigned hexadecimal integer (using <> as + digits beyond <<9>>); takes an <> + + o f + prints a signed value of the form <<[-]9999.9999>>; takes + a floating-point number + + o e + prints a signed value of the form <<[-]9.9999e[+|-]999>>; takes a + floating-point number + + o E + prints the same way as <>, but using <> to introduce the + exponent; takes a floating-point number + + o g + prints a signed value in either <> or <> form, based on given + value and precision---trailing zeros and the decimal point are + printed only if necessary; takes a floating-point number + + o G + prints the same way as <>, but using <> for the exponent if an + exponent is needed; takes a floating-point number + + o n + stores (in the same object) a count of the characters written; + takes a pointer to <> + + o p + prints a pointer in an implementation-defined format. + This implementation treats the pointer as an + <> (same as <>). + o- +O- + + +RETURNS +<> and <> return the number of bytes in the output string, +save that the concluding <> is not counted. +<> and <> return the number of characters transmitted. +If an error occurs, <> and <> return <> and +<> returns -1. No error returns occur for <>. + +PORTABILITY + The ANSI C standard specifies that implementations must + support at least formatted output of up to 509 characters. + +Supporting OS subroutines required: <>, <>, <>, +<>, <>, <>, <>. +*/ + +#include +#ifdef _HAVE_STDC +#include +#else +#include +#endif +#include +#include <_ansi.h> + +#ifndef _SMALL_PRINTF + #include "local.h" +#else + #ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #endif +#endif + + +#ifndef _SMALL_PRINTF + int + #ifdef _HAVE_STDC + _DEFUN (_sprintf_r, (ptr, str, fmt), struct _reent *ptr _AND char *str _AND _CONST char *fmt _DOTS) + #else + _sprintf_r (ptr, str, fmt, va_alist) + struct _reent *ptr; + char *str; + _CONST char *fmt; + va_dcl + #endif + { + int ret; + va_list ap; + FILE f; + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = INT_MAX; + f._file = -1; /* No file. */ + #ifdef _HAVE_STDC + va_start (ap, fmt); + #else + va_start (ap); + #endif + ret = _vfprintf_r (ptr, &f, fmt, ap); + va_end (ap); + *f._p = 0; + return (ret); + } +#endif + +#ifndef _REENT_ONLY +int +#ifdef _HAVE_STDC +_DEFUN (sprintf, (str, fmt), char *str _AND _CONST char *fmt _DOTS) +#else +sprintf (str, fmt, va_alist) + char *str; + _CONST char *fmt; + va_dcl +#endif +{ + int ret; + va_list ap; + FILE f; + + f._flags = __SWR | __SSTR; + f._bf._base = f._p = (unsigned char *) str; + f._bf._size = f._w = INT_MAX; + f._file = -1; /* No file. */ +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else + va_start (ap); +#endif + ret = _vfprintf_r (_REENT, &f, fmt, ap); + va_end (ap); + *f._p = 0; + return (ret); +} +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_vfprintf.c b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_vfprintf.c new file mode 100644 index 000000000..80ad4bab4 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/_SP_vfprintf.c @@ -0,0 +1,1774 @@ +/* +FUNCTION +<>, <>, <>---format argument list + +INDEX + vprintf +INDEX + vfprintf +INDEX + vsprintf +INDEX + vsnprintf + +ANSI_SYNOPSIS + #include + #include + int vprintf(const char *<[fmt]>, va_list <[list]>); + int vfprintf(FILE *<[fp]>, const char *<[fmt]>, va_list <[list]>); + int vsprintf(char *<[str]>, const char *<[fmt]>, va_list <[list]>); + int vasprintf(char **<[strp]>, const char *<[fmt]>, va_list <[list]>); + int vsnprintf(char *<[str]>, size_t <[size]>, const char *<[fmt]>, va_list <[list]>); + + int _vprintf_r(void *<[reent]>, const char *<[fmt]>, + va_list <[list]>); + int _vfprintf_r(void *<[reent]>, FILE *<[fp]>, const char *<[fmt]>, + va_list <[list]>); + int _vasprintf_r(void *<[reent]>, char **<[str]>, const char *<[fmt]>, + va_list <[list]>); + int _vsprintf_r(void *<[reent]>, char *<[str]>, const char *<[fmt]>, + va_list <[list]>); + int _vsnprintf_r(void *<[reent]>, char *<[str]>, size_t <[size]>, const char *<[fmt]>, + va_list <[list]>); + +TRAD_SYNOPSIS + #include + #include + int vprintf( <[fmt]>, <[list]>) + char *<[fmt]>; + va_list <[list]>; + + int vfprintf(<[fp]>, <[fmt]>, <[list]>) + FILE *<[fp]>; + char *<[fmt]>; + va_list <[list]>; + + int vasprintf(<[strp]>, <[fmt]>, <[list]>) + char **<[strp]>; + char *<[fmt]>; + va_list <[list]>; + + int vsprintf(<[str]>, <[fmt]>, <[list]>) + char *<[str]>; + char *<[fmt]>; + va_list <[list]>; + + int vsnprintf(<[str]>, <[size]>, <[fmt]>, <[list]>) + char *<[str]>; + size_t <[size]>; + char *<[fmt]>; + va_list <[list]>; + + int _vprintf_r(<[reent]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[fmt]>; + va_list <[list]>; + + int _vfprintf_r(<[reent]>, <[fp]>, <[fmt]>, <[list]>) + char *<[reent]>; + FILE *<[fp]>; + char *<[fmt]>; + va_list <[list]>; + + int _vasprintf_r(<[reent]>, <[strp]>, <[fmt]>, <[list]>) + char *<[reent]>; + char **<[strp]>; + char *<[fmt]>; + va_list <[list]>; + + int _vsprintf_r(<[reent]>, <[str]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[str]>; + char *<[fmt]>; + va_list <[list]>; + + int _vsnprintf_r(<[reent]>, <[str]>, <[size]>, <[fmt]>, <[list]>) + char *<[reent]>; + char *<[str]>; + size_t <[size]>; + char *<[fmt]>; + va_list <[list]>; + +DESCRIPTION +<>, <>, <>, <> and <> are +(respectively) variants of <>, <>, <>, <>, +and <>. They differ only in allowing their caller to pass the +variable argument list as a <> object (initialized by <>) +rather than directly accepting a variable number of arguments. + +RETURNS +The return values are consistent with the corresponding functions: +<>/<> returns the number of bytes in the output string, +save that the concluding <> is not counted. +<> and <> return the number of characters transmitted. +If an error occurs, <> and <> return <> and +<> returns -1. No error returns occur for <>. + +PORTABILITY +ANSI C requires all three functions. + +Supporting OS subroutines required: <>, <>, <>, +<>, <>, <>, <>. +*/ + +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if defined(LIBC_SCCS) && !defined(lint) +static char *sccsid = "from: @(#)vfprintf.c 5.50 (Berkeley) 12/16/92"; +#endif /* LIBC_SCCS and not lint */ + +/* + * Actual printf innards. + * + * This code is large and complicated... + */ + +#ifdef INTEGER_ONLY + #define VFPRINTF vfiprintf + #define _VFPRINTF_R _vfiprintf_r +#else + #define VFPRINTF vfprintf + #define _VFPRINTF_R _vfprintf_r + #ifndef NO_FLOATING_POINT + #define FLOATING_POINT + #endif +#endif + +#define _NO_LONGLONG +#if defined WANT_PRINTF_LONG_LONG && defined __GNUC__ +# undef _NO_LONGLONG +#endif + +#define _NO_POS_ARGS +#if defined WANT_IO_POS_ARGS +# undef _NO_POS_ARGS +#endif + +#include <_ansi.h> +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef _HAVE_STDC +#include +#else +#include +#endif + +#ifndef _SMALL_PRINTF + #include "local.h" + #include "fvwrite.h" +#else + #define MAXBUFLOC 80 +#endif + + #include "vfieeefp.h" + +/* Currently a test is made to see if long double processing is warranted. + This could be changed in the future should the _ldtoa_r code be + preferred over _dtoa_r. */ +#define _NO_LONGDBL +#if defined WANT_IO_LONG_DBL && (LDBL_MANT_DIG > DBL_MANT_DIG) +# undef _NO_LONGDBL +#endif + + +#ifndef _SMALL_PRINTF +/* + * Flush out all the vectors defined by the given uio, + * then reset it so that it can be reused. + */ +static int +__sprint(fp, uio) + FILE *fp; + register struct __suio *uio; +{ + register int err; + + if (uio->uio_resid == 0) { + uio->uio_iovcnt = 0; + return (0); + } + err = __sfvwrite(fp, uio); + uio->uio_resid = 0; + uio->uio_iovcnt = 0; + return (err); +} + +/* + * Helper function for `fprintf to unbuffered unix file': creates a + * temporary buffer. We only work on write-only files; this avoids + * worries about ungetc buffers and so forth. + */ +static int +__sbprintf(fp, fmt, ap) + register FILE *fp; + const char *fmt; + va_list ap; +{ + int ret; + FILE fake; + unsigned char buf[BUFSIZ]; + + /* copy the important variables */ + fake._flags = fp->_flags & ~__SNBF; + fake._file = fp->_file; + fake._cookie = fp->_cookie; + fake._write = fp->_write; + + /* set up the buffer */ + fake._bf._base = fake._p = buf; + fake._bf._size = fake._w = sizeof(buf); + fake._lbfsize = 0; /* not actually used, but Just In Case */ +#ifndef __SINGLE_THREAD__ + __lock_init_recursive (*(_LOCK_RECURSIVE_T *)&fake._lock); +#endif + + /* do the work, then copy any error status */ + ret = VFPRINTF(&fake, fmt, ap); + if (ret >= 0 && fflush(&fake)) + ret = EOF; + if (fake._flags & __SERR) + fp->_flags |= __SERR; + +#ifndef __SINGLE_THREAD__ + __lock_close_recursive (*(_LOCK_RECURSIVE_T *)&fake._lock); +#endif + return (ret); +} +#endif + + + +#ifdef FLOATING_POINT +#include +#include +#include "floatio.h" + +#if ((MAXEXP+MAXFRACT+1) > MB_LEN_MAX) +# define BUF (MAXEXP+MAXFRACT+1) /* + decimal point */ +#else +# define BUF MB_LEN_MAX +#endif + +#define DEFPREC 6 + +#ifdef _NO_LONGDBL +static char *cvt _PARAMS((struct _reent *, double, int, int, char *, int *, int, int *)); +#else +static char *cvt _PARAMS((struct _reent *, _LONG_DOUBLE, int, int, char *, int *, int, int *)); +extern int _ldcheck _PARAMS((_LONG_DOUBLE *)); +#endif + +static int exponent _PARAMS((char *, int, int)); + +#else /* no FLOATING_POINT */ + +#define BUF 40 + +#endif /* FLOATING_POINT */ + +#ifndef _NO_LONGLONG +#define quad_t long long +#define u_quad_t unsigned long long +#else +#define quad_t long +#define u_quad_t unsigned long +#endif + +typedef quad_t * quad_ptr_t; +typedef void * void_ptr_t; +typedef char * char_ptr_t; +typedef long * long_ptr_t; +typedef int * int_ptr_t; +typedef short * short_ptr_t; + +#ifndef _NO_POS_ARGS +#define MAX_POS_ARGS 32 + +union arg_val +{ + int val_int; + u_int val_u_int; + long val_long; + u_long val_u_long; + float val_float; + double val_double; + _LONG_DOUBLE val__LONG_DOUBLE; + int_ptr_t val_int_ptr_t; + short_ptr_t val_short_ptr_t; + long_ptr_t val_long_ptr_t; + char_ptr_t val_char_ptr_t; + quad_ptr_t val_quad_ptr_t; + void_ptr_t val_void_ptr_t; + quad_t val_quad_t; + u_quad_t val_u_quad_t; + wint_t val_wint_t; +}; + +static union arg_val *get_arg (struct _reent *data, int n, char *fmt, + va_list *ap, int *numargs, union arg_val *args, + int *arg_type, char **last_fmt); +#endif /* !_NO_POS_ARGS */ + +/* + * Macros for converting digits to letters and vice versa + */ +#define to_digit(c) ((c) - '0') +#define is_digit(c) ((unsigned)to_digit(c) <= 9) +#define to_char(n) ((n) + '0') + +/* + * Flags used during conversion. + */ +#define ALT 0x001 /* alternate form */ +#define HEXPREFIX 0x002 /* add 0x or 0X prefix */ +#define LADJUST 0x004 /* left adjustment */ +#define LONGDBL 0x008 /* long double */ +#define LONGINT 0x010 /* long integer */ +#ifndef _NO_LONGLONG +#define QUADINT 0x020 /* quad integer */ +#else /* ifdef _NO_LONGLONG, make QUADINT equivalent to LONGINT, so + that %lld behaves the same as %ld, not as %d, as expected if: + sizeof (long long) = sizeof long > sizeof int */ +#define QUADINT LONGINT +#endif +#define SHORTINT 0x040 /* short integer */ +#define ZEROPAD 0x080 /* zero (as opposed to blank) pad */ +#define FPT 0x100 /* Floating point number */ + + + int _EXFUN (_VFPRINTF_R, (struct _reent *, FILE *, _CONST char *, va_list)); + + int + _DEFUN (VFPRINTF, (fp, fmt0, ap), + FILE * fp _AND + _CONST char *fmt0 _AND + va_list ap) + { + int result; + _flockfile(fp); +#ifndef _SMALL_PRINTF + CHECK_INIT (fp); +#endif + result = _VFPRINTF_R (_REENT, fp, fmt0, ap); + _funlockfile(fp); + return result; + } + + + +int +_DEFUN (_VFPRINTF_R, (data, fp, fmt0, ap), + struct _reent *data _AND + FILE * fp _AND + _CONST char *fmt0 _AND + va_list ap) +{ + register char *fmt; /* format string */ + register int ch; /* character from fmt */ + register int n, m; /* handy integers (short term usage) */ + register char *cp; /* handy char pointer (short term usage) */ + register struct __siov *iovp;/* for PRINT macro */ + register int flags; /* flags as above */ + char *fmt_anchor; /* current format spec being processed */ + int N; /* arg number */ + int arg_index; /* index into args processed directly */ +#ifndef _NO_POS_ARGS + int numargs; /* number of varargs read */ + char *saved_fmt; /* saved fmt pointer */ + union arg_val args[MAX_POS_ARGS]; + int arg_type[MAX_POS_ARGS]; + int is_pos_arg; /* is current format positional? */ + int old_is_pos_arg; /* is current format positional? */ +#endif + int ret; /* return value accumulator */ + int width; /* width from format (%8d), or 0 */ + int prec; /* precision from format (%.3d), or -1 */ + char sign; /* sign prefix (' ', '+', '-', or \0) */ +#ifdef FLOATING_POINT +#ifdef _SMALL_PRINTF + char *decimal_point = "."; +#else + char *decimal_point = localeconv()->decimal_point; +#endif + char softsign; /* temporary negative sign for floats */ +#ifdef _NO_LONGDBL + union { int i; double d; } _double_ = {0}; + #define _fpvalue (_double_.d) +#else + union { int i; _LONG_DOUBLE ld; } _long_double_ = {0}; + #define _fpvalue (_long_double_.ld) + int tmp; +#endif + int expt; /* integer value of exponent */ + int expsize = 0; /* character count for expstr */ + int ndig; /* actual number of digits returned by cvt */ + char expstr[7]; /* buffer for exponent string */ +#endif + u_quad_t _uquad; /* integer arguments %[diouxX] */ + enum { OCT, DEC, HEX } base;/* base for [diouxX] conversion */ + int dprec; /* a copy of prec if [diouxX], 0 otherwise */ + int realsz; /* field size expanded by dprec */ + int size; /* size of converted field or string */ + char *xdigs = NULL; /* digits for [xX] conversion */ +#ifndef _SMALL_PRINTF + #define NIOV 8 + struct __suio uio; /* output information: summary */ + struct __siov iov[NIOV];/* ... and individual io vectors */ + char *malloc_buf = NULL;/* handy pointer for malloced buffers */ +#else + char malloc_buf [MAXBUFLOC]; /* local buffers */ +#endif + + char buf[BUF]; /* space for %c, %[diouxX], %[eEfgG] */ + char ox[2]; /* space for 0x hex-prefix */ +#ifdef MB_CAPABLE + wchar_t wc; + mbstate_t state; /* mbtowc calls from library must not change state */ +#endif + + + /* + * Choose PADSIZE to trade efficiency vs. size. If larger printf + * fields occur frequently, increase PADSIZE and make the initialisers + * below longer. + */ +#define PADSIZE 16 /* pad chunk size */ + static _CONST char blanks[PADSIZE] = + {' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '}; + static _CONST char zeroes[PADSIZE] = + {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0'}; + +#ifdef MB_CAPABLE + memset (&state, '\0', sizeof (state)); +#endif + +#ifndef _SMALL_PRINTF + /* + * BEWARE, these `goto error' on error, and PAD uses `n'. + */ + #define PRINT(ptr, len,f) { \ + iovp->iov_base = (ptr); \ + iovp->iov_len = (len); \ + uio.uio_resid += (len); \ + iovp++; \ + if (++uio.uio_iovcnt >= NIOV) { \ + if (__sprint(fp, &uio)) \ + goto error; \ + iovp = iov; \ + } \ + } + #define PAD(howmany, with,f) { \ + if ((n = (howmany)) > 0) { \ + while (n > PADSIZE) { \ + PRINT(with, PADSIZE,f); \ + n -= PADSIZE; \ + } \ + PRINT(with, n,f); \ + } \ + } + #define FLUSH() { \ + if (uio.uio_resid && __sprint(fp, &uio)) \ + goto error; \ + uio.uio_iovcnt = 0; \ + iovp = iov; \ + } +#else + //Macros for _SMALL_PRINTF + void _SMALL_PRINTF_puts(const char *ptr, int len, FILE *f); + #define PRINT(ptr, len, f) {_SMALL_PRINTF_puts(ptr,len,f);} + #define PAD(howmany, with, f) { \ + if ((n = (howmany)) > 0) { \ + while (n > PADSIZE) { \ + PRINT(with, PADSIZE,f); \ + n -= PADSIZE; \ + } \ + PRINT(with, n, f); \ + } \ + } + #define FLUSH() { ; } +#endif + + + /* Macros to support positional arguments */ +#ifndef _NO_POS_ARGS +#define GET_ARG(n, ap, type) \ + ( is_pos_arg \ + ? n < numargs \ + ? args[n].val_##type \ + : get_arg (data, n, fmt_anchor, &ap, &numargs, args, arg_type, &saved_fmt)->val_##type \ + : arg_index++ < numargs \ + ? args[n].val_##type \ + : numargs < MAX_POS_ARGS \ + ? args[numargs++].val_##type = va_arg(ap, type) \ + : va_arg(ap, type) \ + ) +#else +#define GET_ARG(n, ap, type) (va_arg(ap, type)) +#endif + + /* + * To extend shorts properly, we need both signed and unsigned + * argument extraction methods. + */ +#ifndef _NO_LONGLONG +#define SARG() \ + (flags&QUADINT ? GET_ARG(N, ap, quad_t) : \ + flags&LONGINT ? GET_ARG(N, ap, long) : \ + flags&SHORTINT ? (long)(short)GET_ARG(N, ap, int) : \ + (long)GET_ARG(N, ap, int)) +#define UARG() \ + (flags&QUADINT ? GET_ARG(N, ap, u_quad_t) : \ + flags&LONGINT ? GET_ARG(N, ap, u_long) : \ + flags&SHORTINT ? (u_long)(u_short)GET_ARG(N, ap, int) : \ + (u_long)GET_ARG(N, ap, u_int)) +#else +#define SARG() \ + (flags&LONGINT ? GET_ARG(N, ap, long) : \ + flags&SHORTINT ? (long)(short)GET_ARG(N, ap, int) : \ + (long)GET_ARG(N, ap, int)) +#define UARG() \ + (flags&LONGINT ? GET_ARG(N, ap, u_long) : \ + flags&SHORTINT ? (u_long)(u_short)GET_ARG(N, ap, int) : \ + (u_long)GET_ARG(N, ap, u_int)) +#endif + +#ifndef _SMALL_PRINTF + /* sorry, fprintf(read_only_file, "") returns EOF, not 0 */ + if (cantwrite(fp)) + return (EOF); + + /* optimise fprintf(stderr) (and other unbuffered Unix files) */ + if ((fp->_flags & (__SNBF|__SWR|__SRW)) == (__SNBF|__SWR) && + fp->_file >= 0) + return (__sbprintf(fp, fmt0, ap)); + + uio.uio_iov = iovp = iov; + uio.uio_resid = 0; + uio.uio_iovcnt = 0; +#endif + fmt = (char *)fmt0; + + ret = 0; + arg_index = 0; + +#ifndef _NO_POS_ARGS + saved_fmt = NULL; + arg_type[0] = -1; + numargs = 0; + is_pos_arg = 0; +#endif + + /* + * Scan the format for conversions (`%' character). + */ + for (;;) { + cp = fmt; +#ifdef MB_CAPABLE + while ((n = _mbtowc_r(data, &wc, fmt, MB_CUR_MAX, &state)) > 0) { + if (wc == '%') + break; + fmt += n; + } +#else + while (*fmt != '\0' && *fmt != '%') + fmt += 1; +#endif + if ((m = fmt - cp) != 0) { + PRINT(cp, m, fp); + ret += m; + } +#ifdef MB_CAPABLE + if (n <= 0) + goto done; +#else + if (*fmt == '\0') + goto done; +#endif + fmt_anchor = fmt; + fmt++; /* skip over '%' */ + + flags = 0; + dprec = 0; + width = 0; + prec = -1; + sign = '\0'; + N = arg_index; +#ifndef _NO_POS_ARGS + is_pos_arg = 0; +#endif + +rflag: ch = *fmt++; +reswitch: switch (ch) { + case ' ': + /* + * ``If the space and + flags both appear, the space + * flag will be ignored.'' + * -- ANSI X3J11 + */ + if (!sign) + sign = ' '; + goto rflag; + case '#': + flags |= ALT; + goto rflag; + case '*': + n = N; +#ifndef _NO_POS_ARGS + /* we must check for positional arg used for dynamic width */ + old_is_pos_arg = is_pos_arg; + is_pos_arg = 0; + if (is_digit(*fmt)) { + char *old_fmt = fmt; + + n = 0; + ch = *fmt++; + do { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); + + if (ch == '$') { + if (n <= MAX_POS_ARGS) { + n -= 1; + is_pos_arg = 1; + } + else + goto error; + } + else { + fmt = old_fmt; + goto rflag; + } + } +#endif /* !_NO_POS_ARGS */ + + /* + * ``A negative field width argument is taken as a + * - flag followed by a positive field width.'' + * -- ANSI X3J11 + * They don't exclude field widths read from args. + */ + width = GET_ARG(n, ap, int); +#ifndef _NO_POS_ARGS + is_pos_arg = old_is_pos_arg; +#endif + if (width >= 0) + goto rflag; + width = -width; + /* FALLTHROUGH */ + case '-': + flags |= LADJUST; + goto rflag; + case '+': + sign = '+'; + goto rflag; + case '.': + if ((ch = *fmt++) == '*') { + n = N; +#ifndef _NO_POS_ARGS + /* we must check for positional arg used for dynamic width */ + old_is_pos_arg = is_pos_arg; + is_pos_arg = 0; + if (is_digit(*fmt)) { + char *old_fmt = fmt; + + n = 0; + ch = *fmt++; + do { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); + + if (ch == '$') { + if (n <= MAX_POS_ARGS) { + n -= 1; + is_pos_arg = 1; + } + else + goto error; + } + else { + fmt = old_fmt; + goto rflag; + } + } +#endif /* !_NO_POS_ARGS */ + prec = GET_ARG(n, ap, int); +#ifndef _NO_POS_ARGS + is_pos_arg = old_is_pos_arg; +#endif + if (prec < 0) + prec = -1; + goto rflag; + } + n = 0; + while (is_digit(ch)) { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } + prec = n < 0 ? -1 : n; + goto reswitch; + case '0': + /* + * ``Note that 0 is taken as a flag, not as the + * beginning of a field width.'' + * -- ANSI X3J11 + */ + flags |= ZEROPAD; + goto rflag; + case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + n = 0; + do { + n = 10 * n + to_digit(ch); + ch = *fmt++; + } while (is_digit(ch)); +#ifndef _NO_POS_ARGS + if (ch == '$') { + if (n <= MAX_POS_ARGS) { + N = n - 1; + is_pos_arg = 1; + goto rflag; + } + else + goto error; + } +#endif /* !_NO_POS_ARGS */ + width = n; + goto reswitch; +#ifdef FLOATING_POINT + case 'L': + flags |= LONGDBL; + goto rflag; +#endif + case 'h': + flags |= SHORTINT; + goto rflag; + case 'l': + if (*fmt == 'l') { + fmt++; + flags |= QUADINT; + } else { + flags |= LONGINT; + } + goto rflag; + case 'q': + flags |= QUADINT; + goto rflag; + case 'c': + case 'C': + cp = buf; + if (ch == 'C' || (flags & LONGINT)) { + mbstate_t ps; + + memset((void *)&ps, '\0', sizeof(mbstate_t)); + if ((size = (int)_wcrtomb_r(data, cp, + (wchar_t)GET_ARG(N, ap, wint_t), + &ps)) == -1) + goto error; + } + else { + *cp = GET_ARG(N, ap, int); + size = 1; + } + sign = '\0'; + break; + case 'D': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'd': + case 'i': + _uquad = SARG(); +#ifndef _NO_LONGLONG + if ((quad_t)_uquad < 0) +#else + if ((long) _uquad < 0) +#endif + { + + _uquad = -_uquad; + sign = '-'; + } + base = DEC; + goto number; +#ifdef FLOATING_POINT + case 'e': + case 'E': + case 'f': + case 'g': + case 'G': + if (prec == -1) { + prec = DEFPREC; + } else if ((ch == 'g' || ch == 'G') && prec == 0) { + prec = 1; + } + +#ifdef _NO_LONGDBL + if (flags & LONGDBL) { + _fpvalue = (double) GET_ARG(N, ap, _LONG_DOUBLE); + } else { + _fpvalue = GET_ARG(N, ap, double); + } + + /* do this before tricky precision changes */ + if (isinf(_fpvalue)) { + if (_fpvalue < 0) + sign = '-'; + cp = "Inf"; + size = 3; + break; + } + if (isnan(_fpvalue)) { + cp = "NaN"; + size = 3; + break; + } + +#else /* !_NO_LONGDBL */ + + if (flags & LONGDBL) { + _fpvalue = GET_ARG(N, ap, _LONG_DOUBLE); + } else { + _fpvalue = (_LONG_DOUBLE)GET_ARG(N, ap, double); + } + + /* do this before tricky precision changes */ + tmp = _ldcheck (&_fpvalue); + if (tmp == 2) { + if (_fpvalue < 0) + sign = '-'; + cp = "Inf"; + size = 3; + break; + } + if (tmp == 1) { + cp = "NaN"; + size = 3; + break; + } +#endif /* !_NO_LONGDBL */ + + flags |= FPT; + + cp = cvt(data, _fpvalue, prec, flags, &softsign, + &expt, ch, &ndig); + + if (ch == 'g' || ch == 'G') { + if (expt <= -4 || expt > prec) + ch = (ch == 'g') ? 'e' : 'E'; + else + ch = 'g'; + } + if (ch <= 'e') { /* 'e' or 'E' fmt */ + --expt; + expsize = exponent(expstr, expt, ch); + size = expsize + ndig; + if (ndig > 1 || flags & ALT) + ++size; + } else if (ch == 'f') { /* f fmt */ + if (expt > 0) { + size = expt; + if (prec || flags & ALT) + size += prec + 1; + } else /* "0.X" */ + size = (prec || flags & ALT) + ? prec + 2 + : 1; + } else if (expt >= ndig) { /* fixed g fmt */ + size = expt; + if (flags & ALT) + ++size; + } else + size = ndig + (expt > 0 ? + 1 : 2 - expt); + + if (softsign) + sign = '-'; + break; +#endif /* FLOATING_POINT */ + case 'n': +#ifndef _NO_LONGLONG + if (flags & QUADINT) + *GET_ARG(N, ap, quad_ptr_t) = ret; + else +#endif + if (flags & LONGINT) + *GET_ARG(N, ap, long_ptr_t) = ret; + else if (flags & SHORTINT) + *GET_ARG(N, ap, short_ptr_t) = ret; + else + *GET_ARG(N, ap, int_ptr_t) = ret; + continue; /* no output */ + case 'O': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'o': + _uquad = UARG(); + base = OCT; + goto nosign; + case 'p': + /* + * ``The argument shall be a pointer to void. The + * value of the pointer is converted to a sequence + * of printable characters, in an implementation- + * defined manner.'' + * -- ANSI X3J11 + */ + /* NOSTRICT */ + _uquad = (u_long)(unsigned _POINTER_INT)GET_ARG(N, ap, void_ptr_t); + base = HEX; + xdigs = "0123456789abcdef"; + flags |= HEXPREFIX; + ch = 'x'; + goto nosign; + case 's': + case 'S': + sign = '\0'; + if ((cp = GET_ARG(N, ap, char_ptr_t)) == NULL) { + cp = "(null)"; + size = 6; + } + else if (ch == 'S' || (flags & LONGINT)) { + mbstate_t ps; + _CONST wchar_t *wcp; + + wcp = (_CONST wchar_t *)cp; + size = m = 0; + memset((void *)&ps, '\0', sizeof(mbstate_t)); + + /* Count number of bytes needed for multibyte + string that will be produced from widechar + string. */ + if (prec >= 0) { + while (1) { + if (wcp[m] == L'\0') + break; + if ((n = (int)_wcrtomb_r(data, + buf, wcp[m], &ps)) == -1) + goto error; + if (n + size > prec) + break; + m += 1; + size += n; + if (size == prec) + break; + } + } + else { + if ((size = (int)_wcsrtombs_r(data, + NULL, &wcp, 0, &ps)) == -1) + goto error; + wcp = (_CONST wchar_t *)cp; + } + + if (size == 0) + break; + + #ifndef _SMALL_PRINTF + if ((malloc_buf = + (char *)_malloc_r(data, size + 1)) == NULL) + goto error; + #endif + + /* Convert widechar string to multibyte string. */ + memset((void *)&ps, '\0', sizeof(mbstate_t)); + if (_wcsrtombs_r(data, malloc_buf, &wcp, size, &ps) != size) + goto error; + cp = malloc_buf; + cp[size] = '\0'; + } + else if (prec >= 0) { + /* + * can't use strlen; can only look for the + * NUL in the first `prec' characters, and + * strlen() will go further. + */ + char *p = memchr(cp, 0, prec); + + if (p != NULL) { + size = p - cp; + if (size > prec) + size = prec; + } else + size = prec; + } else + size = strlen(cp); + + break; + case 'U': + flags |= LONGINT; + /*FALLTHROUGH*/ + case 'u': + _uquad = UARG(); + base = DEC; + goto nosign; + case 'X': + xdigs = "0123456789ABCDEF"; + goto hex; + case 'x': + xdigs = "0123456789abcdef"; +hex: _uquad = UARG(); + base = HEX; + /* leading 0x/X only if non-zero */ + if (flags & ALT && _uquad != 0) + flags |= HEXPREFIX; + + /* unsigned conversions */ +nosign: sign = '\0'; + /* + * ``... diouXx conversions ... if a precision is + * specified, the 0 flag will be ignored.'' + * -- ANSI X3J11 + */ +number: if ((dprec = prec) >= 0) + flags &= ~ZEROPAD; + + /* + * ``The result of converting a zero value with an + * explicit precision of zero is no characters.'' + * -- ANSI X3J11 + */ + cp = buf + BUF; + if (_uquad != 0 || prec != 0) { + /* + * Unsigned mod is hard, and unsigned mod + * by a constant is easier than that by + * a variable; hence this switch. + */ + switch (base) { + case OCT: + do { + *--cp = to_char(_uquad & 7); + _uquad >>= 3; + } while (_uquad); + /* handle octal leading 0 */ + if (flags & ALT && *cp != '0') + *--cp = '0'; + break; + + case DEC: + /* many numbers are 1 digit */ + while (_uquad >= 10) { + *--cp = to_char(_uquad % 10); + _uquad /= 10; + } + *--cp = to_char(_uquad); + break; + + case HEX: + do { + *--cp = xdigs[_uquad & 15]; + _uquad >>= 4; + } while (_uquad); + break; + + default: + cp = "bug in vfprintf: bad base"; + size = strlen(cp); + goto skipsize; + } + } + /* + * ...result is to be converted to an 'alternate form'. + * For o conversion, it increases the precision to force + * the first digit of the result to be a zero." + * -- ANSI X3J11 + * + * To demonstrate this case, compile and run: + * printf ("%#.0o",0); + */ + else if (base == OCT && (flags & ALT)) + *--cp = '0'; + + size = buf + BUF - cp; + skipsize: + break; + default: /* "%?" prints ?, unless ? is NUL */ + if (ch == '\0') + goto done; + /* pretend it was %c with argument ch */ + cp = buf; + *cp = ch; + size = 1; + sign = '\0'; + break; + } + + /* + * All reasonable formats wind up here. At this point, `cp' + * points to a string which (if not flags&LADJUST) should be + * padded out to `width' places. If flags&ZEROPAD, it should + * first be prefixed by any sign or other prefix; otherwise, + * it should be blank padded before the prefix is emitted. + * After any left-hand padding and prefixing, emit zeroes + * required by a decimal [diouxX] precision, then print the + * string proper, then emit zeroes required by any leftover + * floating precision; finally, if LADJUST, pad with blanks. + * + * Compute actual size, so we know how much to pad. + * size excludes decimal prec; realsz includes it. + */ + realsz = dprec > size ? dprec : size; + if (sign) + realsz++; + else if (flags & HEXPREFIX) + realsz+= 2; + + /* right-adjusting blank padding */ + if ((flags & (LADJUST|ZEROPAD)) == 0) + PAD(width - realsz, blanks, fp); + + /* prefix */ + if (sign) { + PRINT(&sign, 1, fp); + } else if (flags & HEXPREFIX) { + ox[0] = '0'; + ox[1] = ch; + PRINT(ox, 2 ,fp); + } + + /* right-adjusting zero padding */ + if ((flags & (LADJUST|ZEROPAD)) == ZEROPAD) + PAD(width - realsz, zeroes, fp); + + /* leading zeroes from decimal precision */ + PAD(dprec - size, zeroes, fp); + + /* the string or number proper */ +#ifdef FLOATING_POINT + if ((flags & FPT) == 0) { + PRINT(cp, size, fp); + } else { /* glue together f_p fragments */ + if (ch >= 'f') { /* 'f' or 'g' */ + if (_fpvalue == 0) { + /* kludge for __dtoa irregularity */ + PRINT("0", 1, fp); + if (expt < ndig || (flags & ALT) != 0) { + PRINT(decimal_point, 1, fp); + PAD(ndig - 1, zeroes, fp); + } + } else if (expt <= 0) { + PRINT("0", 1, fp); + if(expt || ndig) { + PRINT(decimal_point, 1, fp); + PAD(-expt, zeroes, fp); + PRINT(cp, ndig, fp); + } + } else if (expt >= ndig) { + PRINT(cp, ndig, fp); + PAD(expt - ndig, zeroes, fp); + if (flags & ALT) + PRINT(".", 1, fp); + } else { + PRINT(cp, expt, fp); + cp += expt; + PRINT(".", 1, fp); + PRINT(cp, ndig-expt, fp); + } + } else { /* 'e' or 'E' */ + if (ndig > 1 || flags & ALT) { + ox[0] = *cp++; + ox[1] = '.'; + PRINT(ox, 2, fp); + if (_fpvalue) { + PRINT(cp, ndig-1, fp); + } else /* 0.[0..] */ + /* __dtoa irregularity */ + PAD(ndig - 1, zeroes, fp); + } else /* XeYYY */ + PRINT(cp, 1, fp); + PRINT(expstr, expsize, fp); + } + } +#else + PRINT(cp, size, fp); +#endif + /* left-adjusting padding (always blank) */ + if (flags & LADJUST) + PAD(width - realsz, blanks, fp); + + /* finally, adjust ret */ + ret += width > realsz ? width : realsz; + + FLUSH(); /* copy out the I/O vectors */ + +#ifndef _SMALL_PRINTF + if (malloc_buf != NULL) { + free(malloc_buf); + malloc_buf = NULL; + } +#endif + } +done: + FLUSH(); +error: + +#ifndef _SMALL_PRINTF + if (malloc_buf != NULL) + free(malloc_buf); + return (__sferror(fp) ? EOF : ret); +#else + return ret; +#endif + /* NOTREACHED */ +} + +#ifdef FLOATING_POINT + +#ifdef _NO_LONGDBL +extern char *_dtoa_r _PARAMS((struct _reent *, double, int, + int, int *, int *, char **)); +#else +extern char *_ldtoa_r _PARAMS((struct _reent *, _LONG_DOUBLE, int, + int, int *, int *, char **)); +#undef word0 +#define word0(x) ldword0(x) +#endif + +static char * +cvt(data, value, ndigits, flags, sign, decpt, ch, length) + struct _reent *data; +#ifdef _NO_LONGDBL + double value; +#else + _LONG_DOUBLE value; +#endif + int ndigits, flags, *decpt, ch, *length; + char *sign; +{ + int mode, dsgn; + char *digits, *bp, *rve; +#ifdef _NO_LONGDBL + union double_union tmp; +#else + struct ldieee *ldptr; +#endif + + if (ch == 'f') { + mode = 3; /* ndigits after the decimal point */ + } else { + /* To obtain ndigits after the decimal point for the 'e' + * and 'E' formats, round to ndigits + 1 significant + * figures. + */ + if (ch == 'e' || ch == 'E') { + ndigits++; + } + mode = 2; /* ndigits significant digits */ + } + +#ifdef _NO_LONGDBL + tmp.d = value; + + if (word0(tmp) & Sign_bit) { /* this will check for < 0 and -0.0 */ + value = -value; + *sign = '-'; + } else + *sign = '\000'; + + digits = _dtoa_r(data, value, mode, ndigits, decpt, &dsgn, &rve); +#else /* !_NO_LONGDBL */ + ldptr = (struct ldieee *)&value; + if (ldptr->sign) { /* this will check for < 0 and -0.0 */ + value = -value; + *sign = '-'; + } else + *sign = '\000'; + + digits = _ldtoa_r(data, value, mode, ndigits, decpt, &dsgn, &rve); +#endif /* !_NO_LONGDBL */ + + if ((ch != 'g' && ch != 'G') || flags & ALT) { /* Print trailing zeros */ + bp = digits + ndigits; + if (ch == 'f') { + if (*digits == '0' && value) + *decpt = -ndigits + 1; + bp += *decpt; + } + if (value == 0) /* kludge for __dtoa irregularity */ + rve = bp; + while (rve < bp) + *rve++ = '0'; + } + *length = rve - digits; + return (digits); +} + +static int +exponent(p0, exp, fmtch) + char *p0; + int exp, fmtch; +{ + register char *p, *t; + char expbuf[40]; + + p = p0; + *p++ = fmtch; + if (exp < 0) { + exp = -exp; + *p++ = '-'; + } + else + *p++ = '+'; + t = expbuf + 40; + if (exp > 9) { + do { + *--t = to_char(exp % 10); + } while ((exp /= 10) > 9); + *--t = to_char(exp); + for (; t < expbuf + 40; *p++ = *t++); + } + else { + *p++ = '0'; + *p++ = to_char(exp); + } + return (p - p0); +} +#endif /* FLOATING_POINT */ + + +#ifndef _NO_POS_ARGS + +/* Positional argument support. + Written by Jeff Johnston + + Copyright (c) 2002 Red Hat Incorporated. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + The name of Red Hat Incorporated may not be used to endorse + or promote products derived from this software without specific + prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + +typedef enum { + ZERO, /* '0' */ + DIGIT, /* '1-9' */ + DOLLAR, /* '$' */ + MODFR, /* spec modifier */ + SPEC, /* format specifier */ + DOT, /* '.' */ + STAR, /* '*' */ + FLAG, /* format flag */ + OTHER, /* all other chars */ + MAX_CH_CLASS /* place-holder */ +} CH_CLASS; + +typedef enum { + START, /* start */ + SFLAG, /* seen a flag */ + WDIG, /* seen digits in width area */ + WIDTH, /* processed width */ + SMOD, /* seen spec modifier */ + SDOT, /* seen dot */ + VARW, /* have variable width specifier */ + VARP, /* have variable precision specifier */ + PREC, /* processed precision */ + VWDIG, /* have digits in variable width specification */ + VPDIG, /* have digits in variable precision specification */ + DONE, /* done */ + MAX_STATE, /* place-holder */ +} STATE; + +typedef enum { + NOOP, /* do nothing */ + NUMBER, /* build a number from digits */ + SKIPNUM, /* skip over digits */ + GETMOD, /* get and process format modifier */ + GETARG, /* get and process argument */ + GETPW, /* get variable precision or width */ + GETPWB, /* get variable precision or width and pushback fmt char */ + GETPOS, /* get positional parameter value */ + PWPOS, /* get positional parameter value for variable width or precision */ +} ACTION; + +const static CH_CLASS chclass[256] = { + /* 00-07 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 08-0f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 10-17 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 18-1f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 20-27 */ FLAG, OTHER, OTHER, FLAG, DOLLAR, OTHER, OTHER, OTHER, + /* 28-2f */ OTHER, OTHER, STAR, FLAG, OTHER, FLAG, DOT, OTHER, + /* 30-37 */ ZERO, DIGIT, DIGIT, DIGIT, DIGIT, DIGIT, DIGIT, DIGIT, + /* 38-3f */ DIGIT, DIGIT, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 40-47 */ OTHER, OTHER, OTHER, SPEC, SPEC, SPEC, OTHER, SPEC, + /* 48-4f */ OTHER, OTHER, OTHER, OTHER, MODFR, OTHER, OTHER, SPEC, + /* 50-57 */ OTHER, OTHER, OTHER, SPEC, OTHER, SPEC, OTHER, SPEC, + /* 58-5f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 60-67 */ OTHER, OTHER, OTHER, SPEC, SPEC, SPEC, SPEC, SPEC, + /* 68-6f */ MODFR, SPEC, OTHER, OTHER, MODFR, OTHER, OTHER, SPEC, + /* 70-77 */ SPEC, MODFR, OTHER, SPEC, OTHER, SPEC, OTHER, OTHER, + /* 78-7f */ SPEC, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 80-87 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 88-8f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 90-97 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* 98-9f */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* a0-a7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* a8-af */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* b0-b7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* b8-bf */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* c0-c7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* c8-cf */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* d0-d7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* d8-df */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* e0-e7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* e8-ef */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* f0-f7 */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, + /* f8-ff */ OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, OTHER, +}; + +const static STATE state_table[MAX_STATE][MAX_CH_CLASS] = { + /* '0' '1-9' '$' MODFR SPEC '.' '*' FLAG OTHER */ + /* START */ { SFLAG, WDIG, DONE, SMOD, DONE, SDOT, VARW, SFLAG, DONE }, + /* SFLAG */ { SFLAG, WDIG, DONE, SMOD, DONE, SDOT, VARW, SFLAG, DONE }, + /* WDIG */ { DONE, DONE, WIDTH, SMOD, DONE, SDOT, DONE, DONE, DONE }, + /* WIDTH */ { DONE, DONE, DONE, SMOD, DONE, SDOT, DONE, DONE, DONE }, + /* SMOD */ { DONE, DONE, DONE, DONE, DONE, DONE, DONE, DONE, DONE }, + /* SDOT */ { SDOT, PREC, DONE, SMOD, DONE, DONE, VARP, DONE, DONE }, + /* VARW */ { DONE, VWDIG, DONE, SMOD, DONE, SDOT, DONE, DONE, DONE }, + /* VARP */ { DONE, VPDIG, DONE, SMOD, DONE, DONE, DONE, DONE, DONE }, + /* PREC */ { DONE, DONE, DONE, SMOD, DONE, DONE, DONE, DONE, DONE }, + /* VWDIG */ { DONE, DONE, WIDTH, DONE, DONE, DONE, DONE, DONE, DONE }, + /* VPDIG */ { DONE, DONE, PREC, DONE, DONE, DONE, DONE, DONE, DONE }, +}; + +const static ACTION action_table[MAX_STATE][MAX_CH_CLASS] = { + /* '0' '1-9' '$' MODFR SPEC '.' '*' FLAG OTHER */ + /* START */ { NOOP, NUMBER, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* SFLAG */ { NOOP, NUMBER, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* WDIG */ { NOOP, NOOP, GETPOS, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* WIDTH */ { NOOP, NOOP, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* SMOD */ { NOOP, NOOP, NOOP, NOOP, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* SDOT */ { NOOP, SKIPNUM, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* VARW */ { NOOP, NUMBER, NOOP, GETPW, GETPWB, GETPW, NOOP, NOOP, NOOP }, + /* VARP */ { NOOP, NUMBER, NOOP, GETPW, GETPWB, NOOP, NOOP, NOOP, NOOP }, + /* PREC */ { NOOP, NOOP, NOOP, GETMOD, GETARG, NOOP, NOOP, NOOP, NOOP }, + /* VWDIG */ { NOOP, NOOP, PWPOS, NOOP, NOOP, NOOP, NOOP, NOOP, NOOP }, + /* VPDIG */ { NOOP, NOOP, PWPOS, NOOP, NOOP, NOOP, NOOP, NOOP, NOOP }, +}; + +/* function to get positional parameter N where n = N - 1 */ +static union arg_val * +get_arg (struct _reent *data, int n, char *fmt, va_list *ap, + int *numargs_p, union arg_val *args, + int *arg_type, char **last_fmt) +{ + int ch; + int number, flags; + int spec_type; + int numargs = *numargs_p; + CH_CLASS chtype; + STATE state, next_state; + ACTION action; + int pos, last_arg; + int max_pos_arg = n; + enum types { INT, LONG_INT, SHORT_INT, QUAD_INT, CHAR, CHAR_PTR, DOUBLE, LONG_DOUBLE, WIDE_CHAR }; +#ifdef MB_CAPABLE + wchar_t wc; + mbstate_t wc_state; + int nbytes; +#endif + + /* if this isn't the first call, pick up where we left off last time */ + if (*last_fmt != NULL) + fmt = *last_fmt; + +#ifdef MB_CAPABLE + memset (&wc_state, '\0', sizeof (wc_state)); +#endif + + /* we need to process either to end of fmt string or until we have actually + read the desired parameter from the vararg list. */ + while (*fmt && n >= numargs) + { +#ifdef MB_CAPABLE + while ((nbytes = _mbtowc_r(data, &wc, fmt, MB_CUR_MAX, &wc_state)) > 0) + { + fmt += nbytes; + if (wc == '%') + break; + } + + if (nbytes <= 0) + break; +#else + while (*fmt != '\0' && *fmt != '%') + fmt += 1; + + if (*fmt == '\0') + break; +#endif + state = START; + flags = 0; + pos = -1; + number = 0; + spec_type = INT; + + /* Use state/action table to process format specifiers. We ignore invalid + formats and we are only interested in information that tells us how to + read the vararg list. */ + while (state != DONE) + { + ch = *fmt++; + chtype = chclass[ch]; + next_state = state_table[state][chtype]; + action = action_table[state][chtype]; + state = next_state; + + switch (action) + { + case GETMOD: /* we have format modifier */ + switch (ch) + { + case 'h': + flags |= SHORTINT; + break; + case 'L': + flags |= LONGDBL; + break; + case 'q': + flags |= QUADINT; + break; + case 'l': + default: + if (*fmt == 'l') + { + flags |= QUADINT; + ++fmt; + } + else + flags |= LONGINT; + break; + } + break; + case GETARG: /* we have format specifier */ + { + numargs &= (MAX_POS_ARGS - 1); + /* process the specifier and translate it to a type to fetch from varargs */ + switch (ch) + { + case 'd': + case 'i': + case 'o': + case 'x': + case 'X': + case 'u': + if (flags & LONGINT) + spec_type = LONG_INT; + else if (flags & SHORTINT) + spec_type = SHORT_INT; +#ifndef _NO_LONGLONG + else if (flags & QUADINT) + spec_type = QUAD_INT; +#endif + else + spec_type = INT; + break; + case 'D': + case 'U': + case 'O': + spec_type = LONG_INT; + break; + case 'f': + case 'g': + case 'G': + case 'E': + case 'e': +#ifndef _NO_LONGDBL + if (flags & LONGDBL) + spec_type = LONG_DOUBLE; + else +#endif + spec_type = DOUBLE; + break; + case 's': + case 'S': + case 'p': + spec_type = CHAR_PTR; + break; + case 'c': + spec_type = CHAR; + break; + case 'C': + spec_type = WIDE_CHAR; + break; + } + + /* if we have a positional parameter, just store the type, otherwise + fetch the parameter from the vararg list */ + if (pos != -1) + arg_type[pos] = spec_type; + else + { + switch (spec_type) + { + case LONG_INT: + args[numargs++].val_long = va_arg(*ap, long); + break; + case QUAD_INT: + args[numargs++].val_quad_t = va_arg(*ap, quad_t); + break; + case WIDE_CHAR: + args[numargs++].val_wint_t = va_arg(*ap, wint_t); + break; + case CHAR: + case SHORT_INT: + case INT: + args[numargs++].val_int = va_arg(*ap, int); + break; + case CHAR_PTR: + args[numargs++].val_char_ptr_t = va_arg(*ap, char *); + break; + case DOUBLE: + args[numargs++].val_double = va_arg(*ap, double); + break; + case LONG_DOUBLE: + args[numargs++].val__LONG_DOUBLE = va_arg(*ap, _LONG_DOUBLE); + break; + } + } + } + break; + case GETPOS: /* we have positional specifier */ + if (arg_type[0] == -1) + memset (arg_type, 0, sizeof(int) * MAX_POS_ARGS); + pos = number - 1; + max_pos_arg = (max_pos_arg > pos ? max_pos_arg : pos); + break; + case PWPOS: /* we have positional specifier for width or precision */ + if (arg_type[0] == -1) + memset (arg_type, 0, sizeof(int) * MAX_POS_ARGS); + number -= 1; + arg_type[number] = INT; + max_pos_arg = (max_pos_arg > number ? max_pos_arg : number); + break; + case GETPWB: /* we require format pushback */ + --fmt; + /* fallthrough */ + case GETPW: /* we have a variable precision or width to acquire */ + args[numargs++].val_int = va_arg(*ap, int); + break; + case NUMBER: /* we have a number to process */ + number = (ch - '0'); + while ((ch = *fmt) != '\0' && is_digit(ch)) + { + number = number * 10 + (ch - '0'); + ++fmt; + } + break; + case SKIPNUM: /* we have a number to skip */ + while ((ch = *fmt) != '\0' && is_digit(ch)) + ++fmt; + break; + case NOOP: + default: + break; /* do nothing */ + } + } + } + + /* process all arguments up to at least the one we are looking for and if we + have seen the end of the string, then process up to the max argument needed */ + if (*fmt == '\0') + last_arg = max_pos_arg; + else + last_arg = n; + + while (numargs <= last_arg) + { + switch (arg_type[numargs]) + { + case LONG_INT: + args[numargs++].val_long = va_arg(*ap, long); + break; + case QUAD_INT: + args[numargs++].val_quad_t = va_arg(*ap, quad_t); + break; + case CHAR_PTR: + args[numargs++].val_char_ptr_t = va_arg(*ap, char *); + break; + case DOUBLE: + args[numargs++].val_double = va_arg(*ap, double); + break; + case LONG_DOUBLE: + args[numargs++].val__LONG_DOUBLE = va_arg(*ap, _LONG_DOUBLE); + break; + case WIDE_CHAR: + args[numargs++].val_wint_t = va_arg(*ap, wint_t); + break; + case INT: + case SHORT_INT: + case CHAR: + default: + args[numargs++].val_int = va_arg(*ap, int); + break; + } + } + + /* alter the global numargs value and keep a reference to the last bit of the fmt + string we processed here because the caller will continue processing where we started */ + *numargs_p = numargs; + *last_fmt = fmt; + return &args[n]; +} +#endif /* !_NO_POS_ARGS */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/small_printf/vfieeefp.h b/cpu/stm32w108/hal/micro/cortexm3/small_printf/vfieeefp.h new file mode 100644 index 000000000..1b240fcde --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/small_printf/vfieeefp.h @@ -0,0 +1,284 @@ +/**************************************************************** + * + * The author of this software is David M. Gay. + * + * Copyright (c) 1991 by AT&T. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose without fee is hereby granted, provided that this entire notice + * is included in all copies of any software which is or includes a copy + * or modification of this software and in all copies of the supporting + * documentation for such software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY + * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + * + ***************************************************************/ + +/* Please send bug reports to + David M. Gay + AT&T Bell Laboratories, Room 2C-463 + 600 Mountain Avenue + Murray Hill, NJ 07974-2070 + U.S.A. + dmg@research.att.com or research!dmg + */ + +/* This header file is a modification of mprec.h that only contains floating + point union code. */ + +#include +#include +#include +#include +#include + +#ifdef __IEEE_LITTLE_ENDIAN +#define IEEE_8087 +#endif + +#ifdef __IEEE_BIG_ENDIAN +#define IEEE_MC68k +#endif + +#ifdef __Z8000__ +#define Just_16 +#endif + +#ifdef Unsigned_Shifts +#define Sign_Extend(a,b) if (b < 0) a |= (__uint32_t)0xffff0000; +#else +#define Sign_Extend(a,b) /*no-op*/ +#endif + +#if defined(IEEE_8087) + defined(IEEE_MC68k) + defined(VAX) + defined(IBM) != 1 +Exactly one of IEEE_8087, IEEE_MC68k, VAX, or IBM should be defined. +#endif + +#ifdef WANT_IO_LONG_DBL +/* If we are going to examine or modify specific bits in a long double using + the lword0 or lwordx macros, then we must wrap the long double inside + a union. This is necessary to avoid undefined behavior according to + the ANSI C spec. */ + +#ifdef IEEE_8087 +#if LDBL_MANT_DIG == 24 +struct ldieee +{ + unsigned manh:23; + unsigned exp:8; + unsigned sign:1; +}; +#elif LDBL_MANT_DIG == 53 +struct ldieee +{ + unsigned manl:20; + unsigned manh:32; + unsigned exp:11; + unsigned sign:1; +}; +#elif LDBL_MANT_DIG == 64 +struct ldieee +{ + unsigned manl:32; + unsigned manh:32; + unsigned exp:15; + unsigned sign:1; +}; +#elif LDBL_MANT_DIG > 64 +struct ldieee +{ + unsigned manl3:16; + unsigned manl2:32; + unsigned manl:32; + unsigned manh:32; + unsigned exp:15; + unsigned sign:1; +}; +#endif /* LDBL_MANT_DIG */ +#else /* !IEEE_8087 */ +#if LDBL_MANT_DIG == 24 +struct ldieee +{ + unsigned sign:1; + unsigned exp:8; + unsigned manh:23; +}; +#elif LDBL_MANT_DIG == 53 +struct ldieee +{ + unsigned sign:1; + unsigned exp:11; + unsigned manh:32; + unsigned manl:20; +}; +#elif LDBL_MANT_DIG == 64 +struct ldieee +{ + unsigned sign:1; + unsigned exp:15; + unsigned manh:32; + unsigned manl:32; +}; +#elif LDBL_MANT_DIG > 64 +struct ldieee +{ + unsigned sign:1; + unsigned exp:15; + unsigned manh:32; + unsigned manl:32; + unsigned manl2:32; + unsigned manl3;16; +}; +#endif /* LDBL_MANT_DIG */ +#endif /* !IEEE_8087 */ +#endif /* WANT_IO_LONG_DBL */ + +/* If we are going to examine or modify specific bits in a double using + the word0 and/or word1 macros, then we must wrap the double inside + a union. This is necessary to avoid undefined behavior according to + the ANSI C spec. */ +union double_union +{ + double d; + __uint32_t i[2]; +}; + +#ifdef IEEE_8087 +#define word0(x) (x.i[1]) +#define word1(x) (x.i[0]) +#else +#define word0(x) (x.i[0]) +#define word1(x) (x.i[1]) +#endif + +/* #define P DBL_MANT_DIG */ +/* Ten_pmax = floor(P*log(2)/log(5)) */ +/* Bletch = (highest power of 2 < DBL_MAX_10_EXP) / 16 */ +/* Quick_max = floor((P-1)*log(FLT_RADIX)/log(10) - 1) */ +/* Int_max = floor(P*log(FLT_RADIX)/log(10) - 1) */ + +#if defined(IEEE_8087) + defined(IEEE_MC68k) +#if defined (_DOUBLE_IS_32BITS) +#define Exp_shift 23 +#define Exp_shift1 23 +#define Exp_msk1 ((__uint32_t)0x00800000L) +#define Exp_msk11 ((__uint32_t)0x00800000L) +#define Exp_mask ((__uint32_t)0x7f800000L) +#define P 24 +#define Bias 127 +#if 0 +#define IEEE_Arith /* it is, but the code doesn't handle IEEE singles yet */ +#endif +#define Emin (-126) +#define Exp_1 ((__uint32_t)0x3f800000L) +#define Exp_11 ((__uint32_t)0x3f800000L) +#define Ebits 8 +#define Frac_mask ((__uint32_t)0x007fffffL) +#define Frac_mask1 ((__uint32_t)0x007fffffL) +#define Ten_pmax 10 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Ten_pmax 10 +#define Bletch 2 +#define Bndry_mask ((__uint32_t)0x007fffffL) +#define Bndry_mask1 ((__uint32_t)0x007fffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 1 +#define Tiny0 0 +#define Tiny1 1 +#define Quick_max 5 +#define Int_max 6 +#define Infinite(x) (word0(x) == ((__uint32_t)0x7f800000L)) +#undef word0 +#undef word1 + +#define word0(x) (x.i[0]) +#define word1(x) 0 +#else + +#define Exp_shift 20 +#define Exp_shift1 20 +#define Exp_msk1 ((__uint32_t)0x100000L) +#define Exp_msk11 ((__uint32_t)0x100000L) +#define Exp_mask ((__uint32_t)0x7ff00000L) +#define P 53 +#define Bias 1023 +#define IEEE_Arith +#define Emin (-1022) +#define Exp_1 ((__uint32_t)0x3ff00000L) +#define Exp_11 ((__uint32_t)0x3ff00000L) +#define Ebits 11 +#define Frac_mask ((__uint32_t)0xfffffL) +#define Frac_mask1 ((__uint32_t)0xfffffL) +#define Ten_pmax 22 +#define Bletch 0x10 +#define Bndry_mask ((__uint32_t)0xfffffL) +#define Bndry_mask1 ((__uint32_t)0xfffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 1 +#define Tiny0 0 +#define Tiny1 1 +#define Quick_max 14 +#define Int_max 14 +#define Infinite(x) (word0(x) == ((__uint32_t)0x7ff00000L)) /* sufficient test for here */ +#endif + +#else +#undef Sudden_Underflow +#define Sudden_Underflow +#ifdef IBM +#define Exp_shift 24 +#define Exp_shift1 24 +#define Exp_msk1 ((__uint32_t)0x1000000L) +#define Exp_msk11 ((__uint32_t)0x1000000L) +#define Exp_mask ((__uint32_t)0x7f000000L) +#define P 14 +#define Bias 65 +#define Exp_1 ((__uint32_t)0x41000000L) +#define Exp_11 ((__uint32_t)0x41000000L) +#define Ebits 8 /* exponent has 7 bits, but 8 is the right value in b2d */ +#define Frac_mask ((__uint32_t)0xffffffL) +#define Frac_mask1 ((__uint32_t)0xffffffL) +#define Bletch 4 +#define Ten_pmax 22 +#define Bndry_mask ((__uint32_t)0xefffffL) +#define Bndry_mask1 ((__uint32_t)0xffffffL) +#define LSB 1 +#define Sign_bit ((__uint32_t)0x80000000L) +#define Log2P 4 +#define Tiny0 ((__uint32_t)0x100000L) +#define Tiny1 0 +#define Quick_max 14 +#define Int_max 15 +#else /* VAX */ +#define Exp_shift 23 +#define Exp_shift1 7 +#define Exp_msk1 0x80 +#define Exp_msk11 ((__uint32_t)0x800000L) +#define Exp_mask ((__uint32_t)0x7f80L) +#define P 56 +#define Bias 129 +#define Exp_1 ((__uint32_t)0x40800000L) +#define Exp_11 ((__uint32_t)0x4080L) +#define Ebits 8 +#define Frac_mask ((__uint32_t)0x7fffffL) +#define Frac_mask1 ((__uint32_t)0xffff007fL) +#define Ten_pmax 24 +#define Bletch 2 +#define Bndry_mask ((__uint32_t)0xffff007fL) +#define Bndry_mask1 ((__uint32_t)0xffff007fL) +#define LSB ((__uint32_t)0x10000L) +#define Sign_bit ((__uint32_t)0x8000L) +#define Log2P 1 +#define Tiny0 0x80 +#define Tiny1 0 +#define Quick_max 15 +#define Int_max 15 +#endif +#endif + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 b/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 new file mode 100644 index 000000000..804282d6d --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 @@ -0,0 +1,181 @@ +//------------------------------------------------------------------------------ +// @file hal/micro/cortexm3/spmr.s79 +// @brief SPMR (Special Purpose Mask Registers) manipulation routines. +// +// Since the compiler does not provide low level intrinsic functions for some +// required operations, this file maintains the small set of assembly code +// needed to manipulate the Special Purpose Mask Registers. +// +// While it is possible to add this functionality as inline assembly in C files, +// IAR highly recommends against this due to not only code being fragile in its +// surroundings, but it also negates the possibility of size optimization. +// +// NOTE: This file looks more complicated than it really is. It was originally +// generated by writing a C file and having the compiler generate the +// corresponding assembly file. This is where all the CFI (Call Frame +// Information) expressions came from. The CFI information enables proper debug +// backtrace ability. The pieces to pay attention to are the actual funtions +// near the end. +// +// * +//------------------------------------------------------------------------------ + +#include "compiler/asm.h" + +// NOTE!! IF THIS VALUE IS CHANGED, NVIC-CONFIG.H MUST ALSO BE UPDATED +#define INTERRUPTS_DISABLED_PRIORITY (12 << 3) + + __EXPORT__ _readBasePri + __EXPORT__ _writeBasePri + __EXPORT__ _disableBasePri + __EXPORT__ _basePriIsDisabled + __EXPORT__ _enableBasePri + __EXPORT__ _setPriMask + __EXPORT__ _clearPriMask + __EXPORT__ _executeBarrierInstructions + +//------------------------------------------------------------------------------ +// int8u _readBasePri(void) +// +// Read and return the BASEPRI value. +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock0 Using cfiCommon0) + __CFI__(Function _readBasePri) +_readBasePri: + MRS R0, BASEPRI // read current BASEPRI + BX LR + __CFI__(EndBlock cfiBlock0) + +//------------------------------------------------------------------------------ +// void _writeBasePri(int8u priority) +// +// Write BASEPRI with the passed value to obtain the proper preemptive priority +// group masking. Note that the value passed must have been left shifted by 3 +// to be properly aligned in the BASEPRI register. +// (Refer to nvic-config.h for the PRIGROUP table.) +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock1 Using cfiCommon0) + __CFI__(Function _writeBasePri) +_writeBasePri: + MSR BASEPRI, R0 // load BASEPRI from variable (R0) + BX LR + __CFI__(EndBlock cfiBlock1) + +//------------------------------------------------------------------------------ +// int8u _disableBasePri(void) +// +// Set BASEPRI to mask out interrupts but allow faults. It returns the value +// BASEPRI had when it was called. +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock2 Using cfiCommon0) + __CFI__(Function _disableBasePri) +_disableBasePri: + MRS R0, BASEPRI // read current BASEPRI + LDR R1, =INTERRUPTS_DISABLED_PRIORITY // disable ints, allow faults + MSR BASEPRI, R1 + BX LR + __CFI__(EndBlock cfiBlock2) + +//------------------------------------------------------------------------------ +// boolean _basePriIsDisabled(void) +// +// Compare BASEPRI to the priority used to disable interrupts (but not faults). +// Return TRUE if the priority is higher or equal to that. +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock3 Using cfiCommon0) + __CFI__(Function _basePriIsDisabled) +_basePriIsDisabled: + MRS R0, BASEPRI // read current BASEPRI + CMP R0, #INTERRUPTS_DISABLED_PRIORITY + ITE le + LDRLE R0, =1 + LDRGT R0, =0 + BX LR + __CFI__(EndBlock cfiBlock3) + +//------------------------------------------------------------------------------ +// void _enableBasePri(void) +// +// Set BASEPRI to 0, which disables it from masking any interrupts. +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock4 Using cfiCommon0) + __CFI__(Function _enableBasePri) +_enableBasePri: + LDR R1, = 0 // zero disables BASEPRI masking + MSR BASEPRI, R1 + BX LR + __CFI__(EndBlock cfiBlock4) + +//------------------------------------------------------------------------------ +// void _setPriMask(void) +// +// Set the 1-bit PRIMASK register, which sets the base priority to 0. This +// locks out all interrupts and configurable faults (usage, memory management +// and bus faults). +// +// Note: generally speaking PRIMASK should not be set because faults should +// be enabled even when interrupts are disabled. If they are not enabled, +// a fault will immediately escalate to a hard fault. +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock5 Using cfiCommon0) + __CFI__(Function _setPriMask) +_setPriMask: + CPSID i + BX LR + __CFI__(EndBlock cfiBlock5) + +//------------------------------------------------------------------------------ +// void _clearPriMask(void) +// +// Clears the 1-bit PRIMASK register, which allows the BASEPRI value to +// mask interrupts (if non-zero). +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock6 Using cfiCommon0) + __CFI__(Function _clearPriMask) +_clearPriMask: + CPSIE i + BX LR + __CFI__(EndBlock cfiBlock6) + +//------------------------------------------------------------------------------ +// void _executeBarrierInstructions(void) +// +//A utility function for inserting barrier instructions. These +//instructions should be used whenever the MPU is enabled or disabled so +//that all memory/instruction accesses can complete before the MPU changes +//state. +// +//------------------------------------------------------------------------------ + __CODE__ + __THUMB__ + __CFI__(Block cfiBlock7 Using cfiCommon0) + __CFI__(Function _executeBarrierInstructions) +_executeBarrierInstructions: + DMB + DSB + ISB + BX LR + __CFI__(EndBlock cfiBlock7) + + __END__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h new file mode 100644 index 000000000..003cd1ca4 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h @@ -0,0 +1,33 @@ +/** @file board.h + * @brief Header file x STM32W108 Kits boards + * + * + */ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef BOARD_MB851 + +/* leds definitions */ +#define LED_D1 PORTB_PIN(6) +#define LED_D3 PORTB_PIN(5) + + +/** Description buttons definition */ +#define BUTTON_S1 PORTA_PIN(7) +#define BUTTON_S1_INPUT_GPIO GPIO_PAIN +#define BUTTON_S1_OUTPUT_GPIO GPIO_PAOUT +#define BUTTON_S1_GPIO_PIN PA7_BIT +#define BUTTON_S1_WAKE_SOURCE 0x00000080 + +/** Description uart definition */ +#define UART_TX PORTB_PIN(1) +#define UART_RX PORTB_PIN(2) +#define UART_RX_WAKE_SOURCE 0x00000400 + +/** Description temperature sensor GPIO */ +#define TEMPERATURE_SENSOR_GPIO PORTB_PIN(7) +#endif /* BOARD_MB851 */ + +#endif /* _BOARD_H_ */ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c new file mode 100644 index 000000000..6be646583 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c @@ -0,0 +1,362 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_vector.c +* Author : MCD Tools Team +* Date First Issued : 05/14/2007 +* Description : This file contains the vector table for STM32F10x. +* After Reset the Cortex-M3 processor is in Thread mode, +* priority is Privileged, and the Stack is set to Main. +******************************************************************************** +* History: +* 05/14/2007: V0.2 +* +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include +#include +#define RESERVED 0 +//#define DUMMY_MALLOC + +/* Includes ----------------------------------------------------------------------*/ +#include PLATFORM_HEADER +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMonitor_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void halTimer1Isr(void); +void halTimer2Isr(void); +void halManagementIsr(void); +void halBaseBandIsr(void); +void halSleepTimerIsr(void); +void halSc1Isr(void); +void halSc2Isr(void); +void halSecurityIsr(void); +void halStackMacTimerIsr(void); +void stmRadioTransmitIsr(void); +void stmRadioReceiveIsr(void); +void halAdcIsr(void); +void halIrqAIsr(void); +void halIrqBIsr(void); +void halIrqCIsr(void); +void halIrqDIsr(void); +void halDebugIsr(void); + +/* Exported types --------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +extern unsigned long _etext; +extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ +extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ +extern unsigned long _edata; /* end address for the .data section. defined in linker script */ + +extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ +extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ + +extern void _estack; /* init value for the stack pointer. defined in linker script */ + +#include "hal/micro/cortexm3/memmap.h" +VAR_AT_SEGMENT(const HalFixedAddressTableType halFixedAddressTable, __FAT__); + + +/* Private typedef -----------------------------------------------------------*/ + +/* function prototypes ------------------------------------------------------*/ +void Reset_Handler(void) __attribute__((__interrupt__)); +extern int main(void); + + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + + +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + &_estack, // The initial stack pointer + Reset_Handler, // 1 The reset handler + NMI_Handler, // 2 + HardFault_Handler, // 3 + MemManage_Handler, // 4 + BusFault_Handler, // 5 + UsageFault_Handler, // 6 + RESERVED, // 7 + RESERVED, // 8 + RESERVED, // 9 + RESERVED, // 10 + SVC_Handler, // 11 + DebugMonitor_Handler, // 12 + RESERVED, // 13 + PendSV_Handler, // 14 + SysTick_Handler, // 15 + halTimer1Isr, // 16 + halTimer2Isr, // 17 + halManagementIsr, // 18 + halBaseBandIsr, // 19 + halSleepTimerIsr, // 20 + halSc1Isr, // 21 + halSc2Isr, // 22 + halSecurityIsr, // 23 + halStackMacTimerIsr, // 24 + stmRadioTransmitIsr, // 25 + stmRadioReceiveIsr, // 26 + halAdcIsr, // 27 + halIrqAIsr, // 28 + halIrqBIsr, // 29 + halIrqCIsr, // 30 + halIrqDIsr, // 31 + halDebugIsr, // 32 +}; + +/******************************************************************************* +* Function Name : Reset_Handler +* Description : This is the code that gets called when the processor first starts execution +* following a reset event. Only the absolutely necessary set is performed, +* after which the application supplied main() routine is called. +* Input : +* Output : +* Return : +*******************************************************************************/ +void Reset_Handler(void) +{ + //Ensure there is enough margin on VREG_1V8 for stable RAM reads by + //setting it to a code of 6. VREG_1V2 can be left at its reset value. + VREG = 0x00000307; + + // This code should be careful about the use of local variables in case the + // reset type happens to be a deep sleep reset. If the reset is not from + // deep sleep, then locals can be freely used + + //When the Cortex-M3 exits reset, interrupts are enable. Explicitely + //disable them immediately using the standard set PRIMASK instruction. + //Injecting an assembly instruction this early does not effect optimization. + asm("CPSID i"); + + //It is quite possible that when the Cortex-M3 begins executing code the + //Core Reset Vector Catch is still left enabled. Because this VC would + //cause us to halt at reset if another reset event tripped, we should + //clear it as soon as possible. If a debugger wants to halt at reset, + //it will set this bit again. + DEBUG_EMCR &= ~DEBUG_EMCR_VC_CORERESET; + + //Configure flash access for optimal current consumption early + //during boot to save as much current as we can. + FLASH_ACCESS = (FLASH_ACCESS_PREFETCH_EN | + (1< (__HEAP_START + sizeof(__HEAP_START))) { + prev_heap = NULL; + } else { + heap += incr; + } + if (prev_heap == NULL) { + printf ("_sbrk %d return %p\n\r", incr, prev_heap); + } + return (caddr_t) prev_heap; +} +#else +# ifdef DUMMY_MALLOC +caddr_t _sbrk ( int incr ) +{ + return NULL; +} +# endif +#endif +int _lseek (int file, + int ptr, + int dir) +{ + return 0; +} +int _close (int file) +{ + return -1; +} + +void _exit (int n) +{ + /* FIXME: return code is thrown away. */ + while(1); +} + + + +int _kill (int n, int m) +{ + return -1; +} +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} +int _isatty (int fd) +{ + return 1; + fd = fd; +} +int _getpid (int n) +{ + return -1; +} +int _open (const char * path, + int flags, + ...) +{ + return -1; +} +int _fflush_r(struct _reent *r, FILE *f) +{ + return 0; +} + +/********************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ + + diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/gnu.ld b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/gnu.ld new file mode 100644 index 000000000..65bbe760c --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/gnu.ld @@ -0,0 +1,245 @@ +/*SEARCH_DIR("C:\Program Files\Raisonance\Ride\Lib\ARM") +EXTERN( __io_putchar ) +EXTERN( _write ) +GROUP( +"std_sbrk_thumb.lib" +"smallprintf_thumb.a" +"libc.a" +"libm.a" +) +*/ +/* default stack sizes. + +These are used by the startup in order to allocate stacks for the different modes. +*/ + +__Stack_Size = 0x400 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x400 ; + + + +/* +this sends all unreferenced IRQHandlers to reset +*/ + +PROVIDE(Default_Handler = 0 ); +PROVIDE(NMI_Handler = Default_Handler ); +PROVIDE(HardFault_Handler = Default_Handler ); +PROVIDE(MemManage_Handler = Default_Handler ); +PROVIDE(BusFault_Handler = Default_Handler ); +PROVIDE(UsageFault_Handler = Default_Handler ); +PROVIDE(SVC_Handler = Default_Handler ); +PROVIDE(DebugMonitor_Handler = Default_Handler ); +PROVIDE(PendSV_Handler = Default_Handler ); +PROVIDE(SysTick_Handler = Default_Handler ); +PROVIDE(halTimer1Isr = Default_Handler ); +PROVIDE(halTimer2Isr = Default_Handler ); +PROVIDE(halManagementIsr = Default_Handler ); +PROVIDE(halBaseBandIsr = Default_Handler ); +PROVIDE(halSleepTimerIsr = Default_Handler ); +PROVIDE(halSc1Isr = Default_Handler ); +PROVIDE(halSc2Isr = Default_Handler ); +PROVIDE(halSecurityIsr = Default_Handler ); +PROVIDE(halStackMacTimerIsr = Default_Handler ); +PROVIDE(stmRadioTransmitIsr = Default_Handler ); +PROVIDE(stmRadioReceiveIsr = Default_Handler ); +PROVIDE(halAdcIsr = Default_Handler ); +PROVIDE(halIrqAIsr = Default_Handler ); +PROVIDE(halIrqBIsr = Default_Handler ); +PROVIDE(halIrqCIsr = Default_Handler ); +PROVIDE(halIrqDIsr = Default_Handler ); +PROVIDE(halDebugIsr = Default_Handler ); +/*PROVIDE(stSerialPrintf = printf );*/ + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/*this allows to compile the ST lib in "non-debug" mode*/ + + +/* include the memory spaces definitions sub-script */ +MEMORY +{ + RAM_region (xrw) : ORIGIN = 0x20000000, LENGTH = 8K + ROM_region (rx) : ORIGIN = 0x08000000, LENGTH = 128K-3K + NVM_region (rx) : ORIGIN = 0x0801F400, LENGTH = 3K + FIB_region (ra) : ORIGIN = 0x08040000, LENGTH = 2K +} + +/* higher address of the user mode stack */ +_estack = 0x20002000; + +/* Sections management for FLASH mode */ + +/* Sections Definitions */ + +SECTIONS +{ + + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM_region + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >ROM_region + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >ROM_region + + NVM (NOLOAD): + { + . = ALIGN(1024); + KEEP(*(NVM)) + . = ALIGN(4); + } > NVM_region + + + FAT (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(FAT)) + . = ALIGN(4); + } > FIB_region + +/* + .FAT (NOLOAD): + { + KEEP(*(.FAT)) + } > FIB_region +*/ + /* after that it's only debugging information. */ + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM_region + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM_region + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM_region + + __exidx_start = .; + __exidx_end = .; + + /* remove the debugging information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/iar-cfg.icf b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/iar-cfg.icf new file mode 100644 index 000000000..74124aac2 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/iar-cfg.icf @@ -0,0 +1,30 @@ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_FIB_start__ = 0x08040000; +define symbol __ICFEDIT_region_FIB_end__ = 0x080407FF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x500; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit, + section FAT, + section NVM }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place at address mem:__ICFEDIT_region_FIB_start__ { section FAT }; +place in ROM_region { readonly }; +place at end of ROM_region { section NVM }; +place in RAM_region { readwrite, + block CSTACK }; diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c new file mode 100644 index 000000000..1ab3d3324 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c @@ -0,0 +1,173 @@ +/************************************************** + * + * This module contains the function `__low_level_init', a function + * that is called before the `main' function of the program. Normally + * low-level initializations - such as setting the prefered interrupt + * level or setting the watchdog - can be performed here. + * + * Note that this function is called before the data segments are + * initialized, this means that this function cannot rely on the + * values of global or static variables. + * + * When this function returns zero, the startup code will inhibit the + * initialization of the data segments. The result is faster startup, + * the drawback is that neither global nor static data will be + * initialized. + * + * Copyright 1999-2004 IAR Systems. All rights reserved. + * Customized by STMicroelectronics for STM32W + * + **************************************************/ + +#include PLATFORM_HEADER + +#ifdef __cplusplus +extern "C" { +#endif + +#pragma language=extended + +#include "hal/micro/cortexm3/memmap.h" +__root __no_init const HalFixedAddressTableType halFixedAddressTable @ __FAT__; + +extern const HalVectorTableType __vector_table[]; + + +__interwork int __low_level_init(void); + +__interwork int __low_level_init(void) +{ + //Ensure there is enough margin on VREG_1V8 for stable RAM reads by + //setting it to a code of 6. VREG_1V2 can be left at its reset value. + VREG = 0x00000307; + + // This code should be careful about the use of local variables in case the + // reset type happens to be a deep sleep reset. If the reset is not from + // deep sleep, then locals can be freely used + + //When the Cortex-M3 exits reset, interrupts are enable. Explicitely + //disable them immediately using the standard set PRIMASK instruction. + //Injecting an assembly instruction this early does not effect optimization. + asm("CPSID i"); + + //It is quite possible that when the Cortex-M3 begins executing code the + //Core Reset Vector Catch is still left enabled. Because this VC would + //cause us to halt at reset if another reset event tripped, we should + //clear it as soon as possible. If a debugger wants to halt at reset, + //it will set this bit again. + DEBUG_EMCR &= ~DEBUG_EMCR_VC_CORERESET; + + //Configure flash access for optimal current consumption early + //during boot to save as much current as we can. + FLASH_ACCESS = (FLASH_ACCESS_PREFETCH_EN | + (1< + */ + +#ifndef __MEMMAP_H__ + #error This header should not be included directly, use hal/micro/cortexm3/memmap.h +#endif + +#ifndef __STM32W108_MEMMAP_H__ +#define __STM32W108_MEMMAP_H__ + +#define RAM_BOTTOM (0x20000000u) +#define RAM_SIZE_B (0x2000) +#define RAM_SIZE_W (RAM_SIZE_B/4) +#define RAM_TOP (RAM_BOTTOM+RAM_SIZE_B-1) + +#define MFB_BOTTOM (0x08000000u) +#define MFB_SIZE_B (0x20000) +#define MFB_SIZE_W (MFB_SIZE_B/4) +#define MFB_TOP (MFB_BOTTOM+MFB_SIZE_B-1) +#define MFB_PAGE_SIZE_B (1024) +#define MFB_PAGE_SIZE_W (MFB_PAGE_SIZE_B/4) +#define MFB_PAGE_MASK_B (0xFFFFFC00) +#define MFB_REGION_SIZE (4) // One write protection region is 4 pages. +#define MFB_ADDR_MASK (0x0003FFFFu) + +#define CIB_BOTTOM (0x08040800u) +#define CIB_SIZE_B (0x200) +#define CIB_SIZE_W (CIB_SIZE_B/4) +#define CIB_TOP (CIB_BOTTOM+CIB_SIZE_B-1) +#define CIB_PAGE_SIZE_B (512) +#define CIB_PAGE_SIZE_W (CIB_PAGE_SIZE_B/4) +#define CIB_OB_BOTTOM (CIB_BOTTOM+0x00) //bottom address of CIB option bytes +#define CIB_OB_TOP (CIB_BOTTOM+0x0F) //top address of CIB option bytes + +#define FIB_BOTTOM (0x08040000u) +#define FIB_SIZE_B (0x800) +#define FIB_SIZE_W (FIB_SIZE_B/4) +#define FIB_TOP (FIB_BOTTOM+FIB_SIZE_B-1) +#define FIB_PAGE_SIZE_B (1024) +#define FIB_PAGE_SIZE_W (FIB_PAGE_SIZE_B/4) + +#define FPEC_KEY1 0x45670123 //magic key defined in hardware +#define FPEC_KEY2 0xCDEF89AB //magic key defined in hardware + +//Translation between page number and simee (word based) address +#define SIMEE_ADDR_TO_PAGE(x) ((int8u)(((int16u)(x)) >> 9)) +#define PAGE_TO_SIMEE_ADDR(x) (((int16u)(x)) << 9) + +//Translation between page number and code addresses, used by bootloaders +#define PROG_ADDR_TO_PAGE(x) ((int8u)((((int32u)(x))&MFB_ADDR_MASK) >> 10)) +#define PAGE_TO_PROG_ADDR(x) ((((int32u)(x)) << 10)|MFB_BOTTOM) + + +#endif //__STM32W108_MEMMAP_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.ddf b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.ddf new file mode 100644 index 000000000..f5a7f0d43 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.ddf @@ -0,0 +1,924 @@ +;------------------------------------------------------------------------------ +; @file regs.ddf +; @brief Device Description File for use with IAR's C-SPY +; +; To see all registers defined in Embedded Workbench's C-SPY Register window, +; this file must be pointed to under +; Project > Options > Debugger > Device description file +; +; Please Note: This file is automatically generated, and should not +; be directly edited +; +; COPYRIGHT 2010 STMicroelectronics. All rights reserved. +;------------------------------------------------------------------------------ + + +; Start of SFR definition. +[Sfr] +; Name Zone Address Bytesize Displaybase Bitrange +; ---- ---- ------- -------- ----------- -------- + +sfr = "INT_TIM1FLAG", "Memory", 0x4000A800, 4, base=16 +sfr = "INT_TIM1FLAG.INT_TIMRSVD", "Memory", 0x4000A800, 4, base=16, bitMask=0x00001E00 +sfr = "INT_TIM1FLAG.INT_TIMTIF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000040 +sfr = "INT_TIM1FLAG.INT_TIMCC4IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000010 +sfr = "INT_TIM1FLAG.INT_TIMCC3IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000008 +sfr = "INT_TIM1FLAG.INT_TIMCC2IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000004 +sfr = "INT_TIM1FLAG.INT_TIMCC1IF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000002 +sfr = "INT_TIM1FLAG.INT_TIMUIF", "Memory", 0x4000A800, 4, base=16, bitMask=0x00000001 + +sfr = "INT_TIM2FLAG", "Memory", 0x4000A804, 4, base=16 +sfr = "INT_TIM2FLAG.INT_TIMRSVD", "Memory", 0x4000A804, 4, base=16, bitMask=0x00001E00 +sfr = "INT_TIM2FLAG.INT_TIMTIF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000040 +sfr = "INT_TIM2FLAG.INT_TIMCC4IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000010 +sfr = "INT_TIM2FLAG.INT_TIMCC3IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000008 +sfr = "INT_TIM2FLAG.INT_TIMCC2IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000004 +sfr = "INT_TIM2FLAG.INT_TIMCC1IF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000002 +sfr = "INT_TIM2FLAG.INT_TIMUIF", "Memory", 0x4000A804, 4, base=16, bitMask=0x00000001 + +sfr = "INT_SC1FLAG", "Memory", 0x4000A808, 4, base=16 +sfr = "INT_SC1FLAG.INT_SC1PARERR", "Memory", 0x4000A808, 4, base=16, bitMask=0x00004000 +sfr = "INT_SC1FLAG.INT_SC1FRMERR", "Memory", 0x4000A808, 4, base=16, bitMask=0x00002000 +sfr = "INT_SC1FLAG.INT_SCTXULDB", "Memory", 0x4000A808, 4, base=16, bitMask=0x00001000 +sfr = "INT_SC1FLAG.INT_SCTXULDA", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000800 +sfr = "INT_SC1FLAG.INT_SCRXULDB", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000400 +sfr = "INT_SC1FLAG.INT_SCRXULDA", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000200 +sfr = "INT_SC1FLAG.INT_SCNAK", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000100 +sfr = "INT_SC1FLAG.INT_SCCMDFIN", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000080 +sfr = "INT_SC1FLAG.INT_SCTXFIN", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000040 +sfr = "INT_SC1FLAG.INT_SCRXFIN", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000020 +sfr = "INT_SC1FLAG.INT_SCTXUND", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000010 +sfr = "INT_SC1FLAG.INT_SCRXOVF", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000008 +sfr = "INT_SC1FLAG.INT_SCTXIDLE", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000004 +sfr = "INT_SC1FLAG.INT_SCTXFREE", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000002 +sfr = "INT_SC1FLAG.INT_SCRXVAL", "Memory", 0x4000A808, 4, base=16, bitMask=0x00000001 + +sfr = "INT_SC2FLAG", "Memory", 0x4000A80C, 4, base=16 +sfr = "INT_SC2FLAG.INT_SCTXULDB", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00001000 +sfr = "INT_SC2FLAG.INT_SCTXULDA", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000800 +sfr = "INT_SC2FLAG.INT_SCRXULDB", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000400 +sfr = "INT_SC2FLAG.INT_SCRXULDA", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000200 +sfr = "INT_SC2FLAG.INT_SCNAK", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000100 +sfr = "INT_SC2FLAG.INT_SCCMDFIN", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000080 +sfr = "INT_SC2FLAG.INT_SCTXFIN", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000040 +sfr = "INT_SC2FLAG.INT_SCRXFIN", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000020 +sfr = "INT_SC2FLAG.INT_SCTXUND", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000010 +sfr = "INT_SC2FLAG.INT_SCRXOVF", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000008 +sfr = "INT_SC2FLAG.INT_SCTXIDLE", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000004 +sfr = "INT_SC2FLAG.INT_SCTXFREE", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000002 +sfr = "INT_SC2FLAG.INT_SCRXVAL", "Memory", 0x4000A80C, 4, base=16, bitMask=0x00000001 + +sfr = "INT_ADCFLAG", "Memory", 0x4000A810, 4, base=16 +sfr = "INT_ADCFLAG.INT_ADCOVF", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000010 +sfr = "INT_ADCFLAG.INT_ADCSAT", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000008 +sfr = "INT_ADCFLAG.INT_ADCULDFULL", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000004 +sfr = "INT_ADCFLAG.INT_ADCULDHALF", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000002 +sfr = "INT_ADCFLAG.INT_ADCFLAGRSVD", "Memory", 0x4000A810, 4, base=16, bitMask=0x00000001 + +sfr = "INT_GPIOFLAG", "Memory", 0x4000A814, 4, base=16 +sfr = "INT_GPIOFLAG.INT_IRQDFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000008 +sfr = "INT_GPIOFLAG.INT_IRQCFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000004 +sfr = "INT_GPIOFLAG.INT_IRQBFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000002 +sfr = "INT_GPIOFLAG.INT_IRQAFLAG", "Memory", 0x4000A814, 4, base=16, bitMask=0x00000001 + +sfr = "INT_TIM1MISS", "Memory", 0x4000A818, 4, base=16 +sfr = "INT_TIM1MISS.INT_TIMMISSCC4IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00001000 +sfr = "INT_TIM1MISS.INT_TIMMISSCC3IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00000800 +sfr = "INT_TIM1MISS.INT_TIMMISSCC2IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00000400 +sfr = "INT_TIM1MISS.INT_TIMMISSCC1IF", "Memory", 0x4000A818, 4, base=16, bitMask=0x00000200 +sfr = "INT_TIM1MISS.INT_TIMMISSRSVD", "Memory", 0x4000A818, 4, base=16, bitMask=0x0000007F + +sfr = "INT_TIM2MISS", "Memory", 0x4000A81C, 4, base=16 +sfr = "INT_TIM2MISS.INT_TIMMISSCC4IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00001000 +sfr = "INT_TIM2MISS.INT_TIMMISSCC3IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00000800 +sfr = "INT_TIM2MISS.INT_TIMMISSCC2IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00000400 +sfr = "INT_TIM2MISS.INT_TIMMISSCC1IF", "Memory", 0x4000A81C, 4, base=16, bitMask=0x00000200 +sfr = "INT_TIM2MISS.INT_TIMMISSRSVD", "Memory", 0x4000A81C, 4, base=16, bitMask=0x0000007F + +sfr = "INT_MISS", "Memory", 0x4000A820, 4, base=16 +sfr = "INT_MISS.INT_MISSIRQD", "Memory", 0x4000A820, 4, base=16, bitMask=0x00008000 +sfr = "INT_MISS.INT_MISSIRQC", "Memory", 0x4000A820, 4, base=16, bitMask=0x00004000 +sfr = "INT_MISS.INT_MISSIRQB", "Memory", 0x4000A820, 4, base=16, bitMask=0x00002000 +sfr = "INT_MISS.INT_MISSIRQA", "Memory", 0x4000A820, 4, base=16, bitMask=0x00001000 +sfr = "INT_MISS.INT_MISSADC", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000800 +sfr = "INT_MISS.INT_MISSMACRX", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000400 +sfr = "INT_MISS.INT_MISSMACTX", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000200 +sfr = "INT_MISS.INT_MISSMACTMR", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000100 +sfr = "INT_MISS.INT_MISSSEC", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000080 +sfr = "INT_MISS.INT_MISSSC2", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000040 +sfr = "INT_MISS.INT_MISSSC1", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000020 +sfr = "INT_MISS.INT_MISSSLEEP", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000010 +sfr = "INT_MISS.INT_MISSBB", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000008 +sfr = "INT_MISS.INT_MISSMGMT", "Memory", 0x4000A820, 4, base=16, bitMask=0x00000004 + +sfr = "INT_TIM1CFG", "Memory", 0x4000A840, 4, base=16 +sfr = "INT_TIM1CFG.INT_TIMTIF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000040 +sfr = "INT_TIM1CFG.INT_TIMCC4IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000010 +sfr = "INT_TIM1CFG.INT_TIMCC3IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000008 +sfr = "INT_TIM1CFG.INT_TIMCC2IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000004 +sfr = "INT_TIM1CFG.INT_TIMCC1IF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000002 +sfr = "INT_TIM1CFG.INT_TIMUIF", "Memory", 0x4000A840, 4, base=16, bitMask=0x00000001 + +sfr = "INT_TIM2CFG", "Memory", 0x4000A844, 4, base=16 +sfr = "INT_TIM2CFG.INT_TIMTIF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000040 +sfr = "INT_TIM2CFG.INT_TIMCC4IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000010 +sfr = "INT_TIM2CFG.INT_TIMCC3IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000008 +sfr = "INT_TIM2CFG.INT_TIMCC2IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000004 +sfr = "INT_TIM2CFG.INT_TIMCC1IF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000002 +sfr = "INT_TIM2CFG.INT_TIMUIF", "Memory", 0x4000A844, 4, base=16, bitMask=0x00000001 + +sfr = "INT_SC1CFG", "Memory", 0x4000A848, 4, base=16 +sfr = "INT_SC1CFG.INT_SC1PARERR", "Memory", 0x4000A848, 4, base=16, bitMask=0x00004000 +sfr = "INT_SC1CFG.INT_SC1FRMERR", "Memory", 0x4000A848, 4, base=16, bitMask=0x00002000 +sfr = "INT_SC1CFG.INT_SCTXULDB", "Memory", 0x4000A848, 4, base=16, bitMask=0x00001000 +sfr = "INT_SC1CFG.INT_SCTXULDA", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000800 +sfr = "INT_SC1CFG.INT_SCRXULDB", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000400 +sfr = "INT_SC1CFG.INT_SCRXULDA", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000200 +sfr = "INT_SC1CFG.INT_SCNAK", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000100 +sfr = "INT_SC1CFG.INT_SCCMDFIN", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000080 +sfr = "INT_SC1CFG.INT_SCTXFIN", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000040 +sfr = "INT_SC1CFG.INT_SCRXFIN", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000020 +sfr = "INT_SC1CFG.INT_SCTXUND", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000010 +sfr = "INT_SC1CFG.INT_SCRXOVF", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000008 +sfr = "INT_SC1CFG.INT_SCTXIDLE", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000004 +sfr = "INT_SC1CFG.INT_SCTXFREE", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000002 +sfr = "INT_SC1CFG.INT_SCRXVAL", "Memory", 0x4000A848, 4, base=16, bitMask=0x00000001 + +sfr = "INT_SC2CFG", "Memory", 0x4000A84C, 4, base=16 +sfr = "INT_SC2CFG.INT_SCTXULDB", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00001000 +sfr = "INT_SC2CFG.INT_SCTXULDA", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000800 +sfr = "INT_SC2CFG.INT_SCRXULDB", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000400 +sfr = "INT_SC2CFG.INT_SCRXULDA", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000200 +sfr = "INT_SC2CFG.INT_SCNAK", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000100 +sfr = "INT_SC2CFG.INT_SCCMDFIN", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000080 +sfr = "INT_SC2CFG.INT_SCTXFIN", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000040 +sfr = "INT_SC2CFG.INT_SCRXFIN", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000020 +sfr = "INT_SC2CFG.INT_SCTXUND", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000010 +sfr = "INT_SC2CFG.INT_SCRXOVF", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000008 +sfr = "INT_SC2CFG.INT_SCTXIDLE", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000004 +sfr = "INT_SC2CFG.INT_SCTXFREE", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000002 +sfr = "INT_SC2CFG.INT_SCRXVAL", "Memory", 0x4000A84C, 4, base=16, bitMask=0x00000001 + +sfr = "INT_ADCCFG", "Memory", 0x4000A850, 4, base=16 +sfr = "INT_ADCCFG.INT_ADCOVF", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000010 +sfr = "INT_ADCCFG.INT_ADCSAT", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000008 +sfr = "INT_ADCCFG.INT_ADCULDFULL", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000004 +sfr = "INT_ADCCFG.INT_ADCULDHALF", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000002 +sfr = "INT_ADCCFG.INT_ADCCFGRSVD", "Memory", 0x4000A850, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_INTMODE", "Memory", 0x4000A854, 4, base=16 +sfr = "SC1_INTMODE.SC_TXIDLELEVEL", "Memory", 0x4000A854, 4, base=16, bitMask=0x00000004 +sfr = "SC1_INTMODE.SC_TXFREELEVEL", "Memory", 0x4000A854, 4, base=16, bitMask=0x00000002 +sfr = "SC1_INTMODE.SC_RXVALLEVEL", "Memory", 0x4000A854, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_INTMODE", "Memory", 0x4000A858, 4, base=16 +sfr = "SC2_INTMODE.SC_TXIDLELEVEL", "Memory", 0x4000A858, 4, base=16, bitMask=0x00000004 +sfr = "SC2_INTMODE.SC_TXFREELEVEL", "Memory", 0x4000A858, 4, base=16, bitMask=0x00000002 +sfr = "SC2_INTMODE.SC_RXVALLEVEL", "Memory", 0x4000A858, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_INTCFGA", "Memory", 0x4000A860, 4, base=16 +sfr = "GPIO_INTCFGA.GPIO_INTFILT", "Memory", 0x4000A860, 4, base=16, bitMask=0x00000100 +sfr = "GPIO_INTCFGA.GPIO_INTMOD", "Memory", 0x4000A860, 4, base=16, bitMask=0x000000E0 + +sfr = "GPIO_INTCFGB", "Memory", 0x4000A864, 4, base=16 +sfr = "GPIO_INTCFGB.GPIO_INTFILT", "Memory", 0x4000A864, 4, base=16, bitMask=0x00000100 +sfr = "GPIO_INTCFGB.GPIO_INTMOD", "Memory", 0x4000A864, 4, base=16, bitMask=0x000000E0 + +sfr = "GPIO_INTCFGC", "Memory", 0x4000A868, 4, base=16 +sfr = "GPIO_INTCFGC.GPIO_INTFILT", "Memory", 0x4000A868, 4, base=16, bitMask=0x00000100 +sfr = "GPIO_INTCFGC.GPIO_INTMOD", "Memory", 0x4000A868, 4, base=16, bitMask=0x000000E0 + +sfr = "GPIO_INTCFGD", "Memory", 0x4000A86C, 4, base=16 +sfr = "GPIO_INTCFGD.GPIO_INTFILT", "Memory", 0x4000A86C, 4, base=16, bitMask=0x00000100 +sfr = "GPIO_INTCFGD.GPIO_INTMOD", "Memory", 0x4000A86C, 4, base=16, bitMask=0x000000E0 + +sfr = "GPIO_PACFGL", "Memory", 0x4000B000, 4, base=16 +sfr = "GPIO_PACFGL.PA3_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x0000F000 +sfr = "GPIO_PACFGL.PA2_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x00000F00 +sfr = "GPIO_PACFGL.PA1_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x000000F0 +sfr = "GPIO_PACFGL.PA0_CFG", "Memory", 0x4000B000, 4, base=16, bitMask=0x0000000F + +sfr = "GPIO_PACFGH", "Memory", 0x4000B004, 4, base=16 +sfr = "GPIO_PACFGH.PA7_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x0000F000 +sfr = "GPIO_PACFGH.PA6_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x00000F00 +sfr = "GPIO_PACFGH.PA5_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x000000F0 +sfr = "GPIO_PACFGH.PA4_CFG", "Memory", 0x4000B004, 4, base=16, bitMask=0x0000000F + +sfr = "GPIO_PAIN", "Memory", 0x4000B008, 4, base=16 +sfr = "GPIO_PAIN.PA7", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PAIN.PA6", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PAIN.PA5", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PAIN.PA4", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PAIN.PA3", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PAIN.PA2", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PAIN.PA1", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PAIN.PA0", "Memory", 0x4000B008, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PAOUT", "Memory", 0x4000B00C, 4, base=16 +sfr = "GPIO_PAOUT.PA7", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PAOUT.PA6", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PAOUT.PA5", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PAOUT.PA4", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PAOUT.PA3", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PAOUT.PA2", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PAOUT.PA1", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PAOUT.PA0", "Memory", 0x4000B00C, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PASET", "Memory", 0x4000B010, 4, base=16 +sfr = "GPIO_PASET.GPIO_PXSETRSVD", "Memory", 0x4000B010, 4, base=16, bitMask=0x0000FF00 +sfr = "GPIO_PASET.PA7", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PASET.PA6", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PASET.PA5", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PASET.PA4", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PASET.PA3", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PASET.PA2", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PASET.PA1", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PASET.PA0", "Memory", 0x4000B010, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PACLR", "Memory", 0x4000B014, 4, base=16 +sfr = "GPIO_PACLR.PA7", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PACLR.PA6", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PACLR.PA5", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PACLR.PA4", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PACLR.PA3", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PACLR.PA2", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PACLR.PA1", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PACLR.PA0", "Memory", 0x4000B014, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PBCFGL", "Memory", 0x4000B400, 4, base=16 +sfr = "GPIO_PBCFGL.PB3_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x0000F000 +sfr = "GPIO_PBCFGL.PB2_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x00000F00 +sfr = "GPIO_PBCFGL.PB1_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x000000F0 +sfr = "GPIO_PBCFGL.PB0_CFG", "Memory", 0x4000B400, 4, base=16, bitMask=0x0000000F + +sfr = "GPIO_PBCFGH", "Memory", 0x4000B404, 4, base=16 +sfr = "GPIO_PBCFGH.PB7_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x0000F000 +sfr = "GPIO_PBCFGH.PB6_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x00000F00 +sfr = "GPIO_PBCFGH.PB5_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x000000F0 +sfr = "GPIO_PBCFGH.PB4_CFG", "Memory", 0x4000B404, 4, base=16, bitMask=0x0000000F + +sfr = "GPIO_PBIN", "Memory", 0x4000B408, 4, base=16 +sfr = "GPIO_PBIN.PB7", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PBIN.PB6", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PBIN.PB5", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PBIN.PB4", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PBIN.PB3", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PBIN.PB2", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PBIN.PB1", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PBIN.PB0", "Memory", 0x4000B408, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PBOUT", "Memory", 0x4000B40C, 4, base=16 +sfr = "GPIO_PBOUT.PB7", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PBOUT.PB6", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PBOUT.PB5", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PBOUT.PB4", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PBOUT.PB3", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PBOUT.PB2", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PBOUT.PB1", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PBOUT.PB0", "Memory", 0x4000B40C, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PBSET", "Memory", 0x4000B410, 4, base=16 +sfr = "GPIO_PBSET.GPIO_PXSETRSVD", "Memory", 0x4000B410, 4, base=16, bitMask=0x0000FF00 +sfr = "GPIO_PBSET.PB7", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PBSET.PB6", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PBSET.PB5", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PBSET.PB4", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PBSET.PB3", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PBSET.PB2", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PBSET.PB1", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PBSET.PB0", "Memory", 0x4000B410, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PBCLR", "Memory", 0x4000B414, 4, base=16 +sfr = "GPIO_PBCLR.PB7", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PBCLR.PB6", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PBCLR.PB5", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PBCLR.PB4", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PBCLR.PB3", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PBCLR.PB2", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PBCLR.PB1", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PBCLR.PB0", "Memory", 0x4000B414, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PCCFGL", "Memory", 0x4000B800, 4, base=16 +sfr = "GPIO_PCCFGL.PC3_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x0000F000 +sfr = "GPIO_PCCFGL.PC2_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x00000F00 +sfr = "GPIO_PCCFGL.PC1_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x000000F0 +sfr = "GPIO_PCCFGL.PC0_CFG", "Memory", 0x4000B800, 4, base=16, bitMask=0x0000000F + +sfr = "GPIO_PCCFGH", "Memory", 0x4000B804, 4, base=16 +sfr = "GPIO_PCCFGH.PC7_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x0000F000 +sfr = "GPIO_PCCFGH.PC6_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x00000F00 +sfr = "GPIO_PCCFGH.PC5_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x000000F0 +sfr = "GPIO_PCCFGH.PC4_CFG", "Memory", 0x4000B804, 4, base=16, bitMask=0x0000000F + +sfr = "GPIO_PCIN", "Memory", 0x4000B808, 4, base=16 +sfr = "GPIO_PCIN.PC7", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PCIN.PC6", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PCIN.PC5", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PCIN.PC4", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PCIN.PC3", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PCIN.PC2", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PCIN.PC1", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PCIN.PC0", "Memory", 0x4000B808, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PCOUT", "Memory", 0x4000B80C, 4, base=16 +sfr = "GPIO_PCOUT.PC7", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PCOUT.PC6", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PCOUT.PC5", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PCOUT.PC4", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PCOUT.PC3", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PCOUT.PC2", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PCOUT.PC1", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PCOUT.PC0", "Memory", 0x4000B80C, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PCSET", "Memory", 0x4000B810, 4, base=16 +sfr = "GPIO_PCSET.GPIO_PXSETRSVD", "Memory", 0x4000B810, 4, base=16, bitMask=0x0000FF00 +sfr = "GPIO_PCSET.PC7", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PCSET.PC6", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PCSET.PC5", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PCSET.PC4", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PCSET.PC3", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PCSET.PC2", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PCSET.PC1", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PCSET.PC0", "Memory", 0x4000B810, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PCCLR", "Memory", 0x4000B814, 4, base=16 +sfr = "GPIO_PCCLR.PC7", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PCCLR.PC6", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PCCLR.PC5", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PCCLR.PC4", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PCCLR.PC3", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PCCLR.PC2", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PCCLR.PC1", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PCCLR.PC0", "Memory", 0x4000B814, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_DBGCFG", "Memory", 0x4000BC00, 4, base=16 +sfr = "GPIO_DBGCFG.GPIO_DEBUGDIS", "Memory", 0x4000BC00, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_DBGCFG.GPIO_EXTREGEN", "Memory", 0x4000BC00, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_DBGCFG.GPIO_DBGCFGRSVD", "Memory", 0x4000BC00, 4, base=16, bitMask=0x00000008 + +sfr = "GPIO_DBGSTAT", "Memory", 0x4000BC04, 4, base=16 +sfr = "GPIO_DBGSTAT.GPIO_BOOTMODE", "Memory", 0x4000BC04, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_DBGSTAT.GPIO_FORCEDBG", "Memory", 0x4000BC04, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_DBGSTAT.GPIO_SWEN", "Memory", 0x4000BC04, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PAWAKE", "Memory", 0x4000BC08, 4, base=16 +sfr = "GPIO_PAWAKE.PA7", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PAWAKE.PA6", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PAWAKE.PA5", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PAWAKE.PA4", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PAWAKE.PA3", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PAWAKE.PA2", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PAWAKE.PA1", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PAWAKE.PA0", "Memory", 0x4000BC08, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PBWAKE", "Memory", 0x4000BC0C, 4, base=16 +sfr = "GPIO_PBWAKE.PB7", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PBWAKE.PB6", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PBWAKE.PB5", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PBWAKE.PB4", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PBWAKE.PB3", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PBWAKE.PB2", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PBWAKE.PB1", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PBWAKE.PB0", "Memory", 0x4000BC0C, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_PCWAKE", "Memory", 0x4000BC10, 4, base=16 +sfr = "GPIO_PCWAKE.PC7", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000080 +sfr = "GPIO_PCWAKE.PC6", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000040 +sfr = "GPIO_PCWAKE.PC5", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000020 +sfr = "GPIO_PCWAKE.PC4", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000010 +sfr = "GPIO_PCWAKE.PC3", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_PCWAKE.PC2", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_PCWAKE.PC1", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_PCWAKE.PC0", "Memory", 0x4000BC10, 4, base=16, bitMask=0x00000001 + +sfr = "GPIO_IRQCSEL", "Memory", 0x4000BC14, 4, base=16 + +sfr = "GPIO_IRQDSEL", "Memory", 0x4000BC18, 4, base=16 + +sfr = "GPIO_WAKEFILT", "Memory", 0x4000BC1C, 4, base=16 +sfr = "GPIO_WAKEFILT.IRQD_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000008 +sfr = "GPIO_WAKEFILT.SC2_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000004 +sfr = "GPIO_WAKEFILT.SC1_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000002 +sfr = "GPIO_WAKEFILT.GPIO_WAKE_FILTER", "Memory", 0x4000BC1C, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_RXBEGA", "Memory", 0x4000C000, 4, base=16 + +sfr = "SC2_RXENDA", "Memory", 0x4000C004, 4, base=16 + +sfr = "SC2_RXBEGB", "Memory", 0x4000C008, 4, base=16 + +sfr = "SC2_RXENDB", "Memory", 0x4000C00C, 4, base=16 + +sfr = "SC2_TXBEGA", "Memory", 0x4000C010, 4, base=16 + +sfr = "SC2_TXENDA", "Memory", 0x4000C014, 4, base=16 + +sfr = "SC2_TXBEGB", "Memory", 0x4000C018, 4, base=16 + +sfr = "SC2_TXENDB", "Memory", 0x4000C01C, 4, base=16 + +sfr = "SC2_RXCNTA", "Memory", 0x4000C020, 4, base=16 + +sfr = "SC2_RXCNTB", "Memory", 0x4000C024, 4, base=16 + +sfr = "SC2_TXCNT", "Memory", 0x4000C028, 4, base=16 + +sfr = "SC2_DMASTAT", "Memory", 0x4000C02C, 4, base=16 +sfr = "SC2_DMASTAT.SC_RXSSEL", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00001C00 +sfr = "SC2_DMASTAT.SC_RXOVFB", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000020 +sfr = "SC2_DMASTAT.SC_RXOVFA", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000010 +sfr = "SC2_DMASTAT.SC_TXACTB", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000008 +sfr = "SC2_DMASTAT.SC_TXACTA", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000004 +sfr = "SC2_DMASTAT.SC_RXACTB", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000002 +sfr = "SC2_DMASTAT.SC_RXACTA", "Memory", 0x4000C02C, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_DMACTRL", "Memory", 0x4000C030, 4, base=16 +sfr = "SC2_DMACTRL.SC_TXDMARST", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000020 +sfr = "SC2_DMACTRL.SC_RXDMARST", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000010 +sfr = "SC2_DMACTRL.SC_TXLODB", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000008 +sfr = "SC2_DMACTRL.SC_TXLODA", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000004 +sfr = "SC2_DMACTRL.SC_RXLODB", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000002 +sfr = "SC2_DMACTRL.SC_RXLODA", "Memory", 0x4000C030, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_RXERRA", "Memory", 0x4000C034, 4, base=16 + +sfr = "SC2_RXERRB", "Memory", 0x4000C038, 4, base=16 + +sfr = "SC2_DATA", "Memory", 0x4000C03C, 4, base=16 + +sfr = "SC2_SPISTAT", "Memory", 0x4000C040, 4, base=16 +sfr = "SC2_SPISTAT.SC_SPITXIDLE", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000008 +sfr = "SC2_SPISTAT.SC_SPITXFREE", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000004 +sfr = "SC2_SPISTAT.SC_SPIRXVAL", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000002 +sfr = "SC2_SPISTAT.SC_SPIRXOVF", "Memory", 0x4000C040, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_TWISTAT", "Memory", 0x4000C044, 4, base=16 +sfr = "SC2_TWISTAT.SC_TWICMDFIN", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000008 +sfr = "SC2_TWISTAT.SC_TWIRXFIN", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000004 +sfr = "SC2_TWISTAT.SC_TWITXFIN", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000002 +sfr = "SC2_TWISTAT.SC_TWIRXNAK", "Memory", 0x4000C044, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_TWICTRL1", "Memory", 0x4000C04C, 4, base=16 +sfr = "SC2_TWICTRL1.SC_TWISTOP", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000008 +sfr = "SC2_TWICTRL1.SC_TWISTART", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000004 +sfr = "SC2_TWICTRL1.SC_TWISEND", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000002 +sfr = "SC2_TWICTRL1.SC_TWIRECV", "Memory", 0x4000C04C, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_TWICTRL2", "Memory", 0x4000C050, 4, base=16 + +sfr = "SC2_MODE", "Memory", 0x4000C054, 4, base=16 + +sfr = "SC2_SPICFG", "Memory", 0x4000C058, 4, base=16 +sfr = "SC2_SPICFG.SC_SPIRXDRV", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000020 +sfr = "SC2_SPICFG.SC_SPIMST", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000010 +sfr = "SC2_SPICFG.SC_SPIRPT", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000008 +sfr = "SC2_SPICFG.SC_SPIORD", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000004 +sfr = "SC2_SPICFG.SC_SPIPHA", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000002 +sfr = "SC2_SPICFG.SC_SPIPOL", "Memory", 0x4000C058, 4, base=16, bitMask=0x00000001 + +sfr = "SC2_RATELIN", "Memory", 0x4000C060, 4, base=16 +sfr = "SC2_RATELIN.SC_RATELIN", "Memory", 0x4000C060, 4, base=16, bitMask=0x0000000F + +sfr = "SC2_RATEEXP", "Memory", 0x4000C064, 4, base=16 +sfr = "SC2_RATEEXP.SC_RATEEXP", "Memory", 0x4000C064, 4, base=16, bitMask=0x0000000F + +sfr = "SC2_RXCNTSAVED", "Memory", 0x4000C070, 4, base=16 + +sfr = "SC1_RXBEGA", "Memory", 0x4000C800, 4, base=16 + +sfr = "SC1_RXENDA", "Memory", 0x4000C804, 4, base=16 + +sfr = "SC1_RXBEGB", "Memory", 0x4000C808, 4, base=16 + +sfr = "SC1_RXENDB", "Memory", 0x4000C80C, 4, base=16 + +sfr = "SC1_TXBEGA", "Memory", 0x4000C810, 4, base=16 + +sfr = "SC1_TXENDA", "Memory", 0x4000C814, 4, base=16 + +sfr = "SC1_TXBEGB", "Memory", 0x4000C818, 4, base=16 + +sfr = "SC1_TXENDB", "Memory", 0x4000C81C, 4, base=16 + +sfr = "SC1_RXCNTA", "Memory", 0x4000C820, 4, base=16 + +sfr = "SC1_RXCNTB", "Memory", 0x4000C824, 4, base=16 + +sfr = "SC1_TXCNT", "Memory", 0x4000C828, 4, base=16 + +sfr = "SC1_DMASTAT", "Memory", 0x4000C82C, 4, base=16 +sfr = "SC1_DMASTAT.SC_RXSSEL", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00001C00 +sfr = "SC1_DMASTAT.SC_RXFRMB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000200 +sfr = "SC1_DMASTAT.SC_RXFRMA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000100 +sfr = "SC1_DMASTAT.SC_RXPARB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000080 +sfr = "SC1_DMASTAT.SC_RXPARA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000040 +sfr = "SC1_DMASTAT.SC_RXOVFB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000020 +sfr = "SC1_DMASTAT.SC_RXOVFA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000010 +sfr = "SC1_DMASTAT.SC_TXACTB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000008 +sfr = "SC1_DMASTAT.SC_TXACTA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000004 +sfr = "SC1_DMASTAT.SC_RXACTB", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000002 +sfr = "SC1_DMASTAT.SC_RXACTA", "Memory", 0x4000C82C, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_DMACTRL", "Memory", 0x4000C830, 4, base=16 +sfr = "SC1_DMACTRL.SC_TXDMARST", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000020 +sfr = "SC1_DMACTRL.SC_RXDMARST", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000010 +sfr = "SC1_DMACTRL.SC_TXLODB", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000008 +sfr = "SC1_DMACTRL.SC_TXLODA", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000004 +sfr = "SC1_DMACTRL.SC_RXLODB", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000002 +sfr = "SC1_DMACTRL.SC_RXLODA", "Memory", 0x4000C830, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_RXERRA", "Memory", 0x4000C834, 4, base=16 + +sfr = "SC1_RXERRB", "Memory", 0x4000C838, 4, base=16 + +sfr = "SC1_DATA", "Memory", 0x4000C83C, 4, base=16 + +sfr = "SC1_SPISTAT", "Memory", 0x4000C840, 4, base=16 +sfr = "SC1_SPISTAT.SC_SPITXIDLE", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000008 +sfr = "SC1_SPISTAT.SC_SPITXFREE", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000004 +sfr = "SC1_SPISTAT.SC_SPIRXVAL", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000002 +sfr = "SC1_SPISTAT.SC_SPIRXOVF", "Memory", 0x4000C840, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_TWISTAT", "Memory", 0x4000C844, 4, base=16 +sfr = "SC1_TWISTAT.SC_TWICMDFIN", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000008 +sfr = "SC1_TWISTAT.SC_TWIRXFIN", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000004 +sfr = "SC1_TWISTAT.SC_TWITXFIN", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000002 +sfr = "SC1_TWISTAT.SC_TWIRXNAK", "Memory", 0x4000C844, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_UARTSTAT", "Memory", 0x4000C848, 4, base=16 +sfr = "SC1_UARTSTAT.SC_UARTTXIDLE", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000040 +sfr = "SC1_UARTSTAT.SC_UARTPARERR", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000020 +sfr = "SC1_UARTSTAT.SC_UARTFRMERR", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000010 +sfr = "SC1_UARTSTAT.SC_UARTRXOVF", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000008 +sfr = "SC1_UARTSTAT.SC_UARTTXFREE", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000004 +sfr = "SC1_UARTSTAT.SC_UARTRXVAL", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000002 +sfr = "SC1_UARTSTAT.SC_UARTCTS", "Memory", 0x4000C848, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_TWICTRL1", "Memory", 0x4000C84C, 4, base=16 +sfr = "SC1_TWICTRL1.SC_TWISTOP", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000008 +sfr = "SC1_TWICTRL1.SC_TWISTART", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000004 +sfr = "SC1_TWICTRL1.SC_TWISEND", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000002 +sfr = "SC1_TWICTRL1.SC_TWIRECV", "Memory", 0x4000C84C, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_TWICTRL2", "Memory", 0x4000C850, 4, base=16 + +sfr = "SC1_MODE", "Memory", 0x4000C854, 4, base=16 + +sfr = "SC1_SPICFG", "Memory", 0x4000C858, 4, base=16 +sfr = "SC1_SPICFG.SC_SPIRXDRV", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000020 +sfr = "SC1_SPICFG.SC_SPIMST", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000010 +sfr = "SC1_SPICFG.SC_SPIRPT", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000008 +sfr = "SC1_SPICFG.SC_SPIORD", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000004 +sfr = "SC1_SPICFG.SC_SPIPHA", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000002 +sfr = "SC1_SPICFG.SC_SPIPOL", "Memory", 0x4000C858, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_UARTCFG", "Memory", 0x4000C85C, 4, base=16 +sfr = "SC1_UARTCFG.SC_UARTAUTO", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000040 +sfr = "SC1_UARTCFG.SC_UARTFLOW", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000020 +sfr = "SC1_UARTCFG.SC_UARTODD", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000010 +sfr = "SC1_UARTCFG.SC_UARTPAR", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000008 +sfr = "SC1_UARTCFG.SC_UART2STP", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000004 +sfr = "SC1_UARTCFG.SC_UART8BIT", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000002 +sfr = "SC1_UARTCFG.SC_UARTRTS", "Memory", 0x4000C85C, 4, base=16, bitMask=0x00000001 + +sfr = "SC1_RATELIN", "Memory", 0x4000C860, 4, base=16 + +sfr = "SC1_RATEEXP", "Memory", 0x4000C864, 4, base=16 + +sfr = "SC1_UARTPER", "Memory", 0x4000C868, 4, base=16 + +sfr = "SC1_UARTFRAC", "Memory", 0x4000C86C, 4, base=16 + +sfr = "SC1_RXCNTSAVED", "Memory", 0x4000C870, 4, base=16 + +sfr = "ADC_CFG", "Memory", 0x4000D004, 4, base=16 +sfr = "ADC_CFG.ADC_PERIOD", "Memory", 0x4000D004, 4, base=16, bitMask=0x0000E000 +sfr = "ADC_CFG.ADC_HVSELP", "Memory", 0x4000D004, 4, base=16, bitMask=0x00001000 +sfr = "ADC_CFG.ADC_HVSELN", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000800 +sfr = "ADC_CFG.ADC_MUXP", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000780 +sfr = "ADC_CFG.ADC_MUXN", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000078 +sfr = "ADC_CFG.ADC_1MHZCLK", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000004 +sfr = "ADC_CFG.ADC_CFGRSVD", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000002 +sfr = "ADC_CFG.ADC_ENABLE", "Memory", 0x4000D004, 4, base=16, bitMask=0x00000001 + +sfr = "ADC_OFFSET", "Memory", 0x4000D008, 4, base=16 + +sfr = "ADC_GAIN", "Memory", 0x4000D00C, 4, base=16 + +sfr = "ADC_DMACFG", "Memory", 0x4000D010, 4, base=16 +sfr = "ADC_DMACFG.ADC_DMARST", "Memory", 0x4000D010, 4, base=16, bitMask=0x00000010 +sfr = "ADC_DMACFG.ADC_DMAAUTOWRAP", "Memory", 0x4000D010, 4, base=16, bitMask=0x00000002 +sfr = "ADC_DMACFG.ADC_DMALOAD", "Memory", 0x4000D010, 4, base=16, bitMask=0x00000001 + +sfr = "ADC_DMASTAT", "Memory", 0x4000D014, 4, base=16 +sfr = "ADC_DMASTAT.ADC_DMAOVF", "Memory", 0x4000D014, 4, base=16, bitMask=0x00000002 +sfr = "ADC_DMASTAT.ADC_DMAACT", "Memory", 0x4000D014, 4, base=16, bitMask=0x00000001 + +sfr = "ADC_DMABEG", "Memory", 0x4000D018, 4, base=16 + +sfr = "ADC_DMASIZE", "Memory", 0x4000D01C, 4, base=16 + +sfr = "ADC_DMACUR", "Memory", 0x4000D020, 4, base=16 + +sfr = "ADC_DMACNT", "Memory", 0x4000D024, 4, base=16 + +sfr = "TIM1_CR1", "Memory", 0x4000E000, 4, base=16 +sfr = "TIM1_CR1.TIM_ARBE", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000080 +sfr = "TIM1_CR1.TIM_CMS", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000060 +sfr = "TIM1_CR1.TIM_DIR", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000010 +sfr = "TIM1_CR1.TIM_OPM", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000008 +sfr = "TIM1_CR1.TIM_URS", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000004 +sfr = "TIM1_CR1.TIM_UDIS", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000002 +sfr = "TIM1_CR1.TIM_CEN", "Memory", 0x4000E000, 4, base=16, bitMask=0x00000001 + +sfr = "TIM1_CR2", "Memory", 0x4000E004, 4, base=16 +sfr = "TIM1_CR2.TIM_TI1S", "Memory", 0x4000E004, 4, base=16, bitMask=0x00000080 +sfr = "TIM1_CR2.TIM_MMS", "Memory", 0x4000E004, 4, base=16, bitMask=0x00000070 + +sfr = "TIM1_SMCR", "Memory", 0x4000E008, 4, base=16 +sfr = "TIM1_SMCR.TIM_ETP", "Memory", 0x4000E008, 4, base=16, bitMask=0x00008000 +sfr = "TIM1_SMCR.TIM_ECE", "Memory", 0x4000E008, 4, base=16, bitMask=0x00004000 +sfr = "TIM1_SMCR.TIM_ETPS", "Memory", 0x4000E008, 4, base=16, bitMask=0x00003000 +sfr = "TIM1_SMCR.TIM_ETF", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000F00 +sfr = "TIM1_SMCR.TIM_MSM", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000080 +sfr = "TIM1_SMCR.TIM_TS", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000070 +sfr = "TIM1_SMCR.TIM_SMS", "Memory", 0x4000E008, 4, base=16, bitMask=0x00000007 + +sfr = "TIM1_EGR", "Memory", 0x4000E014, 4, base=16 +sfr = "TIM1_EGR.TIM_TG", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000040 +sfr = "TIM1_EGR.TIM_CC4G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000010 +sfr = "TIM1_EGR.TIM_CC3G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000008 +sfr = "TIM1_EGR.TIM_CC2G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000004 +sfr = "TIM1_EGR.TIM_CC1G", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000002 +sfr = "TIM1_EGR.TIM_UG", "Memory", 0x4000E014, 4, base=16, bitMask=0x00000001 + +sfr = "TIM1_CCMR1", "Memory", 0x4000E018, 4, base=16 +sfr = "TIM1_CCMR1.TIM_IC2F", "Memory", 0x4000E018, 4, base=16, bitMask=0x0000F000 +sfr = "TIM1_CCMR1.TIM_IC2PSC", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000C00 +sfr = "TIM1_CCMR1.TIM_IC1F", "Memory", 0x4000E018, 4, base=16, bitMask=0x000000F0 +sfr = "TIM1_CCMR1.TIM_IC1PSC", "Memory", 0x4000E018, 4, base=16, bitMask=0x0000000C +sfr = "TIM1_CCMR1.TIM_OC2CE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00008000 +sfr = "TIM1_CCMR1.TIM_OC2M", "Memory", 0x4000E018, 4, base=16, bitMask=0x00007000 +sfr = "TIM1_CCMR1.TIM_OC2BE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000800 +sfr = "TIM1_CCMR1.TIM_OC2FE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000400 +sfr = "TIM1_CCMR1.TIM_CC2S", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000300 +sfr = "TIM1_CCMR1.TIM_OC1CE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000080 +sfr = "TIM1_CCMR1.TIM_OC1M", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000070 +sfr = "TIM1_CCMR1.TIM_OC1PE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000008 +sfr = "TIM1_CCMR1.TIM_OC1FE", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000004 +sfr = "TIM1_CCMR1.TIM_CC1S", "Memory", 0x4000E018, 4, base=16, bitMask=0x00000003 + +sfr = "TIM1_CCMR2", "Memory", 0x4000E01C, 4, base=16 +sfr = "TIM1_CCMR2.TIM_IC4F", "Memory", 0x4000E01C, 4, base=16, bitMask=0x0000F000 +sfr = "TIM1_CCMR2.TIM_IC4PSC", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000C00 +sfr = "TIM1_CCMR2.TIM_IC3F", "Memory", 0x4000E01C, 4, base=16, bitMask=0x000000F0 +sfr = "TIM1_CCMR2.TIM_IC3PSC", "Memory", 0x4000E01C, 4, base=16, bitMask=0x0000000C +sfr = "TIM1_CCMR2.TIM_OC4CE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00008000 +sfr = "TIM1_CCMR2.TIM_OC4M", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00007000 +sfr = "TIM1_CCMR2.TIM_OC4BE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000800 +sfr = "TIM1_CCMR2.TIM_OC4FE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000400 +sfr = "TIM1_CCMR2.TIM_CC4S", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000300 +sfr = "TIM1_CCMR2.TIM_OC3CE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000080 +sfr = "TIM1_CCMR2.TIM_OC3M", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000070 +sfr = "TIM1_CCMR2.TIM_OC3BE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000008 +sfr = "TIM1_CCMR2.TIM_OC3FE", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000004 +sfr = "TIM1_CCMR2.TIM_CC3S", "Memory", 0x4000E01C, 4, base=16, bitMask=0x00000003 + +sfr = "TIM1_CCER", "Memory", 0x4000E020, 4, base=16 +sfr = "TIM1_CCER.TIM_CC4P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00002000 +sfr = "TIM1_CCER.TIM_CC4E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00001000 +sfr = "TIM1_CCER.TIM_CC3P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000200 +sfr = "TIM1_CCER.TIM_CC3E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000100 +sfr = "TIM1_CCER.TIM_CC2P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000020 +sfr = "TIM1_CCER.TIM_CC2E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000010 +sfr = "TIM1_CCER.TIM_CC1P", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000002 +sfr = "TIM1_CCER.TIM_CC1E", "Memory", 0x4000E020, 4, base=16, bitMask=0x00000001 + +sfr = "TIM1_CNT", "Memory", 0x4000E024, 4, base=16 + +sfr = "TIM1_PSC", "Memory", 0x4000E028, 4, base=16 + +sfr = "TIM1_ARR", "Memory", 0x4000E02C, 4, base=16 + +sfr = "TIM1_CCR1", "Memory", 0x4000E034, 4, base=16 + +sfr = "TIM1_CCR2", "Memory", 0x4000E038, 4, base=16 + +sfr = "TIM1_CCR3", "Memory", 0x4000E03C, 4, base=16 + +sfr = "TIM1_CCR4", "Memory", 0x4000E040, 4, base=16 + +sfr = "TIM1_OR", "Memory", 0x4000E050, 4, base=16 +sfr = "TIM1_OR.TIM_ORRSVD", "Memory", 0x4000E050, 4, base=16, bitMask=0x00000008 +sfr = "TIM1_OR.TIM_CLKMSKEN", "Memory", 0x4000E050, 4, base=16, bitMask=0x00000004 +sfr = "TIM1_OR.TIM1_EXTRIGSEL", "Memory", 0x4000E050, 4, base=16, bitMask=0x00000003 + +sfr = "TIM2_CR1", "Memory", 0x4000F000, 4, base=16 +sfr = "TIM2_CR1.TIM_ARBE", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000080 +sfr = "TIM2_CR1.TIM_CMS", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000060 +sfr = "TIM2_CR1.TIM_DIR", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000010 +sfr = "TIM2_CR1.TIM_OPM", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000008 +sfr = "TIM2_CR1.TIM_URS", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000004 +sfr = "TIM2_CR1.TIM_UDIS", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000002 +sfr = "TIM2_CR1.TIM_CEN", "Memory", 0x4000F000, 4, base=16, bitMask=0x00000001 + +sfr = "TIM2_CR2", "Memory", 0x4000F004, 4, base=16 +sfr = "TIM2_CR2.TIM_TI1S", "Memory", 0x4000F004, 4, base=16, bitMask=0x00000080 +sfr = "TIM2_CR2.TIM_MMS", "Memory", 0x4000F004, 4, base=16, bitMask=0x00000070 + +sfr = "TIM2_SMCR", "Memory", 0x4000F008, 4, base=16 +sfr = "TIM2_SMCR.TIM_ETP", "Memory", 0x4000F008, 4, base=16, bitMask=0x00008000 +sfr = "TIM2_SMCR.TIM_ECE", "Memory", 0x4000F008, 4, base=16, bitMask=0x00004000 +sfr = "TIM2_SMCR.TIM_ETPS", "Memory", 0x4000F008, 4, base=16, bitMask=0x00003000 +sfr = "TIM2_SMCR.TIM_ETF", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000F00 +sfr = "TIM2_SMCR.TIM_MSM", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000080 +sfr = "TIM2_SMCR.TIM_TS", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000070 +sfr = "TIM2_SMCR.TIM_SMS", "Memory", 0x4000F008, 4, base=16, bitMask=0x00000007 + +sfr = "TIM2_EGR", "Memory", 0x4000F014, 4, base=16 +sfr = "TIM2_EGR.TIM_TG", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000040 +sfr = "TIM2_EGR.TIM_CC4G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000010 +sfr = "TIM2_EGR.TIM_CC3G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000008 +sfr = "TIM2_EGR.TIM_CC2G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000004 +sfr = "TIM2_EGR.TIM_CC1G", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000002 +sfr = "TIM2_EGR.TIM_UG", "Memory", 0x4000F014, 4, base=16, bitMask=0x00000001 + +sfr = "TIM2_CCMR1", "Memory", 0x4000F018, 4, base=16 +sfr = "TIM2_CCMR1.TIM_IC2F", "Memory", 0x4000F018, 4, base=16, bitMask=0x0000F000 +sfr = "TIM2_CCMR1.TIM_IC2PSC", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000C00 +sfr = "TIM2_CCMR1.TIM_IC1F", "Memory", 0x4000F018, 4, base=16, bitMask=0x000000F0 +sfr = "TIM2_CCMR1.TIM_IC1PSC", "Memory", 0x4000F018, 4, base=16, bitMask=0x0000000C +sfr = "TIM2_CCMR1.TIM_OC2CE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00008000 +sfr = "TIM2_CCMR1.TIM_OC2M", "Memory", 0x4000F018, 4, base=16, bitMask=0x00007000 +sfr = "TIM2_CCMR1.TIM_OC2BE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000800 +sfr = "TIM2_CCMR1.TIM_OC2FE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000400 +sfr = "TIM2_CCMR1.TIM_CC2S", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000300 +sfr = "TIM2_CCMR1.TIM_OC1CE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000080 +sfr = "TIM2_CCMR1.TIM_OC1M", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000070 +sfr = "TIM2_CCMR1.TIM_OC1PE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000008 +sfr = "TIM2_CCMR1.TIM_OC1FE", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000004 +sfr = "TIM2_CCMR1.TIM_CC1S", "Memory", 0x4000F018, 4, base=16, bitMask=0x00000003 + +sfr = "TIM2_CCMR2", "Memory", 0x4000F01C, 4, base=16 +sfr = "TIM2_CCMR2.TIM_IC4F", "Memory", 0x4000F01C, 4, base=16, bitMask=0x0000F000 +sfr = "TIM2_CCMR2.TIM_IC4PSC", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000C00 +sfr = "TIM2_CCMR2.TIM_IC3F", "Memory", 0x4000F01C, 4, base=16, bitMask=0x000000F0 +sfr = "TIM2_CCMR2.TIM_IC3PSC", "Memory", 0x4000F01C, 4, base=16, bitMask=0x0000000C +sfr = "TIM2_CCMR2.TIM_OC4CE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00008000 +sfr = "TIM2_CCMR2.TIM_OC4M", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00007000 +sfr = "TIM2_CCMR2.TIM_OC4BE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000800 +sfr = "TIM2_CCMR2.TIM_OC4FE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000400 +sfr = "TIM2_CCMR2.TIM_CC4S", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000300 +sfr = "TIM2_CCMR2.TIM_OC3CE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000080 +sfr = "TIM2_CCMR2.TIM_OC3M", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000070 +sfr = "TIM2_CCMR2.TIM_OC3BE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000008 +sfr = "TIM2_CCMR2.TIM_OC3FE", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000004 +sfr = "TIM2_CCMR2.TIM_CC3S", "Memory", 0x4000F01C, 4, base=16, bitMask=0x00000003 + +sfr = "TIM2_CCER", "Memory", 0x4000F020, 4, base=16 +sfr = "TIM2_CCER.TIM_CC4P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00002000 +sfr = "TIM2_CCER.TIM_CC4E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00001000 +sfr = "TIM2_CCER.TIM_CC3P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000200 +sfr = "TIM2_CCER.TIM_CC3E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000100 +sfr = "TIM2_CCER.TIM_CC2P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000020 +sfr = "TIM2_CCER.TIM_CC2E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000010 +sfr = "TIM2_CCER.TIM_CC1P", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000002 +sfr = "TIM2_CCER.TIM_CC1E", "Memory", 0x4000F020, 4, base=16, bitMask=0x00000001 + +sfr = "TIM2_CNT", "Memory", 0x4000F024, 4, base=16 + +sfr = "TIM2_PSC", "Memory", 0x4000F028, 4, base=16 + +sfr = "TIM2_ARR", "Memory", 0x4000F02C, 4, base=16 + +sfr = "TIM2_CCR1", "Memory", 0x4000F034, 4, base=16 + +sfr = "TIM2_CCR2", "Memory", 0x4000F038, 4, base=16 + +sfr = "TIM2_CCR3", "Memory", 0x4000F03C, 4, base=16 + +sfr = "TIM2_CCR4", "Memory", 0x4000F040, 4, base=16 + +sfr = "TIM2_OR", "Memory", 0x4000F050, 4, base=16 +sfr = "TIM2_OR.TIM_REMAPC4", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000080 +sfr = "TIM2_OR.TIM_REMAPC3", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000040 +sfr = "TIM2_OR.TIM_REMAPC2", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000020 +sfr = "TIM2_OR.TIM_REMAPC1", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000010 +sfr = "TIM2_OR.TIM_ORRSVD", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000008 +sfr = "TIM2_OR.TIM_CLKMSKEN", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000004 +sfr = "TIM2_OR.TIM1_EXTRIGSEL", "Memory", 0x4000F050, 4, base=16, bitMask=0x00000003 + +sfr = "INT_CFGSET", "Memory", 0xE000E100, 4, base=16 +sfr = "INT_CFGSET.INT_DEBUG", "Memory", 0xE000E100, 4, base=16, bitMask=0x00010000 +sfr = "INT_CFGSET.INT_IRQD", "Memory", 0xE000E100, 4, base=16, bitMask=0x00008000 +sfr = "INT_CFGSET.INT_IRQC", "Memory", 0xE000E100, 4, base=16, bitMask=0x00004000 +sfr = "INT_CFGSET.INT_IRQB", "Memory", 0xE000E100, 4, base=16, bitMask=0x00002000 +sfr = "INT_CFGSET.INT_IRQA", "Memory", 0xE000E100, 4, base=16, bitMask=0x00001000 +sfr = "INT_CFGSET.INT_ADC", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000800 +sfr = "INT_CFGSET.INT_MACRX", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000400 +sfr = "INT_CFGSET.INT_MACTX", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000200 +sfr = "INT_CFGSET.INT_MACTMR", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000100 +sfr = "INT_CFGSET.INT_SEC", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000080 +sfr = "INT_CFGSET.INT_SC2", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000040 +sfr = "INT_CFGSET.INT_SC1", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000020 +sfr = "INT_CFGSET.INT_SLEEPTMR", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000010 +sfr = "INT_CFGSET.INT_BB", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000008 +sfr = "INT_CFGSET.INT_MGMT", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000004 +sfr = "INT_CFGSET.INT_TIM2", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000002 +sfr = "INT_CFGSET.INT_TIM1", "Memory", 0xE000E100, 4, base=16, bitMask=0x00000001 + +sfr = "INT_CFGCLR", "Memory", 0xE000E180, 4, base=16 +sfr = "INT_CFGCLR.INT_DEBUG", "Memory", 0xE000E180, 4, base=16, bitMask=0x00010000 +sfr = "INT_CFGCLR.INT_IRQD", "Memory", 0xE000E180, 4, base=16, bitMask=0x00008000 +sfr = "INT_CFGCLR.INT_IRQC", "Memory", 0xE000E180, 4, base=16, bitMask=0x00004000 +sfr = "INT_CFGCLR.INT_IRQB", "Memory", 0xE000E180, 4, base=16, bitMask=0x00002000 +sfr = "INT_CFGCLR.INT_IRQA", "Memory", 0xE000E180, 4, base=16, bitMask=0x00001000 +sfr = "INT_CFGCLR.INT_ADC", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000800 +sfr = "INT_CFGCLR.INT_MACRX", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000400 +sfr = "INT_CFGCLR.INT_MACTX", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000200 +sfr = "INT_CFGCLR.INT_MACTMR", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000100 +sfr = "INT_CFGCLR.INT_SEC", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000080 +sfr = "INT_CFGCLR.INT_SC2", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000040 +sfr = "INT_CFGCLR.INT_SC1", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000020 +sfr = "INT_CFGCLR.INT_SLEEPTMR", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000010 +sfr = "INT_CFGCLR.INT_BB", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000008 +sfr = "INT_CFGCLR.INT_MGMT", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000004 +sfr = "INT_CFGCLR.INT_TIM2", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000002 +sfr = "INT_CFGCLR.INT_TIM1", "Memory", 0xE000E180, 4, base=16, bitMask=0x00000001 + +sfr = "INT_PENDSET", "Memory", 0xE000E200, 4, base=16 +sfr = "INT_PENDSET.INT_DEBUG", "Memory", 0xE000E200, 4, base=16, bitMask=0x00010000 +sfr = "INT_PENDSET.INT_IRQD", "Memory", 0xE000E200, 4, base=16, bitMask=0x00008000 +sfr = "INT_PENDSET.INT_IRQC", "Memory", 0xE000E200, 4, base=16, bitMask=0x00004000 +sfr = "INT_PENDSET.INT_IRQB", "Memory", 0xE000E200, 4, base=16, bitMask=0x00002000 +sfr = "INT_PENDSET.INT_IRQA", "Memory", 0xE000E200, 4, base=16, bitMask=0x00001000 +sfr = "INT_PENDSET.INT_ADC", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000800 +sfr = "INT_PENDSET.INT_MACRX", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000400 +sfr = "INT_PENDSET.INT_MACTX", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000200 +sfr = "INT_PENDSET.INT_MACTMR", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000100 +sfr = "INT_PENDSET.INT_SEC", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000080 +sfr = "INT_PENDSET.INT_SC2", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000040 +sfr = "INT_PENDSET.INT_SC1", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000020 +sfr = "INT_PENDSET.INT_SLEEPTMR", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000010 +sfr = "INT_PENDSET.INT_BB", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000008 +sfr = "INT_PENDSET.INT_MGMT", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000004 +sfr = "INT_PENDSET.INT_TIM2", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000002 +sfr = "INT_PENDSET.INT_TIM1", "Memory", 0xE000E200, 4, base=16, bitMask=0x00000001 + +sfr = "INT_PENDCLR", "Memory", 0xE000E280, 4, base=16 +sfr = "INT_PENDCLR.INT_DEBUG", "Memory", 0xE000E280, 4, base=16, bitMask=0x00010000 +sfr = "INT_PENDCLR.INT_IRQD", "Memory", 0xE000E280, 4, base=16, bitMask=0x00008000 +sfr = "INT_PENDCLR.INT_IRQC", "Memory", 0xE000E280, 4, base=16, bitMask=0x00004000 +sfr = "INT_PENDCLR.INT_IRQB", "Memory", 0xE000E280, 4, base=16, bitMask=0x00002000 +sfr = "INT_PENDCLR.INT_IRQA", "Memory", 0xE000E280, 4, base=16, bitMask=0x00001000 +sfr = "INT_PENDCLR.INT_ADC", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000800 +sfr = "INT_PENDCLR.INT_MACRX", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000400 +sfr = "INT_PENDCLR.INT_MACTX", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000200 +sfr = "INT_PENDCLR.INT_MACTMR", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000100 +sfr = "INT_PENDCLR.INT_SEC", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000080 +sfr = "INT_PENDCLR.INT_SC2", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000040 +sfr = "INT_PENDCLR.INT_SC1", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000020 +sfr = "INT_PENDCLR.INT_SLEEPTMR", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000010 +sfr = "INT_PENDCLR.INT_BB", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000008 +sfr = "INT_PENDCLR.INT_MGMT", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000004 +sfr = "INT_PENDCLR.INT_TIM2", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000002 +sfr = "INT_PENDCLR.INT_TIM1", "Memory", 0xE000E280, 4, base=16, bitMask=0x00000001 + +sfr = "INT_ACTIVE", "Memory", 0xE000E300, 4, base=16 +sfr = "INT_ACTIVE.INT_DEBUG", "Memory", 0xE000E300, 4, base=16, bitMask=0x00010000 +sfr = "INT_ACTIVE.INT_IRQD", "Memory", 0xE000E300, 4, base=16, bitMask=0x00008000 +sfr = "INT_ACTIVE.INT_IRQC", "Memory", 0xE000E300, 4, base=16, bitMask=0x00004000 +sfr = "INT_ACTIVE.INT_IRQB", "Memory", 0xE000E300, 4, base=16, bitMask=0x00002000 +sfr = "INT_ACTIVE.INT_IRQA", "Memory", 0xE000E300, 4, base=16, bitMask=0x00001000 +sfr = "INT_ACTIVE.INT_ADC", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000800 +sfr = "INT_ACTIVE.INT_MACRX", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000400 +sfr = "INT_ACTIVE.INT_MACTX", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000200 +sfr = "INT_ACTIVE.INT_MACTMR", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000100 +sfr = "INT_ACTIVE.INT_SEC", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000080 +sfr = "INT_ACTIVE.INT_SC2", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000040 +sfr = "INT_ACTIVE.INT_SC1", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000020 +sfr = "INT_ACTIVE.INT_SLEEPTMR", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000010 +sfr = "INT_ACTIVE.INT_BB", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000008 +sfr = "INT_ACTIVE.INT_MGMT", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000004 +sfr = "INT_ACTIVE.INT_TIM2", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000002 +sfr = "INT_ACTIVE.INT_TIM1", "Memory", 0xE000E300, 4, base=16, bitMask=0x00000001 + +sfr = "SCS_AFSR", "Memory", 0xE000ED3C, 4, base=16 +sfr = "SCS_AFSR.WRONGSIZE", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000008 +sfr = "SCS_AFSR.PROTECTED", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000004 +sfr = "SCS_AFSR.RESERVED", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000002 +sfr = "SCS_AFSR.MISSED", "Memory", 0xE000ED3C, 4, base=16, bitMask=0x00000001 + + + +; Group info for SFR Window. +[SfrGroupInfo] +group = "GPIO" , "GPIO_PACFGL" , "GPIO_PACFGH" , "GPIO_PAIN" , "GPIO_PAOUT" , "GPIO_PASET" , "GPIO_PACLR" , "GPIO_PBCFGL" , "GPIO_PBCFGH" , "GPIO_PBIN" , "GPIO_PBOUT" , "GPIO_PBSET" , "GPIO_PBCLR" , "GPIO_PCCFGL" , "GPIO_PCCFGH" , "GPIO_PCIN" , "GPIO_PCOUT" , "GPIO_PCSET" , "GPIO_PCCLR" , "GPIO_DBGCFG" , "GPIO_DBGSTAT" +group = "Top-level Interrupts" , "INT_CFGSET" , "INT_CFGCLR" , "INT_PENDSET" , "INT_PENDCLR" , "INT_MISS" , "INT_ACTIVE" , "SCS_AFSR" +group = "External Interrupts" , "GPIO_IRQCSEL" , "GPIO_IRQDSEL" , "GPIO_INTCFGA" , "GPIO_INTCFGB" , "GPIO_INTCFGC" , "GPIO_INTCFGD" , "INT_GPIOFLAG" +group = "Serial Controller 1" , "INT_SC1CFG" , "SC1_INTMODE" , "INT_SC1FLAG" , "SC1_RXBEGA" , "SC1_RXENDA" , "SC1_RXBEGB" , "SC1_RXENDB" , "SC1_TXBEGA" , "SC1_TXENDA" , "SC1_TXBEGB" , "SC1_TXENDB" , "SC1_RXCNTA" , "SC1_RXCNTB" , "SC1_TXCNT" , "SC1_DMASTAT" , "SC1_DMACTRL" , "SC1_RXERRA" , "SC1_RXERRB" , "SC1_DATA" , "SC1_SPISTAT" , "SC1_TWISTAT" , "SC1_UARTSTAT" , "SC1_TWICTRL1" , "SC1_TWICTRL2" , "SC1_MODE" , "SC1_SPICFG" , "SC1_UARTCFG" , "SC1_RATELIN" , "SC1_RATEEXP" , "SC1_UARTPER" , "SC1_UARTFRAC" , "SC1_RXCNTSAVED" +group = "Serial Controller 2" , "INT_SC2CFG" , "SC2_INTMODE" , "INT_SC2FLAG" , "SC2_RXBEGA" , "SC2_RXENDA" , "SC2_RXBEGB" , "SC2_RXENDB" , "SC2_TXBEGA" , "SC2_TXENDA" , "SC2_TXBEGB" , "SC2_TXENDB" , "SC2_RXCNTA" , "SC2_RXCNTB" , "SC2_TXCNT" , "SC2_DMASTAT" , "SC2_DMACTRL" , "SC2_RXERRA" , "SC2_RXERRB" , "SC2_DATA" , "SC2_SPISTAT" , "SC2_TWISTAT" , "SC2_TWICTRL1" , "SC2_TWICTRL2" , "SC2_MODE" , "SC2_SPICFG" , "SC2_RATELIN" , "SC2_RATEEXP" , "SC2_RXCNTSAVED" +group = "ADC" , "INT_ADCCFG" , "INT_ADCFLAG" , "ADC_CFG" , "ADC_OFFSET" , "ADC_GAIN" , "ADC_DMACFG" , "ADC_DMASTAT" , "ADC_DMABEG" , "ADC_DMASIZE" , "ADC_DMACUR" , "ADC_DMACNT" +group = "Timer 1" , "INT_TIM1CFG" , "INT_TIM1FLAG" , "INT_TIM1MISS" , "TIM1_CR1" , "TIM1_CR2" , "TIM1_SMCR" , "TIM1_EGR" , "TIM1_CCMR1" , "TIM1_CCMR2" , "TIM1_CCER" , "TIM1_CNT" , "TIM1_PSC" , "TIM1_ARR" , "TIM1_CCR1" , "TIM1_CCR2" , "TIM1_CCR3" , "TIM1_CCR4" , "TIM1_OR" +group = "Timer 2" , "INT_TIM2CFG" , "INT_TIM2FLAG" , "INT_TIM2MISS" ,"TIM2_CR1" , "TIM2_CR2" , "TIM2_SMCR" , "TIM2_EGR" , "TIM2_CCMR1" , "TIM2_CCMR2" , "TIM2_CCER" , "TIM2_CNT" , "TIM2_PSC" , "TIM2_ARR" , "TIM2_CCR1" , "TIM2_CCR2" , "TIM2_CCR3" , "TIM2_CCR4" , "TIM2_OR" +group = "Wake-Up Controls" , "GPIO_PAWAKE" , "GPIO_PBWAKE" , "GPIO_PCWAKE" , "GPIO_WAKEFILT" diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h new file mode 100644 index 000000000..31ab3b216 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h @@ -0,0 +1,11541 @@ +#ifndef __REGS_H__ +#define __REGS_H__ 1 + + +/* FLASH_BASE block */ +#define DATA_FLASH_BASE_BASE (0x00000000u) +#define DATA_FLASH_BASE_END (0x0001FFFFu) +#define DATA_FLASH_BASE_SIZE (DATA_FLASH_BASE_END - DATA_FLASH_BASE_BASE + 1) + +/* FLASH block */ +#define DATA_FLASH_BASE (0x08000000u) +#define DATA_FLASH_END (0x0801FFFFu) +#define DATA_FLASH_SIZE (DATA_FLASH_END - DATA_FLASH_BASE + 1) + +/* BIG_INFO_BASE block */ +#define DATA_BIG_INFO_BASE_BASE (0x00000000u) +#define DATA_BIG_INFO_BASE_END (0x000007FFu) +#define DATA_BIG_INFO_BASE_SIZE (DATA_BIG_INFO_BASE_END - DATA_BIG_INFO_BASE_BASE + 1) + +/* BIG_INFO block */ +#define DATA_BIG_INFO_BASE (0x08040000u) +#define DATA_BIG_INFO_END (0x080407FFu) +#define DATA_BIG_INFO_SIZE (DATA_BIG_INFO_END - DATA_BIG_INFO_BASE + 1) + +/* SMALL_INFO block */ +#define DATA_SMALL_INFO_BASE (0x08040800u) +#define DATA_SMALL_INFO_END (0x080409FFu) +#define DATA_SMALL_INFO_SIZE (DATA_SMALL_INFO_END - DATA_SMALL_INFO_BASE + 1) + +/* SRAM block */ +#define DATA_SRAM_BASE (0x20000000u) +#define DATA_SRAM_END (0x20001FFFu) +#define DATA_SRAM_SIZE (DATA_SRAM_END - DATA_SRAM_BASE + 1) + +/* CM_HV block */ +#define DATA_CM_HV_BASE (0x40000000u) +#define DATA_CM_HV_END (0x40000044u) +#define DATA_CM_HV_SIZE (DATA_CM_HV_END - DATA_CM_HV_BASE + 1) + +#define HV_SPARE *((volatile int32u *)0x40000000u) +#define HV_SPARE_REG *((volatile int32u *)0x40000000u) +#define HV_SPARE_ADDR (0x40000000u) +#define HV_SPARE_RESET (0x00000000u) + /* HV_SPARE field */ + #define HV_SPARE_HV_SPARE (0x000000FFu) + #define HV_SPARE_HV_SPARE_MASK (0x000000FFu) + #define HV_SPARE_HV_SPARE_BIT (0) + #define HV_SPARE_HV_SPARE_BITS (8) + +#define EVENT_CTRL *((volatile int32u *)0x40000004u) +#define EVENT_CTRL_REG *((volatile int32u *)0x40000004u) +#define EVENT_CTRL_ADDR (0x40000004u) +#define EVENT_CTRL_RESET (0x00000000u) + /* LV_FREEZE field */ + #define LV_FREEZE (0x00000002u) + #define LV_FREEZE_MASK (0x00000002u) + #define LV_FREEZE_BIT (1) + #define LV_FREEZE_BITS (1) + +#define SLEEPTMR_CLKEN *((volatile int32u *)0x40000008u) +#define SLEEPTMR_CLKEN_REG *((volatile int32u *)0x40000008u) +#define SLEEPTMR_CLKEN_ADDR (0x40000008u) +#define SLEEPTMR_CLKEN_RESET (0x00000002u) + /* SLEEPTMR_CLK10KEN field */ + #define SLEEPTMR_CLK10KEN (0x00000002u) + #define SLEEPTMR_CLK10KEN_MASK (0x00000002u) + #define SLEEPTMR_CLK10KEN_BIT (1) + #define SLEEPTMR_CLK10KEN_BITS (1) + /* SLEEPTMR_CLK32KEN field */ + #define SLEEPTMR_CLK32KEN (0x00000001u) + #define SLEEPTMR_CLK32KEN_MASK (0x00000001u) + #define SLEEPTMR_CLK32KEN_BIT (0) + #define SLEEPTMR_CLK32KEN_BITS (1) + +#define CLKRC_TUNE *((volatile int32u *)0x4000000Cu) +#define CLKRC_TUNE_REG *((volatile int32u *)0x4000000Cu) +#define CLKRC_TUNE_ADDR (0x4000000Cu) +#define CLKRC_TUNE_RESET (0x00000000u) + /* CLKRC_TUNE_FIELD field */ + #define CLKRC_TUNE_FIELD (0x0000000Fu) + #define CLKRC_TUNE_FIELD_MASK (0x0000000Fu) + #define CLKRC_TUNE_FIELD_BIT (0) + #define CLKRC_TUNE_FIELD_BITS (4) + +#define CLK1K_CAL *((volatile int32u *)0x40000010u) +#define CLK1K_CAL_REG *((volatile int32u *)0x40000010u) +#define CLK1K_CAL_ADDR (0x40000010u) +#define CLK1K_CAL_RESET (0x00005000u) + /* CLK1K_INTEGER field */ + #define CLK1K_INTEGER (0x0000F800u) + #define CLK1K_INTEGER_MASK (0x0000F800u) + #define CLK1K_INTEGER_BIT (11) + #define CLK1K_INTEGER_BITS (5) + /* CLK1K_FRACTIONAL field */ + #define CLK1K_FRACTIONAL (0x000007FFu) + #define CLK1K_FRACTIONAL_MASK (0x000007FFu) + #define CLK1K_FRACTIONAL_BIT (0) + #define CLK1K_FRACTIONAL_BITS (11) + +#define REGEN_DSLEEP *((volatile int32u *)0x40000014u) +#define REGEN_DSLEEP_REG *((volatile int32u *)0x40000014u) +#define REGEN_DSLEEP_ADDR (0x40000014u) +#define REGEN_DSLEEP_RESET (0x00000001u) + /* REGEN_DSLEEP_FIELD field */ + #define REGEN_DSLEEP_FIELD (0x00000001u) + #define REGEN_DSLEEP_FIELD_MASK (0x00000001u) + #define REGEN_DSLEEP_FIELD_BIT (0) + #define REGEN_DSLEEP_FIELD_BITS (1) + +#define VREG *((volatile int32u *)0x40000018u) +#define VREG_REG *((volatile int32u *)0x40000018u) +#define VREG_ADDR (0x40000018u) +#define VREG_RESET (0x00000207u) + /* VREF_EN field */ + #define VREG_VREF_EN (0x00008000u) + #define VREG_VREF_EN_MASK (0x00008000u) + #define VREG_VREF_EN_BIT (15) + #define VREG_VREF_EN_BITS (1) + /* VREF_TEST field */ + #define VREG_VREF_TEST (0x00004000u) + #define VREG_VREF_TEST_MASK (0x00004000u) + #define VREG_VREF_TEST_BIT (14) + #define VREG_VREF_TEST_BITS (1) + /* VREG_1V8_EN field */ + #define VREG_VREG_1V8_EN (0x00000800u) + #define VREG_VREG_1V8_EN_MASK (0x00000800u) + #define VREG_VREG_1V8_EN_BIT (11) + #define VREG_VREG_1V8_EN_BITS (1) + /* VREG_1V8_TEST field */ + #define VREG_VREG_1V8_TEST (0x00000400u) + #define VREG_VREG_1V8_TEST_MASK (0x00000400u) + #define VREG_VREG_1V8_TEST_BIT (10) + #define VREG_VREG_1V8_TEST_BITS (1) + /* VREG_1V8_TRIM field */ + #define VREG_VREG_1V8_TRIM (0x00000380u) + #define VREG_VREG_1V8_TRIM_MASK (0x00000380u) + #define VREG_VREG_1V8_TRIM_BIT (7) + #define VREG_VREG_1V8_TRIM_BITS (3) + /* VREG_1V2_EN field */ + #define VREG_VREG_1V2_EN (0x00000010u) + #define VREG_VREG_1V2_EN_MASK (0x00000010u) + #define VREG_VREG_1V2_EN_BIT (4) + #define VREG_VREG_1V2_EN_BITS (1) + /* VREG_1V2_TEST field */ + #define VREG_VREG_1V2_TEST (0x00000008u) + #define VREG_VREG_1V2_TEST_MASK (0x00000008u) + #define VREG_VREG_1V2_TEST_BIT (3) + #define VREG_VREG_1V2_TEST_BITS (1) + /* VREG_1V2_TRIM field */ + #define VREG_VREG_1V2_TRIM (0x00000007u) + #define VREG_VREG_1V2_TRIM_MASK (0x00000007u) + #define VREG_VREG_1V2_TRIM_BIT (0) + #define VREG_VREG_1V2_TRIM_BITS (3) + +#define WAKE_SEL *((volatile int32u *)0x40000020u) +#define WAKE_SEL_REG *((volatile int32u *)0x40000020u) +#define WAKE_SEL_ADDR (0x40000020u) +#define WAKE_SEL_RESET (0x00000200u) + /* WAKE_CSYSPWRUPREQ field */ + #define WAKE_CSYSPWRUPREQ (0x00000200u) + #define WAKE_CSYSPWRUPREQ_MASK (0x00000200u) + #define WAKE_CSYSPWRUPREQ_BIT (9) + #define WAKE_CSYSPWRUPREQ_BITS (1) + /* WAKE_CDBGPWRUPREQ field */ + #define WAKE_CDBGPWRUPREQ (0x00000100u) + #define WAKE_CDBGPWRUPREQ_MASK (0x00000100u) + #define WAKE_CDBGPWRUPREQ_BIT (8) + #define WAKE_CDBGPWRUPREQ_BITS (1) + /* WAKE_WAKE_CORE field */ + #define WAKE_WAKE_CORE (0x00000080u) + #define WAKE_WAKE_CORE_MASK (0x00000080u) + #define WAKE_WAKE_CORE_BIT (7) + #define WAKE_WAKE_CORE_BITS (1) + /* WAKE_SLEEPTMRWRAP field */ + #define WAKE_SLEEPTMRWRAP (0x00000040u) + #define WAKE_SLEEPTMRWRAP_MASK (0x00000040u) + #define WAKE_SLEEPTMRWRAP_BIT (6) + #define WAKE_SLEEPTMRWRAP_BITS (1) + /* WAKE_SLEEPTMRCMPB field */ + #define WAKE_SLEEPTMRCMPB (0x00000020u) + #define WAKE_SLEEPTMRCMPB_MASK (0x00000020u) + #define WAKE_SLEEPTMRCMPB_BIT (5) + #define WAKE_SLEEPTMRCMPB_BITS (1) + /* WAKE_SLEEPTMRCMPA field */ + #define WAKE_SLEEPTMRCMPA (0x00000010u) + #define WAKE_SLEEPTMRCMPA_MASK (0x00000010u) + #define WAKE_SLEEPTMRCMPA_BIT (4) + #define WAKE_SLEEPTMRCMPA_BITS (1) + /* WAKE_IRQD field */ + #define WAKE_IRQD (0x00000008u) + #define WAKE_IRQD_MASK (0x00000008u) + #define WAKE_IRQD_BIT (3) + #define WAKE_IRQD_BITS (1) + /* WAKE_SC2 field */ + #define WAKE_SC2 (0x00000004u) + #define WAKE_SC2_MASK (0x00000004u) + #define WAKE_SC2_BIT (2) + #define WAKE_SC2_BITS (1) + /* WAKE_SC1 field */ + #define WAKE_SC1 (0x00000002u) + #define WAKE_SC1_MASK (0x00000002u) + #define WAKE_SC1_BIT (1) + #define WAKE_SC1_BITS (1) + /* GPIO_WAKE field */ + #define GPIO_WAKE (0x00000001u) + #define GPIO_WAKE_MASK (0x00000001u) + #define GPIO_WAKE_BIT (0) + #define GPIO_WAKE_BITS (1) + +#define WAKE_CORE *((volatile int32u *)0x40000024u) +#define WAKE_CORE_REG *((volatile int32u *)0x40000024u) +#define WAKE_CORE_ADDR (0x40000024u) +#define WAKE_CORE_RESET (0x00000000u) + /* WAKE_CORE_FIELD field */ + #define WAKE_CORE_FIELD (0x00000020u) + #define WAKE_CORE_FIELD_MASK (0x00000020u) + #define WAKE_CORE_FIELD_BIT (5) + #define WAKE_CORE_FIELD_BITS (1) + +#define PWRUP_EVENT *((volatile int32u *)0x40000028u) +#define PWRUP_EVENT_REG *((volatile int32u *)0x40000028u) +#define PWRUP_EVENT_ADDR (0x40000028u) +#define PWRUP_EVENT_RESET (0x00000000u) + /* PWRUP_CSYSPWRUPREQ field */ + #define PWRUP_CSYSPWRUPREQ (0x00000200u) + #define PWRUP_CSYSPWRUPREQ_MASK (0x00000200u) + #define PWRUP_CSYSPWRUPREQ_BIT (9) + #define PWRUP_CSYSPWRUPREQ_BITS (1) + /* PWRUP_CDBGPWRUPREQ field */ + #define PWRUP_CDBGPWRUPREQ (0x00000100u) + #define PWRUP_CDBGPWRUPREQ_MASK (0x00000100u) + #define PWRUP_CDBGPWRUPREQ_BIT (8) + #define PWRUP_CDBGPWRUPREQ_BITS (1) + /* PWRUP_WAKECORE field */ + #define PWRUP_WAKECORE (0x00000080u) + #define PWRUP_WAKECORE_MASK (0x00000080u) + #define PWRUP_WAKECORE_BIT (7) + #define PWRUP_WAKECORE_BITS (1) + /* PWRUP_SLEEPTMRWRAP field */ + #define PWRUP_SLEEPTMRWRAP (0x00000040u) + #define PWRUP_SLEEPTMRWRAP_MASK (0x00000040u) + #define PWRUP_SLEEPTMRWRAP_BIT (6) + #define PWRUP_SLEEPTMRWRAP_BITS (1) + /* PWRUP_SLEEPTMRCOMPB field */ + #define PWRUP_SLEEPTMRCOMPB (0x00000020u) + #define PWRUP_SLEEPTMRCOMPB_MASK (0x00000020u) + #define PWRUP_SLEEPTMRCOMPB_BIT (5) + #define PWRUP_SLEEPTMRCOMPB_BITS (1) + /* PWRUP_SLEEPTMRCOMPA field */ + #define PWRUP_SLEEPTMRCOMPA (0x00000010u) + #define PWRUP_SLEEPTMRCOMPA_MASK (0x00000010u) + #define PWRUP_SLEEPTMRCOMPA_BIT (4) + #define PWRUP_SLEEPTMRCOMPA_BITS (1) + /* PWRUP_IRQD field */ + #define PWRUP_IRQD (0x00000008u) + #define PWRUP_IRQD_MASK (0x00000008u) + #define PWRUP_IRQD_BIT (3) + #define PWRUP_IRQD_BITS (1) + /* PWRUP_SC2 field */ + #define PWRUP_SC2 (0x00000004u) + #define PWRUP_SC2_MASK (0x00000004u) + #define PWRUP_SC2_BIT (2) + #define PWRUP_SC2_BITS (1) + /* PWRUP_SC1 field */ + #define PWRUP_SC1 (0x00000002u) + #define PWRUP_SC1_MASK (0x00000002u) + #define PWRUP_SC1_BIT (1) + #define PWRUP_SC1_BITS (1) + /* PWRUP_GPIO field */ + #define PWRUP_GPIO (0x00000001u) + #define PWRUP_GPIO_MASK (0x00000001u) + #define PWRUP_GPIO_BIT (0) + #define PWRUP_GPIO_BITS (1) + +#define RESET_EVENT *((volatile int32u *)0x4000002Cu) +#define RESET_EVENT_REG *((volatile int32u *)0x4000002Cu) +#define RESET_EVENT_ADDR (0x4000002Cu) +#define RESET_EVENT_RESET (0x00000001u) + /* RESET_CPULOCKUP field */ + #define RESET_CPULOCKUP (0x00000080u) + #define RESET_CPULOCKUP_MASK (0x00000080u) + #define RESET_CPULOCKUP_BIT (7) + #define RESET_CPULOCKUP_BITS (1) + /* RESET_OPTBYTEFAIL field */ + #define RESET_OPTBYTEFAIL (0x00000040u) + #define RESET_OPTBYTEFAIL_MASK (0x00000040u) + #define RESET_OPTBYTEFAIL_BIT (6) + #define RESET_OPTBYTEFAIL_BITS (1) + /* RESET_DSLEEP field */ + #define RESET_DSLEEP (0x00000020u) + #define RESET_DSLEEP_MASK (0x00000020u) + #define RESET_DSLEEP_BIT (5) + #define RESET_DSLEEP_BITS (1) + /* RESET_SW field */ + #define RESET_SW (0x00000010u) + #define RESET_SW_MASK (0x00000010u) + #define RESET_SW_BIT (4) + #define RESET_SW_BITS (1) + /* RESET_WDOG field */ + #define RESET_WDOG (0x00000008u) + #define RESET_WDOG_MASK (0x00000008u) + #define RESET_WDOG_BIT (3) + #define RESET_WDOG_BITS (1) + /* RESET_NRESET field */ + #define RESET_NRESET (0x00000004u) + #define RESET_NRESET_MASK (0x00000004u) + #define RESET_NRESET_BIT (2) + #define RESET_NRESET_BITS (1) + /* RESET_PWRLV field */ + #define RESET_PWRLV (0x00000002u) + #define RESET_PWRLV_MASK (0x00000002u) + #define RESET_PWRLV_BIT (1) + #define RESET_PWRLV_BITS (1) + /* RESET_PWRHV field */ + #define RESET_PWRHV (0x00000001u) + #define RESET_PWRHV_MASK (0x00000001u) + #define RESET_PWRHV_BIT (0) + #define RESET_PWRHV_BITS (1) + +#define DBG_MBOX *((volatile int32u *)0x40000030u) +#define DBG_MBOX_REG *((volatile int32u *)0x40000030u) +#define DBG_MBOX_ADDR (0x40000030u) +#define DBG_MBOX_RESET (0x00000000u) + /* DBG_MBOX field */ + #define DBG_MBOX_DBG_MBOX (0x0000FFFFu) + #define DBG_MBOX_DBG_MBOX_MASK (0x0000FFFFu) + #define DBG_MBOX_DBG_MBOX_BIT (0) + #define DBG_MBOX_DBG_MBOX_BITS (16) + +#define CPWRUPREQ_STATUS *((volatile int32u *)0x40000034u) +#define CPWRUPREQ_STATUS_REG *((volatile int32u *)0x40000034u) +#define CPWRUPREQ_STATUS_ADDR (0x40000034u) +#define CPWRUPREQ_STATUS_RESET (0x00000000u) + /* CPWRUPREQ field */ + #define CPWRUPREQ_STATUS_CPWRUPREQ (0x00000001u) + #define CPWRUPREQ_STATUS_CPWRUPREQ_MASK (0x00000001u) + #define CPWRUPREQ_STATUS_CPWRUPREQ_BIT (0) + #define CPWRUPREQ_STATUS_CPWRUPREQ_BITS (1) + +#define CSYSPWRUPREQ_STATUS *((volatile int32u *)0x40000038u) +#define CSYSPWRUPREQ_STATUS_REG *((volatile int32u *)0x40000038u) +#define CSYSPWRUPREQ_STATUS_ADDR (0x40000038u) +#define CSYSPWRUPREQ_STATUS_RESET (0x00000000u) + /* CSYSPWRUPREQ field */ + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ (0x00000001u) + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK (0x00000001u) + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT (0) + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS (1) + +#define CSYSPWRUPACK_STATUS *((volatile int32u *)0x4000003Cu) +#define CSYSPWRUPACK_STATUS_REG *((volatile int32u *)0x4000003Cu) +#define CSYSPWRUPACK_STATUS_ADDR (0x4000003Cu) +#define CSYSPWRUPACK_STATUS_RESET (0x00000000u) + /* CSYSPWRUPACK field */ + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK (0x00000001u) + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK (0x00000001u) + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT (0) + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS (1) + +#define CSYSPWRUPACK_INHIBIT *((volatile int32u *)0x40000040u) +#define CSYSPWRUPACK_INHIBIT_REG *((volatile int32u *)0x40000040u) +#define CSYSPWRUPACK_INHIBIT_ADDR (0x40000040u) +#define CSYSPWRUPACK_INHIBIT_RESET (0x00000000u) + /* CSYSPWRUPACK_INHIBIT field */ + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT (0x00000001u) + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK (0x00000001u) + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT (0) + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS (1) + +#define OPT_ERR_MAINTAIN_WAKE *((volatile int32u *)0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_REG *((volatile int32u *)0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_ADDR (0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_RESET (0x00000000u) + /* OPT_ERR_MAINTAIN_WAKE field */ + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE (0x00000001u) + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK (0x00000001u) + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT (0) + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS (1) + +/* BASEBAND block */ +#define DATA_BASEBAND_BASE (0x40001000u) +#define DATA_BASEBAND_END (0x40001114u) +#define DATA_BASEBAND_SIZE (DATA_BASEBAND_END - DATA_BASEBAND_BASE + 1) + +#define MOD_CAL_CTRL *((volatile int32u *)0x40001000u) +#define MOD_CAL_CTRL_REG *((volatile int32u *)0x40001000u) +#define MOD_CAL_CTRL_ADDR (0x40001000u) +#define MOD_CAL_CTRL_RESET (0x00000000u) + /* MOD_CAL_GO field */ + #define MOD_CAL_CTRL_MOD_CAL_GO (0x00008000u) + #define MOD_CAL_CTRL_MOD_CAL_GO_MASK (0x00008000u) + #define MOD_CAL_CTRL_MOD_CAL_GO_BIT (15) + #define MOD_CAL_CTRL_MOD_CAL_GO_BITS (1) + /* MOD_CAL_DONE field */ + #define MOD_CAL_CTRL_MOD_CAL_DONE (0x00000010u) + #define MOD_CAL_CTRL_MOD_CAL_DONE_MASK (0x00000010u) + #define MOD_CAL_CTRL_MOD_CAL_DONE_BIT (4) + #define MOD_CAL_CTRL_MOD_CAL_DONE_BITS (1) + /* MOD_CAL_CYCLES field */ + #define MOD_CAL_CTRL_MOD_CAL_CYCLES (0x00000003u) + #define MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK (0x00000003u) + #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT (0) + #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS (2) + +#define MOD_CAL_COUNT_H *((volatile int32u *)0x40001004u) +#define MOD_CAL_COUNT_H_REG *((volatile int32u *)0x40001004u) +#define MOD_CAL_COUNT_H_ADDR (0x40001004u) +#define MOD_CAL_COUNT_H_RESET (0x00000000u) + /* MOD_CAL_COUNT_H field */ + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H (0x000000FFu) + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK (0x000000FFu) + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT (0) + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS (8) + +#define MOD_CAL_COUNT_L *((volatile int32u *)0x40001008u) +#define MOD_CAL_COUNT_L_REG *((volatile int32u *)0x40001008u) +#define MOD_CAL_COUNT_L_ADDR (0x40001008u) +#define MOD_CAL_COUNT_L_RESET (0x00000000u) + /* MOD_CAL_COUNT_L field */ + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L (0x0000FFFFu) + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK (0x0000FFFFu) + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT (0) + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS (16) + +#define RSSI_ROLLING *((volatile int32u *)0x4000100Cu) +#define RSSI_ROLLING_REG *((volatile int32u *)0x4000100Cu) +#define RSSI_ROLLING_ADDR (0x4000100Cu) +#define RSSI_ROLLING_RESET (0x00000000u) + /* RSSI_ROLLING field */ + #define RSSI_ROLLING_RSSI_ROLLING (0x00003FFFu) + #define RSSI_ROLLING_RSSI_ROLLING_MASK (0x00003FFFu) + #define RSSI_ROLLING_RSSI_ROLLING_BIT (0) + #define RSSI_ROLLING_RSSI_ROLLING_BITS (14) + +#define RSSI_PKT *((volatile int32u *)0x40001010u) +#define RSSI_PKT_REG *((volatile int32u *)0x40001010u) +#define RSSI_PKT_ADDR (0x40001010u) +#define RSSI_PKT_RESET (0x00000000u) + /* RSSI_PKT field */ + #define RSSI_PKT_RSSI_PKT (0x000000FFu) + #define RSSI_PKT_RSSI_PKT_MASK (0x000000FFu) + #define RSSI_PKT_RSSI_PKT_BIT (0) + #define RSSI_PKT_RSSI_PKT_BITS (8) + +#define RX_ADC *((volatile int32u *)0x40001014u) +#define RX_ADC_REG *((volatile int32u *)0x40001014u) +#define RX_ADC_ADDR (0x40001014u) +#define RX_ADC_RESET (0x00000024u) + /* RX_ADC field */ + #define RX_ADC_RX_ADC (0x0000007Fu) + #define RX_ADC_RX_ADC_MASK (0x0000007Fu) + #define RX_ADC_RX_ADC_BIT (0) + #define RX_ADC_RX_ADC_BITS (7) + +#define DEBUG_BB_MODE *((volatile int32u *)0x40001018u) +#define DEBUG_BB_MODE_REG *((volatile int32u *)0x40001018u) +#define DEBUG_BB_MODE_ADDR (0x40001018u) +#define DEBUG_BB_MODE_RESET (0x00000000u) + /* DEBUG_BB_MODE_EN field */ + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN (0x00008000u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK (0x00008000u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT (15) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS (1) + /* DEBUG_BB_MODE field */ + #define DEBUG_BB_MODE_DEBUG_BB_MODE (0x00000003u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_MASK (0x00000003u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT (0) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS (2) + +#define BB_DEBUG *((volatile int32u *)0x4000101Cu) +#define BB_DEBUG_REG *((volatile int32u *)0x4000101Cu) +#define BB_DEBUG_ADDR (0x4000101Cu) +#define BB_DEBUG_RESET (0x00000002u) + /* SYNC_REG_EN field */ + #define BB_DEBUG_SYNC_REG_EN (0x00008000u) + #define BB_DEBUG_SYNC_REG_EN_MASK (0x00008000u) + #define BB_DEBUG_SYNC_REG_EN_BIT (15) + #define BB_DEBUG_SYNC_REG_EN_BITS (1) + /* DEBUG_MUX_ADDR field */ + #define BB_DEBUG_DEBUG_MUX_ADDR (0x000000F0u) + #define BB_DEBUG_DEBUG_MUX_ADDR_MASK (0x000000F0u) + #define BB_DEBUG_DEBUG_MUX_ADDR_BIT (4) + #define BB_DEBUG_DEBUG_MUX_ADDR_BITS (4) + /* BB_DEBUG_SEL field */ + #define BB_DEBUG_BB_DEBUG_SEL (0x00000003u) + #define BB_DEBUG_BB_DEBUG_SEL_MASK (0x00000003u) + #define BB_DEBUG_BB_DEBUG_SEL_BIT (0) + #define BB_DEBUG_BB_DEBUG_SEL_BITS (2) + +#define BB_DEBUG_VIEW *((volatile int32u *)0x40001020u) +#define BB_DEBUG_VIEW_REG *((volatile int32u *)0x40001020u) +#define BB_DEBUG_VIEW_ADDR (0x40001020u) +#define BB_DEBUG_VIEW_RESET (0x00000000u) + /* BB_DEBUG_VIEW field */ + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW (0x0000FFFFu) + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK (0x0000FFFFu) + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT (0) + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS (16) + +#define IF_FREQ *((volatile int32u *)0x40001024u) +#define IF_FREQ_REG *((volatile int32u *)0x40001024u) +#define IF_FREQ_ADDR (0x40001024u) +#define IF_FREQ_RESET (0x00000155u) + /* TIMING_CORR_EN field */ + #define IF_FREQ_TIMING_CORR_EN (0x00008000u) + #define IF_FREQ_TIMING_CORR_EN_MASK (0x00008000u) + #define IF_FREQ_TIMING_CORR_EN_BIT (15) + #define IF_FREQ_TIMING_CORR_EN_BITS (1) + /* IF_FREQ field */ + #define IF_FREQ_IF_FREQ (0x000001FFu) + #define IF_FREQ_IF_FREQ_MASK (0x000001FFu) + #define IF_FREQ_IF_FREQ_BIT (0) + #define IF_FREQ_IF_FREQ_BITS (9) + +#define MOD_EN *((volatile int32u *)0x40001028u) +#define MOD_EN_REG *((volatile int32u *)0x40001028u) +#define MOD_EN_ADDR (0x40001028u) +#define MOD_EN_RESET (0x00000001u) + /* MOD_EN field */ + #define MOD_EN_MOD_EN (0x00000001u) + #define MOD_EN_MOD_EN_MASK (0x00000001u) + #define MOD_EN_MOD_EN_BIT (0) + #define MOD_EN_MOD_EN_BITS (1) + +#define PRESCALE_CTRL *((volatile int32u *)0x4000102Cu) +#define PRESCALE_CTRL_REG *((volatile int32u *)0x4000102Cu) +#define PRESCALE_CTRL_ADDR (0x4000102Cu) +#define PRESCALE_CTRL_RESET (0x00000000u) + /* PRESCALE_SET field */ + #define PRESCALE_CTRL_PRESCALE_SET (0x00008000u) + #define PRESCALE_CTRL_PRESCALE_SET_MASK (0x00008000u) + #define PRESCALE_CTRL_PRESCALE_SET_BIT (15) + #define PRESCALE_CTRL_PRESCALE_SET_BITS (1) + /* PRESCALE_VAL field */ + #define PRESCALE_CTRL_PRESCALE_VAL (0x00000007u) + #define PRESCALE_CTRL_PRESCALE_VAL_MASK (0x00000007u) + #define PRESCALE_CTRL_PRESCALE_VAL_BIT (0) + #define PRESCALE_CTRL_PRESCALE_VAL_BITS (3) + +#define ADC_BYPASS_EN *((volatile int32u *)0x40001030u) +#define ADC_BYPASS_EN_REG *((volatile int32u *)0x40001030u) +#define ADC_BYPASS_EN_ADDR (0x40001030u) +#define ADC_BYPASS_EN_RESET (0x00000000u) + /* ADC_BYPASS_EN field */ + #define ADC_BYPASS_EN_ADC_BYPASS_EN (0x00000001u) + #define ADC_BYPASS_EN_ADC_BYPASS_EN_MASK (0x00000001u) + #define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT (0) + #define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS (1) + +#define FIXED_CODE_EN *((volatile int32u *)0x40001034u) +#define FIXED_CODE_EN_REG *((volatile int32u *)0x40001034u) +#define FIXED_CODE_EN_ADDR (0x40001034u) +#define FIXED_CODE_EN_RESET (0x00000000u) + /* FIXED_CODE_EN field */ + #define FIXED_CODE_EN_FIXED_CODE_EN (0x00000001u) + #define FIXED_CODE_EN_FIXED_CODE_EN_MASK (0x00000001u) + #define FIXED_CODE_EN_FIXED_CODE_EN_BIT (0) + #define FIXED_CODE_EN_FIXED_CODE_EN_BITS (1) + +#define FIXED_CODE_H *((volatile int32u *)0x40001038u) +#define FIXED_CODE_H_REG *((volatile int32u *)0x40001038u) +#define FIXED_CODE_H_ADDR (0x40001038u) +#define FIXED_CODE_H_RESET (0x00000000u) + /* FIXED_CODE_H field */ + #define FIXED_CODE_H_FIXED_CODE_H (0x0000FFFFu) + #define FIXED_CODE_H_FIXED_CODE_H_MASK (0x0000FFFFu) + #define FIXED_CODE_H_FIXED_CODE_H_BIT (0) + #define FIXED_CODE_H_FIXED_CODE_H_BITS (16) + +#define FIXED_CODE_L *((volatile int32u *)0x4000103Cu) +#define FIXED_CODE_L_REG *((volatile int32u *)0x4000103Cu) +#define FIXED_CODE_L_ADDR (0x4000103Cu) +#define FIXED_CODE_L_RESET (0x00000000u) + /* FIXED_CODE_L field */ + #define FIXED_CODE_L_FIXED_CODE_L (0x0000FFFFu) + #define FIXED_CODE_L_FIXED_CODE_L_MASK (0x0000FFFFu) + #define FIXED_CODE_L_FIXED_CODE_L_BIT (0) + #define FIXED_CODE_L_FIXED_CODE_L_BITS (16) + +#define FIXED_CODE_L_SHADOW *((volatile int32u *)0x40001040u) +#define FIXED_CODE_L_SHADOW_REG *((volatile int32u *)0x40001040u) +#define FIXED_CODE_L_SHADOW_ADDR (0x40001040u) +#define FIXED_CODE_L_SHADOW_RESET (0x00000000u) + /* FIXED_CODE_L_SHADOW field */ + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW (0x0000FFFFu) + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK (0x0000FFFFu) + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT (0) + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS (16) + +#define RX_GAIN_CTRL *((volatile int32u *)0x40001044u) +#define RX_GAIN_CTRL_REG *((volatile int32u *)0x40001044u) +#define RX_GAIN_CTRL_ADDR (0x40001044u) +#define RX_GAIN_CTRL_RESET (0x00000000u) + /* RX_GAIN_MUX field */ + #define RX_GAIN_CTRL_RX_GAIN_MUX (0x00008000u) + #define RX_GAIN_CTRL_RX_GAIN_MUX_MASK (0x00008000u) + #define RX_GAIN_CTRL_RX_GAIN_MUX_BIT (15) + #define RX_GAIN_CTRL_RX_GAIN_MUX_BITS (1) + /* RX_RF_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST (0x00000080u) + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK (0x00000080u) + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT (7) + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS (1) + /* RX_MIXER_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST (0x00000040u) + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK (0x00000040u) + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT (6) + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS (1) + /* RX_FILTER_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST (0x00000030u) + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK (0x00000030u) + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT (4) + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS (2) + /* RX_IF_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST (0x0000000Fu) + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK (0x0000000Fu) + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT (0) + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS (4) + +#define PD_DITHER_EN *((volatile int32u *)0x40001048u) +#define PD_DITHER_EN_REG *((volatile int32u *)0x40001048u) +#define PD_DITHER_EN_ADDR (0x40001048u) +#define PD_DITHER_EN_RESET (0x00000001u) + /* PD_DITHER_EN field */ + #define PD_DITHER_EN_PD_DITHER_EN (0x00000001u) + #define PD_DITHER_EN_PD_DITHER_EN_MASK (0x00000001u) + #define PD_DITHER_EN_PD_DITHER_EN_BIT (0) + #define PD_DITHER_EN_PD_DITHER_EN_BITS (1) + +#define RX_ERR_THRESH *((volatile int32u *)0x4000104Cu) +#define RX_ERR_THRESH_REG *((volatile int32u *)0x4000104Cu) +#define RX_ERR_THRESH_ADDR (0x4000104Cu) +#define RX_ERR_THRESH_RESET (0x00004608u) + /* LPF_RX_ERR_COEFF field */ + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF (0x0000E000u) + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK (0x0000E000u) + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT (13) + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS (3) + /* LPF_RX_ERR_THRESH field */ + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH (0x00001F00u) + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK (0x00001F00u) + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT (8) + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS (5) + /* RX_ERR_THRESH field */ + #define RX_ERR_THRESH_RX_ERR_THRESH (0x0000001Fu) + #define RX_ERR_THRESH_RX_ERR_THRESH_MASK (0x0000001Fu) + #define RX_ERR_THRESH_RX_ERR_THRESH_BIT (0) + #define RX_ERR_THRESH_RX_ERR_THRESH_BITS (5) + +#define CARRIER_THRESH *((volatile int32u *)0x40001050u) +#define CARRIER_THRESH_REG *((volatile int32u *)0x40001050u) +#define CARRIER_THRESH_ADDR (0x40001050u) +#define CARRIER_THRESH_RESET (0x00002332u) + /* CARRIER_SPIKE_THRESH field */ + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH (0x0000FF00u) + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK (0x0000FF00u) + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT (8) + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS (8) + /* CARRIER_THRESH field */ + #define CARRIER_THRESH_CARRIER_THRESH (0x000000FFu) + #define CARRIER_THRESH_CARRIER_THRESH_MASK (0x000000FFu) + #define CARRIER_THRESH_CARRIER_THRESH_BIT (0) + #define CARRIER_THRESH_CARRIER_THRESH_BITS (8) + +#define RSSI_THRESH *((volatile int32u *)0x40001054u) +#define RSSI_THRESH_REG *((volatile int32u *)0x40001054u) +#define RSSI_THRESH_ADDR (0x40001054u) +#define RSSI_THRESH_RESET (0x00000100u) + /* RSSI_THRESH field */ + #define RSSI_THRESH_RSSI_THRESH (0x0000FFFFu) + #define RSSI_THRESH_RSSI_THRESH_MASK (0x0000FFFFu) + #define RSSI_THRESH_RSSI_THRESH_BIT (0) + #define RSSI_THRESH_RSSI_THRESH_BITS (16) + +#define SYNTH_START *((volatile int32u *)0x40001058u) +#define SYNTH_START_REG *((volatile int32u *)0x40001058u) +#define SYNTH_START_ADDR (0x40001058u) +#define SYNTH_START_RESET (0x00006464u) + /* SYNTH_WARM_START field */ + #define SYNTH_START_SYNTH_WARM_START (0x0000FF00u) + #define SYNTH_START_SYNTH_WARM_START_MASK (0x0000FF00u) + #define SYNTH_START_SYNTH_WARM_START_BIT (8) + #define SYNTH_START_SYNTH_WARM_START_BITS (8) + /* SYNTH_COLD_START field */ + #define SYNTH_START_SYNTH_COLD_START (0x000000FFu) + #define SYNTH_START_SYNTH_COLD_START_MASK (0x000000FFu) + #define SYNTH_START_SYNTH_COLD_START_BIT (0) + #define SYNTH_START_SYNTH_COLD_START_BITS (8) + +#define IN_LOCK_EN *((volatile int32u *)0x4000105Cu) +#define IN_LOCK_EN_REG *((volatile int32u *)0x4000105Cu) +#define IN_LOCK_EN_ADDR (0x4000105Cu) +#define IN_LOCK_EN_RESET (0x00000001u) + /* IN_LOCK_EN field */ + #define IN_LOCK_EN_IN_LOCK_EN (0x00000001u) + #define IN_LOCK_EN_IN_LOCK_EN_MASK (0x00000001u) + #define IN_LOCK_EN_IN_LOCK_EN_BIT (0) + #define IN_LOCK_EN_IN_LOCK_EN_BITS (1) + +#define DITHER_AMPLITUDE *((volatile int32u *)0x40001060u) +#define DITHER_AMPLITUDE_REG *((volatile int32u *)0x40001060u) +#define DITHER_AMPLITUDE_ADDR (0x40001060u) +#define DITHER_AMPLITUDE_RESET (0x0000003Fu) + /* DITHER_AMP field */ + #define DITHER_AMPLITUDE_DITHER_AMP (0x0000003Fu) + #define DITHER_AMPLITUDE_DITHER_AMP_MASK (0x0000003Fu) + #define DITHER_AMPLITUDE_DITHER_AMP_BIT (0) + #define DITHER_AMPLITUDE_DITHER_AMP_BITS (6) + +#define TX_STEP_TIME *((volatile int32u *)0x40001064u) +#define TX_STEP_TIME_REG *((volatile int32u *)0x40001064u) +#define TX_STEP_TIME_ADDR (0x40001064u) +#define TX_STEP_TIME_RESET (0x00000000u) + /* TX_STEP_TIME field */ + #define TX_STEP_TIME_TX_STEP_TIME (0x000000FFu) + #define TX_STEP_TIME_TX_STEP_TIME_MASK (0x000000FFu) + #define TX_STEP_TIME_TX_STEP_TIME_BIT (0) + #define TX_STEP_TIME_TX_STEP_TIME_BITS (8) + +#define GAIN_THRESH_MAX *((volatile int32u *)0x40001068u) +#define GAIN_THRESH_MAX_REG *((volatile int32u *)0x40001068u) +#define GAIN_THRESH_MAX_ADDR (0x40001068u) +#define GAIN_THRESH_MAX_RESET (0x00000060u) + /* GAIN_THRESH_MAX field */ + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX (0x000000FFu) + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK (0x000000FFu) + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT (0) + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS (8) + +#define GAIN_THRESH_MID *((volatile int32u *)0x4000106Cu) +#define GAIN_THRESH_MID_REG *((volatile int32u *)0x4000106Cu) +#define GAIN_THRESH_MID_ADDR (0x4000106Cu) +#define GAIN_THRESH_MID_RESET (0x00000030u) + /* GAIN_THRESH_MID field */ + #define GAIN_THRESH_MID_GAIN_THRESH_MID (0x000000FFu) + #define GAIN_THRESH_MID_GAIN_THRESH_MID_MASK (0x000000FFu) + #define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT (0) + #define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS (8) + +#define GAIN_THRESH_MIN *((volatile int32u *)0x40001070u) +#define GAIN_THRESH_MIN_REG *((volatile int32u *)0x40001070u) +#define GAIN_THRESH_MIN_ADDR (0x40001070u) +#define GAIN_THRESH_MIN_RESET (0x00000018u) + /* GAIN_THRESH_MIN field */ + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN (0x000000FFu) + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK (0x000000FFu) + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT (0) + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS (8) + +#define GAIN_SETTING_0 *((volatile int32u *)0x40001074u) +#define GAIN_SETTING_0_REG *((volatile int32u *)0x40001074u) +#define GAIN_SETTING_0_ADDR (0x40001074u) +#define GAIN_SETTING_0_RESET (0x00000000u) + /* RX_MIXER_GAIN_0 field */ + #define GAIN_SETTING_0_RX_MIXER_GAIN_0 (0x00000040u) + #define GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK (0x00000040u) + #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT (6) + #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS (1) + /* RX_FILTER_GAIN_0 field */ + #define GAIN_SETTING_0_RX_FILTER_GAIN_0 (0x00000030u) + #define GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK (0x00000030u) + #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT (4) + #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS (2) + /* RX_IF_GAIN_0 field */ + #define GAIN_SETTING_0_RX_IF_GAIN_0 (0x0000000Fu) + #define GAIN_SETTING_0_RX_IF_GAIN_0_MASK (0x0000000Fu) + #define GAIN_SETTING_0_RX_IF_GAIN_0_BIT (0) + #define GAIN_SETTING_0_RX_IF_GAIN_0_BITS (4) + +#define GAIN_SETTING_1 *((volatile int32u *)0x40001078u) +#define GAIN_SETTING_1_REG *((volatile int32u *)0x40001078u) +#define GAIN_SETTING_1_ADDR (0x40001078u) +#define GAIN_SETTING_1_RESET (0x00000010u) + /* RX_MIXER_GAIN_1 field */ + #define GAIN_SETTING_1_RX_MIXER_GAIN_1 (0x00000040u) + #define GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK (0x00000040u) + #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT (6) + #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS (1) + /* RX_FILTER_GAIN_1 field */ + #define GAIN_SETTING_1_RX_FILTER_GAIN_1 (0x00000030u) + #define GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK (0x00000030u) + #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT (4) + #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS (2) + /* RX_IF_GAIN_1 field */ + #define GAIN_SETTING_1_RX_IF_GAIN_1 (0x0000000Fu) + #define GAIN_SETTING_1_RX_IF_GAIN_1_MASK (0x0000000Fu) + #define GAIN_SETTING_1_RX_IF_GAIN_1_BIT (0) + #define GAIN_SETTING_1_RX_IF_GAIN_1_BITS (4) + +#define GAIN_SETTING_2 *((volatile int32u *)0x4000107Cu) +#define GAIN_SETTING_2_REG *((volatile int32u *)0x4000107Cu) +#define GAIN_SETTING_2_ADDR (0x4000107Cu) +#define GAIN_SETTING_2_RESET (0x00000030u) + /* RX_MIXER_GAIN_2 field */ + #define GAIN_SETTING_2_RX_MIXER_GAIN_2 (0x00000040u) + #define GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK (0x00000040u) + #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT (6) + #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS (1) + /* RX_FILTER_GAIN_2 field */ + #define GAIN_SETTING_2_RX_FILTER_GAIN_2 (0x00000030u) + #define GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK (0x00000030u) + #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT (4) + #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS (2) + /* RX_IF_GAIN_2 field */ + #define GAIN_SETTING_2_RX_IF_GAIN_2 (0x0000000Fu) + #define GAIN_SETTING_2_RX_IF_GAIN_2_MASK (0x0000000Fu) + #define GAIN_SETTING_2_RX_IF_GAIN_2_BIT (0) + #define GAIN_SETTING_2_RX_IF_GAIN_2_BITS (4) + +#define GAIN_SETTING_3 *((volatile int32u *)0x40001080u) +#define GAIN_SETTING_3_REG *((volatile int32u *)0x40001080u) +#define GAIN_SETTING_3_ADDR (0x40001080u) +#define GAIN_SETTING_3_RESET (0x00000031u) + /* RX_MIXER_GAIN_3 field */ + #define GAIN_SETTING_3_RX_MIXER_GAIN_3 (0x00000040u) + #define GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK (0x00000040u) + #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT (6) + #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS (1) + /* RX_FILTER_GAIN_3 field */ + #define GAIN_SETTING_3_RX_FILTER_GAIN_3 (0x00000030u) + #define GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK (0x00000030u) + #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT (4) + #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS (2) + /* RX_IF_GAIN_3 field */ + #define GAIN_SETTING_3_RX_IF_GAIN_3 (0x0000000Fu) + #define GAIN_SETTING_3_RX_IF_GAIN_3_MASK (0x0000000Fu) + #define GAIN_SETTING_3_RX_IF_GAIN_3_BIT (0) + #define GAIN_SETTING_3_RX_IF_GAIN_3_BITS (4) + +#define GAIN_SETTING_4 *((volatile int32u *)0x40001084u) +#define GAIN_SETTING_4_REG *((volatile int32u *)0x40001084u) +#define GAIN_SETTING_4_ADDR (0x40001084u) +#define GAIN_SETTING_4_RESET (0x00000032u) + /* RX_MIXER_GAIN_4 field */ + #define GAIN_SETTING_4_RX_MIXER_GAIN_4 (0x00000040u) + #define GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK (0x00000040u) + #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT (6) + #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS (1) + /* RX_FILTER_GAIN_4 field */ + #define GAIN_SETTING_4_RX_FILTER_GAIN_4 (0x00000030u) + #define GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK (0x00000030u) + #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT (4) + #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS (2) + /* RX_IF_GAIN_4 field */ + #define GAIN_SETTING_4_RX_IF_GAIN_4 (0x0000000Fu) + #define GAIN_SETTING_4_RX_IF_GAIN_4_MASK (0x0000000Fu) + #define GAIN_SETTING_4_RX_IF_GAIN_4_BIT (0) + #define GAIN_SETTING_4_RX_IF_GAIN_4_BITS (4) + +#define GAIN_SETTING_5 *((volatile int32u *)0x40001088u) +#define GAIN_SETTING_5_REG *((volatile int32u *)0x40001088u) +#define GAIN_SETTING_5_ADDR (0x40001088u) +#define GAIN_SETTING_5_RESET (0x00000033u) + /* RX_MIXER_GAIN_5 field */ + #define GAIN_SETTING_5_RX_MIXER_GAIN_5 (0x00000040u) + #define GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK (0x00000040u) + #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT (6) + #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS (1) + /* RX_FILTER_GAIN_5 field */ + #define GAIN_SETTING_5_RX_FILTER_GAIN_5 (0x00000030u) + #define GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK (0x00000030u) + #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT (4) + #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS (2) + /* RX_IF_GAIN_5 field */ + #define GAIN_SETTING_5_RX_IF_GAIN_5 (0x0000000Fu) + #define GAIN_SETTING_5_RX_IF_GAIN_5_MASK (0x0000000Fu) + #define GAIN_SETTING_5_RX_IF_GAIN_5_BIT (0) + #define GAIN_SETTING_5_RX_IF_GAIN_5_BITS (4) + +#define GAIN_SETTING_6 *((volatile int32u *)0x4000108Cu) +#define GAIN_SETTING_6_REG *((volatile int32u *)0x4000108Cu) +#define GAIN_SETTING_6_ADDR (0x4000108Cu) +#define GAIN_SETTING_6_RESET (0x00000034u) + /* RX_MIXER_GAIN_6 field */ + #define GAIN_SETTING_6_RX_MIXER_GAIN_6 (0x00000040u) + #define GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK (0x00000040u) + #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT (6) + #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS (1) + /* RX_FILTER_GAIN_6 field */ + #define GAIN_SETTING_6_RX_FILTER_GAIN_6 (0x00000030u) + #define GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK (0x00000030u) + #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT (4) + #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS (2) + /* RX_IF_GAIN_6 field */ + #define GAIN_SETTING_6_RX_IF_GAIN_6 (0x0000000Fu) + #define GAIN_SETTING_6_RX_IF_GAIN_6_MASK (0x0000000Fu) + #define GAIN_SETTING_6_RX_IF_GAIN_6_BIT (0) + #define GAIN_SETTING_6_RX_IF_GAIN_6_BITS (4) + +#define GAIN_SETTING_7 *((volatile int32u *)0x40001090u) +#define GAIN_SETTING_7_REG *((volatile int32u *)0x40001090u) +#define GAIN_SETTING_7_ADDR (0x40001090u) +#define GAIN_SETTING_7_RESET (0x00000035u) + /* RX_MIXER_GAIN_7 field */ + #define GAIN_SETTING_7_RX_MIXER_GAIN_7 (0x00000040u) + #define GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK (0x00000040u) + #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT (6) + #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS (1) + /* RX_FILTER_GAIN_7 field */ + #define GAIN_SETTING_7_RX_FILTER_GAIN_7 (0x00000030u) + #define GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK (0x00000030u) + #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT (4) + #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS (2) + /* RX_IF_GAIN_7 field */ + #define GAIN_SETTING_7_RX_IF_GAIN_7 (0x0000000Fu) + #define GAIN_SETTING_7_RX_IF_GAIN_7_MASK (0x0000000Fu) + #define GAIN_SETTING_7_RX_IF_GAIN_7_BIT (0) + #define GAIN_SETTING_7_RX_IF_GAIN_7_BITS (4) + +#define GAIN_SETTING_8 *((volatile int32u *)0x40001094u) +#define GAIN_SETTING_8_REG *((volatile int32u *)0x40001094u) +#define GAIN_SETTING_8_ADDR (0x40001094u) +#define GAIN_SETTING_8_RESET (0x00000036u) + /* RX_MIXER_GAIN_8 field */ + #define GAIN_SETTING_8_RX_MIXER_GAIN_8 (0x00000040u) + #define GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK (0x00000040u) + #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT (6) + #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS (1) + /* RX_FILTER_GAIN_8 field */ + #define GAIN_SETTING_8_RX_FILTER_GAIN_8 (0x00000030u) + #define GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK (0x00000030u) + #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT (4) + #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS (2) + /* RX_IF_GAIN_8 field */ + #define GAIN_SETTING_8_RX_IF_GAIN_8 (0x0000000Fu) + #define GAIN_SETTING_8_RX_IF_GAIN_8_MASK (0x0000000Fu) + #define GAIN_SETTING_8_RX_IF_GAIN_8_BIT (0) + #define GAIN_SETTING_8_RX_IF_GAIN_8_BITS (4) + +#define GAIN_SETTING_9 *((volatile int32u *)0x40001098u) +#define GAIN_SETTING_9_REG *((volatile int32u *)0x40001098u) +#define GAIN_SETTING_9_ADDR (0x40001098u) +#define GAIN_SETTING_9_RESET (0x00000076u) + /* RX_MIXER_GAIN_9 field */ + #define GAIN_SETTING_9_RX_MIXER_GAIN_9 (0x00000040u) + #define GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK (0x00000040u) + #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT (6) + #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS (1) + /* RX_FILTER_GAIN_9 field */ + #define GAIN_SETTING_9_RX_FILTER_GAIN_9 (0x00000030u) + #define GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK (0x00000030u) + #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT (4) + #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS (2) + /* RX_IF_GAIN_9 field */ + #define GAIN_SETTING_9_RX_IF_GAIN_9 (0x0000000Fu) + #define GAIN_SETTING_9_RX_IF_GAIN_9_MASK (0x0000000Fu) + #define GAIN_SETTING_9_RX_IF_GAIN_9_BIT (0) + #define GAIN_SETTING_9_RX_IF_GAIN_9_BITS (4) + +#define GAIN_SETTING_10 *((volatile int32u *)0x4000109Cu) +#define GAIN_SETTING_10_REG *((volatile int32u *)0x4000109Cu) +#define GAIN_SETTING_10_ADDR (0x4000109Cu) +#define GAIN_SETTING_10_RESET (0x00000077u) + /* RX_MIXER_GAIN_10 field */ + #define GAIN_SETTING_10_RX_MIXER_GAIN_10 (0x00000040u) + #define GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK (0x00000040u) + #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT (6) + #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS (1) + /* RX_FILTER_GAIN_10 field */ + #define GAIN_SETTING_10_RX_FILTER_GAIN_10 (0x00000030u) + #define GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK (0x00000030u) + #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT (4) + #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS (2) + /* RX_IF_GAIN_10 field */ + #define GAIN_SETTING_10_RX_IF_GAIN_10 (0x0000000Fu) + #define GAIN_SETTING_10_RX_IF_GAIN_10_MASK (0x0000000Fu) + #define GAIN_SETTING_10_RX_IF_GAIN_10_BIT (0) + #define GAIN_SETTING_10_RX_IF_GAIN_10_BITS (4) + +#define GAIN_SETTING_11 *((volatile int32u *)0x400010A0u) +#define GAIN_SETTING_11_REG *((volatile int32u *)0x400010A0u) +#define GAIN_SETTING_11_ADDR (0x400010A0u) +#define GAIN_SETTING_11_RESET (0x00000078u) + /* RX_MIXER_GAIN_11 field */ + #define GAIN_SETTING_11_RX_MIXER_GAIN_11 (0x00000040u) + #define GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK (0x00000040u) + #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT (6) + #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS (1) + /* RX_FILTER_GAIN_11 field */ + #define GAIN_SETTING_11_RX_FILTER_GAIN_11 (0x00000030u) + #define GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK (0x00000030u) + #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT (4) + #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS (2) + /* RX_IF_GAIN_11 field */ + #define GAIN_SETTING_11_RX_IF_GAIN_11 (0x0000000Fu) + #define GAIN_SETTING_11_RX_IF_GAIN_11_MASK (0x0000000Fu) + #define GAIN_SETTING_11_RX_IF_GAIN_11_BIT (0) + #define GAIN_SETTING_11_RX_IF_GAIN_11_BITS (4) + +#define GAIN_CTRL_MIN_RF *((volatile int32u *)0x400010A4u) +#define GAIN_CTRL_MIN_RF_REG *((volatile int32u *)0x400010A4u) +#define GAIN_CTRL_MIN_RF_ADDR (0x400010A4u) +#define GAIN_CTRL_MIN_RF_RESET (0x000000F0u) + /* GAIN_CTRL_MIN_RF field */ + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF (0x000001FFu) + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK (0x000001FFu) + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT (0) + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS (9) + +#define GAIN_CTRL_MAX_RF *((volatile int32u *)0x400010A8u) +#define GAIN_CTRL_MAX_RF_REG *((volatile int32u *)0x400010A8u) +#define GAIN_CTRL_MAX_RF_ADDR (0x400010A8u) +#define GAIN_CTRL_MAX_RF_RESET (0x000000FCu) + /* GAIN_CTRL_MAX_RF field */ + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF (0x000001FFu) + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK (0x000001FFu) + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT (0) + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS (9) + +#define MIXER_GAIN_STEP *((volatile int32u *)0x400010ACu) +#define MIXER_GAIN_STEP_REG *((volatile int32u *)0x400010ACu) +#define MIXER_GAIN_STEP_ADDR (0x400010ACu) +#define MIXER_GAIN_STEP_RESET (0x0000000Cu) + /* MIXER_GAIN_STEP field */ + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP (0x0000000Fu) + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK (0x0000000Fu) + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT (0) + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS (4) + +#define PREAMBLE_EVENT *((volatile int32u *)0x400010B0u) +#define PREAMBLE_EVENT_REG *((volatile int32u *)0x400010B0u) +#define PREAMBLE_EVENT_ADDR (0x400010B0u) +#define PREAMBLE_EVENT_RESET (0x00005877u) + /* PREAMBLE_CONFIRM_THRESH field */ + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH (0x0000FF00u) + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK (0x0000FF00u) + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT (8) + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS (8) + /* PREAMBLE_EVENT_THRESH field */ + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH (0x000000FFu) + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK (0x000000FFu) + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT (0) + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS (8) + +#define PREAMBLE_ABORT_THRESH *((volatile int32u *)0x400010B4u) +#define PREAMBLE_ABORT_THRESH_REG *((volatile int32u *)0x400010B4u) +#define PREAMBLE_ABORT_THRESH_ADDR (0x400010B4u) +#define PREAMBLE_ABORT_THRESH_RESET (0x00000071u) + /* PREAMBLE_ABORT_THRESH field */ + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH (0x000000FFu) + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK (0x000000FFu) + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT (0) + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS (8) + +#define PREAMBLE_ACCEPT_WINDOW *((volatile int32u *)0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_REG *((volatile int32u *)0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_ADDR (0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_RESET (0x00000003u) + /* PREAMBLE_ACCEPT_WINDOW field */ + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW (0x0000007Fu) + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK (0x0000007Fu) + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT (0) + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS (7) + +#define CCA_MODE *((volatile int32u *)0x400010BCu) +#define CCA_MODE_REG *((volatile int32u *)0x400010BCu) +#define CCA_MODE_ADDR (0x400010BCu) +#define CCA_MODE_RESET (0x00000000u) + /* CCA_MODE field */ + #define CCA_MODE_CCA_MODE (0x00000003u) + #define CCA_MODE_CCA_MODE_MASK (0x00000003u) + #define CCA_MODE_CCA_MODE_BIT (0) + #define CCA_MODE_CCA_MODE_BITS (2) + +#define TX_POWER_MAX *((volatile int32u *)0x400010C0u) +#define TX_POWER_MAX_REG *((volatile int32u *)0x400010C0u) +#define TX_POWER_MAX_ADDR (0x400010C0u) +#define TX_POWER_MAX_RESET (0x00000000u) + /* MANUAL_POWER field */ + #define TX_POWER_MAX_MANUAL_POWER (0x00008000u) + #define TX_POWER_MAX_MANUAL_POWER_MASK (0x00008000u) + #define TX_POWER_MAX_MANUAL_POWER_BIT (15) + #define TX_POWER_MAX_MANUAL_POWER_BITS (1) + /* TX_POWER_MAX field */ + #define TX_POWER_MAX_TX_POWER_MAX (0x0000001Fu) + #define TX_POWER_MAX_TX_POWER_MAX_MASK (0x0000001Fu) + #define TX_POWER_MAX_TX_POWER_MAX_BIT (0) + #define TX_POWER_MAX_TX_POWER_MAX_BITS (5) + +#define SYNTH_FREQ_H *((volatile int32u *)0x400010C4u) +#define SYNTH_FREQ_H_REG *((volatile int32u *)0x400010C4u) +#define SYNTH_FREQ_H_ADDR (0x400010C4u) +#define SYNTH_FREQ_H_RESET (0x00000003u) + /* SYNTH_FREQ_H field */ + #define SYNTH_FREQ_H_SYNTH_FREQ_H (0x00000003u) + #define SYNTH_FREQ_H_SYNTH_FREQ_H_MASK (0x00000003u) + #define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT (0) + #define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS (2) + +#define SYNTH_FREQ_L *((volatile int32u *)0x400010C8u) +#define SYNTH_FREQ_L_REG *((volatile int32u *)0x400010C8u) +#define SYNTH_FREQ_L_ADDR (0x400010C8u) +#define SYNTH_FREQ_L_RESET (0x00003800u) + /* SYNTH_FREQ_L field */ + #define SYNTH_FREQ_L_SYNTH_FREQ_L (0x0000FFFFu) + #define SYNTH_FREQ_L_SYNTH_FREQ_L_MASK (0x0000FFFFu) + #define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT (0) + #define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS (16) + +#define RSSI_INST *((volatile int32u *)0x400010CCu) +#define RSSI_INST_REG *((volatile int32u *)0x400010CCu) +#define RSSI_INST_ADDR (0x400010CCu) +#define RSSI_INST_RESET (0x00000000u) + /* NEW_RSSI_INST field */ + #define RSSI_INST_NEW_RSSI_INST (0x00000200u) + #define RSSI_INST_NEW_RSSI_INST_MASK (0x00000200u) + #define RSSI_INST_NEW_RSSI_INST_BIT (9) + #define RSSI_INST_NEW_RSSI_INST_BITS (1) + /* RSSI_INST field */ + #define RSSI_INST_RSSI_INST (0x000001FFu) + #define RSSI_INST_RSSI_INST_MASK (0x000001FFu) + #define RSSI_INST_RSSI_INST_BIT (0) + #define RSSI_INST_RSSI_INST_BITS (9) + +#define FREQ_MEAS_CTRL1 *((volatile int32u *)0x400010D0u) +#define FREQ_MEAS_CTRL1_REG *((volatile int32u *)0x400010D0u) +#define FREQ_MEAS_CTRL1_ADDR (0x400010D0u) +#define FREQ_MEAS_CTRL1_RESET (0x00000160u) + /* AUTO_TUNE_EN field */ + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN (0x00008000u) + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK (0x00008000u) + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT (15) + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS (1) + /* FREQ_MEAS_EN field */ + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN (0x00004000u) + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK (0x00004000u) + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT (14) + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS (1) + /* OPEN_LOOP_MANUAL field */ + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL (0x00002000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK (0x00002000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT (13) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS (1) + /* OPEN_LOOP field */ + #define FREQ_MEAS_CTRL1_OPEN_LOOP (0x00001000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MASK (0x00001000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_BIT (12) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_BITS (1) + /* DELAY_FIRST_MEAS field */ + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS (0x00000400u) + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK (0x00000400u) + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT (10) + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS (1) + /* DELAY_ALL_MEAS field */ + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS (0x00000200u) + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK (0x00000200u) + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT (9) + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS (1) + /* BIN_SEARCH_MSB field */ + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB (0x000001C0u) + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK (0x000001C0u) + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT (6) + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS (3) + /* TUNE_VCO_INIT field */ + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT (0x0000003Fu) + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK (0x0000003Fu) + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT (0) + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS (6) + +#define FREQ_MEAS_CTRL2 *((volatile int32u *)0x400010D4u) +#define FREQ_MEAS_CTRL2_REG *((volatile int32u *)0x400010D4u) +#define FREQ_MEAS_CTRL2_ADDR (0x400010D4u) +#define FREQ_MEAS_CTRL2_RESET (0x0000201Eu) + /* FREQ_MEAS_TIMER field */ + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER (0x0000FF00u) + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK (0x0000FF00u) + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT (8) + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS (8) + /* TARGET_PERIOD field */ + #define FREQ_MEAS_CTRL2_TARGET_PERIOD (0x000000FFu) + #define FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK (0x000000FFu) + #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT (0) + #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS (8) + +#define FREQ_MEAS_SHIFT *((volatile int32u *)0x400010D8u) +#define FREQ_MEAS_SHIFT_REG *((volatile int32u *)0x400010D8u) +#define FREQ_MEAS_SHIFT_ADDR (0x400010D8u) +#define FREQ_MEAS_SHIFT_RESET (0x00000035u) + /* FREQ_MEAS_SHIFT field */ + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT (0x000000FFu) + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK (0x000000FFu) + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT (0) + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS (8) + +#define FREQ_MEAS_STATUS1 *((volatile int32u *)0x400010DCu) +#define FREQ_MEAS_STATUS1_REG *((volatile int32u *)0x400010DCu) +#define FREQ_MEAS_STATUS1_ADDR (0x400010DCu) +#define FREQ_MEAS_STATUS1_RESET (0x00000000u) + /* INVALID_EDGE field */ + #define FREQ_MEAS_STATUS1_INVALID_EDGE (0x00008000u) + #define FREQ_MEAS_STATUS1_INVALID_EDGE_MASK (0x00008000u) + #define FREQ_MEAS_STATUS1_INVALID_EDGE_BIT (15) + #define FREQ_MEAS_STATUS1_INVALID_EDGE_BITS (1) + /* SIGN_FOUND field */ + #define FREQ_MEAS_STATUS1_SIGN_FOUND (0x00004000u) + #define FREQ_MEAS_STATUS1_SIGN_FOUND_MASK (0x00004000u) + #define FREQ_MEAS_STATUS1_SIGN_FOUND_BIT (14) + #define FREQ_MEAS_STATUS1_SIGN_FOUND_BITS (1) + /* FREQ_SIGN field */ + #define FREQ_MEAS_STATUS1_FREQ_SIGN (0x00002000u) + #define FREQ_MEAS_STATUS1_FREQ_SIGN_MASK (0x00002000u) + #define FREQ_MEAS_STATUS1_FREQ_SIGN_BIT (13) + #define FREQ_MEAS_STATUS1_FREQ_SIGN_BITS (1) + /* PERIOD_FOUND field */ + #define FREQ_MEAS_STATUS1_PERIOD_FOUND (0x00001000u) + #define FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK (0x00001000u) + #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT (12) + #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS (1) + /* NEAREST_DIFF field */ + #define FREQ_MEAS_STATUS1_NEAREST_DIFF (0x000003FFu) + #define FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK (0x000003FFu) + #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT (0) + #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS (10) + +#define FREQ_MEAS_STATUS2 *((volatile int32u *)0x400010E0u) +#define FREQ_MEAS_STATUS2_REG *((volatile int32u *)0x400010E0u) +#define FREQ_MEAS_STATUS2_ADDR (0x400010E0u) +#define FREQ_MEAS_STATUS2_RESET (0x00000000u) + /* BEAT_TIMER field */ + #define FREQ_MEAS_STATUS2_BEAT_TIMER (0x0000FFC0u) + #define FREQ_MEAS_STATUS2_BEAT_TIMER_MASK (0x0000FFC0u) + #define FREQ_MEAS_STATUS2_BEAT_TIMER_BIT (6) + #define FREQ_MEAS_STATUS2_BEAT_TIMER_BITS (10) + /* BEATS field */ + #define FREQ_MEAS_STATUS2_BEATS (0x0000003Fu) + #define FREQ_MEAS_STATUS2_BEATS_MASK (0x0000003Fu) + #define FREQ_MEAS_STATUS2_BEATS_BIT (0) + #define FREQ_MEAS_STATUS2_BEATS_BITS (6) + +#define FREQ_MEAS_STATUS3 *((volatile int32u *)0x400010E4u) +#define FREQ_MEAS_STATUS3_REG *((volatile int32u *)0x400010E4u) +#define FREQ_MEAS_STATUS3_ADDR (0x400010E4u) +#define FREQ_MEAS_STATUS3_RESET (0x00000020u) + /* TUNE_VCO field */ + #define FREQ_MEAS_STATUS3_TUNE_VCO (0x0000003Fu) + #define FREQ_MEAS_STATUS3_TUNE_VCO_MASK (0x0000003Fu) + #define FREQ_MEAS_STATUS3_TUNE_VCO_BIT (0) + #define FREQ_MEAS_STATUS3_TUNE_VCO_BITS (6) + +#define SCR_CTRL *((volatile int32u *)0x400010E8u) +#define SCR_CTRL_REG *((volatile int32u *)0x400010E8u) +#define SCR_CTRL_ADDR (0x400010E8u) +#define SCR_CTRL_RESET (0x00000004u) + /* SCR_RESET field */ + #define SCR_CTRL_SCR_RESET (0x00000004u) + #define SCR_CTRL_SCR_RESET_MASK (0x00000004u) + #define SCR_CTRL_SCR_RESET_BIT (2) + #define SCR_CTRL_SCR_RESET_BITS (1) + /* SCR_WRITE field */ + #define SCR_CTRL_SCR_WRITE (0x00000002u) + #define SCR_CTRL_SCR_WRITE_MASK (0x00000002u) + #define SCR_CTRL_SCR_WRITE_BIT (1) + #define SCR_CTRL_SCR_WRITE_BITS (1) + /* SCR_READ field */ + #define SCR_CTRL_SCR_READ (0x00000001u) + #define SCR_CTRL_SCR_READ_MASK (0x00000001u) + #define SCR_CTRL_SCR_READ_BIT (0) + #define SCR_CTRL_SCR_READ_BITS (1) + +#define SCR_BUSY *((volatile int32u *)0x400010ECu) +#define SCR_BUSY_REG *((volatile int32u *)0x400010ECu) +#define SCR_BUSY_ADDR (0x400010ECu) +#define SCR_BUSY_RESET (0x00000000u) + /* SCR_BUSY field */ + #define SCR_BUSY_SCR_BUSY (0x00000001u) + #define SCR_BUSY_SCR_BUSY_MASK (0x00000001u) + #define SCR_BUSY_SCR_BUSY_BIT (0) + #define SCR_BUSY_SCR_BUSY_BITS (1) + +#define SCR_ADDR *((volatile int32u *)0x400010F0u) +#define SCR_ADDR_REG *((volatile int32u *)0x400010F0u) +#define SCR_ADDR_ADDR (0x400010F0u) +#define SCR_ADDR_RESET (0x00000000u) + /* SCR_ADDR field */ + #define SCR_ADDR_SCR_ADDR (0x000000FFu) + #define SCR_ADDR_SCR_ADDR_MASK (0x000000FFu) + #define SCR_ADDR_SCR_ADDR_BIT (0) + #define SCR_ADDR_SCR_ADDR_BITS (8) + +#define SCR_WRITE *((volatile int32u *)0x400010F4u) +#define SCR_WRITE_REG *((volatile int32u *)0x400010F4u) +#define SCR_WRITE_ADDR (0x400010F4u) +#define SCR_WRITE_RESET (0x00000000u) + /* SCR_WRITE field */ + #define SCR_WRITE_SCR_WRITE (0x0000FFFFu) + #define SCR_WRITE_SCR_WRITE_MASK (0x0000FFFFu) + #define SCR_WRITE_SCR_WRITE_BIT (0) + #define SCR_WRITE_SCR_WRITE_BITS (16) + +#define SCR_READ *((volatile int32u *)0x400010F8u) +#define SCR_READ_REG *((volatile int32u *)0x400010F8u) +#define SCR_READ_ADDR (0x400010F8u) +#define SCR_READ_RESET (0x00000000u) + /* SCR_READ field */ + #define SCR_READ_SCR_READ (0x0000FFFFu) + #define SCR_READ_SCR_READ_MASK (0x0000FFFFu) + #define SCR_READ_SCR_READ_BIT (0) + #define SCR_READ_SCR_READ_BITS (16) + +#define SYNTH_LOCK *((volatile int32u *)0x400010FCu) +#define SYNTH_LOCK_REG *((volatile int32u *)0x400010FCu) +#define SYNTH_LOCK_ADDR (0x400010FCu) +#define SYNTH_LOCK_RESET (0x00000000u) + /* IN_LOCK field */ + #define SYNTH_LOCK_IN_LOCK (0x00000001u) + #define SYNTH_LOCK_IN_LOCK_MASK (0x00000001u) + #define SYNTH_LOCK_IN_LOCK_BIT (0) + #define SYNTH_LOCK_IN_LOCK_BITS (1) + +#define AN_CAL_STATUS *((volatile int32u *)0x40001100u) +#define AN_CAL_STATUS_REG *((volatile int32u *)0x40001100u) +#define AN_CAL_STATUS_ADDR (0x40001100u) +#define AN_CAL_STATUS_RESET (0x00000000u) + /* VCO_CTRL field */ + #define AN_CAL_STATUS_VCO_CTRL (0x0000000Cu) + #define AN_CAL_STATUS_VCO_CTRL_MASK (0x0000000Cu) + #define AN_CAL_STATUS_VCO_CTRL_BIT (2) + #define AN_CAL_STATUS_VCO_CTRL_BITS (2) + +#define BIAS_CAL_STATUS *((volatile int32u *)0x40001104u) +#define BIAS_CAL_STATUS_REG *((volatile int32u *)0x40001104u) +#define BIAS_CAL_STATUS_ADDR (0x40001104u) +#define BIAS_CAL_STATUS_RESET (0x00000000u) + /* VCOMP field */ + #define BIAS_CAL_STATUS_VCOMP (0x00000002u) + #define BIAS_CAL_STATUS_VCOMP_MASK (0x00000002u) + #define BIAS_CAL_STATUS_VCOMP_BIT (1) + #define BIAS_CAL_STATUS_VCOMP_BITS (1) + /* ICOMP field */ + #define BIAS_CAL_STATUS_ICOMP (0x00000001u) + #define BIAS_CAL_STATUS_ICOMP_MASK (0x00000001u) + #define BIAS_CAL_STATUS_ICOMP_BIT (0) + #define BIAS_CAL_STATUS_ICOMP_BITS (1) + +#define ATEST_SEL *((volatile int32u *)0x40001108u) +#define ATEST_SEL_REG *((volatile int32u *)0x40001108u) +#define ATEST_SEL_ADDR (0x40001108u) +#define ATEST_SEL_RESET (0x00000000u) + /* ATEST_CTRL field */ + #define ATEST_SEL_ATEST_CTRL (0x0000FF00u) + #define ATEST_SEL_ATEST_CTRL_MASK (0x0000FF00u) + #define ATEST_SEL_ATEST_CTRL_BIT (8) + #define ATEST_SEL_ATEST_CTRL_BITS (8) + /* ATEST_SEL field */ + #define ATEST_SEL_ATEST_SEL (0x0000001Fu) + #define ATEST_SEL_ATEST_SEL_MASK (0x0000001Fu) + #define ATEST_SEL_ATEST_SEL_BIT (0) + #define ATEST_SEL_ATEST_SEL_BITS (5) + +#define AN_EN_TEST *((volatile int32u *)0x4000110Cu) +#define AN_EN_TEST_REG *((volatile int32u *)0x4000110Cu) +#define AN_EN_TEST_ADDR (0x4000110Cu) +#define AN_EN_TEST_RESET (0x00000000u) + /* AN_TEST_MODE field */ + #define AN_EN_TEST_AN_TEST_MODE (0x00008000u) + #define AN_EN_TEST_AN_TEST_MODE_MASK (0x00008000u) + #define AN_EN_TEST_AN_TEST_MODE_BIT (15) + #define AN_EN_TEST_AN_TEST_MODE_BITS (1) + /* PFD_EN field */ + #define AN_EN_TEST_PFD_EN (0x00004000u) + #define AN_EN_TEST_PFD_EN_MASK (0x00004000u) + #define AN_EN_TEST_PFD_EN_BIT (14) + #define AN_EN_TEST_PFD_EN_BITS (1) + /* ADC_EN field */ + #define AN_EN_TEST_ADC_EN (0x00002000u) + #define AN_EN_TEST_ADC_EN_MASK (0x00002000u) + #define AN_EN_TEST_ADC_EN_BIT (13) + #define AN_EN_TEST_ADC_EN_BITS (1) + /* UNUSED field */ + #define AN_EN_TEST_UNUSED (0x00001000u) + #define AN_EN_TEST_UNUSED_MASK (0x00001000u) + #define AN_EN_TEST_UNUSED_BIT (12) + #define AN_EN_TEST_UNUSED_BITS (1) + /* PRE_FILT_EN field */ + #define AN_EN_TEST_PRE_FILT_EN (0x00000800u) + #define AN_EN_TEST_PRE_FILT_EN_MASK (0x00000800u) + #define AN_EN_TEST_PRE_FILT_EN_BIT (11) + #define AN_EN_TEST_PRE_FILT_EN_BITS (1) + /* IF_AMP_EN field */ + #define AN_EN_TEST_IF_AMP_EN (0x00000400u) + #define AN_EN_TEST_IF_AMP_EN_MASK (0x00000400u) + #define AN_EN_TEST_IF_AMP_EN_BIT (10) + #define AN_EN_TEST_IF_AMP_EN_BITS (1) + /* LNA_EN field */ + #define AN_EN_TEST_LNA_EN (0x00000200u) + #define AN_EN_TEST_LNA_EN_MASK (0x00000200u) + #define AN_EN_TEST_LNA_EN_BIT (9) + #define AN_EN_TEST_LNA_EN_BITS (1) + /* MIXER_EN field */ + #define AN_EN_TEST_MIXER_EN (0x00000100u) + #define AN_EN_TEST_MIXER_EN_MASK (0x00000100u) + #define AN_EN_TEST_MIXER_EN_BIT (8) + #define AN_EN_TEST_MIXER_EN_BITS (1) + /* CH_FILT_EN field */ + #define AN_EN_TEST_CH_FILT_EN (0x00000080u) + #define AN_EN_TEST_CH_FILT_EN_MASK (0x00000080u) + #define AN_EN_TEST_CH_FILT_EN_BIT (7) + #define AN_EN_TEST_CH_FILT_EN_BITS (1) + /* MOD_DAC_EN field */ + #define AN_EN_TEST_MOD_DAC_EN (0x00000040u) + #define AN_EN_TEST_MOD_DAC_EN_MASK (0x00000040u) + #define AN_EN_TEST_MOD_DAC_EN_BIT (6) + #define AN_EN_TEST_MOD_DAC_EN_BITS (1) + /* PA_EN field */ + #define AN_EN_TEST_PA_EN (0x00000010u) + #define AN_EN_TEST_PA_EN_MASK (0x00000010u) + #define AN_EN_TEST_PA_EN_BIT (4) + #define AN_EN_TEST_PA_EN_BITS (1) + /* PRESCALER_EN field */ + #define AN_EN_TEST_PRESCALER_EN (0x00000008u) + #define AN_EN_TEST_PRESCALER_EN_MASK (0x00000008u) + #define AN_EN_TEST_PRESCALER_EN_BIT (3) + #define AN_EN_TEST_PRESCALER_EN_BITS (1) + /* VCO_EN field */ + #define AN_EN_TEST_VCO_EN (0x00000004u) + #define AN_EN_TEST_VCO_EN_MASK (0x00000004u) + #define AN_EN_TEST_VCO_EN_BIT (2) + #define AN_EN_TEST_VCO_EN_BITS (1) + /* BIAS_EN field */ + #define AN_EN_TEST_BIAS_EN (0x00000001u) + #define AN_EN_TEST_BIAS_EN_MASK (0x00000001u) + #define AN_EN_TEST_BIAS_EN_BIT (0) + #define AN_EN_TEST_BIAS_EN_BITS (1) + +#define TUNE_FILTER_CTRL *((volatile int32u *)0x40001110u) +#define TUNE_FILTER_CTRL_REG *((volatile int32u *)0x40001110u) +#define TUNE_FILTER_CTRL_ADDR (0x40001110u) +#define TUNE_FILTER_CTRL_RESET (0x00000000u) + /* TUNE_FILTER_EN field */ + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN (0x00000002u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK (0x00000002u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT (1) + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS (1) + /* TUNE_FILTER_RESET field */ + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET (0x00000001u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK (0x00000001u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT (0) + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS (1) + +#define NOISE_EN *((volatile int32u *)0x40001114u) +#define NOISE_EN_REG *((volatile int32u *)0x40001114u) +#define NOISE_EN_ADDR (0x40001114u) +#define NOISE_EN_RESET (0x00000000u) + /* NOISE_EN field */ + #define NOISE_EN_NOISE_EN (0x00000001u) + #define NOISE_EN_NOISE_EN_MASK (0x00000001u) + #define NOISE_EN_NOISE_EN_BIT (0) + #define NOISE_EN_NOISE_EN_BITS (1) + +/* MAC block */ +#define DATA_MAC_BASE (0x40002000u) +#define DATA_MAC_END (0x400020C8u) +#define DATA_MAC_SIZE (DATA_MAC_END - DATA_MAC_BASE + 1) + +#define MAC_RX_ST_ADDR_A *((volatile int32u *)0x40002000u) +#define MAC_RX_ST_ADDR_A_REG *((volatile int32u *)0x40002000u) +#define MAC_RX_ST_ADDR_A_ADDR (0x40002000u) +#define MAC_RX_ST_ADDR_A_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_ST_ADDR_A field */ + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A (0x00001FFEu) + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK (0x00001FFEu) + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT (1) + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS (12) + +#define MAC_RX_END_ADDR_A *((volatile int32u *)0x40002004u) +#define MAC_RX_END_ADDR_A_REG *((volatile int32u *)0x40002004u) +#define MAC_RX_END_ADDR_A_ADDR (0x40002004u) +#define MAC_RX_END_ADDR_A_RESET (0x20000088u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_END_ADDR_A field */ + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A (0x00001FFEu) + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK (0x00001FFEu) + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT (1) + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS (12) + +#define MAC_RX_ST_ADDR_B *((volatile int32u *)0x40002008u) +#define MAC_RX_ST_ADDR_B_REG *((volatile int32u *)0x40002008u) +#define MAC_RX_ST_ADDR_B_ADDR (0x40002008u) +#define MAC_RX_ST_ADDR_B_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_ST_ADDR_B field */ + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B (0x00001FFEu) + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK (0x00001FFEu) + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT (1) + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS (12) + +#define MAC_RX_END_ADDR_B *((volatile int32u *)0x4000200Cu) +#define MAC_RX_END_ADDR_B_REG *((volatile int32u *)0x4000200Cu) +#define MAC_RX_END_ADDR_B_ADDR (0x4000200Cu) +#define MAC_RX_END_ADDR_B_RESET (0x20000088u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_END_ADDR_B field */ + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B (0x00001FFEu) + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK (0x00001FFEu) + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT (1) + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS (12) + +#define MAC_TX_ST_ADDR_A *((volatile int32u *)0x40002010u) +#define MAC_TX_ST_ADDR_A_REG *((volatile int32u *)0x40002010u) +#define MAC_TX_ST_ADDR_A_ADDR (0x40002010u) +#define MAC_TX_ST_ADDR_A_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_ST_ADDR_A field */ + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A (0x00001FFEu) + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK (0x00001FFEu) + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT (1) + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS (12) + +#define MAC_TX_END_ADDR_A *((volatile int32u *)0x40002014u) +#define MAC_TX_END_ADDR_A_REG *((volatile int32u *)0x40002014u) +#define MAC_TX_END_ADDR_A_ADDR (0x40002014u) +#define MAC_TX_END_ADDR_A_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_END_ADDR_A field */ + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A (0x00001FFEu) + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK (0x00001FFEu) + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT (1) + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS (12) + +#define MAC_TX_ST_ADDR_B *((volatile int32u *)0x40002018u) +#define MAC_TX_ST_ADDR_B_REG *((volatile int32u *)0x40002018u) +#define MAC_TX_ST_ADDR_B_ADDR (0x40002018u) +#define MAC_TX_ST_ADDR_B_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_ST_ADDR_B field */ + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B (0x00001FFEu) + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK (0x00001FFEu) + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT (1) + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS (12) + +#define MAC_TX_END_ADDR_B *((volatile int32u *)0x4000201Cu) +#define MAC_TX_END_ADDR_B_REG *((volatile int32u *)0x4000201Cu) +#define MAC_TX_END_ADDR_B_ADDR (0x4000201Cu) +#define MAC_TX_END_ADDR_B_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_END_ADDR_B field */ + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B (0x00001FFEu) + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK (0x00001FFEu) + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT (1) + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS (12) + +#define RX_A_COUNT *((volatile int32u *)0x40002020u) +#define RX_A_COUNT_REG *((volatile int32u *)0x40002020u) +#define RX_A_COUNT_ADDR (0x40002020u) +#define RX_A_COUNT_RESET (0x00000000u) + /* RX_A_COUNT field */ + #define RX_A_COUNT_RX_A_COUNT (0x000007FFu) + #define RX_A_COUNT_RX_A_COUNT_MASK (0x000007FFu) + #define RX_A_COUNT_RX_A_COUNT_BIT (0) + #define RX_A_COUNT_RX_A_COUNT_BITS (11) + +#define RX_B_COUNT *((volatile int32u *)0x40002024u) +#define RX_B_COUNT_REG *((volatile int32u *)0x40002024u) +#define RX_B_COUNT_ADDR (0x40002024u) +#define RX_B_COUNT_RESET (0x00000000u) + /* RX_B_COUNT field */ + #define RX_B_COUNT_RX_B_COUNT (0x000007FFu) + #define RX_B_COUNT_RX_B_COUNT_MASK (0x000007FFu) + #define RX_B_COUNT_RX_B_COUNT_BIT (0) + #define RX_B_COUNT_RX_B_COUNT_BITS (11) + +#define TX_COUNT *((volatile int32u *)0x40002028u) +#define TX_COUNT_REG *((volatile int32u *)0x40002028u) +#define TX_COUNT_ADDR (0x40002028u) +#define TX_COUNT_RESET (0x00000000u) + /* TX_COUNT field */ + #define TX_COUNT_TX_COUNT (0x000007FFu) + #define TX_COUNT_TX_COUNT_MASK (0x000007FFu) + #define TX_COUNT_TX_COUNT_BIT (0) + #define TX_COUNT_TX_COUNT_BITS (11) + +#define MAC_DMA_STATUS *((volatile int32u *)0x4000202Cu) +#define MAC_DMA_STATUS_REG *((volatile int32u *)0x4000202Cu) +#define MAC_DMA_STATUS_ADDR (0x4000202Cu) +#define MAC_DMA_STATUS_RESET (0x00000000u) + /* TX_ACTIVE_B field */ + #define MAC_DMA_STATUS_TX_ACTIVE_B (0x00000008u) + #define MAC_DMA_STATUS_TX_ACTIVE_B_MASK (0x00000008u) + #define MAC_DMA_STATUS_TX_ACTIVE_B_BIT (3) + #define MAC_DMA_STATUS_TX_ACTIVE_B_BITS (1) + /* TX_ACTIVE_A field */ + #define MAC_DMA_STATUS_TX_ACTIVE_A (0x00000004u) + #define MAC_DMA_STATUS_TX_ACTIVE_A_MASK (0x00000004u) + #define MAC_DMA_STATUS_TX_ACTIVE_A_BIT (2) + #define MAC_DMA_STATUS_TX_ACTIVE_A_BITS (1) + /* RX_ACTIVE_B field */ + #define MAC_DMA_STATUS_RX_ACTIVE_B (0x00000002u) + #define MAC_DMA_STATUS_RX_ACTIVE_B_MASK (0x00000002u) + #define MAC_DMA_STATUS_RX_ACTIVE_B_BIT (1) + #define MAC_DMA_STATUS_RX_ACTIVE_B_BITS (1) + /* RX_ACTIVE_A field */ + #define MAC_DMA_STATUS_RX_ACTIVE_A (0x00000001u) + #define MAC_DMA_STATUS_RX_ACTIVE_A_MASK (0x00000001u) + #define MAC_DMA_STATUS_RX_ACTIVE_A_BIT (0) + #define MAC_DMA_STATUS_RX_ACTIVE_A_BITS (1) + +#define MAC_DMA_CONFIG *((volatile int32u *)0x40002030u) +#define MAC_DMA_CONFIG_REG *((volatile int32u *)0x40002030u) +#define MAC_DMA_CONFIG_ADDR (0x40002030u) +#define MAC_DMA_CONFIG_RESET (0x00000000u) + /* TX_DMA_RESET field */ + #define MAC_DMA_CONFIG_TX_DMA_RESET (0x00000020u) + #define MAC_DMA_CONFIG_TX_DMA_RESET_MASK (0x00000020u) + #define MAC_DMA_CONFIG_TX_DMA_RESET_BIT (5) + #define MAC_DMA_CONFIG_TX_DMA_RESET_BITS (1) + /* RX_DMA_RESET field */ + #define MAC_DMA_CONFIG_RX_DMA_RESET (0x00000010u) + #define MAC_DMA_CONFIG_RX_DMA_RESET_MASK (0x00000010u) + #define MAC_DMA_CONFIG_RX_DMA_RESET_BIT (4) + #define MAC_DMA_CONFIG_RX_DMA_RESET_BITS (1) + /* TX_LOAD_B field */ + #define MAC_DMA_CONFIG_TX_LOAD_B (0x00000008u) + #define MAC_DMA_CONFIG_TX_LOAD_B_MASK (0x00000008u) + #define MAC_DMA_CONFIG_TX_LOAD_B_BIT (3) + #define MAC_DMA_CONFIG_TX_LOAD_B_BITS (1) + /* TX_LOAD_A field */ + #define MAC_DMA_CONFIG_TX_LOAD_A (0x00000004u) + #define MAC_DMA_CONFIG_TX_LOAD_A_MASK (0x00000004u) + #define MAC_DMA_CONFIG_TX_LOAD_A_BIT (2) + #define MAC_DMA_CONFIG_TX_LOAD_A_BITS (1) + /* RX_LOAD_B field */ + #define MAC_DMA_CONFIG_RX_LOAD_B (0x00000002u) + #define MAC_DMA_CONFIG_RX_LOAD_B_MASK (0x00000002u) + #define MAC_DMA_CONFIG_RX_LOAD_B_BIT (1) + #define MAC_DMA_CONFIG_RX_LOAD_B_BITS (1) + /* RX_LOAD_A field */ + #define MAC_DMA_CONFIG_RX_LOAD_A (0x00000001u) + #define MAC_DMA_CONFIG_RX_LOAD_A_MASK (0x00000001u) + #define MAC_DMA_CONFIG_RX_LOAD_A_BIT (0) + #define MAC_DMA_CONFIG_RX_LOAD_A_BITS (1) + +#define MAC_TIMER *((volatile int32u *)0x40002038u) +#define MAC_TIMER_REG *((volatile int32u *)0x40002038u) +#define MAC_TIMER_ADDR (0x40002038u) +#define MAC_TIMER_RESET (0x00000000u) + /* MAC_TIMER field */ + #define MAC_TIMER_MAC_TIMER (0x000FFFFFu) + #define MAC_TIMER_MAC_TIMER_MASK (0x000FFFFFu) + #define MAC_TIMER_MAC_TIMER_BIT (0) + #define MAC_TIMER_MAC_TIMER_BITS (20) + +#define MAC_TIMER_COMPARE_A_H *((volatile int32u *)0x40002040u) +#define MAC_TIMER_COMPARE_A_H_REG *((volatile int32u *)0x40002040u) +#define MAC_TIMER_COMPARE_A_H_ADDR (0x40002040u) +#define MAC_TIMER_COMPARE_A_H_RESET (0x00000000u) + /* MAC_COMPARE_A_H field */ + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H (0x0000000Fu) + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK (0x0000000Fu) + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT (0) + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS (4) + +#define MAC_TIMER_COMPARE_A_L *((volatile int32u *)0x40002044u) +#define MAC_TIMER_COMPARE_A_L_REG *((volatile int32u *)0x40002044u) +#define MAC_TIMER_COMPARE_A_L_ADDR (0x40002044u) +#define MAC_TIMER_COMPARE_A_L_RESET (0x00000000u) + /* MAC_COMPARE_A_L field */ + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L (0x0000FFFFu) + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK (0x0000FFFFu) + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT (0) + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS (16) + +#define MAC_TIMER_COMPARE_B_H *((volatile int32u *)0x40002048u) +#define MAC_TIMER_COMPARE_B_H_REG *((volatile int32u *)0x40002048u) +#define MAC_TIMER_COMPARE_B_H_ADDR (0x40002048u) +#define MAC_TIMER_COMPARE_B_H_RESET (0x00000000u) + /* MAC_COMPARE_B_H field */ + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H (0x0000000Fu) + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK (0x0000000Fu) + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT (0) + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS (4) + +#define MAC_TIMER_COMPARE_B_L *((volatile int32u *)0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_REG *((volatile int32u *)0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_ADDR (0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_RESET (0x00000000u) + /* MAC_COMPARE_B_L field */ + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L (0x0000FFFFu) + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK (0x0000FFFFu) + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT (0) + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS (16) + +#define MAC_TIMER_CAPTURE_H *((volatile int32u *)0x40002050u) +#define MAC_TIMER_CAPTURE_H_REG *((volatile int32u *)0x40002050u) +#define MAC_TIMER_CAPTURE_H_ADDR (0x40002050u) +#define MAC_TIMER_CAPTURE_H_RESET (0x00000000u) + /* MAC_SFD_CAPTURE_HIGH field */ + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH (0x0000000Fu) + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK (0x0000000Fu) + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT (0) + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS (4) + +#define MAC_TIMER_CAPTURE_L *((volatile int32u *)0x40002054u) +#define MAC_TIMER_CAPTURE_L_REG *((volatile int32u *)0x40002054u) +#define MAC_TIMER_CAPTURE_L_ADDR (0x40002054u) +#define MAC_TIMER_CAPTURE_L_RESET (0x00000000u) + /* MAC_SFD_CAPTURE_LOW field */ + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW (0x0000FFFFu) + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK (0x0000FFFFu) + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT (0) + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS (16) + +#define MAC_BO_TIMER *((volatile int32u *)0x40002058u) +#define MAC_BO_TIMER_REG *((volatile int32u *)0x40002058u) +#define MAC_BO_TIMER_ADDR (0x40002058u) +#define MAC_BO_TIMER_RESET (0x00000000u) + /* MAC_BO_TIMER field */ + #define MAC_BO_TIMER_MAC_BO_TIMER (0x00000FFFu) + #define MAC_BO_TIMER_MAC_BO_TIMER_MASK (0x00000FFFu) + #define MAC_BO_TIMER_MAC_BO_TIMER_BIT (0) + #define MAC_BO_TIMER_MAC_BO_TIMER_BITS (12) + +#define MAC_BOP_TIMER *((volatile int32u *)0x4000205Cu) +#define MAC_BOP_TIMER_REG *((volatile int32u *)0x4000205Cu) +#define MAC_BOP_TIMER_ADDR (0x4000205Cu) +#define MAC_BOP_TIMER_RESET (0x00000000u) + /* MAC_BOP_TIMER field */ + #define MAC_BOP_TIMER_MAC_BOP_TIMER (0x0000007Fu) + #define MAC_BOP_TIMER_MAC_BOP_TIMER_MASK (0x0000007Fu) + #define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT (0) + #define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS (7) + +#define MAC_TX_STROBE *((volatile int32u *)0x40002060u) +#define MAC_TX_STROBE_REG *((volatile int32u *)0x40002060u) +#define MAC_TX_STROBE_ADDR (0x40002060u) +#define MAC_TX_STROBE_RESET (0x00000000u) + /* AUTO_CRC_TX field */ + #define MAC_TX_STROBE_AUTO_CRC_TX (0x00000008u) + #define MAC_TX_STROBE_AUTO_CRC_TX_MASK (0x00000008u) + #define MAC_TX_STROBE_AUTO_CRC_TX_BIT (3) + #define MAC_TX_STROBE_AUTO_CRC_TX_BITS (1) + /* CCA_ON field */ + #define MAC_TX_STROBE_CCA_ON (0x00000004u) + #define MAC_TX_STROBE_CCA_ON_MASK (0x00000004u) + #define MAC_TX_STROBE_CCA_ON_BIT (2) + #define MAC_TX_STROBE_CCA_ON_BITS (1) + /* MAC_TX_RST field */ + #define MAC_TX_STROBE_MAC_TX_RST (0x00000002u) + #define MAC_TX_STROBE_MAC_TX_RST_MASK (0x00000002u) + #define MAC_TX_STROBE_MAC_TX_RST_BIT (1) + #define MAC_TX_STROBE_MAC_TX_RST_BITS (1) + /* START_TX field */ + #define MAC_TX_STROBE_START_TX (0x00000001u) + #define MAC_TX_STROBE_START_TX_MASK (0x00000001u) + #define MAC_TX_STROBE_START_TX_BIT (0) + #define MAC_TX_STROBE_START_TX_BITS (1) + +#define MAC_ACK_STROBE *((volatile int32u *)0x40002064u) +#define MAC_ACK_STROBE_REG *((volatile int32u *)0x40002064u) +#define MAC_ACK_STROBE_ADDR (0x40002064u) +#define MAC_ACK_STROBE_RESET (0x00000000u) + /* MANUAL_ACK field */ + #define MAC_ACK_STROBE_MANUAL_ACK (0x00000002u) + #define MAC_ACK_STROBE_MANUAL_ACK_MASK (0x00000002u) + #define MAC_ACK_STROBE_MANUAL_ACK_BIT (1) + #define MAC_ACK_STROBE_MANUAL_ACK_BITS (1) + /* FRAME_PENDING field */ + #define MAC_ACK_STROBE_FRAME_PENDING (0x00000001u) + #define MAC_ACK_STROBE_FRAME_PENDING_MASK (0x00000001u) + #define MAC_ACK_STROBE_FRAME_PENDING_BIT (0) + #define MAC_ACK_STROBE_FRAME_PENDING_BITS (1) + +#define MAC_STATUS *((volatile int32u *)0x40002068u) +#define MAC_STATUS_REG *((volatile int32u *)0x40002068u) +#define MAC_STATUS_ADDR (0x40002068u) +#define MAC_STATUS_RESET (0x00000000u) + /* RX_B_PEND_TX_ACK field */ + #define MAC_STATUS_RX_B_PEND_TX_ACK (0x00000800u) + #define MAC_STATUS_RX_B_PEND_TX_ACK_MASK (0x00000800u) + #define MAC_STATUS_RX_B_PEND_TX_ACK_BIT (11) + #define MAC_STATUS_RX_B_PEND_TX_ACK_BITS (1) + /* RX_A_PEND_TX_ACK field */ + #define MAC_STATUS_RX_A_PEND_TX_ACK (0x00000400u) + #define MAC_STATUS_RX_A_PEND_TX_ACK_MASK (0x00000400u) + #define MAC_STATUS_RX_A_PEND_TX_ACK_BIT (10) + #define MAC_STATUS_RX_A_PEND_TX_ACK_BITS (1) + /* RX_B_LAST_UNLOAD field */ + #define MAC_STATUS_RX_B_LAST_UNLOAD (0x00000200u) + #define MAC_STATUS_RX_B_LAST_UNLOAD_MASK (0x00000200u) + #define MAC_STATUS_RX_B_LAST_UNLOAD_BIT (9) + #define MAC_STATUS_RX_B_LAST_UNLOAD_BITS (1) + /* RX_A_LAST_UNLOAD field */ + #define MAC_STATUS_RX_A_LAST_UNLOAD (0x00000100u) + #define MAC_STATUS_RX_A_LAST_UNLOAD_MASK (0x00000100u) + #define MAC_STATUS_RX_A_LAST_UNLOAD_BIT (8) + #define MAC_STATUS_RX_A_LAST_UNLOAD_BITS (1) + /* WRONG_FORMAT field */ + #define MAC_STATUS_WRONG_FORMAT (0x00000080u) + #define MAC_STATUS_WRONG_FORMAT_MASK (0x00000080u) + #define MAC_STATUS_WRONG_FORMAT_BIT (7) + #define MAC_STATUS_WRONG_FORMAT_BITS (1) + /* WRONG_ADDRESS field */ + #define MAC_STATUS_WRONG_ADDRESS (0x00000040u) + #define MAC_STATUS_WRONG_ADDRESS_MASK (0x00000040u) + #define MAC_STATUS_WRONG_ADDRESS_BIT (6) + #define MAC_STATUS_WRONG_ADDRESS_BITS (1) + /* RX_ACK_REC field */ + #define MAC_STATUS_RX_ACK_REC (0x00000020u) + #define MAC_STATUS_RX_ACK_REC_MASK (0x00000020u) + #define MAC_STATUS_RX_ACK_REC_BIT (5) + #define MAC_STATUS_RX_ACK_REC_BITS (1) + /* SENDING_ACK field */ + #define MAC_STATUS_SENDING_ACK (0x00000010u) + #define MAC_STATUS_SENDING_ACK_MASK (0x00000010u) + #define MAC_STATUS_SENDING_ACK_BIT (4) + #define MAC_STATUS_SENDING_ACK_BITS (1) + /* RUN_BO field */ + #define MAC_STATUS_RUN_BO (0x00000008u) + #define MAC_STATUS_RUN_BO_MASK (0x00000008u) + #define MAC_STATUS_RUN_BO_BIT (3) + #define MAC_STATUS_RUN_BO_BITS (1) + /* TX_FRAME field */ + #define MAC_STATUS_TX_FRAME (0x00000004u) + #define MAC_STATUS_TX_FRAME_MASK (0x00000004u) + #define MAC_STATUS_TX_FRAME_BIT (2) + #define MAC_STATUS_TX_FRAME_BITS (1) + /* RX_FRAME field */ + #define MAC_STATUS_RX_FRAME (0x00000002u) + #define MAC_STATUS_RX_FRAME_MASK (0x00000002u) + #define MAC_STATUS_RX_FRAME_BIT (1) + #define MAC_STATUS_RX_FRAME_BITS (1) + /* RX_CRC_PASS field */ + #define MAC_STATUS_RX_CRC_PASS (0x00000001u) + #define MAC_STATUS_RX_CRC_PASS_MASK (0x00000001u) + #define MAC_STATUS_RX_CRC_PASS_BIT (0) + #define MAC_STATUS_RX_CRC_PASS_BITS (1) + +#define TX_CRC *((volatile int32u *)0x4000206Cu) +#define TX_CRC_REG *((volatile int32u *)0x4000206Cu) +#define TX_CRC_ADDR (0x4000206Cu) +#define TX_CRC_RESET (0x00000000u) + /* TX_CRC field */ + #define TX_CRC_TX_CRC (0x0000FFFFu) + #define TX_CRC_TX_CRC_MASK (0x0000FFFFu) + #define TX_CRC_TX_CRC_BIT (0) + #define TX_CRC_TX_CRC_BITS (16) + +#define RX_CRC *((volatile int32u *)0x40002070u) +#define RX_CRC_REG *((volatile int32u *)0x40002070u) +#define RX_CRC_ADDR (0x40002070u) +#define RX_CRC_RESET (0x00000000u) + /* RX_CRC field */ + #define RX_CRC_RX_CRC (0x0000FFFFu) + #define RX_CRC_RX_CRC_MASK (0x0000FFFFu) + #define RX_CRC_RX_CRC_BIT (0) + #define RX_CRC_RX_CRC_BITS (16) + +#define MAC_ACK_TO *((volatile int32u *)0x40002074u) +#define MAC_ACK_TO_REG *((volatile int32u *)0x40002074u) +#define MAC_ACK_TO_ADDR (0x40002074u) +#define MAC_ACK_TO_RESET (0x00000300u) + /* ACK_TO field */ + #define MAC_ACK_TO_ACK_TO (0x00003FFFu) + #define MAC_ACK_TO_ACK_TO_MASK (0x00003FFFu) + #define MAC_ACK_TO_ACK_TO_BIT (0) + #define MAC_ACK_TO_ACK_TO_BITS (14) + +#define MAC_BOP_COMPARE *((volatile int32u *)0x40002078u) +#define MAC_BOP_COMPARE_REG *((volatile int32u *)0x40002078u) +#define MAC_BOP_COMPARE_ADDR (0x40002078u) +#define MAC_BOP_COMPARE_RESET (0x00000014u) + /* MAC_BOP_COMPARE field */ + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE (0x0000007Fu) + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK (0x0000007Fu) + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT (0) + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS (7) + +#define MAC_TX_ACK_FRAME *((volatile int32u *)0x4000207Cu) +#define MAC_TX_ACK_FRAME_REG *((volatile int32u *)0x4000207Cu) +#define MAC_TX_ACK_FRAME_ADDR (0x4000207Cu) +#define MAC_TX_ACK_FRAME_RESET (0x00000002u) + /* ACK_SRC_AM field */ + #define MAC_TX_ACK_FRAME_ACK_SRC_AM (0x0000C000u) + #define MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK (0x0000C000u) + #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT (14) + #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS (2) + /* RES1213 field */ + #define MAC_TX_ACK_FRAME_RES1213 (0x00003000u) + #define MAC_TX_ACK_FRAME_RES1213_MASK (0x00003000u) + #define MAC_TX_ACK_FRAME_RES1213_BIT (12) + #define MAC_TX_ACK_FRAME_RES1213_BITS (2) + /* ACK_DST_AM field */ + #define MAC_TX_ACK_FRAME_ACK_DST_AM (0x00000C00u) + #define MAC_TX_ACK_FRAME_ACK_DST_AM_MASK (0x00000C00u) + #define MAC_TX_ACK_FRAME_ACK_DST_AM_BIT (10) + #define MAC_TX_ACK_FRAME_ACK_DST_AM_BITS (2) + /* RES789 field */ + #define MAC_TX_ACK_FRAME_RES789 (0x00000380u) + #define MAC_TX_ACK_FRAME_RES789_MASK (0x00000380u) + #define MAC_TX_ACK_FRAME_RES789_BIT (7) + #define MAC_TX_ACK_FRAME_RES789_BITS (3) + /* ACK_IP field */ + #define MAC_TX_ACK_FRAME_ACK_IP (0x00000040u) + #define MAC_TX_ACK_FRAME_ACK_IP_MASK (0x00000040u) + #define MAC_TX_ACK_FRAME_ACK_IP_BIT (6) + #define MAC_TX_ACK_FRAME_ACK_IP_BITS (1) + /* ACK_ACK_REQ field */ + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ (0x00000020u) + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK (0x00000020u) + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT (5) + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS (1) + /* ACK_FRAME_P field */ + #define MAC_TX_ACK_FRAME_ACK_FRAME_P (0x00000010u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK (0x00000010u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT (4) + #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS (1) + /* ACK_SEC_EN field */ + #define MAC_TX_ACK_FRAME_ACK_SEC_EN (0x00000008u) + #define MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK (0x00000008u) + #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT (3) + #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS (1) + /* ACK_FRAME_T field */ + #define MAC_TX_ACK_FRAME_ACK_FRAME_T (0x00000007u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK (0x00000007u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT (0) + #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS (3) + +#define MAC_CONFIG *((volatile int32u *)0x40002080u) +#define MAC_CONFIG_REG *((volatile int32u *)0x40002080u) +#define MAC_CONFIG_ADDR (0x40002080u) +#define MAC_CONFIG_RESET (0x00000000u) + /* RSSI_INST_EN field */ + #define MAC_CONFIG_RSSI_INST_EN (0x00000004u) + #define MAC_CONFIG_RSSI_INST_EN_MASK (0x00000004u) + #define MAC_CONFIG_RSSI_INST_EN_BIT (2) + #define MAC_CONFIG_RSSI_INST_EN_BITS (1) + /* SPI_SPY_EN field */ + #define MAC_CONFIG_SPI_SPY_EN (0x00000002u) + #define MAC_CONFIG_SPI_SPY_EN_MASK (0x00000002u) + #define MAC_CONFIG_SPI_SPY_EN_BIT (1) + #define MAC_CONFIG_SPI_SPY_EN_BITS (1) + /* MAC_MODE field */ + #define MAC_CONFIG_MAC_MODE (0x00000001u) + #define MAC_CONFIG_MAC_MODE_MASK (0x00000001u) + #define MAC_CONFIG_MAC_MODE_BIT (0) + #define MAC_CONFIG_MAC_MODE_BITS (1) + +#define MAC_RX_CONFIG *((volatile int32u *)0x40002084u) +#define MAC_RX_CONFIG_REG *((volatile int32u *)0x40002084u) +#define MAC_RX_CONFIG_ADDR (0x40002084u) +#define MAC_RX_CONFIG_RESET (0x00000000u) + /* AUTO_ACK field */ + #define MAC_RX_CONFIG_AUTO_ACK (0x00000080u) + #define MAC_RX_CONFIG_AUTO_ACK_MASK (0x00000080u) + #define MAC_RX_CONFIG_AUTO_ACK_BIT (7) + #define MAC_RX_CONFIG_AUTO_ACK_BITS (1) + /* APPEND_INFO field */ + #define MAC_RX_CONFIG_APPEND_INFO (0x00000040u) + #define MAC_RX_CONFIG_APPEND_INFO_MASK (0x00000040u) + #define MAC_RX_CONFIG_APPEND_INFO_BIT (6) + #define MAC_RX_CONFIG_APPEND_INFO_BITS (1) + /* COORDINATOR field */ + #define MAC_RX_CONFIG_COORDINATOR (0x00000020u) + #define MAC_RX_CONFIG_COORDINATOR_MASK (0x00000020u) + #define MAC_RX_CONFIG_COORDINATOR_BIT (5) + #define MAC_RX_CONFIG_COORDINATOR_BITS (1) + /* FILT_ADDR_ON field */ + #define MAC_RX_CONFIG_FILT_ADDR_ON (0x00000010u) + #define MAC_RX_CONFIG_FILT_ADDR_ON_MASK (0x00000010u) + #define MAC_RX_CONFIG_FILT_ADDR_ON_BIT (4) + #define MAC_RX_CONFIG_FILT_ADDR_ON_BITS (1) + /* RES_FILT_PASS_ADDR field */ + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR (0x00000008u) + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK (0x00000008u) + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT (3) + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS (1) + /* RES_FILT_PASS field */ + #define MAC_RX_CONFIG_RES_FILT_PASS (0x00000004u) + #define MAC_RX_CONFIG_RES_FILT_PASS_MASK (0x00000004u) + #define MAC_RX_CONFIG_RES_FILT_PASS_BIT (2) + #define MAC_RX_CONFIG_RES_FILT_PASS_BITS (1) + /* FILT_FORMAT_ON field */ + #define MAC_RX_CONFIG_FILT_FORMAT_ON (0x00000002u) + #define MAC_RX_CONFIG_FILT_FORMAT_ON_MASK (0x00000002u) + #define MAC_RX_CONFIG_FILT_FORMAT_ON_BIT (1) + #define MAC_RX_CONFIG_FILT_FORMAT_ON_BITS (1) + /* MAC_RX_RST field */ + #define MAC_RX_CONFIG_MAC_RX_RST (0x00000001u) + #define MAC_RX_CONFIG_MAC_RX_RST_MASK (0x00000001u) + #define MAC_RX_CONFIG_MAC_RX_RST_BIT (0) + #define MAC_RX_CONFIG_MAC_RX_RST_BITS (1) + +#define MAC_TX_CONFIG *((volatile int32u *)0x40002088u) +#define MAC_TX_CONFIG_REG *((volatile int32u *)0x40002088u) +#define MAC_TX_CONFIG_ADDR (0x40002088u) +#define MAC_TX_CONFIG_RESET (0x00000008u) + /* SLOTTED field */ + #define MAC_TX_CONFIG_SLOTTED (0x00000010u) + #define MAC_TX_CONFIG_SLOTTED_MASK (0x00000010u) + #define MAC_TX_CONFIG_SLOTTED_BIT (4) + #define MAC_TX_CONFIG_SLOTTED_BITS (1) + /* CCA_DELAY field */ + #define MAC_TX_CONFIG_CCA_DELAY (0x00000008u) + #define MAC_TX_CONFIG_CCA_DELAY_MASK (0x00000008u) + #define MAC_TX_CONFIG_CCA_DELAY_BIT (3) + #define MAC_TX_CONFIG_CCA_DELAY_BITS (1) + /* SLOTTED_ACK field */ + #define MAC_TX_CONFIG_SLOTTED_ACK (0x00000004u) + #define MAC_TX_CONFIG_SLOTTED_ACK_MASK (0x00000004u) + #define MAC_TX_CONFIG_SLOTTED_ACK_BIT (2) + #define MAC_TX_CONFIG_SLOTTED_ACK_BITS (1) + /* INFINITE_CRC field */ + #define MAC_TX_CONFIG_INFINITE_CRC (0x00000002u) + #define MAC_TX_CONFIG_INFINITE_CRC_MASK (0x00000002u) + #define MAC_TX_CONFIG_INFINITE_CRC_BIT (1) + #define MAC_TX_CONFIG_INFINITE_CRC_BITS (1) + /* WAIT_ACK field */ + #define MAC_TX_CONFIG_WAIT_ACK (0x00000001u) + #define MAC_TX_CONFIG_WAIT_ACK_MASK (0x00000001u) + #define MAC_TX_CONFIG_WAIT_ACK_BIT (0) + #define MAC_TX_CONFIG_WAIT_ACK_BITS (1) + +#define MAC_TIMER_CTRL *((volatile int32u *)0x4000208Cu) +#define MAC_TIMER_CTRL_REG *((volatile int32u *)0x4000208Cu) +#define MAC_TIMER_CTRL_ADDR (0x4000208Cu) +#define MAC_TIMER_CTRL_RESET (0x00000000u) + /* COMP_A_SYNC field */ + #define MAC_TIMER_CTRL_COMP_A_SYNC (0x00000040u) + #define MAC_TIMER_CTRL_COMP_A_SYNC_MASK (0x00000040u) + #define MAC_TIMER_CTRL_COMP_A_SYNC_BIT (6) + #define MAC_TIMER_CTRL_COMP_A_SYNC_BITS (1) + /* BOP_TIMER_RST field */ + #define MAC_TIMER_CTRL_BOP_TIMER_RST (0x00000020u) + #define MAC_TIMER_CTRL_BOP_TIMER_RST_MASK (0x00000020u) + #define MAC_TIMER_CTRL_BOP_TIMER_RST_BIT (5) + #define MAC_TIMER_CTRL_BOP_TIMER_RST_BITS (1) + /* BOP_TIMER_EN field */ + #define MAC_TIMER_CTRL_BOP_TIMER_EN (0x00000010u) + #define MAC_TIMER_CTRL_BOP_TIMER_EN_MASK (0x00000010u) + #define MAC_TIMER_CTRL_BOP_TIMER_EN_BIT (4) + #define MAC_TIMER_CTRL_BOP_TIMER_EN_BITS (1) + /* BO_TIMER_RST field */ + #define MAC_TIMER_CTRL_BO_TIMER_RST (0x00000008u) + #define MAC_TIMER_CTRL_BO_TIMER_RST_MASK (0x00000008u) + #define MAC_TIMER_CTRL_BO_TIMER_RST_BIT (3) + #define MAC_TIMER_CTRL_BO_TIMER_RST_BITS (1) + /* BO_TIMER_EN field */ + #define MAC_TIMER_CTRL_BO_TIMER_EN (0x00000004u) + #define MAC_TIMER_CTRL_BO_TIMER_EN_MASK (0x00000004u) + #define MAC_TIMER_CTRL_BO_TIMER_EN_BIT (2) + #define MAC_TIMER_CTRL_BO_TIMER_EN_BITS (1) + /* MAC_TIMER_RST field */ + #define MAC_TIMER_CTRL_MAC_TIMER_RST (0x00000002u) + #define MAC_TIMER_CTRL_MAC_TIMER_RST_MASK (0x00000002u) + #define MAC_TIMER_CTRL_MAC_TIMER_RST_BIT (1) + #define MAC_TIMER_CTRL_MAC_TIMER_RST_BITS (1) + /* MAC_TIMER_EN field */ + #define MAC_TIMER_CTRL_MAC_TIMER_EN (0x00000001u) + #define MAC_TIMER_CTRL_MAC_TIMER_EN_MASK (0x00000001u) + #define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT (0) + #define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS (1) + +#define PAN_ID *((volatile int32u *)0x40002090u) +#define PAN_ID_REG *((volatile int32u *)0x40002090u) +#define PAN_ID_ADDR (0x40002090u) +#define PAN_ID_RESET (0x00000000u) + /* PAN_ID field */ + #define PAN_ID_PAN_ID (0x0000FFFFu) + #define PAN_ID_PAN_ID_MASK (0x0000FFFFu) + #define PAN_ID_PAN_ID_BIT (0) + #define PAN_ID_PAN_ID_BITS (16) + +#define SHORT_ADDR *((volatile int32u *)0x40002094u) +#define SHORT_ADDR_REG *((volatile int32u *)0x40002094u) +#define SHORT_ADDR_ADDR (0x40002094u) +#define SHORT_ADDR_RESET (0x00000000u) + /* SHORT_ADDR field */ + #define SHORT_ADDR_SHORT_ADDR (0x0000FFFFu) + #define SHORT_ADDR_SHORT_ADDR_MASK (0x0000FFFFu) + #define SHORT_ADDR_SHORT_ADDR_BIT (0) + #define SHORT_ADDR_SHORT_ADDR_BITS (16) + +#define EXT_ADDR_0 *((volatile int32u *)0x40002098u) +#define EXT_ADDR_0_REG *((volatile int32u *)0x40002098u) +#define EXT_ADDR_0_ADDR (0x40002098u) +#define EXT_ADDR_0_RESET (0x00000000u) + /* EXT_ADDR_0 field */ + #define EXT_ADDR_0_EXT_ADDR_0 (0x0000FFFFu) + #define EXT_ADDR_0_EXT_ADDR_0_MASK (0x0000FFFFu) + #define EXT_ADDR_0_EXT_ADDR_0_BIT (0) + #define EXT_ADDR_0_EXT_ADDR_0_BITS (16) + +#define EXT_ADDR_1 *((volatile int32u *)0x4000209Cu) +#define EXT_ADDR_1_REG *((volatile int32u *)0x4000209Cu) +#define EXT_ADDR_1_ADDR (0x4000209Cu) +#define EXT_ADDR_1_RESET (0x00000000u) + /* EXT_ADDR_1 field */ + #define EXT_ADDR_1_EXT_ADDR_1 (0x0000FFFFu) + #define EXT_ADDR_1_EXT_ADDR_1_MASK (0x0000FFFFu) + #define EXT_ADDR_1_EXT_ADDR_1_BIT (0) + #define EXT_ADDR_1_EXT_ADDR_1_BITS (16) + +#define EXT_ADDR_2 *((volatile int32u *)0x400020A0u) +#define EXT_ADDR_2_REG *((volatile int32u *)0x400020A0u) +#define EXT_ADDR_2_ADDR (0x400020A0u) +#define EXT_ADDR_2_RESET (0x00000000u) + /* EXT_ADDR_2 field */ + #define EXT_ADDR_2_EXT_ADDR_2 (0x0000FFFFu) + #define EXT_ADDR_2_EXT_ADDR_2_MASK (0x0000FFFFu) + #define EXT_ADDR_2_EXT_ADDR_2_BIT (0) + #define EXT_ADDR_2_EXT_ADDR_2_BITS (16) + +#define EXT_ADDR_3 *((volatile int32u *)0x400020A4u) +#define EXT_ADDR_3_REG *((volatile int32u *)0x400020A4u) +#define EXT_ADDR_3_ADDR (0x400020A4u) +#define EXT_ADDR_3_RESET (0x00000000u) + /* EXT_ADDR_3 field */ + #define EXT_ADDR_3_EXT_ADDR_3 (0x0000FFFFu) + #define EXT_ADDR_3_EXT_ADDR_3_MASK (0x0000FFFFu) + #define EXT_ADDR_3_EXT_ADDR_3_BIT (0) + #define EXT_ADDR_3_EXT_ADDR_3_BITS (16) + +#define MAC_STATE *((volatile int32u *)0x400020A8u) +#define MAC_STATE_REG *((volatile int32u *)0x400020A8u) +#define MAC_STATE_ADDR (0x400020A8u) +#define MAC_STATE_RESET (0x00000000u) + /* SPY_STATE field */ + #define MAC_STATE_SPY_STATE (0x00000700u) + #define MAC_STATE_SPY_STATE_MASK (0x00000700u) + #define MAC_STATE_SPY_STATE_BIT (8) + #define MAC_STATE_SPY_STATE_BITS (3) + /* ACK_STATE field */ + #define MAC_STATE_ACK_STATE (0x000000C0u) + #define MAC_STATE_ACK_STATE_MASK (0x000000C0u) + #define MAC_STATE_ACK_STATE_BIT (6) + #define MAC_STATE_ACK_STATE_BITS (2) + /* BO_STATE field */ + #define MAC_STATE_BO_STATE (0x0000003Cu) + #define MAC_STATE_BO_STATE_MASK (0x0000003Cu) + #define MAC_STATE_BO_STATE_BIT (2) + #define MAC_STATE_BO_STATE_BITS (4) + /* TOP_STATE field */ + #define MAC_STATE_TOP_STATE (0x00000003u) + #define MAC_STATE_TOP_STATE_MASK (0x00000003u) + #define MAC_STATE_TOP_STATE_BIT (0) + #define MAC_STATE_TOP_STATE_BITS (2) + +#define RX_STATE *((volatile int32u *)0x400020ACu) +#define RX_STATE_REG *((volatile int32u *)0x400020ACu) +#define RX_STATE_ADDR (0x400020ACu) +#define RX_STATE_RESET (0x00000000u) + /* RX_BUFFER_STATE field */ + #define RX_STATE_RX_BUFFER_STATE (0x000001E0u) + #define RX_STATE_RX_BUFFER_STATE_MASK (0x000001E0u) + #define RX_STATE_RX_BUFFER_STATE_BIT (5) + #define RX_STATE_RX_BUFFER_STATE_BITS (4) + /* RX_TOP_STATE field */ + #define RX_STATE_RX_TOP_STATE (0x0000001Fu) + #define RX_STATE_RX_TOP_STATE_MASK (0x0000001Fu) + #define RX_STATE_RX_TOP_STATE_BIT (0) + #define RX_STATE_RX_TOP_STATE_BITS (5) + +#define TX_STATE *((volatile int32u *)0x400020B0u) +#define TX_STATE_REG *((volatile int32u *)0x400020B0u) +#define TX_STATE_ADDR (0x400020B0u) +#define TX_STATE_RESET (0x00000000u) + /* TX_BUFFER_STATE field */ + #define TX_STATE_TX_BUFFER_STATE (0x000000F0u) + #define TX_STATE_TX_BUFFER_STATE_MASK (0x000000F0u) + #define TX_STATE_TX_BUFFER_STATE_BIT (4) + #define TX_STATE_TX_BUFFER_STATE_BITS (4) + /* TX_TOP_STATE field */ + #define TX_STATE_TX_TOP_STATE (0x0000000Fu) + #define TX_STATE_TX_TOP_STATE_MASK (0x0000000Fu) + #define TX_STATE_TX_TOP_STATE_BIT (0) + #define TX_STATE_TX_TOP_STATE_BITS (4) + +#define DMA_STATE *((volatile int32u *)0x400020B4u) +#define DMA_STATE_REG *((volatile int32u *)0x400020B4u) +#define DMA_STATE_ADDR (0x400020B4u) +#define DMA_STATE_RESET (0x00000000u) + /* DMA_RX_STATE field */ + #define DMA_STATE_DMA_RX_STATE (0x00000038u) + #define DMA_STATE_DMA_RX_STATE_MASK (0x00000038u) + #define DMA_STATE_DMA_RX_STATE_BIT (3) + #define DMA_STATE_DMA_RX_STATE_BITS (3) + /* DMA_TX_STATE field */ + #define DMA_STATE_DMA_TX_STATE (0x00000007u) + #define DMA_STATE_DMA_TX_STATE_MASK (0x00000007u) + #define DMA_STATE_DMA_TX_STATE_BIT (0) + #define DMA_STATE_DMA_TX_STATE_BITS (3) + +#define MAC_DEBUG *((volatile int32u *)0x400020B8u) +#define MAC_DEBUG_REG *((volatile int32u *)0x400020B8u) +#define MAC_DEBUG_ADDR (0x400020B8u) +#define MAC_DEBUG_RESET (0x00000000u) + /* SW_DEBUG_OUT field */ + #define MAC_DEBUG_SW_DEBUG_OUT (0x00000060u) + #define MAC_DEBUG_SW_DEBUG_OUT_MASK (0x00000060u) + #define MAC_DEBUG_SW_DEBUG_OUT_BIT (5) + #define MAC_DEBUG_SW_DEBUG_OUT_BITS (2) + /* MAC_DEBUG_MUX field */ + #define MAC_DEBUG_MAC_DEBUG_MUX (0x0000001Fu) + #define MAC_DEBUG_MAC_DEBUG_MUX_MASK (0x0000001Fu) + #define MAC_DEBUG_MAC_DEBUG_MUX_BIT (0) + #define MAC_DEBUG_MAC_DEBUG_MUX_BITS (5) + +#define MAC_DEBUG_VIEW *((volatile int32u *)0x400020BCu) +#define MAC_DEBUG_VIEW_REG *((volatile int32u *)0x400020BCu) +#define MAC_DEBUG_VIEW_ADDR (0x400020BCu) +#define MAC_DEBUG_VIEW_RESET (0x00000010u) + /* MAC_DEBUG_VIEW field */ + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW (0x0000FFFFu) + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK (0x0000FFFFu) + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT (0) + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS (16) + +#define MAC_RSSI_DELAY *((volatile int32u *)0x400020C0u) +#define MAC_RSSI_DELAY_REG *((volatile int32u *)0x400020C0u) +#define MAC_RSSI_DELAY_ADDR (0x400020C0u) +#define MAC_RSSI_DELAY_RESET (0x00000000u) + /* RSSI_INST_DELAY_OK field */ + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK (0x00000FC0u) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK (0x00000FC0u) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT (6) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS (6) + /* RSSI_INST_DELAY field */ + #define MAC_RSSI_DELAY_RSSI_INST_DELAY (0x0000003Fu) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK (0x0000003Fu) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT (0) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS (6) + +#define PANID_COUNT *((volatile int32u *)0x400020C4u) +#define PANID_COUNT_REG *((volatile int32u *)0x400020C4u) +#define PANID_COUNT_ADDR (0x400020C4u) +#define PANID_COUNT_RESET (0x00000000u) + /* PANID_COUNT field */ + #define PANID_COUNT_PANID_COUNT (0x0000FFFFu) + #define PANID_COUNT_PANID_COUNT_MASK (0x0000FFFFu) + #define PANID_COUNT_PANID_COUNT_BIT (0) + #define PANID_COUNT_PANID_COUNT_BITS (16) + +#define NONPAN_COUNT *((volatile int32u *)0x400020C8u) +#define NONPAN_COUNT_REG *((volatile int32u *)0x400020C8u) +#define NONPAN_COUNT_ADDR (0x400020C8u) +#define NONPAN_COUNT_RESET (0x00000000u) + /* NONPAN_COUNT field */ + #define NONPAN_COUNT_NONPAN_COUNT (0x0000FFFFu) + #define NONPAN_COUNT_NONPAN_COUNT_MASK (0x0000FFFFu) + #define NONPAN_COUNT_NONPAN_COUNT_BIT (0) + #define NONPAN_COUNT_NONPAN_COUNT_BITS (16) + +/* SECURITY block */ +#define DATA_SECURITY_BASE (0x40003000u) +#define DATA_SECURITY_END (0x40003044u) +#define DATA_SECURITY_SIZE (DATA_SECURITY_END - DATA_SECURITY_BASE + 1) + +#define SECURITY_CONFIG *((volatile int32u *)0x40003000u) +#define SECURITY_CONFIG_REG *((volatile int32u *)0x40003000u) +#define SECURITY_CONFIG_ADDR (0x40003000u) +#define SECURITY_CONFIG_RESET (0x00000000u) + /* SEC_RST field */ + #define SECURITY_CONFIG_SEC_RST (0x00000080u) + #define SECURITY_CONFIG_SEC_RST_MASK (0x00000080u) + #define SECURITY_CONFIG_SEC_RST_BIT (7) + #define SECURITY_CONFIG_SEC_RST_BITS (1) + /* CTR_IN field */ + #define SECURITY_CONFIG_CTR_IN (0x00000040u) + #define SECURITY_CONFIG_CTR_IN_MASK (0x00000040u) + #define SECURITY_CONFIG_CTR_IN_BIT (6) + #define SECURITY_CONFIG_CTR_IN_BITS (1) + /* MIC_XOR_CT field */ + #define SECURITY_CONFIG_MIC_XOR_CT (0x00000020u) + #define SECURITY_CONFIG_MIC_XOR_CT_MASK (0x00000020u) + #define SECURITY_CONFIG_MIC_XOR_CT_BIT (5) + #define SECURITY_CONFIG_MIC_XOR_CT_BITS (1) + /* CBC_XOR_PT field */ + #define SECURITY_CONFIG_CBC_XOR_PT (0x00000010u) + #define SECURITY_CONFIG_CBC_XOR_PT_MASK (0x00000010u) + #define SECURITY_CONFIG_CBC_XOR_PT_BIT (4) + #define SECURITY_CONFIG_CBC_XOR_PT_BITS (1) + /* CT_TO_CBC_ST field */ + #define SECURITY_CONFIG_CT_TO_CBC_ST (0x00000008u) + #define SECURITY_CONFIG_CT_TO_CBC_ST_MASK (0x00000008u) + #define SECURITY_CONFIG_CT_TO_CBC_ST_BIT (3) + #define SECURITY_CONFIG_CT_TO_CBC_ST_BITS (1) + /* WAIT_CT_READ field */ + #define SECURITY_CONFIG_WAIT_CT_READ (0x00000004u) + #define SECURITY_CONFIG_WAIT_CT_READ_MASK (0x00000004u) + #define SECURITY_CONFIG_WAIT_CT_READ_BIT (2) + #define SECURITY_CONFIG_WAIT_CT_READ_BITS (1) + /* WAIT_PT_WRITE field */ + #define SECURITY_CONFIG_WAIT_PT_WRITE (0x00000002u) + #define SECURITY_CONFIG_WAIT_PT_WRITE_MASK (0x00000002u) + #define SECURITY_CONFIG_WAIT_PT_WRITE_BIT (1) + #define SECURITY_CONFIG_WAIT_PT_WRITE_BITS (1) + /* START_AES field */ + #define SECURITY_CONFIG_START_AES (0x00000001u) + #define SECURITY_CONFIG_START_AES_MASK (0x00000001u) + #define SECURITY_CONFIG_START_AES_BIT (0) + #define SECURITY_CONFIG_START_AES_BITS (1) + +#define SECURITY_STATUS *((volatile int32u *)0x40003004u) +#define SECURITY_STATUS_REG *((volatile int32u *)0x40003004u) +#define SECURITY_STATUS_ADDR (0x40003004u) +#define SECURITY_STATUS_RESET (0x00000000u) + /* SEC_BUSY field */ + #define SECURITY_STATUS_SEC_BUSY (0x00000001u) + #define SECURITY_STATUS_SEC_BUSY_MASK (0x00000001u) + #define SECURITY_STATUS_SEC_BUSY_BIT (0) + #define SECURITY_STATUS_SEC_BUSY_BITS (1) + +#define CBC_STATE_0 *((volatile int32u *)0x40003008u) +#define CBC_STATE_0_REG *((volatile int32u *)0x40003008u) +#define CBC_STATE_0_ADDR (0x40003008u) +#define CBC_STATE_0_RESET (0x00000000u) + /* CBC_STATE field */ + #define CBC_STATE_0_CBC_STATE (0xFFFFFFFFu) + #define CBC_STATE_0_CBC_STATE_MASK (0xFFFFFFFFu) + #define CBC_STATE_0_CBC_STATE_BIT (0) + #define CBC_STATE_0_CBC_STATE_BITS (32) + +#define CBC_STATE_1 *((volatile int32u *)0x4000300Cu) +#define CBC_STATE_1_REG *((volatile int32u *)0x4000300Cu) +#define CBC_STATE_1_ADDR (0x4000300Cu) +#define CBC_STATE_1_RESET (0x00000000u) + /* CBC_STATE_1 field */ + #define CBC_STATE_1_CBC_STATE_1 (0xFFFFFFFFu) + #define CBC_STATE_1_CBC_STATE_1_MASK (0xFFFFFFFFu) + #define CBC_STATE_1_CBC_STATE_1_BIT (0) + #define CBC_STATE_1_CBC_STATE_1_BITS (32) + +#define CBC_STATE_2 *((volatile int32u *)0x40003010u) +#define CBC_STATE_2_REG *((volatile int32u *)0x40003010u) +#define CBC_STATE_2_ADDR (0x40003010u) +#define CBC_STATE_2_RESET (0x00000000u) + /* CBC_STATE_2 field */ + #define CBC_STATE_2_CBC_STATE_2 (0xFFFFFFFFu) + #define CBC_STATE_2_CBC_STATE_2_MASK (0xFFFFFFFFu) + #define CBC_STATE_2_CBC_STATE_2_BIT (0) + #define CBC_STATE_2_CBC_STATE_2_BITS (32) + +#define CBC_STATE_3 *((volatile int32u *)0x40003014u) +#define CBC_STATE_3_REG *((volatile int32u *)0x40003014u) +#define CBC_STATE_3_ADDR (0x40003014u) +#define CBC_STATE_3_RESET (0x00000000u) + /* CBC_STATE_3 field */ + #define CBC_STATE_3_CBC_STATE_3 (0xFFFFFFFFu) + #define CBC_STATE_3_CBC_STATE_3_MASK (0xFFFFFFFFu) + #define CBC_STATE_3_CBC_STATE_3_BIT (0) + #define CBC_STATE_3_CBC_STATE_3_BITS (32) + +#define PT *((volatile int32u *)0x40003028u) +#define PT_REG *((volatile int32u *)0x40003028u) +#define PT_ADDR (0x40003028u) +#define PT_RESET (0x00000000u) + /* PT field */ + #define PT_PT (0xFFFFFFFFu) + #define PT_PT_MASK (0xFFFFFFFFu) + #define PT_PT_BIT (0) + #define PT_PT_BITS (32) + +#define CT *((volatile int32u *)0x40003030u) +#define CT_REG *((volatile int32u *)0x40003030u) +#define CT_ADDR (0x40003030u) +#define CT_RESET (0x00000000u) + /* CT field */ + #define CT_CT (0xFFFFFFFFu) + #define CT_CT_MASK (0xFFFFFFFFu) + #define CT_CT_BIT (0) + #define CT_CT_BITS (32) + +#define KEY_0 *((volatile int32u *)0x40003038u) +#define KEY_0_REG *((volatile int32u *)0x40003038u) +#define KEY_0_ADDR (0x40003038u) +#define KEY_0_RESET (0x00000000u) + /* KEY_O field */ + #define KEY_0_KEY_O (0xFFFFFFFFu) + #define KEY_0_KEY_O_MASK (0xFFFFFFFFu) + #define KEY_0_KEY_O_BIT (0) + #define KEY_0_KEY_O_BITS (32) + +#define KEY_1 *((volatile int32u *)0x4000303Cu) +#define KEY_1_REG *((volatile int32u *)0x4000303Cu) +#define KEY_1_ADDR (0x4000303Cu) +#define KEY_1_RESET (0x00000000u) + /* KEY_1 field */ + #define KEY_1_KEY_1 (0xFFFFFFFFu) + #define KEY_1_KEY_1_MASK (0xFFFFFFFFu) + #define KEY_1_KEY_1_BIT (0) + #define KEY_1_KEY_1_BITS (32) + +#define KEY_2 *((volatile int32u *)0x40003040u) +#define KEY_2_REG *((volatile int32u *)0x40003040u) +#define KEY_2_ADDR (0x40003040u) +#define KEY_2_RESET (0x00000000u) + /* KEY_2 field */ + #define KEY_2_KEY_2 (0xFFFFFFFFu) + #define KEY_2_KEY_2_MASK (0xFFFFFFFFu) + #define KEY_2_KEY_2_BIT (0) + #define KEY_2_KEY_2_BITS (32) + +#define KEY_3 *((volatile int32u *)0x40003044u) +#define KEY_3_REG *((volatile int32u *)0x40003044u) +#define KEY_3_ADDR (0x40003044u) +#define KEY_3_RESET (0x00000000u) + /* KEY_3 field */ + #define KEY_3_KEY_3 (0xFFFFFFFFu) + #define KEY_3_KEY_3_MASK (0xFFFFFFFFu) + #define KEY_3_KEY_3_BIT (0) + #define KEY_3_KEY_3_BITS (32) + +/* CM_LV block */ +#define BLOCK_CM_LV_BASE (0x40004000u) +#define BLOCK_CM_LV_END (0x40004034u) +#define BLOCK_CM_LV_SIZE (BLOCK_CM_LV_END - BLOCK_CM_LV_BASE + 1) + +#define SILICON_ID *((volatile int32u *)0x40004000u) +#define SILICON_ID_REG *((volatile int32u *)0x40004000u) +#define SILICON_ID_ADDR (0x40004000u) +#define SILICON_ID_RESET (0x069A862Bu) + /* HW_VERSION field */ + #define SILICON_ID_HW_VERSION (0xF0000000u) + #define SILICON_ID_HW_VERSION_MASK (0xF0000000u) + #define SILICON_ID_HW_VERSION_BIT (28) + #define SILICON_ID_HW_VERSION_BITS (4) + /* ST_DIVISION field */ + #define SILICON_ID_ST_DIVISION (0x0F000000u) + #define SILICON_ID_ST_DIVISION_MASK (0x0F000000u) + #define SILICON_ID_ST_DIVISION_BIT (24) + #define SILICON_ID_ST_DIVISION_BITS (4) + /* CHIP_TYPE field */ + #define SILICON_ID_CHIP_TYPE (0x00FF8000u) + #define SILICON_ID_CHIP_TYPE_MASK (0x00FF8000u) + #define SILICON_ID_CHIP_TYPE_BIT (15) + #define SILICON_ID_CHIP_TYPE_BITS (9) + /* SUB_TYPE field */ + #define SILICON_ID_SUB_TYPE (0x00007000u) + #define SILICON_ID_SUB_TYPE_MASK (0x00007000u) + #define SILICON_ID_SUB_TYPE_BIT (12) + #define SILICON_ID_SUB_TYPE_BITS (3) + /* JEDEC_MAN_ID field */ + #define SILICON_ID_JEDEC_MAN_ID (0x00000FFEu) + #define SILICON_ID_JEDEC_MAN_ID_MASK (0x00000FFEu) + #define SILICON_ID_JEDEC_MAN_ID_BIT (1) + #define SILICON_ID_JEDEC_MAN_ID_BITS (11) + /* ONE field */ + #define SILICON_ID_ONE (0x00000001u) + #define SILICON_ID_ONE_MASK (0x00000001u) + #define SILICON_ID_ONE_BIT (0) + #define SILICON_ID_ONE_BITS (1) + +#define OSC24M_BIASTRIM *((volatile int32u *)0x40004004u) +#define OSC24M_BIASTRIM_REG *((volatile int32u *)0x40004004u) +#define OSC24M_BIASTRIM_ADDR (0x40004004u) +#define OSC24M_BIASTRIM_RESET (0x0000000Fu) + /* OSC24M_BIAS_TRIM field */ + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM (0x0000000Fu) + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK (0x0000000Fu) + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT (0) + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS (4) + +#define OSCHF_TUNE *((volatile int32u *)0x40004008u) +#define OSCHF_TUNE_REG *((volatile int32u *)0x40004008u) +#define OSCHF_TUNE_ADDR (0x40004008u) +#define OSCHF_TUNE_RESET (0x00000017u) + /* OSCHF_TUNE_FIELD field */ + #define OSCHF_TUNE_FIELD (0x0000001Fu) + #define OSCHF_TUNE_FIELD_MASK (0x0000001Fu) + #define OSCHF_TUNE_FIELD_BIT (0) + #define OSCHF_TUNE_FIELD_BITS (5) + +#define OSC24M_COMP *((volatile int32u *)0x4000400Cu) +#define OSC24M_COMP_REG *((volatile int32u *)0x4000400Cu) +#define OSC24M_COMP_ADDR (0x4000400Cu) +#define OSC24M_COMP_RESET (0x00000000u) + /* OSC24M_HI field */ + #define OSC24M_HI (0x00000002u) + #define OSC24M_HI_MASK (0x00000002u) + #define OSC24M_HI_BIT (1) + #define OSC24M_HI_BITS (1) + /* OSC24M_LO field */ + #define OSC24M_LO (0x00000001u) + #define OSC24M_LO_MASK (0x00000001u) + #define OSC24M_LO_BIT (0) + #define OSC24M_LO_BITS (1) + +#define CLK_PERIODMODE *((volatile int32u *)0x40004010u) +#define CLK_PERIODMODE_REG *((volatile int32u *)0x40004010u) +#define CLK_PERIODMODE_ADDR (0x40004010u) +#define CLK_PERIODMODE_RESET (0x00000000u) + /* CLK_PERIODMODE_FIELD field */ + #define CLK_PERIODMODE_FIELD (0x00000003u) + #define CLK_PERIODMODE_FIELD_MASK (0x00000003u) + #define CLK_PERIODMODE_FIELD_BIT (0) + #define CLK_PERIODMODE_FIELD_BITS (2) + +#define CLK_PERIOD *((volatile int32u *)0x40004014u) +#define CLK_PERIOD_REG *((volatile int32u *)0x40004014u) +#define CLK_PERIOD_ADDR (0x40004014u) +#define CLK_PERIOD_RESET (0x00000000u) + /* CLK_PERIOD_FIELD field */ + #define CLK_PERIOD_FIELD (0x0000FFFFu) + #define CLK_PERIOD_FIELD_MASK (0x0000FFFFu) + #define CLK_PERIOD_FIELD_BIT (0) + #define CLK_PERIOD_FIELD_BITS (16) + +#define DITHER_DIS *((volatile int32u *)0x40004018u) +#define DITHER_DIS_REG *((volatile int32u *)0x40004018u) +#define DITHER_DIS_ADDR (0x40004018u) +#define DITHER_DIS_RESET (0x00000000u) + /* DITHER_DIS field */ + #define DITHER_DIS_DITHER_DIS (0x00000001u) + #define DITHER_DIS_DITHER_DIS_MASK (0x00000001u) + #define DITHER_DIS_DITHER_DIS_BIT (0) + #define DITHER_DIS_DITHER_DIS_BITS (1) + +#define OSC24M_CTRL *((volatile int32u *)0x4000401Cu) +#define OSC24M_CTRL_REG *((volatile int32u *)0x4000401Cu) +#define OSC24M_CTRL_ADDR (0x4000401Cu) +#define OSC24M_CTRL_RESET (0x00000000u) + /* OSC24M_EN field */ + #define OSC24M_CTRL_OSC24M_EN (0x00000002u) + #define OSC24M_CTRL_OSC24M_EN_MASK (0x00000002u) + #define OSC24M_CTRL_OSC24M_EN_BIT (1) + #define OSC24M_CTRL_OSC24M_EN_BITS (1) + /* OSC24M_SEL field */ + #define OSC24M_CTRL_OSC24M_SEL (0x00000001u) + #define OSC24M_CTRL_OSC24M_SEL_MASK (0x00000001u) + #define OSC24M_CTRL_OSC24M_SEL_BIT (0) + #define OSC24M_CTRL_OSC24M_SEL_BITS (1) + +#define CPU_CLKSEL *((volatile int32u *)0x40004020u) +#define CPU_CLKSEL_REG *((volatile int32u *)0x40004020u) +#define CPU_CLKSEL_ADDR (0x40004020u) +#define CPU_CLKSEL_RESET (0x00000000u) + /* CPU_CLKSEL_FIELD field */ + #define CPU_CLKSEL_FIELD (0x00000001u) + #define CPU_CLKSEL_FIELD_MASK (0x00000001u) + #define CPU_CLKSEL_FIELD_BIT (0) + #define CPU_CLKSEL_FIELD_BITS (1) + +#define BUS_FAULT *((volatile int32u *)0x40004024u) +#define BUS_FAULT_REG *((volatile int32u *)0x40004024u) +#define BUS_FAULT_ADDR (0x40004024u) +#define BUS_FAULT_RESET (0x00000000u) + /* WRONGSIZE field */ + #define BUS_FAULT_WRONGSIZE (0x00000008u) + #define BUS_FAULT_WRONGSIZE_MASK (0x00000008u) + #define BUS_FAULT_WRONGSIZE_BIT (3) + #define BUS_FAULT_WRONGSIZE_BITS (1) + /* PROTECTED field */ + #define BUS_FAULT_PROTECTED (0x00000004u) + #define BUS_FAULT_PROTECTED_MASK (0x00000004u) + #define BUS_FAULT_PROTECTED_BIT (2) + #define BUS_FAULT_PROTECTED_BITS (1) + /* RESERVED field */ + #define BUS_FAULT_RESERVED (0x00000002u) + #define BUS_FAULT_RESERVED_MASK (0x00000002u) + #define BUS_FAULT_RESERVED_BIT (1) + #define BUS_FAULT_RESERVED_BITS (1) + /* MISSED field */ + #define BUS_FAULT_MISSED (0x00000001u) + #define BUS_FAULT_MISSED_MASK (0x00000001u) + #define BUS_FAULT_MISSED_BIT (0) + #define BUS_FAULT_MISSED_BITS (1) + +#define PCTRACE_SEL *((volatile int32u *)0x40004028u) +#define PCTRACE_SEL_REG *((volatile int32u *)0x40004028u) +#define PCTRACE_SEL_ADDR (0x40004028u) +#define PCTRACE_SEL_RESET (0x00000000u) + /* PCTRACE_SEL_FIELD field */ + #define PCTRACE_SEL_FIELD (0x00000001u) + #define PCTRACE_SEL_FIELD_MASK (0x00000001u) + #define PCTRACE_SEL_FIELD_BIT (0) + #define PCTRACE_SEL_FIELD_BITS (1) + +#define FPEC_CLKREQ *((volatile int32u *)0x4000402Cu) +#define FPEC_CLKREQ_REG *((volatile int32u *)0x4000402Cu) +#define FPEC_CLKREQ_ADDR (0x4000402Cu) +#define FPEC_CLKREQ_RESET (0x00000000u) + /* FPEC_CLKREQ_FIELD field */ + #define FPEC_CLKREQ_FIELD (0x00000001u) + #define FPEC_CLKREQ_FIELD_MASK (0x00000001u) + #define FPEC_CLKREQ_FIELD_BIT (0) + #define FPEC_CLKREQ_FIELD_BITS (1) + +#define FPEC_CLKSTAT *((volatile int32u *)0x40004030u) +#define FPEC_CLKSTAT_REG *((volatile int32u *)0x40004030u) +#define FPEC_CLKSTAT_ADDR (0x40004030u) +#define FPEC_CLKSTAT_RESET (0x00000000u) + /* FPEC_CLKBSY field */ + #define FPEC_CLKBSY (0x00000002u) + #define FPEC_CLKBSY_MASK (0x00000002u) + #define FPEC_CLKBSY_BIT (1) + #define FPEC_CLKBSY_BITS (1) + /* FPEC_CLKACK field */ + #define FPEC_CLKACK (0x00000001u) + #define FPEC_CLKACK_MASK (0x00000001u) + #define FPEC_CLKACK_BIT (0) + #define FPEC_CLKACK_BITS (1) + +#define LV_SPARE *((volatile int32u *)0x40004034u) +#define LV_SPARE_REG *((volatile int32u *)0x40004034u) +#define LV_SPARE_ADDR (0x40004034u) +#define LV_SPARE_RESET (0x00000000u) + /* LV_SPARE field */ + #define LV_SPARE_LV_SPARE (0x000000FFu) + #define LV_SPARE_LV_SPARE_MASK (0x000000FFu) + #define LV_SPARE_LV_SPARE_BIT (0) + #define LV_SPARE_LV_SPARE_BITS (8) + +/* RAM_CTRL block */ +#define DATA_RAM_CTRL_BASE (0x40005000u) +#define DATA_RAM_CTRL_END (0x40005028u) +#define DATA_RAM_CTRL_SIZE (DATA_RAM_CTRL_END - DATA_RAM_CTRL_BASE + 1) + +#define MEM_PROT_0 *((volatile int32u *)0x40005000u) +#define MEM_PROT_0_REG *((volatile int32u *)0x40005000u) +#define MEM_PROT_0_ADDR (0x40005000u) +#define MEM_PROT_0_RESET (0x00000000u) + /* MEM_PROT_0 field */ + #define MEM_PROT_0_MEM_PROT_0 (0xFFFFFFFFu) + #define MEM_PROT_0_MEM_PROT_0_MASK (0xFFFFFFFFu) + #define MEM_PROT_0_MEM_PROT_0_BIT (0) + #define MEM_PROT_0_MEM_PROT_0_BITS (32) + +#define MEM_PROT_1 *((volatile int32u *)0x40005004u) +#define MEM_PROT_1_REG *((volatile int32u *)0x40005004u) +#define MEM_PROT_1_ADDR (0x40005004u) +#define MEM_PROT_1_RESET (0x00000000u) + /* MEM_PROT_1 field */ + #define MEM_PROT_1_MEM_PROT_1 (0xFFFFFFFFu) + #define MEM_PROT_1_MEM_PROT_1_MASK (0xFFFFFFFFu) + #define MEM_PROT_1_MEM_PROT_1_BIT (0) + #define MEM_PROT_1_MEM_PROT_1_BITS (32) + +#define MEM_PROT_2 *((volatile int32u *)0x40005008u) +#define MEM_PROT_2_REG *((volatile int32u *)0x40005008u) +#define MEM_PROT_2_ADDR (0x40005008u) +#define MEM_PROT_2_RESET (0x00000000u) + /* MEM_PROT_2 field */ + #define MEM_PROT_2_MEM_PROT_2 (0xFFFFFFFFu) + #define MEM_PROT_2_MEM_PROT_2_MASK (0xFFFFFFFFu) + #define MEM_PROT_2_MEM_PROT_2_BIT (0) + #define MEM_PROT_2_MEM_PROT_2_BITS (32) + +#define MEM_PROT_3 *((volatile int32u *)0x4000500Cu) +#define MEM_PROT_3_REG *((volatile int32u *)0x4000500Cu) +#define MEM_PROT_3_ADDR (0x4000500Cu) +#define MEM_PROT_3_RESET (0x00000000u) + /* MEM_PROT_3 field */ + #define MEM_PROT_3_MEM_PROT_3 (0xFFFFFFFFu) + #define MEM_PROT_3_MEM_PROT_3_MASK (0xFFFFFFFFu) + #define MEM_PROT_3_MEM_PROT_3_BIT (0) + #define MEM_PROT_3_MEM_PROT_3_BITS (32) + +#define MEM_PROT_4 *((volatile int32u *)0x40005010u) +#define MEM_PROT_4_REG *((volatile int32u *)0x40005010u) +#define MEM_PROT_4_ADDR (0x40005010u) +#define MEM_PROT_4_RESET (0x00000000u) + /* MEM_PROT_4 field */ + #define MEM_PROT_4_MEM_PROT_4 (0xFFFFFFFFu) + #define MEM_PROT_4_MEM_PROT_4_MASK (0xFFFFFFFFu) + #define MEM_PROT_4_MEM_PROT_4_BIT (0) + #define MEM_PROT_4_MEM_PROT_4_BITS (32) + +#define MEM_PROT_5 *((volatile int32u *)0x40005014u) +#define MEM_PROT_5_REG *((volatile int32u *)0x40005014u) +#define MEM_PROT_5_ADDR (0x40005014u) +#define MEM_PROT_5_RESET (0x00000000u) + /* MEM_PROT_5 field */ + #define MEM_PROT_5_MEM_PROT_5 (0xFFFFFFFFu) + #define MEM_PROT_5_MEM_PROT_5_MASK (0xFFFFFFFFu) + #define MEM_PROT_5_MEM_PROT_5_BIT (0) + #define MEM_PROT_5_MEM_PROT_5_BITS (32) + +#define MEM_PROT_6 *((volatile int32u *)0x40005018u) +#define MEM_PROT_6_REG *((volatile int32u *)0x40005018u) +#define MEM_PROT_6_ADDR (0x40005018u) +#define MEM_PROT_6_RESET (0x00000000u) + /* MEM_PROT_6 field */ + #define MEM_PROT_6_MEM_PROT_6 (0xFFFFFFFFu) + #define MEM_PROT_6_MEM_PROT_6_MASK (0xFFFFFFFFu) + #define MEM_PROT_6_MEM_PROT_6_BIT (0) + #define MEM_PROT_6_MEM_PROT_6_BITS (32) + +#define MEM_PROT_7 *((volatile int32u *)0x4000501Cu) +#define MEM_PROT_7_REG *((volatile int32u *)0x4000501Cu) +#define MEM_PROT_7_ADDR (0x4000501Cu) +#define MEM_PROT_7_RESET (0x00000000u) + /* MEM_PROT_7 field */ + #define MEM_PROT_7_MEM_PROT_7 (0xFFFFFFFFu) + #define MEM_PROT_7_MEM_PROT_7_MASK (0xFFFFFFFFu) + #define MEM_PROT_7_MEM_PROT_7_BIT (0) + #define MEM_PROT_7_MEM_PROT_7_BITS (32) + +#define DMA_PROT_ADDR *((volatile int32u *)0x40005020u) +#define DMA_PROT_ADDR_REG *((volatile int32u *)0x40005020u) +#define DMA_PROT_ADDR_ADDR (0x40005020u) +#define DMA_PROT_ADDR_RESET (0x20000000u) + /* DMA_PROT_OFFS field */ + #define DMA_PROT_ADDR_DMA_PROT_OFFS (0xFFFFE000u) + #define DMA_PROT_ADDR_DMA_PROT_OFFS_MASK (0xFFFFE000u) + #define DMA_PROT_ADDR_DMA_PROT_OFFS_BIT (13) + #define DMA_PROT_ADDR_DMA_PROT_OFFS_BITS (19) + /* DMA_PROT_ADDR field */ + #define DMA_PROT_ADDR_DMA_PROT_ADDR (0x00001FFFu) + #define DMA_PROT_ADDR_DMA_PROT_ADDR_MASK (0x00001FFFu) + #define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT (0) + #define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS (13) + +#define DMA_PROT_CH *((volatile int32u *)0x40005024u) +#define DMA_PROT_CH_REG *((volatile int32u *)0x40005024u) +#define DMA_PROT_CH_ADDR (0x40005024u) +#define DMA_PROT_CH_RESET (0x00000000u) + /* DMA_PROT_CH field */ + #define DMA_PROT_CH_DMA_PROT_CH (0x00000007u) + #define DMA_PROT_CH_DMA_PROT_CH_MASK (0x00000007u) + #define DMA_PROT_CH_DMA_PROT_CH_BIT (0) + #define DMA_PROT_CH_DMA_PROT_CH_BITS (3) + +#define MEM_PROT_EN *((volatile int32u *)0x40005028u) +#define MEM_PROT_EN_REG *((volatile int32u *)0x40005028u) +#define MEM_PROT_EN_ADDR (0x40005028u) +#define MEM_PROT_EN_RESET (0x00000000u) + /* FORCE_PROT field */ + #define MEM_PROT_EN_FORCE_PROT (0x00000004u) + #define MEM_PROT_EN_FORCE_PROT_MASK (0x00000004u) + #define MEM_PROT_EN_FORCE_PROT_BIT (2) + #define MEM_PROT_EN_FORCE_PROT_BITS (1) + /* DMA_PROT_EN_MAC field */ + #define MEM_PROT_EN_DMA_PROT_EN_MAC (0x00000002u) + #define MEM_PROT_EN_DMA_PROT_EN_MAC_MASK (0x00000002u) + #define MEM_PROT_EN_DMA_PROT_EN_MAC_BIT (1) + #define MEM_PROT_EN_DMA_PROT_EN_MAC_BITS (1) + /* DMA_PROT_EN_OTHER field */ + #define MEM_PROT_EN_DMA_PROT_EN_OTHER (0x00000001u) + #define MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK (0x00000001u) + #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT (0) + #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS (1) + +/* SLOW_TIMERS block */ +#define DATA_SLOW_TIMERS_BASE (0x40006000u) +#define DATA_SLOW_TIMERS_END (0x40006024u) +#define DATA_SLOW_TIMERS_SIZE (DATA_SLOW_TIMERS_END - DATA_SLOW_TIMERS_BASE + 1) + +#define WDOG_CFG *((volatile int32u *)0x40006000u) +#define WDOG_CFG_REG *((volatile int32u *)0x40006000u) +#define WDOG_CFG_ADDR (0x40006000u) +#define WDOG_CFG_RESET (0x00000002u) + /* WDOG_DISABLE field */ + #define WDOG_DISABLE (0x00000002u) + #define WDOG_DISABLE_MASK (0x00000002u) + #define WDOG_DISABLE_BIT (1) + #define WDOG_DISABLE_BITS (1) + /* WDOG_ENABLE field */ + #define WDOG_ENABLE (0x00000001u) + #define WDOG_ENABLE_MASK (0x00000001u) + #define WDOG_ENABLE_BIT (0) + #define WDOG_ENABLE_BITS (1) + +#define WDOG_KEY *((volatile int32u *)0x40006004u) +#define WDOG_KEY_REG *((volatile int32u *)0x40006004u) +#define WDOG_KEY_ADDR (0x40006004u) +#define WDOG_KEY_RESET (0x00000000u) + /* WDOG_KEY_FIELD field */ + #define WDOG_KEY_FIELD (0x0000FFFFu) + #define WDOG_KEY_FIELD_MASK (0x0000FFFFu) + #define WDOG_KEY_FIELD_BIT (0) + #define WDOG_KEY_FIELD_BITS (16) + +#define WDOG_RESET *((volatile int32u *)0x40006008u) +#define WDOG_RESET_REG *((volatile int32u *)0x40006008u) +#define WDOG_RESET_ADDR (0x40006008u) +#define WDOG_RESET_RESET (0x00000000u) + +#define SLEEPTMR_CFG *((volatile int32u *)0x4000600Cu) +#define SLEEPTMR_CFG_REG *((volatile int32u *)0x4000600Cu) +#define SLEEPTMR_CFG_ADDR (0x4000600Cu) +#define SLEEPTMR_CFG_RESET (0x00000400u) + /* SLEEPTMR_REVERSE field */ + #define SLEEPTMR_REVERSE (0x00001000u) + #define SLEEPTMR_REVERSE_MASK (0x00001000u) + #define SLEEPTMR_REVERSE_BIT (12) + #define SLEEPTMR_REVERSE_BITS (1) + /* SLEEPTMR_ENABLE field */ + #define SLEEPTMR_ENABLE (0x00000800u) + #define SLEEPTMR_ENABLE_MASK (0x00000800u) + #define SLEEPTMR_ENABLE_BIT (11) + #define SLEEPTMR_ENABLE_BITS (1) + /* SLEEPTMR_DBGPAUSE field */ + #define SLEEPTMR_DBGPAUSE (0x00000400u) + #define SLEEPTMR_DBGPAUSE_MASK (0x00000400u) + #define SLEEPTMR_DBGPAUSE_BIT (10) + #define SLEEPTMR_DBGPAUSE_BITS (1) + /* SLEEPTMR_CLKDIV field */ + #define SLEEPTMR_CLKDIV (0x000000F0u) + #define SLEEPTMR_CLKDIV_MASK (0x000000F0u) + #define SLEEPTMR_CLKDIV_BIT (4) + #define SLEEPTMR_CLKDIV_BITS (4) + /* SLEEPTMR_CLKSEL field */ + #define SLEEPTMR_CLKSEL (0x00000001u) + #define SLEEPTMR_CLKSEL_MASK (0x00000001u) + #define SLEEPTMR_CLKSEL_BIT (0) + #define SLEEPTMR_CLKSEL_BITS (1) + +#define SLEEPTMR_CNTH *((volatile int32u *)0x40006010u) +#define SLEEPTMR_CNTH_REG *((volatile int32u *)0x40006010u) +#define SLEEPTMR_CNTH_ADDR (0x40006010u) +#define SLEEPTMR_CNTH_RESET (0x00000000u) + /* SLEEPTMR_CNTH_FIELD field */ + #define SLEEPTMR_CNTH_FIELD (0x0000FFFFu) + #define SLEEPTMR_CNTH_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CNTH_FIELD_BIT (0) + #define SLEEPTMR_CNTH_FIELD_BITS (16) + +#define SLEEPTMR_CNTL *((volatile int32u *)0x40006014u) +#define SLEEPTMR_CNTL_REG *((volatile int32u *)0x40006014u) +#define SLEEPTMR_CNTL_ADDR (0x40006014u) +#define SLEEPTMR_CNTL_RESET (0x00000000u) + /* SLEEPTMR_CNTL_FIELD field */ + #define SLEEPTMR_CNTL_FIELD (0x0000FFFFu) + #define SLEEPTMR_CNTL_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CNTL_FIELD_BIT (0) + #define SLEEPTMR_CNTL_FIELD_BITS (16) + +#define SLEEPTMR_CMPAH *((volatile int32u *)0x40006018u) +#define SLEEPTMR_CMPAH_REG *((volatile int32u *)0x40006018u) +#define SLEEPTMR_CMPAH_ADDR (0x40006018u) +#define SLEEPTMR_CMPAH_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPAH_FIELD field */ + #define SLEEPTMR_CMPAH_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPAH_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPAH_FIELD_BIT (0) + #define SLEEPTMR_CMPAH_FIELD_BITS (16) + +#define SLEEPTMR_CMPAL *((volatile int32u *)0x4000601Cu) +#define SLEEPTMR_CMPAL_REG *((volatile int32u *)0x4000601Cu) +#define SLEEPTMR_CMPAL_ADDR (0x4000601Cu) +#define SLEEPTMR_CMPAL_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPAL_FIELD field */ + #define SLEEPTMR_CMPAL_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPAL_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPAL_FIELD_BIT (0) + #define SLEEPTMR_CMPAL_FIELD_BITS (16) + +#define SLEEPTMR_CMPBH *((volatile int32u *)0x40006020u) +#define SLEEPTMR_CMPBH_REG *((volatile int32u *)0x40006020u) +#define SLEEPTMR_CMPBH_ADDR (0x40006020u) +#define SLEEPTMR_CMPBH_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPBH_FIELD field */ + #define SLEEPTMR_CMPBH_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPBH_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPBH_FIELD_BIT (0) + #define SLEEPTMR_CMPBH_FIELD_BITS (16) + +#define SLEEPTMR_CMPBL *((volatile int32u *)0x40006024u) +#define SLEEPTMR_CMPBL_REG *((volatile int32u *)0x40006024u) +#define SLEEPTMR_CMPBL_ADDR (0x40006024u) +#define SLEEPTMR_CMPBL_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPBL_FIELD field */ + #define SLEEPTMR_CMPBL_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPBL_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPBL_FIELD_BIT (0) + #define SLEEPTMR_CMPBL_FIELD_BITS (16) + +/* CAL_ADC block */ +#define DATA_CAL_ADC_BASE (0x40007000u) +#define DATA_CAL_ADC_END (0x40007004u) +#define DATA_CAL_ADC_SIZE (DATA_CAL_ADC_END - DATA_CAL_ADC_BASE + 1) + +#define CAL_ADC_DATA *((volatile int32u *)0x40007000u) +#define CAL_ADC_DATA_REG *((volatile int32u *)0x40007000u) +#define CAL_ADC_DATA_ADDR (0x40007000u) +#define CAL_ADC_DATA_RESET (0x00000000u) + /* CAL_ADC_DATA field */ + #define CAL_ADC_DATA_CAL_ADC_DATA (0x0000FFFFu) + #define CAL_ADC_DATA_CAL_ADC_DATA_MASK (0x0000FFFFu) + #define CAL_ADC_DATA_CAL_ADC_DATA_BIT (0) + #define CAL_ADC_DATA_CAL_ADC_DATA_BITS (16) + +#define CAL_ADC_CONFIG *((volatile int32u *)0x40007004u) +#define CAL_ADC_CONFIG_REG *((volatile int32u *)0x40007004u) +#define CAL_ADC_CONFIG_ADDR (0x40007004u) +#define CAL_ADC_CONFIG_RESET (0x00000000u) + /* CAL_ADC_RATE field */ + #define CAL_ADC_CONFIG_CAL_ADC_RATE (0x00007000u) + #define CAL_ADC_CONFIG_CAL_ADC_RATE_MASK (0x00007000u) + #define CAL_ADC_CONFIG_CAL_ADC_RATE_BIT (12) + #define CAL_ADC_CONFIG_CAL_ADC_RATE_BITS (3) + /* CAL_ADC_MUX field */ + #define CAL_ADC_CONFIG_CAL_ADC_MUX (0x00000F80u) + #define CAL_ADC_CONFIG_CAL_ADC_MUX_MASK (0x00000F80u) + #define CAL_ADC_CONFIG_CAL_ADC_MUX_BIT (7) + #define CAL_ADC_CONFIG_CAL_ADC_MUX_BITS (5) + /* CAL_ADC_CLKSEL field */ + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL (0x00000004u) + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK (0x00000004u) + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT (2) + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS (1) + /* CAL_ADC_DITHER_DIS field */ + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS (0x00000002u) + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK (0x00000002u) + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT (1) + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS (1) + /* CAL_ADC_EN field */ + #define CAL_ADC_CONFIG_CAL_ADC_EN (0x00000001u) + #define CAL_ADC_CONFIG_CAL_ADC_EN_MASK (0x00000001u) + #define CAL_ADC_CONFIG_CAL_ADC_EN_BIT (0) + #define CAL_ADC_CONFIG_CAL_ADC_EN_BITS (1) + +/* FLASH_CONTROL block */ +#define DATA_FLASH_CONTROL_BASE (0x40008000u) +#define DATA_FLASH_CONTROL_END (0x40008084u) +#define DATA_FLASH_CONTROL_SIZE (DATA_FLASH_CONTROL_END - DATA_FLASH_CONTROL_BASE + 1) + +#define FLASH_ACCESS *((volatile int32u *)0x40008000u) +#define FLASH_ACCESS_REG *((volatile int32u *)0x40008000u) +#define FLASH_ACCESS_ADDR (0x40008000u) +#define FLASH_ACCESS_RESET (0x00000031u) + /* PREFETCH_STATUS field */ + #define FLASH_ACCESS_PREFETCH_STATUS (0x00000020u) + #define FLASH_ACCESS_PREFETCH_STATUS_MASK (0x00000020u) + #define FLASH_ACCESS_PREFETCH_STATUS_BIT (5) + #define FLASH_ACCESS_PREFETCH_STATUS_BITS (1) + /* PREFETCH_EN field */ + #define FLASH_ACCESS_PREFETCH_EN (0x00000010u) + #define FLASH_ACCESS_PREFETCH_EN_MASK (0x00000010u) + #define FLASH_ACCESS_PREFETCH_EN_BIT (4) + #define FLASH_ACCESS_PREFETCH_EN_BITS (1) + /* HALFCYCLE_ACCESS field */ + #define FLASH_ACCESS_HALFCYCLE_ACCESS (0x00000008u) + #define FLASH_ACCESS_HALFCYCLE_ACCESS_MASK (0x00000008u) + #define FLASH_ACCESS_HALFCYCLE_ACCESS_BIT (3) + #define FLASH_ACCESS_HALFCYCLE_ACCESS_BITS (1) + /* CODE_LATENCY field */ + #define FLASH_ACCESS_CODE_LATENCY (0x00000007u) + #define FLASH_ACCESS_CODE_LATENCY_MASK (0x00000007u) + #define FLASH_ACCESS_CODE_LATENCY_BIT (0) + #define FLASH_ACCESS_CODE_LATENCY_BITS (3) + +#define FPEC_KEY *((volatile int32u *)0x40008004u) +#define FPEC_KEY_REG *((volatile int32u *)0x40008004u) +#define FPEC_KEY_ADDR (0x40008004u) +#define FPEC_KEY_RESET (0x00000000u) + /* FKEYR field */ + #define FPEC_KEY_FKEYR (0xFFFFFFFFu) + #define FPEC_KEY_FKEYR_MASK (0xFFFFFFFFu) + #define FPEC_KEY_FKEYR_BIT (0) + #define FPEC_KEY_FKEYR_BITS (32) + +#define OPT_KEY *((volatile int32u *)0x40008008u) +#define OPT_KEY_REG *((volatile int32u *)0x40008008u) +#define OPT_KEY_ADDR (0x40008008u) +#define OPT_KEY_RESET (0x00000000u) + /* OPTKEYR field */ + #define OPT_KEY_OPTKEYR (0xFFFFFFFFu) + #define OPT_KEY_OPTKEYR_MASK (0xFFFFFFFFu) + #define OPT_KEY_OPTKEYR_BIT (0) + #define OPT_KEY_OPTKEYR_BITS (32) + +#define FLASH_STATUS *((volatile int32u *)0x4000800Cu) +#define FLASH_STATUS_REG *((volatile int32u *)0x4000800Cu) +#define FLASH_STATUS_ADDR (0x4000800Cu) +#define FLASH_STATUS_RESET (0x00000000u) + /* EOP field */ + #define FLASH_STATUS_EOP (0x00000020u) + #define FLASH_STATUS_EOP_MASK (0x00000020u) + #define FLASH_STATUS_EOP_BIT (5) + #define FLASH_STATUS_EOP_BITS (1) + /* WRP_ERR field */ + #define FLASH_STATUS_WRP_ERR (0x00000010u) + #define FLASH_STATUS_WRP_ERR_MASK (0x00000010u) + #define FLASH_STATUS_WRP_ERR_BIT (4) + #define FLASH_STATUS_WRP_ERR_BITS (1) + /* PAGE_PROG_ERR field */ + #define FLASH_STATUS_PAGE_PROG_ERR (0x00000008u) + #define FLASH_STATUS_PAGE_PROG_ERR_MASK (0x00000008u) + #define FLASH_STATUS_PAGE_PROG_ERR_BIT (3) + #define FLASH_STATUS_PAGE_PROG_ERR_BITS (1) + /* PROG_ERR field */ + #define FLASH_STATUS_PROG_ERR (0x00000004u) + #define FLASH_STATUS_PROG_ERR_MASK (0x00000004u) + #define FLASH_STATUS_PROG_ERR_BIT (2) + #define FLASH_STATUS_PROG_ERR_BITS (1) + /* EARLY_BSY field */ + #define FLASH_STATUS_EARLY_BSY (0x00000002u) + #define FLASH_STATUS_EARLY_BSY_MASK (0x00000002u) + #define FLASH_STATUS_EARLY_BSY_BIT (1) + #define FLASH_STATUS_EARLY_BSY_BITS (1) + /* FLA_BSY field */ + #define FLASH_STATUS_FLA_BSY (0x00000001u) + #define FLASH_STATUS_FLA_BSY_MASK (0x00000001u) + #define FLASH_STATUS_FLA_BSY_BIT (0) + #define FLASH_STATUS_FLA_BSY_BITS (1) + +#define FLASH_CTRL *((volatile int32u *)0x40008010u) +#define FLASH_CTRL_REG *((volatile int32u *)0x40008010u) +#define FLASH_CTRL_ADDR (0x40008010u) +#define FLASH_CTRL_RESET (0x00000080u) + /* EOPIE field */ + #define FLASH_CTRL_EOPIE (0x00001000u) + #define FLASH_CTRL_EOPIE_MASK (0x00001000u) + #define FLASH_CTRL_EOPIE_BIT (12) + #define FLASH_CTRL_EOPIE_BITS (1) + /* EARLYBSYIE field */ + #define FLASH_CTRL_EARLYBSYIE (0x00000800u) + #define FLASH_CTRL_EARLYBSYIE_MASK (0x00000800u) + #define FLASH_CTRL_EARLYBSYIE_BIT (11) + #define FLASH_CTRL_EARLYBSYIE_BITS (1) + /* ERRIE field */ + #define FLASH_CTRL_ERRIE (0x00000400u) + #define FLASH_CTRL_ERRIE_MASK (0x00000400u) + #define FLASH_CTRL_ERRIE_BIT (10) + #define FLASH_CTRL_ERRIE_BITS (1) + /* OPTWREN field */ + #define FLASH_CTRL_OPTWREN (0x00000200u) + #define FLASH_CTRL_OPTWREN_MASK (0x00000200u) + #define FLASH_CTRL_OPTWREN_BIT (9) + #define FLASH_CTRL_OPTWREN_BITS (1) + /* FSTPROG field */ + #define FLASH_CTRL_FSTPROG (0x00000100u) + #define FLASH_CTRL_FSTPROG_MASK (0x00000100u) + #define FLASH_CTRL_FSTPROG_BIT (8) + #define FLASH_CTRL_FSTPROG_BITS (1) + /* LOCK field */ + #define FLASH_CTRL_LOCK (0x00000080u) + #define FLASH_CTRL_LOCK_MASK (0x00000080u) + #define FLASH_CTRL_LOCK_BIT (7) + #define FLASH_CTRL_LOCK_BITS (1) + /* FLA_START field */ + #define FLASH_CTRL_FLA_START (0x00000040u) + #define FLASH_CTRL_FLA_START_MASK (0x00000040u) + #define FLASH_CTRL_FLA_START_BIT (6) + #define FLASH_CTRL_FLA_START_BITS (1) + /* OPTERASE field */ + #define FLASH_CTRL_OPTERASE (0x00000020u) + #define FLASH_CTRL_OPTERASE_MASK (0x00000020u) + #define FLASH_CTRL_OPTERASE_BIT (5) + #define FLASH_CTRL_OPTERASE_BITS (1) + /* OPTPROG field */ + #define FLASH_CTRL_OPTPROG (0x00000010u) + #define FLASH_CTRL_OPTPROG_MASK (0x00000010u) + #define FLASH_CTRL_OPTPROG_BIT (4) + #define FLASH_CTRL_OPTPROG_BITS (1) + /* GLOBALERASE field */ + #define FLASH_CTRL_GLOBALERASE (0x00000008u) + #define FLASH_CTRL_GLOBALERASE_MASK (0x00000008u) + #define FLASH_CTRL_GLOBALERASE_BIT (3) + #define FLASH_CTRL_GLOBALERASE_BITS (1) + /* MASSERASE field */ + #define FLASH_CTRL_MASSERASE (0x00000004u) + #define FLASH_CTRL_MASSERASE_MASK (0x00000004u) + #define FLASH_CTRL_MASSERASE_BIT (2) + #define FLASH_CTRL_MASSERASE_BITS (1) + /* PAGEERASE field */ + #define FLASH_CTRL_PAGEERASE (0x00000002u) + #define FLASH_CTRL_PAGEERASE_MASK (0x00000002u) + #define FLASH_CTRL_PAGEERASE_BIT (1) + #define FLASH_CTRL_PAGEERASE_BITS (1) + /* PROG field */ + #define FLASH_CTRL_PROG (0x00000001u) + #define FLASH_CTRL_PROG_MASK (0x00000001u) + #define FLASH_CTRL_PROG_BIT (0) + #define FLASH_CTRL_PROG_BITS (1) + +#define FLASH_ADDR *((volatile int32u *)0x40008014u) +#define FLASH_ADDR_REG *((volatile int32u *)0x40008014u) +#define FLASH_ADDR_ADDR (0x40008014u) +#define FLASH_ADDR_RESET (0x00000000u) + /* FAR field */ + #define FLASH_ADDR_FAR (0xFFFFFFFFu) + #define FLASH_ADDR_FAR_MASK (0xFFFFFFFFu) + #define FLASH_ADDR_FAR_BIT (0) + #define FLASH_ADDR_FAR_BITS (32) + +#define OPT_BYTE *((volatile int32u *)0x4000801Cu) +#define OPT_BYTE_REG *((volatile int32u *)0x4000801Cu) +#define OPT_BYTE_ADDR (0x4000801Cu) +#define OPT_BYTE_RESET (0xFBFFFFFEu) + /* RSVD field */ + #define OPT_BYTE_RSVD (0xF8000000u) + #define OPT_BYTE_RSVD_MASK (0xF8000000u) + #define OPT_BYTE_RSVD_BIT (27) + #define OPT_BYTE_RSVD_BITS (5) + /* OBR field */ + #define OPT_BYTE_OBR (0x07FFFFFCu) + #define OPT_BYTE_OBR_MASK (0x07FFFFFCu) + #define OPT_BYTE_OBR_BIT (2) + #define OPT_BYTE_OBR_BITS (25) + /* RDPROT field */ + #define OPT_BYTE_RDPROT (0x00000002u) + #define OPT_BYTE_RDPROT_MASK (0x00000002u) + #define OPT_BYTE_RDPROT_BIT (1) + #define OPT_BYTE_RDPROT_BITS (1) + /* OPT_ERR field */ + #define OPT_BYTE_OPT_ERR (0x00000001u) + #define OPT_BYTE_OPT_ERR_MASK (0x00000001u) + #define OPT_BYTE_OPT_ERR_BIT (0) + #define OPT_BYTE_OPT_ERR_BITS (1) + +#define WRPROT *((volatile int32u *)0x40008020u) +#define WRPROT_REG *((volatile int32u *)0x40008020u) +#define WRPROT_ADDR (0x40008020u) +#define WRPROT_RESET (0xFFFFFFFFu) + /* WRP field */ + #define WRPROT_WRP (0xFFFFFFFFu) + #define WRPROT_WRP_MASK (0xFFFFFFFFu) + #define WRPROT_WRP_BIT (0) + #define WRPROT_WRP_BITS (32) + +#define FLASH_TEST_CTRL *((volatile int32u *)0x40008080u) +#define FLASH_TEST_CTRL_REG *((volatile int32u *)0x40008080u) +#define FLASH_TEST_CTRL_ADDR (0x40008080u) +#define FLASH_TEST_CTRL_RESET (0x00000000u) + /* TMR field */ + #define FLASH_TEST_CTRL_TMR (0x00001000u) + #define FLASH_TEST_CTRL_TMR_MASK (0x00001000u) + #define FLASH_TEST_CTRL_TMR_BIT (12) + #define FLASH_TEST_CTRL_TMR_BITS (1) + /* ERASE field */ + #define FLASH_TEST_CTRL_ERASE (0x00000800u) + #define FLASH_TEST_CTRL_ERASE_MASK (0x00000800u) + #define FLASH_TEST_CTRL_ERASE_BIT (11) + #define FLASH_TEST_CTRL_ERASE_BITS (1) + /* MAS1 field */ + #define FLASH_TEST_CTRL_MAS1 (0x00000400u) + #define FLASH_TEST_CTRL_MAS1_MASK (0x00000400u) + #define FLASH_TEST_CTRL_MAS1_BIT (10) + #define FLASH_TEST_CTRL_MAS1_BITS (1) + /* TEST_PROG field */ + #define FLASH_TEST_CTRL_TEST_PROG (0x00000200u) + #define FLASH_TEST_CTRL_TEST_PROG_MASK (0x00000200u) + #define FLASH_TEST_CTRL_TEST_PROG_BIT (9) + #define FLASH_TEST_CTRL_TEST_PROG_BITS (1) + /* NVSTR field */ + #define FLASH_TEST_CTRL_NVSTR (0x00000100u) + #define FLASH_TEST_CTRL_NVSTR_MASK (0x00000100u) + #define FLASH_TEST_CTRL_NVSTR_BIT (8) + #define FLASH_TEST_CTRL_NVSTR_BITS (1) + /* SE field */ + #define FLASH_TEST_CTRL_SE (0x00000080u) + #define FLASH_TEST_CTRL_SE_MASK (0x00000080u) + #define FLASH_TEST_CTRL_SE_BIT (7) + #define FLASH_TEST_CTRL_SE_BITS (1) + /* IFREN field */ + #define FLASH_TEST_CTRL_IFREN (0x00000040u) + #define FLASH_TEST_CTRL_IFREN_MASK (0x00000040u) + #define FLASH_TEST_CTRL_IFREN_BIT (6) + #define FLASH_TEST_CTRL_IFREN_BITS (1) + /* YE field */ + #define FLASH_TEST_CTRL_YE (0x00000020u) + #define FLASH_TEST_CTRL_YE_MASK (0x00000020u) + #define FLASH_TEST_CTRL_YE_BIT (5) + #define FLASH_TEST_CTRL_YE_BITS (1) + /* XE field */ + #define FLASH_TEST_CTRL_XE (0x00000010u) + #define FLASH_TEST_CTRL_XE_MASK (0x00000010u) + #define FLASH_TEST_CTRL_XE_BIT (4) + #define FLASH_TEST_CTRL_XE_BITS (1) + /* SW_CTRL field */ + #define FLASH_TEST_CTRL_SW_CTRL (0x00000008u) + #define FLASH_TEST_CTRL_SW_CTRL_MASK (0x00000008u) + #define FLASH_TEST_CTRL_SW_CTRL_BIT (3) + #define FLASH_TEST_CTRL_SW_CTRL_BITS (1) + /* SW field */ + #define FLASH_TEST_CTRL_SW (0x00000006u) + #define FLASH_TEST_CTRL_SW_MASK (0x00000006u) + #define FLASH_TEST_CTRL_SW_BIT (1) + #define FLASH_TEST_CTRL_SW_BITS (2) + /* SW_EN field */ + #define FLASH_TEST_CTRL_SW_EN (0x00000001u) + #define FLASH_TEST_CTRL_SW_EN_MASK (0x00000001u) + #define FLASH_TEST_CTRL_SW_EN_BIT (0) + #define FLASH_TEST_CTRL_SW_EN_BITS (1) + +#define FLASH_DATA0 *((volatile int32u *)0x40008084u) +#define FLASH_DATA0_REG *((volatile int32u *)0x40008084u) +#define FLASH_DATA0_ADDR (0x40008084u) +#define FLASH_DATA0_RESET (0xFFFFFFFFu) + /* FDR0 field */ + #define FLASH_DATA0_FDR0 (0xFFFFFFFFu) + #define FLASH_DATA0_FDR0_MASK (0xFFFFFFFFu) + #define FLASH_DATA0_FDR0_BIT (0) + #define FLASH_DATA0_FDR0_BITS (32) + +/* EMU_REGS block */ +#define DATA_EMU_REGS_BASE (0x40009000u) +#define DATA_EMU_REGS_END (0x40009000u) +#define DATA_EMU_REGS_SIZE (DATA_EMU_REGS_END - DATA_EMU_REGS_BASE + 1) + +#define I_AM_AN_EMULATOR *((volatile int32u *)0x40009000u) +#define I_AM_AN_EMULATOR_REG *((volatile int32u *)0x40009000u) +#define I_AM_AN_EMULATOR_ADDR (0x40009000u) +#define I_AM_AN_EMULATOR_RESET (0x00000000u) + /* I_AM_AN_EMULATOR field */ + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR (0x00000001u) + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK (0x00000001u) + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT (0) + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS (1) + +/* INTERRUPTS block */ +#define BLOCK_INTERRUPTS_BASE (0x4000A000u) +#define BLOCK_INTERRUPTS_END (0x4000A86Cu) +#define BLOCK_INTERRUPTS_SIZE (BLOCK_INTERRUPTS_END - BLOCK_INTERRUPTS_BASE + 1) + +#define MAC_RX_INT_SRC *((volatile int32u *)0x4000A000u) +#define MAC_RX_INT_SRC_REG *((volatile int32u *)0x4000A000u) +#define MAC_RX_INT_SRC_ADDR (0x4000A000u) +#define MAC_RX_INT_SRC_RESET (0x00000000u) + /* TX_B_ACK_ERR_SRC field */ + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC (0x00008000u) + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK (0x00008000u) + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT (15) + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS (1) + /* TX_A_ACK_ERR_SRC field */ + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC (0x00004000u) + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK (0x00004000u) + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT (14) + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS (1) + /* RX_OVFLW_SRC field */ + #define MAC_RX_INT_SRC_RX_OVFLW_SRC (0x00002000u) + #define MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK (0x00002000u) + #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT (13) + #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS (1) + /* RX_ERROR_SRC field */ + #define MAC_RX_INT_SRC_RX_ERROR_SRC (0x00001000u) + #define MAC_RX_INT_SRC_RX_ERROR_SRC_MASK (0x00001000u) + #define MAC_RX_INT_SRC_RX_ERROR_SRC_BIT (12) + #define MAC_RX_INT_SRC_RX_ERROR_SRC_BITS (1) + /* BB_RX_LEN_ERR_SRC field */ + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC (0x00000800u) + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK (0x00000800u) + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT (11) + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS (1) + /* TX_COLL_RX_SRC field */ + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC (0x00000400u) + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK (0x00000400u) + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT (10) + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS (1) + /* RSSI_INST_MEAS_SRC field */ + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC (0x00000200u) + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK (0x00000200u) + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT (9) + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS (1) + /* TX_B_ACK_SRC field */ + #define MAC_RX_INT_SRC_TX_B_ACK_SRC (0x00000100u) + #define MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK (0x00000100u) + #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT (8) + #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS (1) + /* TX_A_ACK_SRC field */ + #define MAC_RX_INT_SRC_TX_A_ACK_SRC (0x00000080u) + #define MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK (0x00000080u) + #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT (7) + #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS (1) + /* RX_B_UNLOAD_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC (0x00000040u) + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK (0x00000040u) + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT (6) + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS (1) + /* RX_A_UNLOAD_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC (0x00000020u) + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK (0x00000020u) + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT (5) + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS (1) + /* RX_B_ADDR_REC_SRC field */ + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC (0x00000010u) + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK (0x00000010u) + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT (4) + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS (1) + /* RX_A_ADDR_REC_SRC field */ + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC (0x00000008u) + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK (0x00000008u) + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT (3) + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS (1) + /* RX_B_FILT_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC (0x00000004u) + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK (0x00000004u) + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT (2) + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS (1) + /* RX_A_FILT_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC (0x00000002u) + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK (0x00000002u) + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT (1) + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS (1) + /* RX_FRAME_SRC field */ + #define MAC_RX_INT_SRC_RX_FRAME_SRC (0x00000001u) + #define MAC_RX_INT_SRC_RX_FRAME_SRC_MASK (0x00000001u) + #define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT (0) + #define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS (1) + +#define MAC_TX_INT_SRC *((volatile int32u *)0x4000A004u) +#define MAC_TX_INT_SRC_REG *((volatile int32u *)0x4000A004u) +#define MAC_TX_INT_SRC_ADDR (0x4000A004u) +#define MAC_TX_INT_SRC_RESET (0x00000000u) + /* RX_B_ACK_SRC field */ + #define MAC_TX_INT_SRC_RX_B_ACK_SRC (0x00000800u) + #define MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK (0x00000800u) + #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT (11) + #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS (1) + /* RX_A_ACK_SRC field */ + #define MAC_TX_INT_SRC_RX_A_ACK_SRC (0x00000400u) + #define MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK (0x00000400u) + #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT (10) + #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS (1) + /* TX_B_UNLOAD_SRC field */ + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC (0x00000200u) + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK (0x00000200u) + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT (9) + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS (1) + /* TX_A_UNLOAD_SRC field */ + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC (0x00000100u) + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK (0x00000100u) + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT (8) + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS (1) + /* ACK_EXPIRED_SRC field */ + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC (0x00000080u) + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK (0x00000080u) + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT (7) + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS (1) + /* TX_LOCK_FAIL_SRC field */ + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC (0x00000040u) + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK (0x00000040u) + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT (6) + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS (1) + /* TX_UNDERFLOW_SRC field */ + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC (0x00000020u) + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK (0x00000020u) + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT (5) + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS (1) + /* CCA_FAIL_SRC field */ + #define MAC_TX_INT_SRC_CCA_FAIL_SRC (0x00000010u) + #define MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK (0x00000010u) + #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT (4) + #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS (1) + /* SFD_SENT_SRC field */ + #define MAC_TX_INT_SRC_SFD_SENT_SRC (0x00000008u) + #define MAC_TX_INT_SRC_SFD_SENT_SRC_MASK (0x00000008u) + #define MAC_TX_INT_SRC_SFD_SENT_SRC_BIT (3) + #define MAC_TX_INT_SRC_SFD_SENT_SRC_BITS (1) + /* BO_COMPLETE_SRC field */ + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC (0x00000004u) + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK (0x00000004u) + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT (2) + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS (1) + /* RX_ACK_SRC field */ + #define MAC_TX_INT_SRC_RX_ACK_SRC (0x00000002u) + #define MAC_TX_INT_SRC_RX_ACK_SRC_MASK (0x00000002u) + #define MAC_TX_INT_SRC_RX_ACK_SRC_BIT (1) + #define MAC_TX_INT_SRC_RX_ACK_SRC_BITS (1) + /* TX_COMPLETE_SRC field */ + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC (0x00000001u) + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK (0x00000001u) + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT (0) + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS (1) + +#define MAC_TIMER_INT_SRC *((volatile int32u *)0x4000A008u) +#define MAC_TIMER_INT_SRC_REG *((volatile int32u *)0x4000A008u) +#define MAC_TIMER_INT_SRC_ADDR (0x4000A008u) +#define MAC_TIMER_INT_SRC_RESET (0x00000000u) + /* TIMER_COMP_B_SRC field */ + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC (0x00000004u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK (0x00000004u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT (2) + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS (1) + /* TIMER_COMP_A_SRC field */ + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC (0x00000002u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK (0x00000002u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT (1) + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS (1) + /* TIMER_WRAP_SRC field */ + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC (0x00000001u) + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK (0x00000001u) + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT (0) + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS (1) + +#define BB_INT_SRC *((volatile int32u *)0x4000A00Cu) +#define BB_INT_SRC_REG *((volatile int32u *)0x4000A00Cu) +#define BB_INT_SRC_ADDR (0x4000A00Cu) +#define BB_INT_SRC_RESET (0x00000000u) + /* RSSI_INT_SRC field */ + #define BB_INT_SRC_RSSI_INT_SRC (0x00000002u) + #define BB_INT_SRC_RSSI_INT_SRC_MASK (0x00000002u) + #define BB_INT_SRC_RSSI_INT_SRC_BIT (1) + #define BB_INT_SRC_RSSI_INT_SRC_BITS (1) + /* BASEBAND_INT_SRC field */ + #define BB_INT_SRC_BASEBAND_INT_SRC (0x00000001u) + #define BB_INT_SRC_BASEBAND_INT_SRC_MASK (0x00000001u) + #define BB_INT_SRC_BASEBAND_INT_SRC_BIT (0) + #define BB_INT_SRC_BASEBAND_INT_SRC_BITS (1) + +#define SEC_INT_SRC *((volatile int32u *)0x4000A010u) +#define SEC_INT_SRC_REG *((volatile int32u *)0x4000A010u) +#define SEC_INT_SRC_ADDR (0x4000A010u) +#define SEC_INT_SRC_RESET (0x00000000u) + /* CT_WORD_VALID_SRC field */ + #define SEC_INT_SRC_CT_WORD_VALID_SRC (0x00000004u) + #define SEC_INT_SRC_CT_WORD_VALID_SRC_MASK (0x00000004u) + #define SEC_INT_SRC_CT_WORD_VALID_SRC_BIT (2) + #define SEC_INT_SRC_CT_WORD_VALID_SRC_BITS (1) + /* PT_WORD_REQ_SRC field */ + #define SEC_INT_SRC_PT_WORD_REQ_SRC (0x00000002u) + #define SEC_INT_SRC_PT_WORD_REQ_SRC_MASK (0x00000002u) + #define SEC_INT_SRC_PT_WORD_REQ_SRC_BIT (1) + #define SEC_INT_SRC_PT_WORD_REQ_SRC_BITS (1) + /* ENC_COMPLETE_SRC field */ + #define SEC_INT_SRC_ENC_COMPLETE_SRC (0x00000001u) + #define SEC_INT_SRC_ENC_COMPLETE_SRC_MASK (0x00000001u) + #define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT (0) + #define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS (1) + +#define INT_SLEEPTMRFLAG *((volatile int32u *)0x4000A014u) +#define INT_SLEEPTMRFLAG_REG *((volatile int32u *)0x4000A014u) +#define INT_SLEEPTMRFLAG_ADDR (0x4000A014u) +#define INT_SLEEPTMRFLAG_RESET (0x00000000u) + /* INT_SLEEPTMRCMPB field */ + #define INT_SLEEPTMRCMPB (0x00000004u) + #define INT_SLEEPTMRCMPB_MASK (0x00000004u) + #define INT_SLEEPTMRCMPB_BIT (2) + #define INT_SLEEPTMRCMPB_BITS (1) + /* INT_SLEEPTMRCMPA field */ + #define INT_SLEEPTMRCMPA (0x00000002u) + #define INT_SLEEPTMRCMPA_MASK (0x00000002u) + #define INT_SLEEPTMRCMPA_BIT (1) + #define INT_SLEEPTMRCMPA_BITS (1) + /* INT_SLEEPTMRWRAP field */ + #define INT_SLEEPTMRWRAP (0x00000001u) + #define INT_SLEEPTMRWRAP_MASK (0x00000001u) + #define INT_SLEEPTMRWRAP_BIT (0) + #define INT_SLEEPTMRWRAP_BITS (1) + +#define INT_MGMTFLAG *((volatile int32u *)0x4000A018u) +#define INT_MGMTFLAG_REG *((volatile int32u *)0x4000A018u) +#define INT_MGMTFLAG_ADDR (0x4000A018u) +#define INT_MGMTFLAG_RESET (0x00000000u) + /* INT_MGMTDMAPROT field */ + #define INT_MGMTDMAPROT (0x00000010u) + #define INT_MGMTDMAPROT_MASK (0x00000010u) + #define INT_MGMTDMAPROT_BIT (4) + #define INT_MGMTDMAPROT_BITS (1) + /* INT_MGMTCALADC field */ + #define INT_MGMTCALADC (0x00000008u) + #define INT_MGMTCALADC_MASK (0x00000008u) + #define INT_MGMTCALADC_BIT (3) + #define INT_MGMTCALADC_BITS (1) + /* INT_MGMTFPEC field */ + #define INT_MGMTFPEC (0x00000004u) + #define INT_MGMTFPEC_MASK (0x00000004u) + #define INT_MGMTFPEC_BIT (2) + #define INT_MGMTFPEC_BITS (1) + /* INT_MGMTOSC24MHI field */ + #define INT_MGMTOSC24MHI (0x00000002u) + #define INT_MGMTOSC24MHI_MASK (0x00000002u) + #define INT_MGMTOSC24MHI_BIT (1) + #define INT_MGMTOSC24MHI_BITS (1) + /* INT_MGMTOSC24MLO field */ + #define INT_MGMTOSC24MLO (0x00000001u) + #define INT_MGMTOSC24MLO_MASK (0x00000001u) + #define INT_MGMTOSC24MLO_BIT (0) + #define INT_MGMTOSC24MLO_BITS (1) + +#define INT_NMIFLAG *((volatile int32u *)0x4000A01Cu) +#define INT_NMIFLAG_REG *((volatile int32u *)0x4000A01Cu) +#define INT_NMIFLAG_ADDR (0x4000A01Cu) +#define INT_NMIFLAG_RESET (0x00000000u) + /* INT_NMICLK24M field */ + #define INT_NMICLK24M (0x00000002u) + #define INT_NMICLK24M_MASK (0x00000002u) + #define INT_NMICLK24M_BIT (1) + #define INT_NMICLK24M_BITS (1) + /* INT_NMIWDOG field */ + #define INT_NMIWDOG (0x00000001u) + #define INT_NMIWDOG_MASK (0x00000001u) + #define INT_NMIWDOG_BIT (0) + #define INT_NMIWDOG_BITS (1) + +#define INT_SLEEPTMRFORCE *((volatile int32u *)0x4000A020u) +#define INT_SLEEPTMRFORCE_REG *((volatile int32u *)0x4000A020u) +#define INT_SLEEPTMRFORCE_ADDR (0x4000A020u) +#define INT_SLEEPTMRFORCE_RESET (0x00000000u) + /* INT_SLEEPTMRCMPB field */ + #define INT_SLEEPTMRCMPB (0x00000004u) + #define INT_SLEEPTMRCMPB_MASK (0x00000004u) + #define INT_SLEEPTMRCMPB_BIT (2) + #define INT_SLEEPTMRCMPB_BITS (1) + /* INT_SLEEPTMRCMPA field */ + #define INT_SLEEPTMRCMPA (0x00000002u) + #define INT_SLEEPTMRCMPA_MASK (0x00000002u) + #define INT_SLEEPTMRCMPA_BIT (1) + #define INT_SLEEPTMRCMPA_BITS (1) + /* INT_SLEEPTMRWRAP field */ + #define INT_SLEEPTMRWRAP (0x00000001u) + #define INT_SLEEPTMRWRAP_MASK (0x00000001u) + #define INT_SLEEPTMRWRAP_BIT (0) + #define INT_SLEEPTMRWRAP_BITS (1) + +#define TEST_FORCE_ALL_INT *((volatile int32u *)0x4000A024u) +#define TEST_FORCE_ALL_INT_REG *((volatile int32u *)0x4000A024u) +#define TEST_FORCE_ALL_INT_ADDR (0x4000A024u) +#define TEST_FORCE_ALL_INT_RESET (0x00000000u) + /* FORCE_ALL_INT field */ + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT (0x00000001u) + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK (0x00000001u) + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT (0) + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS (1) + +#define MAC_RX_INT_MASK *((volatile int32u *)0x4000A040u) +#define MAC_RX_INT_MASK_REG *((volatile int32u *)0x4000A040u) +#define MAC_RX_INT_MASK_ADDR (0x4000A040u) +#define MAC_RX_INT_MASK_RESET (0x00000000u) + /* TX_B_ACK_ERR_MSK field */ + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK (0x00008000u) + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK (0x00008000u) + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT (15) + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS (1) + /* TX_A_ACK_ERR_MSK field */ + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK (0x00004000u) + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK (0x00004000u) + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT (14) + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS (1) + /* RX_OVFLW_MSK field */ + #define MAC_RX_INT_MASK_RX_OVFLW_MSK (0x00002000u) + #define MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK (0x00002000u) + #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT (13) + #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS (1) + /* RX_ERROR_MSK field */ + #define MAC_RX_INT_MASK_RX_ERROR_MSK (0x00001000u) + #define MAC_RX_INT_MASK_RX_ERROR_MSK_MASK (0x00001000u) + #define MAC_RX_INT_MASK_RX_ERROR_MSK_BIT (12) + #define MAC_RX_INT_MASK_RX_ERROR_MSK_BITS (1) + /* BB_RX_LEN_ERR_MSK field */ + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK (0x00000800u) + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK (0x00000800u) + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT (11) + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS (1) + /* TX_COLL_RX_MSK field */ + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK (0x00000400u) + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK (0x00000400u) + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT (10) + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS (1) + /* RSSI_INST_MEAS_MSK field */ + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK (0x00000200u) + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK (0x00000200u) + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT (9) + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS (1) + /* TX_B_ACK_MSK field */ + #define MAC_RX_INT_MASK_TX_B_ACK_MSK (0x00000100u) + #define MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK (0x00000100u) + #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT (8) + #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS (1) + /* TX_A_ACK_MSK field */ + #define MAC_RX_INT_MASK_TX_A_ACK_MSK (0x00000080u) + #define MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK (0x00000080u) + #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT (7) + #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS (1) + /* RX_B_UNLOAD_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK (0x00000040u) + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK (0x00000040u) + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT (6) + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS (1) + /* RX_A_UNLOAD_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK (0x00000020u) + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK (0x00000020u) + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT (5) + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS (1) + /* RX_B_ADDR_REC_MSK field */ + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK (0x00000010u) + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK (0x00000010u) + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT (4) + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS (1) + /* RX_A_ADDR_REC_MSK field */ + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK (0x00000008u) + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK (0x00000008u) + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT (3) + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS (1) + /* RX_B_FILT_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK (0x00000004u) + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK (0x00000004u) + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT (2) + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS (1) + /* RX_A_FILT_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK (0x00000002u) + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK (0x00000002u) + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT (1) + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS (1) + /* RX_FRAME_MSK field */ + #define MAC_RX_INT_MASK_RX_FRAME_MSK (0x00000001u) + #define MAC_RX_INT_MASK_RX_FRAME_MSK_MASK (0x00000001u) + #define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT (0) + #define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS (1) + +#define MAC_TX_INT_MASK *((volatile int32u *)0x4000A044u) +#define MAC_TX_INT_MASK_REG *((volatile int32u *)0x4000A044u) +#define MAC_TX_INT_MASK_ADDR (0x4000A044u) +#define MAC_TX_INT_MASK_RESET (0x00000000u) + /* RX_B_ACK_MSK field */ + #define MAC_TX_INT_MASK_RX_B_ACK_MSK (0x00000800u) + #define MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK (0x00000800u) + #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT (11) + #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS (1) + /* RX_A_ACK_MSK field */ + #define MAC_TX_INT_MASK_RX_A_ACK_MSK (0x00000400u) + #define MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK (0x00000400u) + #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT (10) + #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS (1) + /* TX_B_UNLOAD_MSK field */ + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK (0x00000200u) + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK (0x00000200u) + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT (9) + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS (1) + /* TX_A_UNLOAD_MSK field */ + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK (0x00000100u) + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK (0x00000100u) + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT (8) + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS (1) + /* ACK_EXPIRED_MSK field */ + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK (0x00000080u) + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK (0x00000080u) + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT (7) + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS (1) + /* TX_LOCK_FAIL_MSK field */ + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK (0x00000040u) + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK (0x00000040u) + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT (6) + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS (1) + /* TX_UNDERFLOW_MSK field */ + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK (0x00000020u) + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK (0x00000020u) + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT (5) + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS (1) + /* CCA_FAIL_MSK field */ + #define MAC_TX_INT_MASK_CCA_FAIL_MSK (0x00000010u) + #define MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK (0x00000010u) + #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT (4) + #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS (1) + /* SFD_SENT_MSK field */ + #define MAC_TX_INT_MASK_SFD_SENT_MSK (0x00000008u) + #define MAC_TX_INT_MASK_SFD_SENT_MSK_MASK (0x00000008u) + #define MAC_TX_INT_MASK_SFD_SENT_MSK_BIT (3) + #define MAC_TX_INT_MASK_SFD_SENT_MSK_BITS (1) + /* BO_COMPLETE_MSK field */ + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK (0x00000004u) + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK (0x00000004u) + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT (2) + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS (1) + /* RX_ACK_MSK field */ + #define MAC_TX_INT_MASK_RX_ACK_MSK (0x00000002u) + #define MAC_TX_INT_MASK_RX_ACK_MSK_MASK (0x00000002u) + #define MAC_TX_INT_MASK_RX_ACK_MSK_BIT (1) + #define MAC_TX_INT_MASK_RX_ACK_MSK_BITS (1) + /* TX_COMPLETE_MSK field */ + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK (0x00000001u) + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK (0x00000001u) + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT (0) + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS (1) + +#define MAC_TIMER_INT_MASK *((volatile int32u *)0x4000A048u) +#define MAC_TIMER_INT_MASK_REG *((volatile int32u *)0x4000A048u) +#define MAC_TIMER_INT_MASK_ADDR (0x4000A048u) +#define MAC_TIMER_INT_MASK_RESET (0x00000000u) + /* TIMER_COMP_B_MSK field */ + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK (0x00000004u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK (0x00000004u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT (2) + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS (1) + /* TIMER_COMP_A_MSK field */ + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK (0x00000002u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK (0x00000002u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT (1) + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS (1) + /* TIMER_WRAP_MSK field */ + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK (0x00000001u) + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK (0x00000001u) + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT (0) + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS (1) + +#define BB_INT_MASK *((volatile int32u *)0x4000A04Cu) +#define BB_INT_MASK_REG *((volatile int32u *)0x4000A04Cu) +#define BB_INT_MASK_ADDR (0x4000A04Cu) +#define BB_INT_MASK_RESET (0x00000000u) + /* RSSI_INT_MSK field */ + #define BB_INT_MASK_RSSI_INT_MSK (0x00000002u) + #define BB_INT_MASK_RSSI_INT_MSK_MASK (0x00000002u) + #define BB_INT_MASK_RSSI_INT_MSK_BIT (1) + #define BB_INT_MASK_RSSI_INT_MSK_BITS (1) + /* BASEBAND_INT_MSK field */ + #define BB_INT_MASK_BASEBAND_INT_MSK (0x00000001u) + #define BB_INT_MASK_BASEBAND_INT_MSK_MASK (0x00000001u) + #define BB_INT_MASK_BASEBAND_INT_MSK_BIT (0) + #define BB_INT_MASK_BASEBAND_INT_MSK_BITS (1) + +#define SEC_INT_MASK *((volatile int32u *)0x4000A050u) +#define SEC_INT_MASK_REG *((volatile int32u *)0x4000A050u) +#define SEC_INT_MASK_ADDR (0x4000A050u) +#define SEC_INT_MASK_RESET (0x00000000u) + /* CT_WORD_VALID_MSK field */ + #define SEC_INT_MASK_CT_WORD_VALID_MSK (0x00000004u) + #define SEC_INT_MASK_CT_WORD_VALID_MSK_MASK (0x00000004u) + #define SEC_INT_MASK_CT_WORD_VALID_MSK_BIT (2) + #define SEC_INT_MASK_CT_WORD_VALID_MSK_BITS (1) + /* PT_WORD_REQ_MSK field */ + #define SEC_INT_MASK_PT_WORD_REQ_MSK (0x00000002u) + #define SEC_INT_MASK_PT_WORD_REQ_MSK_MASK (0x00000002u) + #define SEC_INT_MASK_PT_WORD_REQ_MSK_BIT (1) + #define SEC_INT_MASK_PT_WORD_REQ_MSK_BITS (1) + /* ENC_COMPLETE_MSK field */ + #define SEC_INT_MASK_ENC_COMPLETE_MSK (0x00000001u) + #define SEC_INT_MASK_ENC_COMPLETE_MSK_MASK (0x00000001u) + #define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT (0) + #define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS (1) + +#define INT_SLEEPTMRCFG *((volatile int32u *)0x4000A054u) +#define INT_SLEEPTMRCFG_REG *((volatile int32u *)0x4000A054u) +#define INT_SLEEPTMRCFG_ADDR (0x4000A054u) +#define INT_SLEEPTMRCFG_RESET (0x00000000u) + /* INT_SLEEPTMRCMPB field */ + #define INT_SLEEPTMRCMPB (0x00000004u) + #define INT_SLEEPTMRCMPB_MASK (0x00000004u) + #define INT_SLEEPTMRCMPB_BIT (2) + #define INT_SLEEPTMRCMPB_BITS (1) + /* INT_SLEEPTMRCMPA field */ + #define INT_SLEEPTMRCMPA (0x00000002u) + #define INT_SLEEPTMRCMPA_MASK (0x00000002u) + #define INT_SLEEPTMRCMPA_BIT (1) + #define INT_SLEEPTMRCMPA_BITS (1) + /* INT_SLEEPTMRWRAP field */ + #define INT_SLEEPTMRWRAP (0x00000001u) + #define INT_SLEEPTMRWRAP_MASK (0x00000001u) + #define INT_SLEEPTMRWRAP_BIT (0) + #define INT_SLEEPTMRWRAP_BITS (1) + +#define INT_MGMTCFG *((volatile int32u *)0x4000A058u) +#define INT_MGMTCFG_REG *((volatile int32u *)0x4000A058u) +#define INT_MGMTCFG_ADDR (0x4000A058u) +#define INT_MGMTCFG_RESET (0x00000000u) + /* INT_MGMTDMAPROT field */ + #define INT_MGMTDMAPROT (0x00000010u) + #define INT_MGMTDMAPROT_MASK (0x00000010u) + #define INT_MGMTDMAPROT_BIT (4) + #define INT_MGMTDMAPROT_BITS (1) + /* INT_MGMTCALADC field */ + #define INT_MGMTCALADC (0x00000008u) + #define INT_MGMTCALADC_MASK (0x00000008u) + #define INT_MGMTCALADC_BIT (3) + #define INT_MGMTCALADC_BITS (1) + /* INT_MGMTFPEC field */ + #define INT_MGMTFPEC (0x00000004u) + #define INT_MGMTFPEC_MASK (0x00000004u) + #define INT_MGMTFPEC_BIT (2) + #define INT_MGMTFPEC_BITS (1) + /* INT_MGMTOSC24MHI field */ + #define INT_MGMTOSC24MHI (0x00000002u) + #define INT_MGMTOSC24MHI_MASK (0x00000002u) + #define INT_MGMTOSC24MHI_BIT (1) + #define INT_MGMTOSC24MHI_BITS (1) + /* INT_MGMTOSC24MLO field */ + #define INT_MGMTOSC24MLO (0x00000001u) + #define INT_MGMTOSC24MLO_MASK (0x00000001u) + #define INT_MGMTOSC24MLO_BIT (0) + #define INT_MGMTOSC24MLO_BITS (1) + +#define INT_TIM1FLAG *((volatile int32u *)0x4000A800u) +#define INT_TIM1FLAG_REG *((volatile int32u *)0x4000A800u) +#define INT_TIM1FLAG_ADDR (0x4000A800u) +#define INT_TIM1FLAG_RESET (0x00000000u) + /* INT_TIMRSVD field */ + #define INT_TIMRSVD (0x00001E00u) + #define INT_TIMRSVD_MASK (0x00001E00u) + #define INT_TIMRSVD_BIT (9) + #define INT_TIMRSVD_BITS (4) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_TIM2FLAG *((volatile int32u *)0x4000A804u) +#define INT_TIM2FLAG_REG *((volatile int32u *)0x4000A804u) +#define INT_TIM2FLAG_ADDR (0x4000A804u) +#define INT_TIM2FLAG_RESET (0x00000000u) + /* INT_TIMRSVD field */ + #define INT_TIMRSVD (0x00001E00u) + #define INT_TIMRSVD_MASK (0x00001E00u) + #define INT_TIMRSVD_BIT (9) + #define INT_TIMRSVD_BITS (4) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_SC1FLAG *((volatile int32u *)0x4000A808u) +#define INT_SC1FLAG_REG *((volatile int32u *)0x4000A808u) +#define INT_SC1FLAG_ADDR (0x4000A808u) +#define INT_SC1FLAG_RESET (0x00000000u) + /* INT_SC1PARERR field */ + #define INT_SC1PARERR (0x00004000u) + #define INT_SC1PARERR_MASK (0x00004000u) + #define INT_SC1PARERR_BIT (14) + #define INT_SC1PARERR_BITS (1) + /* INT_SC1FRMERR field */ + #define INT_SC1FRMERR (0x00002000u) + #define INT_SC1FRMERR_MASK (0x00002000u) + #define INT_SC1FRMERR_BIT (13) + #define INT_SC1FRMERR_BITS (1) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_SC2FLAG *((volatile int32u *)0x4000A80Cu) +#define INT_SC2FLAG_REG *((volatile int32u *)0x4000A80Cu) +#define INT_SC2FLAG_ADDR (0x4000A80Cu) +#define INT_SC2FLAG_RESET (0x00000000u) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_ADCFLAG *((volatile int32u *)0x4000A810u) +#define INT_ADCFLAG_REG *((volatile int32u *)0x4000A810u) +#define INT_ADCFLAG_ADDR (0x4000A810u) +#define INT_ADCFLAG_RESET (0x00000000u) + /* INT_ADCOVF field */ + #define INT_ADCOVF (0x00000010u) + #define INT_ADCOVF_MASK (0x00000010u) + #define INT_ADCOVF_BIT (4) + #define INT_ADCOVF_BITS (1) + /* INT_ADCSAT field */ + #define INT_ADCSAT (0x00000008u) + #define INT_ADCSAT_MASK (0x00000008u) + #define INT_ADCSAT_BIT (3) + #define INT_ADCSAT_BITS (1) + /* INT_ADCULDFULL field */ + #define INT_ADCULDFULL (0x00000004u) + #define INT_ADCULDFULL_MASK (0x00000004u) + #define INT_ADCULDFULL_BIT (2) + #define INT_ADCULDFULL_BITS (1) + /* INT_ADCULDHALF field */ + #define INT_ADCULDHALF (0x00000002u) + #define INT_ADCULDHALF_MASK (0x00000002u) + #define INT_ADCULDHALF_BIT (1) + #define INT_ADCULDHALF_BITS (1) + /* INT_ADCFLAGRSVD field */ + #define INT_ADCFLAGRSVD (0x00000001u) + #define INT_ADCFLAGRSVD_MASK (0x00000001u) + #define INT_ADCFLAGRSVD_BIT (0) + #define INT_ADCFLAGRSVD_BITS (1) + +#define INT_GPIOFLAG *((volatile int32u *)0x4000A814u) +#define INT_GPIOFLAG_REG *((volatile int32u *)0x4000A814u) +#define INT_GPIOFLAG_ADDR (0x4000A814u) +#define INT_GPIOFLAG_RESET (0x00000000u) + /* INT_IRQDFLAG field */ + #define INT_IRQDFLAG (0x00000008u) + #define INT_IRQDFLAG_MASK (0x00000008u) + #define INT_IRQDFLAG_BIT (3) + #define INT_IRQDFLAG_BITS (1) + /* INT_IRQCFLAG field */ + #define INT_IRQCFLAG (0x00000004u) + #define INT_IRQCFLAG_MASK (0x00000004u) + #define INT_IRQCFLAG_BIT (2) + #define INT_IRQCFLAG_BITS (1) + /* INT_IRQBFLAG field */ + #define INT_IRQBFLAG (0x00000002u) + #define INT_IRQBFLAG_MASK (0x00000002u) + #define INT_IRQBFLAG_BIT (1) + #define INT_IRQBFLAG_BITS (1) + /* INT_IRQAFLAG field */ + #define INT_IRQAFLAG (0x00000001u) + #define INT_IRQAFLAG_MASK (0x00000001u) + #define INT_IRQAFLAG_BIT (0) + #define INT_IRQAFLAG_BITS (1) + +#define INT_TIM1MISS *((volatile int32u *)0x4000A818u) +#define INT_TIM1MISS_REG *((volatile int32u *)0x4000A818u) +#define INT_TIM1MISS_ADDR (0x4000A818u) +#define INT_TIM1MISS_RESET (0x00000000u) + /* INT_TIMMISSCC4IF field */ + #define INT_TIMMISSCC4IF (0x00001000u) + #define INT_TIMMISSCC4IF_MASK (0x00001000u) + #define INT_TIMMISSCC4IF_BIT (12) + #define INT_TIMMISSCC4IF_BITS (1) + /* INT_TIMMISSCC3IF field */ + #define INT_TIMMISSCC3IF (0x00000800u) + #define INT_TIMMISSCC3IF_MASK (0x00000800u) + #define INT_TIMMISSCC3IF_BIT (11) + #define INT_TIMMISSCC3IF_BITS (1) + /* INT_TIMMISSCC2IF field */ + #define INT_TIMMISSCC2IF (0x00000400u) + #define INT_TIMMISSCC2IF_MASK (0x00000400u) + #define INT_TIMMISSCC2IF_BIT (10) + #define INT_TIMMISSCC2IF_BITS (1) + /* INT_TIMMISSCC1IF field */ + #define INT_TIMMISSCC1IF (0x00000200u) + #define INT_TIMMISSCC1IF_MASK (0x00000200u) + #define INT_TIMMISSCC1IF_BIT (9) + #define INT_TIMMISSCC1IF_BITS (1) + /* INT_TIMMISSRSVD field */ + #define INT_TIMMISSRSVD (0x0000007Fu) + #define INT_TIMMISSRSVD_MASK (0x0000007Fu) + #define INT_TIMMISSRSVD_BIT (0) + #define INT_TIMMISSRSVD_BITS (7) + +#define INT_TIM2MISS *((volatile int32u *)0x4000A81Cu) +#define INT_TIM2MISS_REG *((volatile int32u *)0x4000A81Cu) +#define INT_TIM2MISS_ADDR (0x4000A81Cu) +#define INT_TIM2MISS_RESET (0x00000000u) + /* INT_TIMMISSCC4IF field */ + #define INT_TIMMISSCC4IF (0x00001000u) + #define INT_TIMMISSCC4IF_MASK (0x00001000u) + #define INT_TIMMISSCC4IF_BIT (12) + #define INT_TIMMISSCC4IF_BITS (1) + /* INT_TIMMISSCC3IF field */ + #define INT_TIMMISSCC3IF (0x00000800u) + #define INT_TIMMISSCC3IF_MASK (0x00000800u) + #define INT_TIMMISSCC3IF_BIT (11) + #define INT_TIMMISSCC3IF_BITS (1) + /* INT_TIMMISSCC2IF field */ + #define INT_TIMMISSCC2IF (0x00000400u) + #define INT_TIMMISSCC2IF_MASK (0x00000400u) + #define INT_TIMMISSCC2IF_BIT (10) + #define INT_TIMMISSCC2IF_BITS (1) + /* INT_TIMMISSCC1IF field */ + #define INT_TIMMISSCC1IF (0x00000200u) + #define INT_TIMMISSCC1IF_MASK (0x00000200u) + #define INT_TIMMISSCC1IF_BIT (9) + #define INT_TIMMISSCC1IF_BITS (1) + /* INT_TIMMISSRSVD field */ + #define INT_TIMMISSRSVD (0x0000007Fu) + #define INT_TIMMISSRSVD_MASK (0x0000007Fu) + #define INT_TIMMISSRSVD_BIT (0) + #define INT_TIMMISSRSVD_BITS (7) + +#define INT_MISS *((volatile int32u *)0x4000A820u) +#define INT_MISS_REG *((volatile int32u *)0x4000A820u) +#define INT_MISS_ADDR (0x4000A820u) +#define INT_MISS_RESET (0x00000000u) + /* INT_MISSIRQD field */ + #define INT_MISSIRQD (0x00008000u) + #define INT_MISSIRQD_MASK (0x00008000u) + #define INT_MISSIRQD_BIT (15) + #define INT_MISSIRQD_BITS (1) + /* INT_MISSIRQC field */ + #define INT_MISSIRQC (0x00004000u) + #define INT_MISSIRQC_MASK (0x00004000u) + #define INT_MISSIRQC_BIT (14) + #define INT_MISSIRQC_BITS (1) + /* INT_MISSIRQB field */ + #define INT_MISSIRQB (0x00002000u) + #define INT_MISSIRQB_MASK (0x00002000u) + #define INT_MISSIRQB_BIT (13) + #define INT_MISSIRQB_BITS (1) + /* INT_MISSIRQA field */ + #define INT_MISSIRQA (0x00001000u) + #define INT_MISSIRQA_MASK (0x00001000u) + #define INT_MISSIRQA_BIT (12) + #define INT_MISSIRQA_BITS (1) + /* INT_MISSADC field */ + #define INT_MISSADC (0x00000800u) + #define INT_MISSADC_MASK (0x00000800u) + #define INT_MISSADC_BIT (11) + #define INT_MISSADC_BITS (1) + /* INT_MISSMACRX field */ + #define INT_MISSMACRX (0x00000400u) + #define INT_MISSMACRX_MASK (0x00000400u) + #define INT_MISSMACRX_BIT (10) + #define INT_MISSMACRX_BITS (1) + /* INT_MISSMACTX field */ + #define INT_MISSMACTX (0x00000200u) + #define INT_MISSMACTX_MASK (0x00000200u) + #define INT_MISSMACTX_BIT (9) + #define INT_MISSMACTX_BITS (1) + /* INT_MISSMACTMR field */ + #define INT_MISSMACTMR (0x00000100u) + #define INT_MISSMACTMR_MASK (0x00000100u) + #define INT_MISSMACTMR_BIT (8) + #define INT_MISSMACTMR_BITS (1) + /* INT_MISSSEC field */ + #define INT_MISSSEC (0x00000080u) + #define INT_MISSSEC_MASK (0x00000080u) + #define INT_MISSSEC_BIT (7) + #define INT_MISSSEC_BITS (1) + /* INT_MISSSC2 field */ + #define INT_MISSSC2 (0x00000040u) + #define INT_MISSSC2_MASK (0x00000040u) + #define INT_MISSSC2_BIT (6) + #define INT_MISSSC2_BITS (1) + /* INT_MISSSC1 field */ + #define INT_MISSSC1 (0x00000020u) + #define INT_MISSSC1_MASK (0x00000020u) + #define INT_MISSSC1_BIT (5) + #define INT_MISSSC1_BITS (1) + /* INT_MISSSLEEP field */ + #define INT_MISSSLEEP (0x00000010u) + #define INT_MISSSLEEP_MASK (0x00000010u) + #define INT_MISSSLEEP_BIT (4) + #define INT_MISSSLEEP_BITS (1) + /* INT_MISSBB field */ + #define INT_MISSBB (0x00000008u) + #define INT_MISSBB_MASK (0x00000008u) + #define INT_MISSBB_BIT (3) + #define INT_MISSBB_BITS (1) + /* INT_MISSMGMT field */ + #define INT_MISSMGMT (0x00000004u) + #define INT_MISSMGMT_MASK (0x00000004u) + #define INT_MISSMGMT_BIT (2) + #define INT_MISSMGMT_BITS (1) + +#define INT_TIM1CFG *((volatile int32u *)0x4000A840u) +#define INT_TIM1CFG_REG *((volatile int32u *)0x4000A840u) +#define INT_TIM1CFG_ADDR (0x4000A840u) +#define INT_TIM1CFG_RESET (0x00000000u) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_TIM2CFG *((volatile int32u *)0x4000A844u) +#define INT_TIM2CFG_REG *((volatile int32u *)0x4000A844u) +#define INT_TIM2CFG_ADDR (0x4000A844u) +#define INT_TIM2CFG_RESET (0x00000000u) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_SC1CFG *((volatile int32u *)0x4000A848u) +#define INT_SC1CFG_REG *((volatile int32u *)0x4000A848u) +#define INT_SC1CFG_ADDR (0x4000A848u) +#define INT_SC1CFG_RESET (0x00000000u) + /* INT_SC1PARERR field */ + #define INT_SC1PARERR (0x00004000u) + #define INT_SC1PARERR_MASK (0x00004000u) + #define INT_SC1PARERR_BIT (14) + #define INT_SC1PARERR_BITS (1) + /* INT_SC1FRMERR field */ + #define INT_SC1FRMERR (0x00002000u) + #define INT_SC1FRMERR_MASK (0x00002000u) + #define INT_SC1FRMERR_BIT (13) + #define INT_SC1FRMERR_BITS (1) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_SC2CFG *((volatile int32u *)0x4000A84Cu) +#define INT_SC2CFG_REG *((volatile int32u *)0x4000A84Cu) +#define INT_SC2CFG_ADDR (0x4000A84Cu) +#define INT_SC2CFG_RESET (0x00000000u) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_ADCCFG *((volatile int32u *)0x4000A850u) +#define INT_ADCCFG_REG *((volatile int32u *)0x4000A850u) +#define INT_ADCCFG_ADDR (0x4000A850u) +#define INT_ADCCFG_RESET (0x00000000u) + /* INT_ADCOVF field */ + #define INT_ADCOVF (0x00000010u) + #define INT_ADCOVF_MASK (0x00000010u) + #define INT_ADCOVF_BIT (4) + #define INT_ADCOVF_BITS (1) + /* INT_ADCSAT field */ + #define INT_ADCSAT (0x00000008u) + #define INT_ADCSAT_MASK (0x00000008u) + #define INT_ADCSAT_BIT (3) + #define INT_ADCSAT_BITS (1) + /* INT_ADCULDFULL field */ + #define INT_ADCULDFULL (0x00000004u) + #define INT_ADCULDFULL_MASK (0x00000004u) + #define INT_ADCULDFULL_BIT (2) + #define INT_ADCULDFULL_BITS (1) + /* INT_ADCULDHALF field */ + #define INT_ADCULDHALF (0x00000002u) + #define INT_ADCULDHALF_MASK (0x00000002u) + #define INT_ADCULDHALF_BIT (1) + #define INT_ADCULDHALF_BITS (1) + /* INT_ADCCFGRSVD field */ + #define INT_ADCCFGRSVD (0x00000001u) + #define INT_ADCCFGRSVD_MASK (0x00000001u) + #define INT_ADCCFGRSVD_BIT (0) + #define INT_ADCCFGRSVD_BITS (1) + +#define SC1_INTMODE *((volatile int32u *)0x4000A854u) +#define SC1_INTMODE_REG *((volatile int32u *)0x4000A854u) +#define SC1_INTMODE_ADDR (0x4000A854u) +#define SC1_INTMODE_RESET (0x00000000u) + /* SC_TXIDLELEVEL field */ + #define SC_TXIDLELEVEL (0x00000004u) + #define SC_TXIDLELEVEL_MASK (0x00000004u) + #define SC_TXIDLELEVEL_BIT (2) + #define SC_TXIDLELEVEL_BITS (1) + /* SC_TXFREELEVEL field */ + #define SC_TXFREELEVEL (0x00000002u) + #define SC_TXFREELEVEL_MASK (0x00000002u) + #define SC_TXFREELEVEL_BIT (1) + #define SC_TXFREELEVEL_BITS (1) + /* SC_RXVALLEVEL field */ + #define SC_RXVALLEVEL (0x00000001u) + #define SC_RXVALLEVEL_MASK (0x00000001u) + #define SC_RXVALLEVEL_BIT (0) + #define SC_RXVALLEVEL_BITS (1) + +#define SC2_INTMODE *((volatile int32u *)0x4000A858u) +#define SC2_INTMODE_REG *((volatile int32u *)0x4000A858u) +#define SC2_INTMODE_ADDR (0x4000A858u) +#define SC2_INTMODE_RESET (0x00000000u) + /* SC_TXIDLELEVEL field */ + #define SC_TXIDLELEVEL (0x00000004u) + #define SC_TXIDLELEVEL_MASK (0x00000004u) + #define SC_TXIDLELEVEL_BIT (2) + #define SC_TXIDLELEVEL_BITS (1) + /* SC_TXFREELEVEL field */ + #define SC_TXFREELEVEL (0x00000002u) + #define SC_TXFREELEVEL_MASK (0x00000002u) + #define SC_TXFREELEVEL_BIT (1) + #define SC_TXFREELEVEL_BITS (1) + /* SC_RXVALLEVEL field */ + #define SC_RXVALLEVEL (0x00000001u) + #define SC_RXVALLEVEL_MASK (0x00000001u) + #define SC_RXVALLEVEL_BIT (0) + #define SC_RXVALLEVEL_BITS (1) + +#define GPIO_INTCFGA *((volatile int32u *)0x4000A860u) +#define GPIO_INTCFGA_REG *((volatile int32u *)0x4000A860u) +#define GPIO_INTCFGA_ADDR (0x4000A860u) +#define GPIO_INTCFGA_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +#define GPIO_INTCFGB *((volatile int32u *)0x4000A864u) +#define GPIO_INTCFGB_REG *((volatile int32u *)0x4000A864u) +#define GPIO_INTCFGB_ADDR (0x4000A864u) +#define GPIO_INTCFGB_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +#define GPIO_INTCFGC *((volatile int32u *)0x4000A868u) +#define GPIO_INTCFGC_REG *((volatile int32u *)0x4000A868u) +#define GPIO_INTCFGC_ADDR (0x4000A868u) +#define GPIO_INTCFGC_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +#define GPIO_INTCFGD *((volatile int32u *)0x4000A86Cu) +#define GPIO_INTCFGD_REG *((volatile int32u *)0x4000A86Cu) +#define GPIO_INTCFGD_ADDR (0x4000A86Cu) +#define GPIO_INTCFGD_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +/* GPIO block */ +#define BLOCK_GPIO_BASE (0x4000B000u) +#define BLOCK_GPIO_END (0x4000BC1Cu) +#define BLOCK_GPIO_SIZE (BLOCK_GPIO_END - BLOCK_GPIO_BASE + 1) + +#define GPIO_PACFGL *((volatile int32u *)0x4000B000u) +#define GPIO_PACFGL_REG *((volatile int32u *)0x4000B000u) +#define GPIO_PACFGL_ADDR (0x4000B000u) +#define GPIO_PACFGL_RESET (0x00004444u) + /* PA3_CFG field */ + #define PA3_CFG (0x0000F000u) + #define PA3_CFG_MASK (0x0000F000u) + #define PA3_CFG_BIT (12) + #define PA3_CFG_BITS (4) + /* PA2_CFG field */ + #define PA2_CFG (0x00000F00u) + #define PA2_CFG_MASK (0x00000F00u) + #define PA2_CFG_BIT (8) + #define PA2_CFG_BITS (4) + /* PA1_CFG field */ + #define PA1_CFG (0x000000F0u) + #define PA1_CFG_MASK (0x000000F0u) + #define PA1_CFG_BIT (4) + #define PA1_CFG_BITS (4) + /* PA0_CFG field */ + #define PA0_CFG (0x0000000Fu) + #define PA0_CFG_MASK (0x0000000Fu) + #define PA0_CFG_BIT (0) + #define PA0_CFG_BITS (4) + /* GPIO_PxCFGx Bit Field Values */ + #define GPIOCFG_OUT (0x1u) + #define GPIOCFG_OUT_OD (0x5u) + #define GPIOCFG_OUT_ALT (0x9u) + #define GPIOCFG_OUT_ALT_OD (0xDu) + #define GPIOCFG_ANALOG (0x0u) + #define GPIOCFG_IN (0x4u) + #define GPIOCFG_IN_PUD (0x8u) + +#define GPIO_PACFGH *((volatile int32u *)0x4000B004u) +#define GPIO_PACFGH_REG *((volatile int32u *)0x4000B004u) +#define GPIO_PACFGH_ADDR (0x4000B004u) +#define GPIO_PACFGH_RESET (0x00004444u) + /* PA7_CFG field */ + #define PA7_CFG (0x0000F000u) + #define PA7_CFG_MASK (0x0000F000u) + #define PA7_CFG_BIT (12) + #define PA7_CFG_BITS (4) + /* PA6_CFG field */ + #define PA6_CFG (0x00000F00u) + #define PA6_CFG_MASK (0x00000F00u) + #define PA6_CFG_BIT (8) + #define PA6_CFG_BITS (4) + /* PA5_CFG field */ + #define PA5_CFG (0x000000F0u) + #define PA5_CFG_MASK (0x000000F0u) + #define PA5_CFG_BIT (4) + #define PA5_CFG_BITS (4) + /* PA4_CFG field */ + #define PA4_CFG (0x0000000Fu) + #define PA4_CFG_MASK (0x0000000Fu) + #define PA4_CFG_BIT (0) + #define PA4_CFG_BITS (4) + +#define GPIO_PAIN *((volatile int32u *)0x4000B008u) +#define GPIO_PAIN_REG *((volatile int32u *)0x4000B008u) +#define GPIO_PAIN_ADDR (0x4000B008u) +#define GPIO_PAIN_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PAOUT *((volatile int32u *)0x4000B00Cu) +#define GPIO_PAOUT_REG *((volatile int32u *)0x4000B00Cu) +#define GPIO_PAOUT_ADDR (0x4000B00Cu) +#define GPIO_PAOUT_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + /* GPIO_PxOUT Bit Field Values */ + #define GPIOOUT_PULLUP (0x1u) + #define GPIOOUT_PULLDOWN (0x0u) + +#define GPIO_PASET *((volatile int32u *)0x4000B010u) +#define GPIO_PASET_REG *((volatile int32u *)0x4000B010u) +#define GPIO_PASET_ADDR (0x4000B010u) +#define GPIO_PASET_RESET (0x00000000u) + /* GPIO_PXSETRSVD field */ + #define GPIO_PXSETRSVD (0x0000FF00u) + #define GPIO_PXSETRSVD_MASK (0x0000FF00u) + #define GPIO_PXSETRSVD_BIT (8) + #define GPIO_PXSETRSVD_BITS (8) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PACLR *((volatile int32u *)0x4000B014u) +#define GPIO_PACLR_REG *((volatile int32u *)0x4000B014u) +#define GPIO_PACLR_ADDR (0x4000B014u) +#define GPIO_PACLR_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PBCFGL *((volatile int32u *)0x4000B400u) +#define GPIO_PBCFGL_REG *((volatile int32u *)0x4000B400u) +#define GPIO_PBCFGL_ADDR (0x4000B400u) +#define GPIO_PBCFGL_RESET (0x00004444u) + /* PB3_CFG field */ + #define PB3_CFG (0x0000F000u) + #define PB3_CFG_MASK (0x0000F000u) + #define PB3_CFG_BIT (12) + #define PB3_CFG_BITS (4) + /* PB2_CFG field */ + #define PB2_CFG (0x00000F00u) + #define PB2_CFG_MASK (0x00000F00u) + #define PB2_CFG_BIT (8) + #define PB2_CFG_BITS (4) + /* PB1_CFG field */ + #define PB1_CFG (0x000000F0u) + #define PB1_CFG_MASK (0x000000F0u) + #define PB1_CFG_BIT (4) + #define PB1_CFG_BITS (4) + /* PB0_CFG field */ + #define PB0_CFG (0x0000000Fu) + #define PB0_CFG_MASK (0x0000000Fu) + #define PB0_CFG_BIT (0) + #define PB0_CFG_BITS (4) + +#define GPIO_PBCFGH *((volatile int32u *)0x4000B404u) +#define GPIO_PBCFGH_REG *((volatile int32u *)0x4000B404u) +#define GPIO_PBCFGH_ADDR (0x4000B404u) +#define GPIO_PBCFGH_RESET (0x00004444u) + /* PB7_CFG field */ + #define PB7_CFG (0x0000F000u) + #define PB7_CFG_MASK (0x0000F000u) + #define PB7_CFG_BIT (12) + #define PB7_CFG_BITS (4) + /* PB6_CFG field */ + #define PB6_CFG (0x00000F00u) + #define PB6_CFG_MASK (0x00000F00u) + #define PB6_CFG_BIT (8) + #define PB6_CFG_BITS (4) + /* PB5_CFG field */ + #define PB5_CFG (0x000000F0u) + #define PB5_CFG_MASK (0x000000F0u) + #define PB5_CFG_BIT (4) + #define PB5_CFG_BITS (4) + /* PB4_CFG field */ + #define PB4_CFG (0x0000000Fu) + #define PB4_CFG_MASK (0x0000000Fu) + #define PB4_CFG_BIT (0) + #define PB4_CFG_BITS (4) + +#define GPIO_PBIN *((volatile int32u *)0x4000B408u) +#define GPIO_PBIN_REG *((volatile int32u *)0x4000B408u) +#define GPIO_PBIN_ADDR (0x4000B408u) +#define GPIO_PBIN_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PBOUT *((volatile int32u *)0x4000B40Cu) +#define GPIO_PBOUT_REG *((volatile int32u *)0x4000B40Cu) +#define GPIO_PBOUT_ADDR (0x4000B40Cu) +#define GPIO_PBOUT_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PBSET *((volatile int32u *)0x4000B410u) +#define GPIO_PBSET_REG *((volatile int32u *)0x4000B410u) +#define GPIO_PBSET_ADDR (0x4000B410u) +#define GPIO_PBSET_RESET (0x00000000u) + /* GPIO_PXSETRSVD field */ + #define GPIO_PXSETRSVD (0x0000FF00u) + #define GPIO_PXSETRSVD_MASK (0x0000FF00u) + #define GPIO_PXSETRSVD_BIT (8) + #define GPIO_PXSETRSVD_BITS (8) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PBCLR *((volatile int32u *)0x4000B414u) +#define GPIO_PBCLR_REG *((volatile int32u *)0x4000B414u) +#define GPIO_PBCLR_ADDR (0x4000B414u) +#define GPIO_PBCLR_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PCCFGL *((volatile int32u *)0x4000B800u) +#define GPIO_PCCFGL_REG *((volatile int32u *)0x4000B800u) +#define GPIO_PCCFGL_ADDR (0x4000B800u) +#define GPIO_PCCFGL_RESET (0x00004444u) + /* PC3_CFG field */ + #define PC3_CFG (0x0000F000u) + #define PC3_CFG_MASK (0x0000F000u) + #define PC3_CFG_BIT (12) + #define PC3_CFG_BITS (4) + /* PC2_CFG field */ + #define PC2_CFG (0x00000F00u) + #define PC2_CFG_MASK (0x00000F00u) + #define PC2_CFG_BIT (8) + #define PC2_CFG_BITS (4) + /* PC1_CFG field */ + #define PC1_CFG (0x000000F0u) + #define PC1_CFG_MASK (0x000000F0u) + #define PC1_CFG_BIT (4) + #define PC1_CFG_BITS (4) + /* PC0_CFG field */ + #define PC0_CFG (0x0000000Fu) + #define PC0_CFG_MASK (0x0000000Fu) + #define PC0_CFG_BIT (0) + #define PC0_CFG_BITS (4) + +#define GPIO_PCCFGH *((volatile int32u *)0x4000B804u) +#define GPIO_PCCFGH_REG *((volatile int32u *)0x4000B804u) +#define GPIO_PCCFGH_ADDR (0x4000B804u) +#define GPIO_PCCFGH_RESET (0x00004444u) + /* PC7_CFG field */ + #define PC7_CFG (0x0000F000u) + #define PC7_CFG_MASK (0x0000F000u) + #define PC7_CFG_BIT (12) + #define PC7_CFG_BITS (4) + /* PC6_CFG field */ + #define PC6_CFG (0x00000F00u) + #define PC6_CFG_MASK (0x00000F00u) + #define PC6_CFG_BIT (8) + #define PC6_CFG_BITS (4) + /* PC5_CFG field */ + #define PC5_CFG (0x000000F0u) + #define PC5_CFG_MASK (0x000000F0u) + #define PC5_CFG_BIT (4) + #define PC5_CFG_BITS (4) + /* PC4_CFG field */ + #define PC4_CFG (0x0000000Fu) + #define PC4_CFG_MASK (0x0000000Fu) + #define PC4_CFG_BIT (0) + #define PC4_CFG_BITS (4) + +#define GPIO_PCIN *((volatile int32u *)0x4000B808u) +#define GPIO_PCIN_REG *((volatile int32u *)0x4000B808u) +#define GPIO_PCIN_ADDR (0x4000B808u) +#define GPIO_PCIN_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_PCOUT *((volatile int32u *)0x4000B80Cu) +#define GPIO_PCOUT_REG *((volatile int32u *)0x4000B80Cu) +#define GPIO_PCOUT_ADDR (0x4000B80Cu) +#define GPIO_PCOUT_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_PCSET *((volatile int32u *)0x4000B810u) +#define GPIO_PCSET_REG *((volatile int32u *)0x4000B810u) +#define GPIO_PCSET_ADDR (0x4000B810u) +#define GPIO_PCSET_RESET (0x00000000u) + /* GPIO_PXSETRSVD field */ + #define GPIO_PXSETRSVD (0x0000FF00u) + #define GPIO_PXSETRSVD_MASK (0x0000FF00u) + #define GPIO_PXSETRSVD_BIT (8) + #define GPIO_PXSETRSVD_BITS (8) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_PCCLR *((volatile int32u *)0x4000B814u) +#define GPIO_PCCLR_REG *((volatile int32u *)0x4000B814u) +#define GPIO_PCCLR_ADDR (0x4000B814u) +#define GPIO_PCCLR_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_DBGCFG *((volatile int32u *)0x4000BC00u) +#define GPIO_DBGCFG_REG *((volatile int32u *)0x4000BC00u) +#define GPIO_DBGCFG_ADDR (0x4000BC00u) +#define GPIO_DBGCFG_RESET (0x00000010u) + /* GPIO_DEBUGDIS field */ + #define GPIO_DEBUGDIS (0x00000020u) + #define GPIO_DEBUGDIS_MASK (0x00000020u) + #define GPIO_DEBUGDIS_BIT (5) + #define GPIO_DEBUGDIS_BITS (1) + /* GPIO_EXTREGEN field */ + #define GPIO_EXTREGEN (0x00000010u) + #define GPIO_EXTREGEN_MASK (0x00000010u) + #define GPIO_EXTREGEN_BIT (4) + #define GPIO_EXTREGEN_BITS (1) + /* GPIO_DBGCFGRSVD field */ + #define GPIO_DBGCFGRSVD (0x00000008u) + #define GPIO_DBGCFGRSVD_MASK (0x00000008u) + #define GPIO_DBGCFGRSVD_BIT (3) + #define GPIO_DBGCFGRSVD_BITS (1) + +#define GPIO_DBGSTAT *((volatile int32u *)0x4000BC04u) +#define GPIO_DBGSTAT_REG *((volatile int32u *)0x4000BC04u) +#define GPIO_DBGSTAT_ADDR (0x4000BC04u) +#define GPIO_DBGSTAT_RESET (0x00000000u) + /* GPIO_BOOTMODE field */ + #define GPIO_BOOTMODE (0x00000008u) + #define GPIO_BOOTMODE_MASK (0x00000008u) + #define GPIO_BOOTMODE_BIT (3) + #define GPIO_BOOTMODE_BITS (1) + /* GPIO_FORCEDBG field */ + #define GPIO_FORCEDBG (0x00000002u) + #define GPIO_FORCEDBG_MASK (0x00000002u) + #define GPIO_FORCEDBG_BIT (1) + #define GPIO_FORCEDBG_BITS (1) + /* GPIO_SWEN field */ + #define GPIO_SWEN (0x00000001u) + #define GPIO_SWEN_MASK (0x00000001u) + #define GPIO_SWEN_BIT (0) + #define GPIO_SWEN_BITS (1) + +#define GPIO_PAWAKE *((volatile int32u *)0x4000BC08u) +#define GPIO_PAWAKE_REG *((volatile int32u *)0x4000BC08u) +#define GPIO_PAWAKE_ADDR (0x4000BC08u) +#define GPIO_PAWAKE_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PBWAKE *((volatile int32u *)0x4000BC0Cu) +#define GPIO_PBWAKE_REG *((volatile int32u *)0x4000BC0Cu) +#define GPIO_PBWAKE_ADDR (0x4000BC0Cu) +#define GPIO_PBWAKE_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PCWAKE *((volatile int32u *)0x4000BC10u) +#define GPIO_PCWAKE_REG *((volatile int32u *)0x4000BC10u) +#define GPIO_PCWAKE_ADDR (0x4000BC10u) +#define GPIO_PCWAKE_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_IRQCSEL *((volatile int32u *)0x4000BC14u) +#define GPIO_IRQCSEL_REG *((volatile int32u *)0x4000BC14u) +#define GPIO_IRQCSEL_ADDR (0x4000BC14u) +#define GPIO_IRQCSEL_RESET (0x0000000Fu) + /* SEL_GPIO field */ + #define SEL_GPIO (0x0000001Fu) + #define SEL_GPIO_MASK (0x0000001Fu) + #define SEL_GPIO_BIT (0) + #define SEL_GPIO_BITS (5) + +#define GPIO_IRQDSEL *((volatile int32u *)0x4000BC18u) +#define GPIO_IRQDSEL_REG *((volatile int32u *)0x4000BC18u) +#define GPIO_IRQDSEL_ADDR (0x4000BC18u) +#define GPIO_IRQDSEL_RESET (0x00000010u) + /* SEL_GPIO field */ + #define SEL_GPIO (0x0000001Fu) + #define SEL_GPIO_MASK (0x0000001Fu) + #define SEL_GPIO_BIT (0) + #define SEL_GPIO_BITS (5) + +#define GPIO_WAKEFILT *((volatile int32u *)0x4000BC1Cu) +#define GPIO_WAKEFILT_REG *((volatile int32u *)0x4000BC1Cu) +#define GPIO_WAKEFILT_ADDR (0x4000BC1Cu) +#define GPIO_WAKEFILT_RESET (0x00000000u) + /* IRQD_WAKE_FILTER field */ + #define IRQD_WAKE_FILTER (0x00000008u) + #define IRQD_WAKE_FILTER_MASK (0x00000008u) + #define IRQD_WAKE_FILTER_BIT (3) + #define IRQD_WAKE_FILTER_BITS (1) + /* SC2_WAKE_FILTER field */ + #define SC2_WAKE_FILTER (0x00000004u) + #define SC2_WAKE_FILTER_MASK (0x00000004u) + #define SC2_WAKE_FILTER_BIT (2) + #define SC2_WAKE_FILTER_BITS (1) + /* SC1_WAKE_FILTER field */ + #define SC1_WAKE_FILTER (0x00000002u) + #define SC1_WAKE_FILTER_MASK (0x00000002u) + #define SC1_WAKE_FILTER_BIT (1) + #define SC1_WAKE_FILTER_BITS (1) + /* GPIO_WAKE_FILTER field */ + #define GPIO_WAKE_FILTER (0x00000001u) + #define GPIO_WAKE_FILTER_MASK (0x00000001u) + #define GPIO_WAKE_FILTER_BIT (0) + #define GPIO_WAKE_FILTER_BITS (1) + +/* SERIAL block */ +#define BLOCK_SERIAL_BASE (0x4000C000u) +#define BLOCK_SERIAL_END (0x4000C870u) +#define BLOCK_SERIAL_SIZE (BLOCK_SERIAL_END - BLOCK_SERIAL_BASE + 1) + +#define SC2_RXBEGA *((volatile int32u *)0x4000C000u) +#define SC2_RXBEGA_REG *((volatile int32u *)0x4000C000u) +#define SC2_RXBEGA_ADDR (0x4000C000u) +#define SC2_RXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXBEGA_FIXED (0xFFFFE000u) + #define SC2_RXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC2_RXBEGA_FIXED_BIT (13) + #define SC2_RXBEGA_FIXED_BITS (19) + /* SC_RXBEGA field */ + #define SC_RXBEGA (0x00001FFFu) + #define SC_RXBEGA_MASK (0x00001FFFu) + #define SC_RXBEGA_BIT (0) + #define SC_RXBEGA_BITS (13) + +#define SC2_RXENDA *((volatile int32u *)0x4000C004u) +#define SC2_RXENDA_REG *((volatile int32u *)0x4000C004u) +#define SC2_RXENDA_ADDR (0x4000C004u) +#define SC2_RXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXENDA_FIXED (0xFFFFE000u) + #define SC2_RXENDA_FIXED_MASK (0xFFFFE000u) + #define SC2_RXENDA_FIXED_BIT (13) + #define SC2_RXENDA_FIXED_BITS (19) + /* SC_RXENDA field */ + #define SC_RXENDA (0x00001FFFu) + #define SC_RXENDA_MASK (0x00001FFFu) + #define SC_RXENDA_BIT (0) + #define SC_RXENDA_BITS (13) + +#define SC2_RXBEGB *((volatile int32u *)0x4000C008u) +#define SC2_RXBEGB_REG *((volatile int32u *)0x4000C008u) +#define SC2_RXBEGB_ADDR (0x4000C008u) +#define SC2_RXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXBEGB_FIXED (0xFFFFE000u) + #define SC2_RXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC2_RXBEGB_FIXED_BIT (13) + #define SC2_RXBEGB_FIXED_BITS (19) + /* SC_RXBEGB field */ + #define SC_RXBEGB (0x00001FFFu) + #define SC_RXBEGB_MASK (0x00001FFFu) + #define SC_RXBEGB_BIT (0) + #define SC_RXBEGB_BITS (13) + +#define SC2_RXENDB *((volatile int32u *)0x4000C00Cu) +#define SC2_RXENDB_REG *((volatile int32u *)0x4000C00Cu) +#define SC2_RXENDB_ADDR (0x4000C00Cu) +#define SC2_RXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXENDB_FIXED (0xFFFFE000u) + #define SC2_RXENDB_FIXED_MASK (0xFFFFE000u) + #define SC2_RXENDB_FIXED_BIT (13) + #define SC2_RXENDB_FIXED_BITS (19) + /* SC_RXENDB field */ + #define SC_RXENDB (0x00001FFFu) + #define SC_RXENDB_MASK (0x00001FFFu) + #define SC_RXENDB_BIT (0) + #define SC_RXENDB_BITS (13) + +#define SC2_TXBEGA *((volatile int32u *)0x4000C010u) +#define SC2_TXBEGA_REG *((volatile int32u *)0x4000C010u) +#define SC2_TXBEGA_ADDR (0x4000C010u) +#define SC2_TXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXBEGA_FIXED (0xFFFFE000u) + #define SC2_TXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC2_TXBEGA_FIXED_BIT (13) + #define SC2_TXBEGA_FIXED_BITS (19) + /* SC_TXBEGA field */ + #define SC_TXBEGA (0x00001FFFu) + #define SC_TXBEGA_MASK (0x00001FFFu) + #define SC_TXBEGA_BIT (0) + #define SC_TXBEGA_BITS (13) + +#define SC2_TXENDA *((volatile int32u *)0x4000C014u) +#define SC2_TXENDA_REG *((volatile int32u *)0x4000C014u) +#define SC2_TXENDA_ADDR (0x4000C014u) +#define SC2_TXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXENDA_FIXED (0xFFFFE000u) + #define SC2_TXENDA_FIXED_MASK (0xFFFFE000u) + #define SC2_TXENDA_FIXED_BIT (13) + #define SC2_TXENDA_FIXED_BITS (19) + /* SC_TXENDA field */ + #define SC_TXENDA (0x00001FFFu) + #define SC_TXENDA_MASK (0x00001FFFu) + #define SC_TXENDA_BIT (0) + #define SC_TXENDA_BITS (13) + +#define SC2_TXBEGB *((volatile int32u *)0x4000C018u) +#define SC2_TXBEGB_REG *((volatile int32u *)0x4000C018u) +#define SC2_TXBEGB_ADDR (0x4000C018u) +#define SC2_TXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXBEGB_FIXED (0xFFFFE000u) + #define SC2_TXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC2_TXBEGB_FIXED_BIT (13) + #define SC2_TXBEGB_FIXED_BITS (19) + /* SC_TXBEGB field */ + #define SC_TXBEGB (0x00001FFFu) + #define SC_TXBEGB_MASK (0x00001FFFu) + #define SC_TXBEGB_BIT (0) + #define SC_TXBEGB_BITS (13) + +#define SC2_TXENDB *((volatile int32u *)0x4000C01Cu) +#define SC2_TXENDB_REG *((volatile int32u *)0x4000C01Cu) +#define SC2_TXENDB_ADDR (0x4000C01Cu) +#define SC2_TXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXENDB_FIXED (0xFFFFE000u) + #define SC2_TXENDB_FIXED_MASK (0xFFFFE000u) + #define SC2_TXENDB_FIXED_BIT (13) + #define SC2_TXENDB_FIXED_BITS (19) + /* SC_TXENDB field */ + #define SC_TXENDB (0x00001FFFu) + #define SC_TXENDB_MASK (0x00001FFFu) + #define SC_TXENDB_BIT (0) + #define SC_TXENDB_BITS (13) + +#define SC2_RXCNTA *((volatile int32u *)0x4000C020u) +#define SC2_RXCNTA_REG *((volatile int32u *)0x4000C020u) +#define SC2_RXCNTA_ADDR (0x4000C020u) +#define SC2_RXCNTA_RESET (0x00000000u) + /* SC_RXCNTA field */ + #define SC_RXCNTA (0x00001FFFu) + #define SC_RXCNTA_MASK (0x00001FFFu) + #define SC_RXCNTA_BIT (0) + #define SC_RXCNTA_BITS (13) + +#define SC2_RXCNTB *((volatile int32u *)0x4000C024u) +#define SC2_RXCNTB_REG *((volatile int32u *)0x4000C024u) +#define SC2_RXCNTB_ADDR (0x4000C024u) +#define SC2_RXCNTB_RESET (0x00000000u) + /* SC_RXCNTB field */ + #define SC_RXCNTB (0x00001FFFu) + #define SC_RXCNTB_MASK (0x00001FFFu) + #define SC_RXCNTB_BIT (0) + #define SC_RXCNTB_BITS (13) + +#define SC2_TXCNT *((volatile int32u *)0x4000C028u) +#define SC2_TXCNT_REG *((volatile int32u *)0x4000C028u) +#define SC2_TXCNT_ADDR (0x4000C028u) +#define SC2_TXCNT_RESET (0x00000000u) + /* SC_TXCNT field */ + #define SC_TXCNT (0x00001FFFu) + #define SC_TXCNT_MASK (0x00001FFFu) + #define SC_TXCNT_BIT (0) + #define SC_TXCNT_BITS (13) + +#define SC2_DMASTAT *((volatile int32u *)0x4000C02Cu) +#define SC2_DMASTAT_REG *((volatile int32u *)0x4000C02Cu) +#define SC2_DMASTAT_ADDR (0x4000C02Cu) +#define SC2_DMASTAT_RESET (0x00000000u) + /* SC_RXSSEL field */ + #define SC_RXSSEL (0x00001C00u) + #define SC_RXSSEL_MASK (0x00001C00u) + #define SC_RXSSEL_BIT (10) + #define SC_RXSSEL_BITS (3) + /* SC_RXOVFB field */ + #define SC_RXOVFB (0x00000020u) + #define SC_RXOVFB_MASK (0x00000020u) + #define SC_RXOVFB_BIT (5) + #define SC_RXOVFB_BITS (1) + /* SC_RXOVFA field */ + #define SC_RXOVFA (0x00000010u) + #define SC_RXOVFA_MASK (0x00000010u) + #define SC_RXOVFA_BIT (4) + #define SC_RXOVFA_BITS (1) + /* SC_TXACTB field */ + #define SC_TXACTB (0x00000008u) + #define SC_TXACTB_MASK (0x00000008u) + #define SC_TXACTB_BIT (3) + #define SC_TXACTB_BITS (1) + /* SC_TXACTA field */ + #define SC_TXACTA (0x00000004u) + #define SC_TXACTA_MASK (0x00000004u) + #define SC_TXACTA_BIT (2) + #define SC_TXACTA_BITS (1) + /* SC_RXACTB field */ + #define SC_RXACTB (0x00000002u) + #define SC_RXACTB_MASK (0x00000002u) + #define SC_RXACTB_BIT (1) + #define SC_RXACTB_BITS (1) + /* SC_RXACTA field */ + #define SC_RXACTA (0x00000001u) + #define SC_RXACTA_MASK (0x00000001u) + #define SC_RXACTA_BIT (0) + #define SC_RXACTA_BITS (1) + +#define SC2_DMACTRL *((volatile int32u *)0x4000C030u) +#define SC2_DMACTRL_REG *((volatile int32u *)0x4000C030u) +#define SC2_DMACTRL_ADDR (0x4000C030u) +#define SC2_DMACTRL_RESET (0x00000000u) + /* SC_TXDMARST field */ + #define SC_TXDMARST (0x00000020u) + #define SC_TXDMARST_MASK (0x00000020u) + #define SC_TXDMARST_BIT (5) + #define SC_TXDMARST_BITS (1) + /* SC_RXDMARST field */ + #define SC_RXDMARST (0x00000010u) + #define SC_RXDMARST_MASK (0x00000010u) + #define SC_RXDMARST_BIT (4) + #define SC_RXDMARST_BITS (1) + /* SC_TXLODB field */ + #define SC_TXLODB (0x00000008u) + #define SC_TXLODB_MASK (0x00000008u) + #define SC_TXLODB_BIT (3) + #define SC_TXLODB_BITS (1) + /* SC_TXLODA field */ + #define SC_TXLODA (0x00000004u) + #define SC_TXLODA_MASK (0x00000004u) + #define SC_TXLODA_BIT (2) + #define SC_TXLODA_BITS (1) + /* SC_RXLODB field */ + #define SC_RXLODB (0x00000002u) + #define SC_RXLODB_MASK (0x00000002u) + #define SC_RXLODB_BIT (1) + #define SC_RXLODB_BITS (1) + /* SC_RXLODA field */ + #define SC_RXLODA (0x00000001u) + #define SC_RXLODA_MASK (0x00000001u) + #define SC_RXLODA_BIT (0) + #define SC_RXLODA_BITS (1) + +#define SC2_RXERRA *((volatile int32u *)0x4000C034u) +#define SC2_RXERRA_REG *((volatile int32u *)0x4000C034u) +#define SC2_RXERRA_ADDR (0x4000C034u) +#define SC2_RXERRA_RESET (0x00000000u) + /* SC_RXERRA field */ + #define SC_RXERRA (0x00001FFFu) + #define SC_RXERRA_MASK (0x00001FFFu) + #define SC_RXERRA_BIT (0) + #define SC_RXERRA_BITS (13) + +#define SC2_RXERRB *((volatile int32u *)0x4000C038u) +#define SC2_RXERRB_REG *((volatile int32u *)0x4000C038u) +#define SC2_RXERRB_ADDR (0x4000C038u) +#define SC2_RXERRB_RESET (0x00000000u) + /* SC_RXERRB field */ + #define SC_RXERRB (0x00001FFFu) + #define SC_RXERRB_MASK (0x00001FFFu) + #define SC_RXERRB_BIT (0) + #define SC_RXERRB_BITS (13) + +#define SC2_DATA *((volatile int32u *)0x4000C03Cu) +#define SC2_DATA_REG *((volatile int32u *)0x4000C03Cu) +#define SC2_DATA_ADDR (0x4000C03Cu) +#define SC2_DATA_RESET (0x00000000u) + /* SC_DATA field */ + #define SC_DATA (0x000000FFu) + #define SC_DATA_MASK (0x000000FFu) + #define SC_DATA_BIT (0) + #define SC_DATA_BITS (8) + +#define SC2_SPISTAT *((volatile int32u *)0x4000C040u) +#define SC2_SPISTAT_REG *((volatile int32u *)0x4000C040u) +#define SC2_SPISTAT_ADDR (0x4000C040u) +#define SC2_SPISTAT_RESET (0x00000000u) + /* SC_SPITXIDLE field */ + #define SC_SPITXIDLE (0x00000008u) + #define SC_SPITXIDLE_MASK (0x00000008u) + #define SC_SPITXIDLE_BIT (3) + #define SC_SPITXIDLE_BITS (1) + /* SC_SPITXFREE field */ + #define SC_SPITXFREE (0x00000004u) + #define SC_SPITXFREE_MASK (0x00000004u) + #define SC_SPITXFREE_BIT (2) + #define SC_SPITXFREE_BITS (1) + /* SC_SPIRXVAL field */ + #define SC_SPIRXVAL (0x00000002u) + #define SC_SPIRXVAL_MASK (0x00000002u) + #define SC_SPIRXVAL_BIT (1) + #define SC_SPIRXVAL_BITS (1) + /* SC_SPIRXOVF field */ + #define SC_SPIRXOVF (0x00000001u) + #define SC_SPIRXOVF_MASK (0x00000001u) + #define SC_SPIRXOVF_BIT (0) + #define SC_SPIRXOVF_BITS (1) + +#define SC2_TWISTAT *((volatile int32u *)0x4000C044u) +#define SC2_TWISTAT_REG *((volatile int32u *)0x4000C044u) +#define SC2_TWISTAT_ADDR (0x4000C044u) +#define SC2_TWISTAT_RESET (0x00000000u) + /* SC_TWICMDFIN field */ + #define SC_TWICMDFIN (0x00000008u) + #define SC_TWICMDFIN_MASK (0x00000008u) + #define SC_TWICMDFIN_BIT (3) + #define SC_TWICMDFIN_BITS (1) + /* SC_TWIRXFIN field */ + #define SC_TWIRXFIN (0x00000004u) + #define SC_TWIRXFIN_MASK (0x00000004u) + #define SC_TWIRXFIN_BIT (2) + #define SC_TWIRXFIN_BITS (1) + /* SC_TWITXFIN field */ + #define SC_TWITXFIN (0x00000002u) + #define SC_TWITXFIN_MASK (0x00000002u) + #define SC_TWITXFIN_BIT (1) + #define SC_TWITXFIN_BITS (1) + /* SC_TWIRXNAK field */ + #define SC_TWIRXNAK (0x00000001u) + #define SC_TWIRXNAK_MASK (0x00000001u) + #define SC_TWIRXNAK_BIT (0) + #define SC_TWIRXNAK_BITS (1) + +#define SC2_TWICTRL1 *((volatile int32u *)0x4000C04Cu) +#define SC2_TWICTRL1_REG *((volatile int32u *)0x4000C04Cu) +#define SC2_TWICTRL1_ADDR (0x4000C04Cu) +#define SC2_TWICTRL1_RESET (0x00000000u) + /* SC_TWISTOP field */ + #define SC_TWISTOP (0x00000008u) + #define SC_TWISTOP_MASK (0x00000008u) + #define SC_TWISTOP_BIT (3) + #define SC_TWISTOP_BITS (1) + /* SC_TWISTART field */ + #define SC_TWISTART (0x00000004u) + #define SC_TWISTART_MASK (0x00000004u) + #define SC_TWISTART_BIT (2) + #define SC_TWISTART_BITS (1) + /* SC_TWISEND field */ + #define SC_TWISEND (0x00000002u) + #define SC_TWISEND_MASK (0x00000002u) + #define SC_TWISEND_BIT (1) + #define SC_TWISEND_BITS (1) + /* SC_TWIRECV field */ + #define SC_TWIRECV (0x00000001u) + #define SC_TWIRECV_MASK (0x00000001u) + #define SC_TWIRECV_BIT (0) + #define SC_TWIRECV_BITS (1) + +#define SC2_TWICTRL2 *((volatile int32u *)0x4000C050u) +#define SC2_TWICTRL2_REG *((volatile int32u *)0x4000C050u) +#define SC2_TWICTRL2_ADDR (0x4000C050u) +#define SC2_TWICTRL2_RESET (0x00000000u) + /* SC_TWIACK field */ + #define SC_TWIACK (0x00000001u) + #define SC_TWIACK_MASK (0x00000001u) + #define SC_TWIACK_BIT (0) + #define SC_TWIACK_BITS (1) + +#define SC2_MODE *((volatile int32u *)0x4000C054u) +#define SC2_MODE_REG *((volatile int32u *)0x4000C054u) +#define SC2_MODE_ADDR (0x4000C054u) +#define SC2_MODE_RESET (0x00000000u) + /* SC_MODE field */ + #define SC_MODE (0x00000003u) + #define SC_MODE_MASK (0x00000003u) + #define SC_MODE_BIT (0) + #define SC_MODE_BITS (2) + /* SC_MODE Bit Field Values */ + #define SC2_MODE_DISABLED (0) + #define SC2_MODE_SPI (2) + #define SC2_MODE_I2C (3) + +#define SC2_SPICFG *((volatile int32u *)0x4000C058u) +#define SC2_SPICFG_REG *((volatile int32u *)0x4000C058u) +#define SC2_SPICFG_ADDR (0x4000C058u) +#define SC2_SPICFG_RESET (0x00000000u) + /* SC_SPIRXDRV field */ + #define SC_SPIRXDRV (0x00000020u) + #define SC_SPIRXDRV_MASK (0x00000020u) + #define SC_SPIRXDRV_BIT (5) + #define SC_SPIRXDRV_BITS (1) + /* SC_SPIMST field */ + #define SC_SPIMST (0x00000010u) + #define SC_SPIMST_MASK (0x00000010u) + #define SC_SPIMST_BIT (4) + #define SC_SPIMST_BITS (1) + /* SC_SPIRPT field */ + #define SC_SPIRPT (0x00000008u) + #define SC_SPIRPT_MASK (0x00000008u) + #define SC_SPIRPT_BIT (3) + #define SC_SPIRPT_BITS (1) + /* SC_SPIORD field */ + #define SC_SPIORD (0x00000004u) + #define SC_SPIORD_MASK (0x00000004u) + #define SC_SPIORD_BIT (2) + #define SC_SPIORD_BITS (1) + /* SC_SPIPHA field */ + #define SC_SPIPHA (0x00000002u) + #define SC_SPIPHA_MASK (0x00000002u) + #define SC_SPIPHA_BIT (1) + #define SC_SPIPHA_BITS (1) + /* SC_SPIPOL field */ + #define SC_SPIPOL (0x00000001u) + #define SC_SPIPOL_MASK (0x00000001u) + #define SC_SPIPOL_BIT (0) + #define SC_SPIPOL_BITS (1) + +#define SC2_RATELIN *((volatile int32u *)0x4000C060u) +#define SC2_RATELIN_REG *((volatile int32u *)0x4000C060u) +#define SC2_RATELIN_ADDR (0x4000C060u) +#define SC2_RATELIN_RESET (0x00000000u) + /* SC_RATELIN field */ + #define SC_RATELIN (0x0000000Fu) + #define SC_RATELIN_MASK (0x0000000Fu) + #define SC_RATELIN_BIT (0) + #define SC_RATELIN_BITS (4) + +#define SC2_RATEEXP *((volatile int32u *)0x4000C064u) +#define SC2_RATEEXP_REG *((volatile int32u *)0x4000C064u) +#define SC2_RATEEXP_ADDR (0x4000C064u) +#define SC2_RATEEXP_RESET (0x00000000u) + /* SC_RATEEXP field */ + #define SC_RATEEXP (0x0000000Fu) + #define SC_RATEEXP_MASK (0x0000000Fu) + #define SC_RATEEXP_BIT (0) + #define SC_RATEEXP_BITS (4) + +#define SC2_RXCNTSAVED *((volatile int32u *)0x4000C070u) +#define SC2_RXCNTSAVED_REG *((volatile int32u *)0x4000C070u) +#define SC2_RXCNTSAVED_ADDR (0x4000C070u) +#define SC2_RXCNTSAVED_RESET (0x00000000u) + /* SC_RXCNTSAVED field */ + #define SC_RXCNTSAVED (0x00001FFFu) + #define SC_RXCNTSAVED_MASK (0x00001FFFu) + #define SC_RXCNTSAVED_BIT (0) + #define SC_RXCNTSAVED_BITS (13) + +#define SC1_RXBEGA *((volatile int32u *)0x4000C800u) +#define SC1_RXBEGA_REG *((volatile int32u *)0x4000C800u) +#define SC1_RXBEGA_ADDR (0x4000C800u) +#define SC1_RXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXBEGA_FIXED (0xFFFFE000u) + #define SC1_RXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC1_RXBEGA_FIXED_BIT (13) + #define SC1_RXBEGA_FIXED_BITS (19) + /* SC_RXBEGA field */ + #define SC_RXBEGA (0x00001FFFu) + #define SC_RXBEGA_MASK (0x00001FFFu) + #define SC_RXBEGA_BIT (0) + #define SC_RXBEGA_BITS (13) + +#define SC1_RXENDA *((volatile int32u *)0x4000C804u) +#define SC1_RXENDA_REG *((volatile int32u *)0x4000C804u) +#define SC1_RXENDA_ADDR (0x4000C804u) +#define SC1_RXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXENDA_FIXED (0xFFFFE000u) + #define SC1_RXENDA_FIXED_MASK (0xFFFFE000u) + #define SC1_RXENDA_FIXED_BIT (13) + #define SC1_RXENDA_FIXED_BITS (19) + /* SC_RXENDA field */ + #define SC_RXENDA (0x00001FFFu) + #define SC_RXENDA_MASK (0x00001FFFu) + #define SC_RXENDA_BIT (0) + #define SC_RXENDA_BITS (13) + +#define SC1_RXBEGB *((volatile int32u *)0x4000C808u) +#define SC1_RXBEGB_REG *((volatile int32u *)0x4000C808u) +#define SC1_RXBEGB_ADDR (0x4000C808u) +#define SC1_RXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXBEGB_FIXED (0xFFFFE000u) + #define SC1_RXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC1_RXBEGB_FIXED_BIT (13) + #define SC1_RXBEGB_FIXED_BITS (19) + /* SC_RXBEGB field */ + #define SC_RXBEGB (0x00001FFFu) + #define SC_RXBEGB_MASK (0x00001FFFu) + #define SC_RXBEGB_BIT (0) + #define SC_RXBEGB_BITS (13) + +#define SC1_RXENDB *((volatile int32u *)0x4000C80Cu) +#define SC1_RXENDB_REG *((volatile int32u *)0x4000C80Cu) +#define SC1_RXENDB_ADDR (0x4000C80Cu) +#define SC1_RXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXENDB_FIXED (0xFFFFE000u) + #define SC1_RXENDB_FIXED_MASK (0xFFFFE000u) + #define SC1_RXENDB_FIXED_BIT (13) + #define SC1_RXENDB_FIXED_BITS (19) + /* SC_RXENDB field */ + #define SC_RXENDB (0x00001FFFu) + #define SC_RXENDB_MASK (0x00001FFFu) + #define SC_RXENDB_BIT (0) + #define SC_RXENDB_BITS (13) + +#define SC1_TXBEGA *((volatile int32u *)0x4000C810u) +#define SC1_TXBEGA_REG *((volatile int32u *)0x4000C810u) +#define SC1_TXBEGA_ADDR (0x4000C810u) +#define SC1_TXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXBEGA_FIXED (0xFFFFE000u) + #define SC1_TXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC1_TXBEGA_FIXED_BIT (13) + #define SC1_TXBEGA_FIXED_BITS (19) + /* SC_TXBEGA field */ + #define SC_TXBEGA (0x00001FFFu) + #define SC_TXBEGA_MASK (0x00001FFFu) + #define SC_TXBEGA_BIT (0) + #define SC_TXBEGA_BITS (13) + +#define SC1_TXENDA *((volatile int32u *)0x4000C814u) +#define SC1_TXENDA_REG *((volatile int32u *)0x4000C814u) +#define SC1_TXENDA_ADDR (0x4000C814u) +#define SC1_TXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXENDA_FIXED (0xFFFFE000u) + #define SC1_TXENDA_FIXED_MASK (0xFFFFE000u) + #define SC1_TXENDA_FIXED_BIT (13) + #define SC1_TXENDA_FIXED_BITS (19) + /* SC_TXENDA field */ + #define SC_TXENDA (0x00001FFFu) + #define SC_TXENDA_MASK (0x00001FFFu) + #define SC_TXENDA_BIT (0) + #define SC_TXENDA_BITS (13) + +#define SC1_TXBEGB *((volatile int32u *)0x4000C818u) +#define SC1_TXBEGB_REG *((volatile int32u *)0x4000C818u) +#define SC1_TXBEGB_ADDR (0x4000C818u) +#define SC1_TXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXBEGB_FIXED (0xFFFFE000u) + #define SC1_TXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC1_TXBEGB_FIXED_BIT (13) + #define SC1_TXBEGB_FIXED_BITS (19) + /* SC_TXBEGB field */ + #define SC_TXBEGB (0x00001FFFu) + #define SC_TXBEGB_MASK (0x00001FFFu) + #define SC_TXBEGB_BIT (0) + #define SC_TXBEGB_BITS (13) + +#define SC1_TXENDB *((volatile int32u *)0x4000C81Cu) +#define SC1_TXENDB_REG *((volatile int32u *)0x4000C81Cu) +#define SC1_TXENDB_ADDR (0x4000C81Cu) +#define SC1_TXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXENDB_FIXED (0xFFFFE000u) + #define SC1_TXENDB_FIXED_MASK (0xFFFFE000u) + #define SC1_TXENDB_FIXED_BIT (13) + #define SC1_TXENDB_FIXED_BITS (19) + /* SC_TXENDB field */ + #define SC_TXENDB (0x00001FFFu) + #define SC_TXENDB_MASK (0x00001FFFu) + #define SC_TXENDB_BIT (0) + #define SC_TXENDB_BITS (13) + +#define SC1_RXCNTA *((volatile int32u *)0x4000C820u) +#define SC1_RXCNTA_REG *((volatile int32u *)0x4000C820u) +#define SC1_RXCNTA_ADDR (0x4000C820u) +#define SC1_RXCNTA_RESET (0x00000000u) + /* SC_RXCNTA field */ + #define SC_RXCNTA (0x00001FFFu) + #define SC_RXCNTA_MASK (0x00001FFFu) + #define SC_RXCNTA_BIT (0) + #define SC_RXCNTA_BITS (13) + +#define SC1_RXCNTB *((volatile int32u *)0x4000C824u) +#define SC1_RXCNTB_REG *((volatile int32u *)0x4000C824u) +#define SC1_RXCNTB_ADDR (0x4000C824u) +#define SC1_RXCNTB_RESET (0x00000000u) + /* SC_RXCNTB field */ + #define SC_RXCNTB (0x00001FFFu) + #define SC_RXCNTB_MASK (0x00001FFFu) + #define SC_RXCNTB_BIT (0) + #define SC_RXCNTB_BITS (13) + +#define SC1_TXCNT *((volatile int32u *)0x4000C828u) +#define SC1_TXCNT_REG *((volatile int32u *)0x4000C828u) +#define SC1_TXCNT_ADDR (0x4000C828u) +#define SC1_TXCNT_RESET (0x00000000u) + /* SC_TXCNT field */ + #define SC_TXCNT (0x00001FFFu) + #define SC_TXCNT_MASK (0x00001FFFu) + #define SC_TXCNT_BIT (0) + #define SC_TXCNT_BITS (13) + +#define SC1_DMASTAT *((volatile int32u *)0x4000C82Cu) +#define SC1_DMASTAT_REG *((volatile int32u *)0x4000C82Cu) +#define SC1_DMASTAT_ADDR (0x4000C82Cu) +#define SC1_DMASTAT_RESET (0x00000000u) + /* SC_RXSSEL field */ + #define SC_RXSSEL (0x00001C00u) + #define SC_RXSSEL_MASK (0x00001C00u) + #define SC_RXSSEL_BIT (10) + #define SC_RXSSEL_BITS (3) + /* SC_RXFRMB field */ + #define SC_RXFRMB (0x00000200u) + #define SC_RXFRMB_MASK (0x00000200u) + #define SC_RXFRMB_BIT (9) + #define SC_RXFRMB_BITS (1) + /* SC_RXFRMA field */ + #define SC_RXFRMA (0x00000100u) + #define SC_RXFRMA_MASK (0x00000100u) + #define SC_RXFRMA_BIT (8) + #define SC_RXFRMA_BITS (1) + /* SC_RXPARB field */ + #define SC_RXPARB (0x00000080u) + #define SC_RXPARB_MASK (0x00000080u) + #define SC_RXPARB_BIT (7) + #define SC_RXPARB_BITS (1) + /* SC_RXPARA field */ + #define SC_RXPARA (0x00000040u) + #define SC_RXPARA_MASK (0x00000040u) + #define SC_RXPARA_BIT (6) + #define SC_RXPARA_BITS (1) + /* SC_RXOVFB field */ + #define SC_RXOVFB (0x00000020u) + #define SC_RXOVFB_MASK (0x00000020u) + #define SC_RXOVFB_BIT (5) + #define SC_RXOVFB_BITS (1) + /* SC_RXOVFA field */ + #define SC_RXOVFA (0x00000010u) + #define SC_RXOVFA_MASK (0x00000010u) + #define SC_RXOVFA_BIT (4) + #define SC_RXOVFA_BITS (1) + /* SC_TXACTB field */ + #define SC_TXACTB (0x00000008u) + #define SC_TXACTB_MASK (0x00000008u) + #define SC_TXACTB_BIT (3) + #define SC_TXACTB_BITS (1) + /* SC_TXACTA field */ + #define SC_TXACTA (0x00000004u) + #define SC_TXACTA_MASK (0x00000004u) + #define SC_TXACTA_BIT (2) + #define SC_TXACTA_BITS (1) + /* SC_RXACTB field */ + #define SC_RXACTB (0x00000002u) + #define SC_RXACTB_MASK (0x00000002u) + #define SC_RXACTB_BIT (1) + #define SC_RXACTB_BITS (1) + /* SC_RXACTA field */ + #define SC_RXACTA (0x00000001u) + #define SC_RXACTA_MASK (0x00000001u) + #define SC_RXACTA_BIT (0) + #define SC_RXACTA_BITS (1) + +#define SC1_DMACTRL *((volatile int32u *)0x4000C830u) +#define SC1_DMACTRL_REG *((volatile int32u *)0x4000C830u) +#define SC1_DMACTRL_ADDR (0x4000C830u) +#define SC1_DMACTRL_RESET (0x00000000u) + /* SC_TXDMARST field */ + #define SC_TXDMARST (0x00000020u) + #define SC_TXDMARST_MASK (0x00000020u) + #define SC_TXDMARST_BIT (5) + #define SC_TXDMARST_BITS (1) + /* SC_RXDMARST field */ + #define SC_RXDMARST (0x00000010u) + #define SC_RXDMARST_MASK (0x00000010u) + #define SC_RXDMARST_BIT (4) + #define SC_RXDMARST_BITS (1) + /* SC_TXLODB field */ + #define SC_TXLODB (0x00000008u) + #define SC_TXLODB_MASK (0x00000008u) + #define SC_TXLODB_BIT (3) + #define SC_TXLODB_BITS (1) + /* SC_TXLODA field */ + #define SC_TXLODA (0x00000004u) + #define SC_TXLODA_MASK (0x00000004u) + #define SC_TXLODA_BIT (2) + #define SC_TXLODA_BITS (1) + /* SC_RXLODB field */ + #define SC_RXLODB (0x00000002u) + #define SC_RXLODB_MASK (0x00000002u) + #define SC_RXLODB_BIT (1) + #define SC_RXLODB_BITS (1) + /* SC_RXLODA field */ + #define SC_RXLODA (0x00000001u) + #define SC_RXLODA_MASK (0x00000001u) + #define SC_RXLODA_BIT (0) + #define SC_RXLODA_BITS (1) + +#define SC1_RXERRA *((volatile int32u *)0x4000C834u) +#define SC1_RXERRA_REG *((volatile int32u *)0x4000C834u) +#define SC1_RXERRA_ADDR (0x4000C834u) +#define SC1_RXERRA_RESET (0x00000000u) + /* SC_RXERRA field */ + #define SC_RXERRA (0x00001FFFu) + #define SC_RXERRA_MASK (0x00001FFFu) + #define SC_RXERRA_BIT (0) + #define SC_RXERRA_BITS (13) + +#define SC1_RXERRB *((volatile int32u *)0x4000C838u) +#define SC1_RXERRB_REG *((volatile int32u *)0x4000C838u) +#define SC1_RXERRB_ADDR (0x4000C838u) +#define SC1_RXERRB_RESET (0x00000000u) + /* SC_RXERRB field */ + #define SC_RXERRB (0x00001FFFu) + #define SC_RXERRB_MASK (0x00001FFFu) + #define SC_RXERRB_BIT (0) + #define SC_RXERRB_BITS (13) + +#define SC1_DATA *((volatile int32u *)0x4000C83Cu) +#define SC1_DATA_REG *((volatile int32u *)0x4000C83Cu) +#define SC1_DATA_ADDR (0x4000C83Cu) +#define SC1_DATA_RESET (0x00000000u) + /* SC_DATA field */ + #define SC_DATA (0x000000FFu) + #define SC_DATA_MASK (0x000000FFu) + #define SC_DATA_BIT (0) + #define SC_DATA_BITS (8) + +#define SC1_SPISTAT *((volatile int32u *)0x4000C840u) +#define SC1_SPISTAT_REG *((volatile int32u *)0x4000C840u) +#define SC1_SPISTAT_ADDR (0x4000C840u) +#define SC1_SPISTAT_RESET (0x00000000u) + /* SC_SPITXIDLE field */ + #define SC_SPITXIDLE (0x00000008u) + #define SC_SPITXIDLE_MASK (0x00000008u) + #define SC_SPITXIDLE_BIT (3) + #define SC_SPITXIDLE_BITS (1) + /* SC_SPITXFREE field */ + #define SC_SPITXFREE (0x00000004u) + #define SC_SPITXFREE_MASK (0x00000004u) + #define SC_SPITXFREE_BIT (2) + #define SC_SPITXFREE_BITS (1) + /* SC_SPIRXVAL field */ + #define SC_SPIRXVAL (0x00000002u) + #define SC_SPIRXVAL_MASK (0x00000002u) + #define SC_SPIRXVAL_BIT (1) + #define SC_SPIRXVAL_BITS (1) + /* SC_SPIRXOVF field */ + #define SC_SPIRXOVF (0x00000001u) + #define SC_SPIRXOVF_MASK (0x00000001u) + #define SC_SPIRXOVF_BIT (0) + #define SC_SPIRXOVF_BITS (1) + +#define SC1_TWISTAT *((volatile int32u *)0x4000C844u) +#define SC1_TWISTAT_REG *((volatile int32u *)0x4000C844u) +#define SC1_TWISTAT_ADDR (0x4000C844u) +#define SC1_TWISTAT_RESET (0x00000000u) + /* SC_TWICMDFIN field */ + #define SC_TWICMDFIN (0x00000008u) + #define SC_TWICMDFIN_MASK (0x00000008u) + #define SC_TWICMDFIN_BIT (3) + #define SC_TWICMDFIN_BITS (1) + /* SC_TWIRXFIN field */ + #define SC_TWIRXFIN (0x00000004u) + #define SC_TWIRXFIN_MASK (0x00000004u) + #define SC_TWIRXFIN_BIT (2) + #define SC_TWIRXFIN_BITS (1) + /* SC_TWITXFIN field */ + #define SC_TWITXFIN (0x00000002u) + #define SC_TWITXFIN_MASK (0x00000002u) + #define SC_TWITXFIN_BIT (1) + #define SC_TWITXFIN_BITS (1) + /* SC_TWIRXNAK field */ + #define SC_TWIRXNAK (0x00000001u) + #define SC_TWIRXNAK_MASK (0x00000001u) + #define SC_TWIRXNAK_BIT (0) + #define SC_TWIRXNAK_BITS (1) + +#define SC1_UARTSTAT *((volatile int32u *)0x4000C848u) +#define SC1_UARTSTAT_REG *((volatile int32u *)0x4000C848u) +#define SC1_UARTSTAT_ADDR (0x4000C848u) +#define SC1_UARTSTAT_RESET (0x00000040u) + /* SC_UARTTXIDLE field */ + #define SC_UARTTXIDLE (0x00000040u) + #define SC_UARTTXIDLE_MASK (0x00000040u) + #define SC_UARTTXIDLE_BIT (6) + #define SC_UARTTXIDLE_BITS (1) + /* SC_UARTPARERR field */ + #define SC_UARTPARERR (0x00000020u) + #define SC_UARTPARERR_MASK (0x00000020u) + #define SC_UARTPARERR_BIT (5) + #define SC_UARTPARERR_BITS (1) + /* SC_UARTFRMERR field */ + #define SC_UARTFRMERR (0x00000010u) + #define SC_UARTFRMERR_MASK (0x00000010u) + #define SC_UARTFRMERR_BIT (4) + #define SC_UARTFRMERR_BITS (1) + /* SC_UARTRXOVF field */ + #define SC_UARTRXOVF (0x00000008u) + #define SC_UARTRXOVF_MASK (0x00000008u) + #define SC_UARTRXOVF_BIT (3) + #define SC_UARTRXOVF_BITS (1) + /* SC_UARTTXFREE field */ + #define SC_UARTTXFREE (0x00000004u) + #define SC_UARTTXFREE_MASK (0x00000004u) + #define SC_UARTTXFREE_BIT (2) + #define SC_UARTTXFREE_BITS (1) + /* SC_UARTRXVAL field */ + #define SC_UARTRXVAL (0x00000002u) + #define SC_UARTRXVAL_MASK (0x00000002u) + #define SC_UARTRXVAL_BIT (1) + #define SC_UARTRXVAL_BITS (1) + /* SC_UARTCTS field */ + #define SC_UARTCTS (0x00000001u) + #define SC_UARTCTS_MASK (0x00000001u) + #define SC_UARTCTS_BIT (0) + #define SC_UARTCTS_BITS (1) + +#define SC1_TWICTRL1 *((volatile int32u *)0x4000C84Cu) +#define SC1_TWICTRL1_REG *((volatile int32u *)0x4000C84Cu) +#define SC1_TWICTRL1_ADDR (0x4000C84Cu) +#define SC1_TWICTRL1_RESET (0x00000000u) + /* SC_TWISTOP field */ + #define SC_TWISTOP (0x00000008u) + #define SC_TWISTOP_MASK (0x00000008u) + #define SC_TWISTOP_BIT (3) + #define SC_TWISTOP_BITS (1) + /* SC_TWISTART field */ + #define SC_TWISTART (0x00000004u) + #define SC_TWISTART_MASK (0x00000004u) + #define SC_TWISTART_BIT (2) + #define SC_TWISTART_BITS (1) + /* SC_TWISEND field */ + #define SC_TWISEND (0x00000002u) + #define SC_TWISEND_MASK (0x00000002u) + #define SC_TWISEND_BIT (1) + #define SC_TWISEND_BITS (1) + /* SC_TWIRECV field */ + #define SC_TWIRECV (0x00000001u) + #define SC_TWIRECV_MASK (0x00000001u) + #define SC_TWIRECV_BIT (0) + #define SC_TWIRECV_BITS (1) + +#define SC1_TWICTRL2 *((volatile int32u *)0x4000C850u) +#define SC1_TWICTRL2_REG *((volatile int32u *)0x4000C850u) +#define SC1_TWICTRL2_ADDR (0x4000C850u) +#define SC1_TWICTRL2_RESET (0x00000000u) + /* SC_TWIACK field */ + #define SC_TWIACK (0x00000001u) + #define SC_TWIACK_MASK (0x00000001u) + #define SC_TWIACK_BIT (0) + #define SC_TWIACK_BITS (1) + +#define SC1_MODE *((volatile int32u *)0x4000C854u) +#define SC1_MODE_REG *((volatile int32u *)0x4000C854u) +#define SC1_MODE_ADDR (0x4000C854u) +#define SC1_MODE_RESET (0x00000000u) + /* SC_MODE field */ + #define SC_MODE (0x00000003u) + #define SC_MODE_MASK (0x00000003u) + #define SC_MODE_BIT (0) + #define SC_MODE_BITS (2) + /* SC_MODE Bit Field Values */ + #define SC1_MODE_DISABLED (0) + #define SC1_MODE_UART (1) + #define SC1_MODE_SPI (2) + #define SC1_MODE_I2C (3) + +#define SC1_SPICFG *((volatile int32u *)0x4000C858u) +#define SC1_SPICFG_REG *((volatile int32u *)0x4000C858u) +#define SC1_SPICFG_ADDR (0x4000C858u) +#define SC1_SPICFG_RESET (0x00000000u) + /* SC_SPIRXDRV field */ + #define SC_SPIRXDRV (0x00000020u) + #define SC_SPIRXDRV_MASK (0x00000020u) + #define SC_SPIRXDRV_BIT (5) + #define SC_SPIRXDRV_BITS (1) + /* SC_SPIMST field */ + #define SC_SPIMST (0x00000010u) + #define SC_SPIMST_MASK (0x00000010u) + #define SC_SPIMST_BIT (4) + #define SC_SPIMST_BITS (1) + /* SC_SPIRPT field */ + #define SC_SPIRPT (0x00000008u) + #define SC_SPIRPT_MASK (0x00000008u) + #define SC_SPIRPT_BIT (3) + #define SC_SPIRPT_BITS (1) + /* SC_SPIORD field */ + #define SC_SPIORD (0x00000004u) + #define SC_SPIORD_MASK (0x00000004u) + #define SC_SPIORD_BIT (2) + #define SC_SPIORD_BITS (1) + /* SC_SPIPHA field */ + #define SC_SPIPHA (0x00000002u) + #define SC_SPIPHA_MASK (0x00000002u) + #define SC_SPIPHA_BIT (1) + #define SC_SPIPHA_BITS (1) + /* SC_SPIPOL field */ + #define SC_SPIPOL (0x00000001u) + #define SC_SPIPOL_MASK (0x00000001u) + #define SC_SPIPOL_BIT (0) + #define SC_SPIPOL_BITS (1) + +#define SC1_UARTCFG *((volatile int32u *)0x4000C85Cu) +#define SC1_UARTCFG_REG *((volatile int32u *)0x4000C85Cu) +#define SC1_UARTCFG_ADDR (0x4000C85Cu) +#define SC1_UARTCFG_RESET (0x00000000u) + /* SC_UARTAUTO field */ + #define SC_UARTAUTO (0x00000040u) + #define SC_UARTAUTO_MASK (0x00000040u) + #define SC_UARTAUTO_BIT (6) + #define SC_UARTAUTO_BITS (1) + /* SC_UARTFLOW field */ + #define SC_UARTFLOW (0x00000020u) + #define SC_UARTFLOW_MASK (0x00000020u) + #define SC_UARTFLOW_BIT (5) + #define SC_UARTFLOW_BITS (1) + /* SC_UARTODD field */ + #define SC_UARTODD (0x00000010u) + #define SC_UARTODD_MASK (0x00000010u) + #define SC_UARTODD_BIT (4) + #define SC_UARTODD_BITS (1) + /* SC_UARTPAR field */ + #define SC_UARTPAR (0x00000008u) + #define SC_UARTPAR_MASK (0x00000008u) + #define SC_UARTPAR_BIT (3) + #define SC_UARTPAR_BITS (1) + /* SC_UART2STP field */ + #define SC_UART2STP (0x00000004u) + #define SC_UART2STP_MASK (0x00000004u) + #define SC_UART2STP_BIT (2) + #define SC_UART2STP_BITS (1) + /* SC_UART8BIT field */ + #define SC_UART8BIT (0x00000002u) + #define SC_UART8BIT_MASK (0x00000002u) + #define SC_UART8BIT_BIT (1) + #define SC_UART8BIT_BITS (1) + /* SC_UARTRTS field */ + #define SC_UARTRTS (0x00000001u) + #define SC_UARTRTS_MASK (0x00000001u) + #define SC_UARTRTS_BIT (0) + #define SC_UARTRTS_BITS (1) + +#define SC1_RATELIN *((volatile int32u *)0x4000C860u) +#define SC1_RATELIN_REG *((volatile int32u *)0x4000C860u) +#define SC1_RATELIN_ADDR (0x4000C860u) +#define SC1_RATELIN_RESET (0x00000000u) + /* SC_RATELIN field */ + #define SC_RATELIN (0x0000000Fu) + #define SC_RATELIN_MASK (0x0000000Fu) + #define SC_RATELIN_BIT (0) + #define SC_RATELIN_BITS (4) + +#define SC1_RATEEXP *((volatile int32u *)0x4000C864u) +#define SC1_RATEEXP_REG *((volatile int32u *)0x4000C864u) +#define SC1_RATEEXP_ADDR (0x4000C864u) +#define SC1_RATEEXP_RESET (0x00000000u) + /* SC_RATEEXP field */ + #define SC_RATEEXP (0x0000000Fu) + #define SC_RATEEXP_MASK (0x0000000Fu) + #define SC_RATEEXP_BIT (0) + #define SC_RATEEXP_BITS (4) + +#define SC1_UARTPER *((volatile int32u *)0x4000C868u) +#define SC1_UARTPER_REG *((volatile int32u *)0x4000C868u) +#define SC1_UARTPER_ADDR (0x4000C868u) +#define SC1_UARTPER_RESET (0x00000000u) + /* SC_UARTPER field */ + #define SC_UARTPER (0x0000FFFFu) + #define SC_UARTPER_MASK (0x0000FFFFu) + #define SC_UARTPER_BIT (0) + #define SC_UARTPER_BITS (16) + +#define SC1_UARTFRAC *((volatile int32u *)0x4000C86Cu) +#define SC1_UARTFRAC_REG *((volatile int32u *)0x4000C86Cu) +#define SC1_UARTFRAC_ADDR (0x4000C86Cu) +#define SC1_UARTFRAC_RESET (0x00000000u) + /* SC_UARTFRAC field */ + #define SC_UARTFRAC (0x00000001u) + #define SC_UARTFRAC_MASK (0x00000001u) + #define SC_UARTFRAC_BIT (0) + #define SC_UARTFRAC_BITS (1) + +#define SC1_RXCNTSAVED *((volatile int32u *)0x4000C870u) +#define SC1_RXCNTSAVED_REG *((volatile int32u *)0x4000C870u) +#define SC1_RXCNTSAVED_ADDR (0x4000C870u) +#define SC1_RXCNTSAVED_RESET (0x00000000u) + /* SC_RXCNTSAVED field */ + #define SC_RXCNTSAVED (0x00001FFFu) + #define SC_RXCNTSAVED_MASK (0x00001FFFu) + #define SC_RXCNTSAVED_BIT (0) + #define SC_RXCNTSAVED_BITS (13) + +/* ADC block */ +#define BLOCK_ADC_BASE (0x4000D000u) +#define BLOCK_ADC_END (0x4000D024u) +#define BLOCK_ADC_SIZE (BLOCK_ADC_END - BLOCK_ADC_BASE + 1) + +#define ADC_DATA *((volatile int32u *)0x4000D000u) +#define ADC_DATA_REG *((volatile int32u *)0x4000D000u) +#define ADC_DATA_ADDR (0x4000D000u) +#define ADC_DATA_RESET (0x00000000u) + /* ADC_DATA_FIELD field */ + #define ADC_DATA_FIELD (0x0000FFFFu) + #define ADC_DATA_FIELD_MASK (0x0000FFFFu) + #define ADC_DATA_FIELD_BIT (0) + #define ADC_DATA_FIELD_BITS (16) + +#define ADC_CFG *((volatile int32u *)0x4000D004u) +#define ADC_CFG_REG *((volatile int32u *)0x4000D004u) +#define ADC_CFG_ADDR (0x4000D004u) +#define ADC_CFG_RESET (0x00001800u) + /* ADC_PERIOD field */ + #define ADC_PERIOD (0x0000E000u) + #define ADC_PERIOD_MASK (0x0000E000u) + #define ADC_PERIOD_BIT (13) + #define ADC_PERIOD_BITS (3) + /* ADC_HVSELP field */ + #define ADC_HVSELP (0x00001000u) + #define ADC_HVSELP_MASK (0x00001000u) + #define ADC_HVSELP_BIT (12) + #define ADC_HVSELP_BITS (1) + /* ADC_HVSELN field */ + #define ADC_HVSELN (0x00000800u) + #define ADC_HVSELN_MASK (0x00000800u) + #define ADC_HVSELN_BIT (11) + #define ADC_HVSELN_BITS (1) + /* ADC_MUXP field */ + #define ADC_MUXP (0x00000780u) + #define ADC_MUXP_MASK (0x00000780u) + #define ADC_MUXP_BIT (7) + #define ADC_MUXP_BITS (4) + /* ADC_MUXN field */ + #define ADC_MUXN (0x00000078u) + #define ADC_MUXN_MASK (0x00000078u) + #define ADC_MUXN_BIT (3) + #define ADC_MUXN_BITS (4) + /* ADC_1MHZCLK field */ + #define ADC_1MHZCLK (0x00000004u) + #define ADC_1MHZCLK_MASK (0x00000004u) + #define ADC_1MHZCLK_BIT (2) + #define ADC_1MHZCLK_BITS (1) + /* ADC_CFGRSVD field */ + #define ADC_CFGRSVD (0x00000002u) + #define ADC_CFGRSVD_MASK (0x00000002u) + #define ADC_CFGRSVD_BIT (1) + #define ADC_CFGRSVD_BITS (1) + /* ADC_ENABLE field */ + #define ADC_ENABLE (0x00000001u) + #define ADC_ENABLE_MASK (0x00000001u) + #define ADC_ENABLE_BIT (0) + #define ADC_ENABLE_BITS (1) + +#define ADC_OFFSET *((volatile int32u *)0x4000D008u) +#define ADC_OFFSET_REG *((volatile int32u *)0x4000D008u) +#define ADC_OFFSET_ADDR (0x4000D008u) +#define ADC_OFFSET_RESET (0x00000000u) + /* ADC_OFFSET_FIELD field */ + #define ADC_OFFSET_FIELD (0x0000FFFFu) + #define ADC_OFFSET_FIELD_MASK (0x0000FFFFu) + #define ADC_OFFSET_FIELD_BIT (0) + #define ADC_OFFSET_FIELD_BITS (16) + +#define ADC_GAIN *((volatile int32u *)0x4000D00Cu) +#define ADC_GAIN_REG *((volatile int32u *)0x4000D00Cu) +#define ADC_GAIN_ADDR (0x4000D00Cu) +#define ADC_GAIN_RESET (0x00008000u) + /* ADC_GAIN_FIELD field */ + #define ADC_GAIN_FIELD (0x0000FFFFu) + #define ADC_GAIN_FIELD_MASK (0x0000FFFFu) + #define ADC_GAIN_FIELD_BIT (0) + #define ADC_GAIN_FIELD_BITS (16) + +#define ADC_DMACFG *((volatile int32u *)0x4000D010u) +#define ADC_DMACFG_REG *((volatile int32u *)0x4000D010u) +#define ADC_DMACFG_ADDR (0x4000D010u) +#define ADC_DMACFG_RESET (0x00000000u) + /* ADC_DMARST field */ + #define ADC_DMARST (0x00000010u) + #define ADC_DMARST_MASK (0x00000010u) + #define ADC_DMARST_BIT (4) + #define ADC_DMARST_BITS (1) + /* ADC_DMAAUTOWRAP field */ + #define ADC_DMAAUTOWRAP (0x00000002u) + #define ADC_DMAAUTOWRAP_MASK (0x00000002u) + #define ADC_DMAAUTOWRAP_BIT (1) + #define ADC_DMAAUTOWRAP_BITS (1) + /* ADC_DMALOAD field */ + #define ADC_DMALOAD (0x00000001u) + #define ADC_DMALOAD_MASK (0x00000001u) + #define ADC_DMALOAD_BIT (0) + #define ADC_DMALOAD_BITS (1) + +#define ADC_DMASTAT *((volatile int32u *)0x4000D014u) +#define ADC_DMASTAT_REG *((volatile int32u *)0x4000D014u) +#define ADC_DMASTAT_ADDR (0x4000D014u) +#define ADC_DMASTAT_RESET (0x00000000u) + /* ADC_DMAOVF field */ + #define ADC_DMAOVF (0x00000002u) + #define ADC_DMAOVF_MASK (0x00000002u) + #define ADC_DMAOVF_BIT (1) + #define ADC_DMAOVF_BITS (1) + /* ADC_DMAACT field */ + #define ADC_DMAACT (0x00000001u) + #define ADC_DMAACT_MASK (0x00000001u) + #define ADC_DMAACT_BIT (0) + #define ADC_DMAACT_BITS (1) + +#define ADC_DMABEG *((volatile int32u *)0x4000D018u) +#define ADC_DMABEG_REG *((volatile int32u *)0x4000D018u) +#define ADC_DMABEG_ADDR (0x4000D018u) +#define ADC_DMABEG_RESET (0x20000000u) + /* ADC_DMABEG_FIXED field */ + #define ADC_DMABEG_FIXED (0xFFFFE000u) + #define ADC_DMABEG_FIXED_MASK (0xFFFFE000u) + #define ADC_DMABEG_FIXED_BIT (13) + #define ADC_DMABEG_FIXED_BITS (19) + /* ADC_DMABEG_FIELD field */ + #define ADC_DMABEG_FIELD (0x00001FFFu) + #define ADC_DMABEG_FIELD_MASK (0x00001FFFu) + #define ADC_DMABEG_FIELD_BIT (0) + #define ADC_DMABEG_FIELD_BITS (13) + +#define ADC_DMASIZE *((volatile int32u *)0x4000D01Cu) +#define ADC_DMASIZE_REG *((volatile int32u *)0x4000D01Cu) +#define ADC_DMASIZE_ADDR (0x4000D01Cu) +#define ADC_DMASIZE_RESET (0x00000000u) + /* ADC_DMASIZE_FIELD field */ + #define ADC_DMASIZE_FIELD (0x00000FFFu) + #define ADC_DMASIZE_FIELD_MASK (0x00000FFFu) + #define ADC_DMASIZE_FIELD_BIT (0) + #define ADC_DMASIZE_FIELD_BITS (12) + +#define ADC_DMACUR *((volatile int32u *)0x4000D020u) +#define ADC_DMACUR_REG *((volatile int32u *)0x4000D020u) +#define ADC_DMACUR_ADDR (0x4000D020u) +#define ADC_DMACUR_RESET (0x20000000u) + /* ADC_DMACUR_FIXED field */ + #define ADC_DMACUR_FIXED (0xFFFFE000u) + #define ADC_DMACUR_FIXED_MASK (0xFFFFE000u) + #define ADC_DMACUR_FIXED_BIT (13) + #define ADC_DMACUR_FIXED_BITS (19) + /* ADC_DMACUR_FIELD field */ + #define ADC_DMACUR_FIELD (0x00001FFFu) + #define ADC_DMACUR_FIELD_MASK (0x00001FFFu) + #define ADC_DMACUR_FIELD_BIT (0) + #define ADC_DMACUR_FIELD_BITS (13) + +#define ADC_DMACNT *((volatile int32u *)0x4000D024u) +#define ADC_DMACNT_REG *((volatile int32u *)0x4000D024u) +#define ADC_DMACNT_ADDR (0x4000D024u) +#define ADC_DMACNT_RESET (0x00000000u) + /* ADC_DMACNT_FIELD field */ + #define ADC_DMACNT_FIELD (0x00000FFFu) + #define ADC_DMACNT_FIELD_MASK (0x00000FFFu) + #define ADC_DMACNT_FIELD_BIT (0) + #define ADC_DMACNT_FIELD_BITS (12) + +/* TIM1 block */ +#define BLOCK_TIM1_BASE (0x4000E000u) +#define BLOCK_TIM1_END (0x4000E050u) +#define BLOCK_TIM1_SIZE (BLOCK_TIM1_END - BLOCK_TIM1_BASE + 1) + +#define TIM1_CR1 *((volatile int32u *)0x4000E000u) +#define TIM1_CR1_REG *((volatile int32u *)0x4000E000u) +#define TIM1_CR1_ADDR (0x4000E000u) +#define TIM1_CR1_RESET (0x00000000u) + /* TIM_ARBE field */ + #define TIM_ARBE (0x00000080u) + #define TIM_ARBE_MASK (0x00000080u) + #define TIM_ARBE_BIT (7) + #define TIM_ARBE_BITS (1) + /* TIM_CMS field */ + #define TIM_CMS (0x00000060u) + #define TIM_CMS_MASK (0x00000060u) + #define TIM_CMS_BIT (5) + #define TIM_CMS_BITS (2) + /* TIM_DIR field */ + #define TIM_DIR (0x00000010u) + #define TIM_DIR_MASK (0x00000010u) + #define TIM_DIR_BIT (4) + #define TIM_DIR_BITS (1) + /* TIM_OPM field */ + #define TIM_OPM (0x00000008u) + #define TIM_OPM_MASK (0x00000008u) + #define TIM_OPM_BIT (3) + #define TIM_OPM_BITS (1) + /* TIM_URS field */ + #define TIM_URS (0x00000004u) + #define TIM_URS_MASK (0x00000004u) + #define TIM_URS_BIT (2) + #define TIM_URS_BITS (1) + /* TIM_UDIS field */ + #define TIM_UDIS (0x00000002u) + #define TIM_UDIS_MASK (0x00000002u) + #define TIM_UDIS_BIT (1) + #define TIM_UDIS_BITS (1) + /* TIM_CEN field */ + #define TIM_CEN (0x00000001u) + #define TIM_CEN_MASK (0x00000001u) + #define TIM_CEN_BIT (0) + #define TIM_CEN_BITS (1) + +#define TIM1_CR2 *((volatile int32u *)0x4000E004u) +#define TIM1_CR2_REG *((volatile int32u *)0x4000E004u) +#define TIM1_CR2_ADDR (0x4000E004u) +#define TIM1_CR2_RESET (0x00000000u) + /* TIM_TI1S field */ + #define TIM_TI1S (0x00000080u) + #define TIM_TI1S_MASK (0x00000080u) + #define TIM_TI1S_BIT (7) + #define TIM_TI1S_BITS (1) + /* TIM_MMS field */ + #define TIM_MMS (0x00000070u) + #define TIM_MMS_MASK (0x00000070u) + #define TIM_MMS_BIT (4) + #define TIM_MMS_BITS (3) + +#define TIM1_SMCR *((volatile int32u *)0x4000E008u) +#define TIM1_SMCR_REG *((volatile int32u *)0x4000E008u) +#define TIM1_SMCR_ADDR (0x4000E008u) +#define TIM1_SMCR_RESET (0x00000000u) + /* TIM_ETP field */ + #define TIM_ETP (0x00008000u) + #define TIM_ETP_MASK (0x00008000u) + #define TIM_ETP_BIT (15) + #define TIM_ETP_BITS (1) + /* TIM_ECE field */ + #define TIM_ECE (0x00004000u) + #define TIM_ECE_MASK (0x00004000u) + #define TIM_ECE_BIT (14) + #define TIM_ECE_BITS (1) + /* TIM_ETPS field */ + #define TIM_ETPS (0x00003000u) + #define TIM_ETPS_MASK (0x00003000u) + #define TIM_ETPS_BIT (12) + #define TIM_ETPS_BITS (2) + /* TIM_ETF field */ + #define TIM_ETF (0x00000F00u) + #define TIM_ETF_MASK (0x00000F00u) + #define TIM_ETF_BIT (8) + #define TIM_ETF_BITS (4) + /* TIM_MSM field */ + #define TIM_MSM (0x00000080u) + #define TIM_MSM_MASK (0x00000080u) + #define TIM_MSM_BIT (7) + #define TIM_MSM_BITS (1) + /* TIM_TS field */ + #define TIM_TS (0x00000070u) + #define TIM_TS_MASK (0x00000070u) + #define TIM_TS_BIT (4) + #define TIM_TS_BITS (3) + /* TIM_SMS field */ + #define TIM_SMS (0x00000007u) + #define TIM_SMS_MASK (0x00000007u) + #define TIM_SMS_BIT (0) + #define TIM_SMS_BITS (3) + +#define TMR1_DIER *((volatile int32u *)0x4000E00Cu) +#define TMR1_DIER_REG *((volatile int32u *)0x4000E00Cu) +#define TMR1_DIER_ADDR (0x4000E00Cu) +#define TMR1_DIER_RESET (0x00000000u) + /* TIE field */ + #define TMR1_DIER_TIE (0x00000040u) + #define TMR1_DIER_TIE_MASK (0x00000040u) + #define TMR1_DIER_TIE_BIT (6) + #define TMR1_DIER_TIE_BITS (1) + /* CC4IE field */ + #define TMR1_DIER_CC4IE (0x00000010u) + #define TMR1_DIER_CC4IE_MASK (0x00000010u) + #define TMR1_DIER_CC4IE_BIT (4) + #define TMR1_DIER_CC4IE_BITS (1) + /* CC3IE field */ + #define TMR1_DIER_CC3IE (0x00000008u) + #define TMR1_DIER_CC3IE_MASK (0x00000008u) + #define TMR1_DIER_CC3IE_BIT (3) + #define TMR1_DIER_CC3IE_BITS (1) + /* CC2IE field */ + #define TMR1_DIER_CC2IE (0x00000004u) + #define TMR1_DIER_CC2IE_MASK (0x00000004u) + #define TMR1_DIER_CC2IE_BIT (2) + #define TMR1_DIER_CC2IE_BITS (1) + /* CC1IE field */ + #define TMR1_DIER_CC1IE (0x00000002u) + #define TMR1_DIER_CC1IE_MASK (0x00000002u) + #define TMR1_DIER_CC1IE_BIT (1) + #define TMR1_DIER_CC1IE_BITS (1) + /* UIE field */ + #define TMR1_DIER_UIE (0x00000001u) + #define TMR1_DIER_UIE_MASK (0x00000001u) + #define TMR1_DIER_UIE_BIT (0) + #define TMR1_DIER_UIE_BITS (1) + +#define TMR1_SR *((volatile int32u *)0x4000E010u) +#define TMR1_SR_REG *((volatile int32u *)0x4000E010u) +#define TMR1_SR_ADDR (0x4000E010u) +#define TMR1_SR_RESET (0x00000000u) + /* CC4OF field */ + #define TMR1_SR_CC4OF (0x00001000u) + #define TMR1_SR_CC4OF_MASK (0x00001000u) + #define TMR1_SR_CC4OF_BIT (12) + #define TMR1_SR_CC4OF_BITS (1) + /* CC3OF field */ + #define TMR1_SR_CC3OF (0x00000800u) + #define TMR1_SR_CC3OF_MASK (0x00000800u) + #define TMR1_SR_CC3OF_BIT (11) + #define TMR1_SR_CC3OF_BITS (1) + /* CC2OF field */ + #define TMR1_SR_CC2OF (0x00000400u) + #define TMR1_SR_CC2OF_MASK (0x00000400u) + #define TMR1_SR_CC2OF_BIT (10) + #define TMR1_SR_CC2OF_BITS (1) + /* CC1OF field */ + #define TMR1_SR_CC1OF (0x00000200u) + #define TMR1_SR_CC1OF_MASK (0x00000200u) + #define TMR1_SR_CC1OF_BIT (9) + #define TMR1_SR_CC1OF_BITS (1) + /* TIF field */ + #define TMR1_SR_TIF (0x00000040u) + #define TMR1_SR_TIF_MASK (0x00000040u) + #define TMR1_SR_TIF_BIT (6) + #define TMR1_SR_TIF_BITS (1) + /* CC4IF field */ + #define TMR1_SR_CC4IF (0x00000010u) + #define TMR1_SR_CC4IF_MASK (0x00000010u) + #define TMR1_SR_CC4IF_BIT (4) + #define TMR1_SR_CC4IF_BITS (1) + /* CC3IF field */ + #define TMR1_SR_CC3IF (0x00000008u) + #define TMR1_SR_CC3IF_MASK (0x00000008u) + #define TMR1_SR_CC3IF_BIT (3) + #define TMR1_SR_CC3IF_BITS (1) + /* CC2IF field */ + #define TMR1_SR_CC2IF (0x00000004u) + #define TMR1_SR_CC2IF_MASK (0x00000004u) + #define TMR1_SR_CC2IF_BIT (2) + #define TMR1_SR_CC2IF_BITS (1) + /* CC1IF field */ + #define TMR1_SR_CC1IF (0x00000002u) + #define TMR1_SR_CC1IF_MASK (0x00000002u) + #define TMR1_SR_CC1IF_BIT (1) + #define TMR1_SR_CC1IF_BITS (1) + /* UIF field */ + #define TMR1_SR_UIF (0x00000001u) + #define TMR1_SR_UIF_MASK (0x00000001u) + #define TMR1_SR_UIF_BIT (0) + #define TMR1_SR_UIF_BITS (1) + +#define TIM1_EGR *((volatile int32u *)0x4000E014u) +#define TIM1_EGR_REG *((volatile int32u *)0x4000E014u) +#define TIM1_EGR_ADDR (0x4000E014u) +#define TIM1_EGR_RESET (0x00000000u) + /* TIM_TG field */ + #define TIM_TG (0x00000040u) + #define TIM_TG_MASK (0x00000040u) + #define TIM_TG_BIT (6) + #define TIM_TG_BITS (1) + /* TIM_CC4G field */ + #define TIM_CC4G (0x00000010u) + #define TIM_CC4G_MASK (0x00000010u) + #define TIM_CC4G_BIT (4) + #define TIM_CC4G_BITS (1) + /* TIM_CC3G field */ + #define TIM_CC3G (0x00000008u) + #define TIM_CC3G_MASK (0x00000008u) + #define TIM_CC3G_BIT (3) + #define TIM_CC3G_BITS (1) + /* TIM_CC2G field */ + #define TIM_CC2G (0x00000004u) + #define TIM_CC2G_MASK (0x00000004u) + #define TIM_CC2G_BIT (2) + #define TIM_CC2G_BITS (1) + /* TIM_CC1G field */ + #define TIM_CC1G (0x00000002u) + #define TIM_CC1G_MASK (0x00000002u) + #define TIM_CC1G_BIT (1) + #define TIM_CC1G_BITS (1) + /* TIM_UG field */ + #define TIM_UG (0x00000001u) + #define TIM_UG_MASK (0x00000001u) + #define TIM_UG_BIT (0) + #define TIM_UG_BITS (1) + +#define TIM1_CCMR1 *((volatile int32u *)0x4000E018u) +#define TIM1_CCMR1_REG *((volatile int32u *)0x4000E018u) +#define TIM1_CCMR1_ADDR (0x4000E018u) +#define TIM1_CCMR1_RESET (0x00000000u) + /* TIM_IC2F field */ + #define TIM_IC2F (0x0000F000u) + #define TIM_IC2F_MASK (0x0000F000u) + #define TIM_IC2F_BIT (12) + #define TIM_IC2F_BITS (4) + /* TIM_IC2PSC field */ + #define TIM_IC2PSC (0x00000C00u) + #define TIM_IC2PSC_MASK (0x00000C00u) + #define TIM_IC2PSC_BIT (10) + #define TIM_IC2PSC_BITS (2) + /* TIM_IC1F field */ + #define TIM_IC1F (0x000000F0u) + #define TIM_IC1F_MASK (0x000000F0u) + #define TIM_IC1F_BIT (4) + #define TIM_IC1F_BITS (4) + /* TIM_IC1PSC field */ + #define TIM_IC1PSC (0x0000000Cu) + #define TIM_IC1PSC_MASK (0x0000000Cu) + #define TIM_IC1PSC_BIT (2) + #define TIM_IC1PSC_BITS (2) + /* TIM_OC2CE field */ + #define TIM_OC2CE (0x00008000u) + #define TIM_OC2CE_MASK (0x00008000u) + #define TIM_OC2CE_BIT (15) + #define TIM_OC2CE_BITS (1) + /* TIM_OC2M field */ + #define TIM_OC2M (0x00007000u) + #define TIM_OC2M_MASK (0x00007000u) + #define TIM_OC2M_BIT (12) + #define TIM_OC2M_BITS (3) + /* TIM_OC2BE field */ + #define TIM_OC2BE (0x00000800u) + #define TIM_OC2BE_MASK (0x00000800u) + #define TIM_OC2BE_BIT (11) + #define TIM_OC2BE_BITS (1) + /* TIM_OC2FE field */ + #define TIM_OC2FE (0x00000400u) + #define TIM_OC2FE_MASK (0x00000400u) + #define TIM_OC2FE_BIT (10) + #define TIM_OC2FE_BITS (1) + /* TIM_CC2S field */ + #define TIM_CC2S (0x00000300u) + #define TIM_CC2S_MASK (0x00000300u) + #define TIM_CC2S_BIT (8) + #define TIM_CC2S_BITS (2) + /* TIM_OC1CE field */ + #define TIM_OC1CE (0x00000080u) + #define TIM_OC1CE_MASK (0x00000080u) + #define TIM_OC1CE_BIT (7) + #define TIM_OC1CE_BITS (1) + /* TIM_OC1M field */ + #define TIM_OC1M (0x00000070u) + #define TIM_OC1M_MASK (0x00000070u) + #define TIM_OC1M_BIT (4) + #define TIM_OC1M_BITS (3) + /* TIM_OC1PE field */ + #define TIM_OC1PE (0x00000008u) + #define TIM_OC1PE_MASK (0x00000008u) + #define TIM_OC1PE_BIT (3) + #define TIM_OC1PE_BITS (1) + /* TIM_OC1FE field */ + #define TIM_OC1FE (0x00000004u) + #define TIM_OC1FE_MASK (0x00000004u) + #define TIM_OC1FE_BIT (2) + #define TIM_OC1FE_BITS (1) + /* TIM_CC1S field */ + #define TIM_CC1S (0x00000003u) + #define TIM_CC1S_MASK (0x00000003u) + #define TIM_CC1S_BIT (0) + #define TIM_CC1S_BITS (2) + +#define TIM1_CCMR2 *((volatile int32u *)0x4000E01Cu) +#define TIM1_CCMR2_REG *((volatile int32u *)0x4000E01Cu) +#define TIM1_CCMR2_ADDR (0x4000E01Cu) +#define TIM1_CCMR2_RESET (0x00000000u) + /* TIM_IC4F field */ + #define TIM_IC4F (0x0000F000u) + #define TIM_IC4F_MASK (0x0000F000u) + #define TIM_IC4F_BIT (12) + #define TIM_IC4F_BITS (4) + /* TIM_IC4PSC field */ + #define TIM_IC4PSC (0x00000C00u) + #define TIM_IC4PSC_MASK (0x00000C00u) + #define TIM_IC4PSC_BIT (10) + #define TIM_IC4PSC_BITS (2) + /* TIM_IC3F field */ + #define TIM_IC3F (0x000000F0u) + #define TIM_IC3F_MASK (0x000000F0u) + #define TIM_IC3F_BIT (4) + #define TIM_IC3F_BITS (4) + /* TIM_IC3PSC field */ + #define TIM_IC3PSC (0x0000000Cu) + #define TIM_IC3PSC_MASK (0x0000000Cu) + #define TIM_IC3PSC_BIT (2) + #define TIM_IC3PSC_BITS (2) + /* TIM_OC4CE field */ + #define TIM_OC4CE (0x00008000u) + #define TIM_OC4CE_MASK (0x00008000u) + #define TIM_OC4CE_BIT (15) + #define TIM_OC4CE_BITS (1) + /* TIM_OC4M field */ + #define TIM_OC4M (0x00007000u) + #define TIM_OC4M_MASK (0x00007000u) + #define TIM_OC4M_BIT (12) + #define TIM_OC4M_BITS (3) + /* TIM_OC4BE field */ + #define TIM_OC4BE (0x00000800u) + #define TIM_OC4BE_MASK (0x00000800u) + #define TIM_OC4BE_BIT (11) + #define TIM_OC4BE_BITS (1) + /* TIM_OC4FE field */ + #define TIM_OC4FE (0x00000400u) + #define TIM_OC4FE_MASK (0x00000400u) + #define TIM_OC4FE_BIT (10) + #define TIM_OC4FE_BITS (1) + /* TIM_CC4S field */ + #define TIM_CC4S (0x00000300u) + #define TIM_CC4S_MASK (0x00000300u) + #define TIM_CC4S_BIT (8) + #define TIM_CC4S_BITS (2) + /* TIM_OC3CE field */ + #define TIM_OC3CE (0x00000080u) + #define TIM_OC3CE_MASK (0x00000080u) + #define TIM_OC3CE_BIT (7) + #define TIM_OC3CE_BITS (1) + /* TIM_OC3M field */ + #define TIM_OC3M (0x00000070u) + #define TIM_OC3M_MASK (0x00000070u) + #define TIM_OC3M_BIT (4) + #define TIM_OC3M_BITS (3) + /* TIM_OC3BE field */ + #define TIM_OC3BE (0x00000008u) + #define TIM_OC3BE_MASK (0x00000008u) + #define TIM_OC3BE_BIT (3) + #define TIM_OC3BE_BITS (1) + /* TIM_OC3FE field */ + #define TIM_OC3FE (0x00000004u) + #define TIM_OC3FE_MASK (0x00000004u) + #define TIM_OC3FE_BIT (2) + #define TIM_OC3FE_BITS (1) + /* TIM_CC3S field */ + #define TIM_CC3S (0x00000003u) + #define TIM_CC3S_MASK (0x00000003u) + #define TIM_CC3S_BIT (0) + #define TIM_CC3S_BITS (2) + +#define TIM1_CCER *((volatile int32u *)0x4000E020u) +#define TIM1_CCER_REG *((volatile int32u *)0x4000E020u) +#define TIM1_CCER_ADDR (0x4000E020u) +#define TIM1_CCER_RESET (0x00000000u) + /* TIM_CC4P field */ + #define TIM_CC4P (0x00002000u) + #define TIM_CC4P_MASK (0x00002000u) + #define TIM_CC4P_BIT (13) + #define TIM_CC4P_BITS (1) + /* TIM_CC4E field */ + #define TIM_CC4E (0x00001000u) + #define TIM_CC4E_MASK (0x00001000u) + #define TIM_CC4E_BIT (12) + #define TIM_CC4E_BITS (1) + /* TIM_CC3P field */ + #define TIM_CC3P (0x00000200u) + #define TIM_CC3P_MASK (0x00000200u) + #define TIM_CC3P_BIT (9) + #define TIM_CC3P_BITS (1) + /* TIM_CC3E field */ + #define TIM_CC3E (0x00000100u) + #define TIM_CC3E_MASK (0x00000100u) + #define TIM_CC3E_BIT (8) + #define TIM_CC3E_BITS (1) + /* TIM_CC2P field */ + #define TIM_CC2P (0x00000020u) + #define TIM_CC2P_MASK (0x00000020u) + #define TIM_CC2P_BIT (5) + #define TIM_CC2P_BITS (1) + /* TIM_CC2E field */ + #define TIM_CC2E (0x00000010u) + #define TIM_CC2E_MASK (0x00000010u) + #define TIM_CC2E_BIT (4) + #define TIM_CC2E_BITS (1) + /* TIM_CC1P field */ + #define TIM_CC1P (0x00000002u) + #define TIM_CC1P_MASK (0x00000002u) + #define TIM_CC1P_BIT (1) + #define TIM_CC1P_BITS (1) + /* TIM_CC1E field */ + #define TIM_CC1E (0x00000001u) + #define TIM_CC1E_MASK (0x00000001u) + #define TIM_CC1E_BIT (0) + #define TIM_CC1E_BITS (1) + +#define TIM1_CNT *((volatile int32u *)0x4000E024u) +#define TIM1_CNT_REG *((volatile int32u *)0x4000E024u) +#define TIM1_CNT_ADDR (0x4000E024u) +#define TIM1_CNT_RESET (0x00000000u) + /* TIM_CNT field */ + #define TIM_CNT (0x0000FFFFu) + #define TIM_CNT_MASK (0x0000FFFFu) + #define TIM_CNT_BIT (0) + #define TIM_CNT_BITS (16) + +#define TIM1_PSC *((volatile int32u *)0x4000E028u) +#define TIM1_PSC_REG *((volatile int32u *)0x4000E028u) +#define TIM1_PSC_ADDR (0x4000E028u) +#define TIM1_PSC_RESET (0x00000000u) + /* TIM_PSC field */ + #define TIM_PSC (0x0000000Fu) + #define TIM_PSC_MASK (0x0000000Fu) + #define TIM_PSC_BIT (0) + #define TIM_PSC_BITS (4) + +#define TIM1_ARR *((volatile int32u *)0x4000E02Cu) +#define TIM1_ARR_REG *((volatile int32u *)0x4000E02Cu) +#define TIM1_ARR_ADDR (0x4000E02Cu) +#define TIM1_ARR_RESET (0x0000FFFFu) + /* TIM_ARR field */ + #define TIM_ARR (0x0000FFFFu) + #define TIM_ARR_MASK (0x0000FFFFu) + #define TIM_ARR_BIT (0) + #define TIM_ARR_BITS (16) + +#define TIM1_CCR1 *((volatile int32u *)0x4000E034u) +#define TIM1_CCR1_REG *((volatile int32u *)0x4000E034u) +#define TIM1_CCR1_ADDR (0x4000E034u) +#define TIM1_CCR1_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_CCR2 *((volatile int32u *)0x4000E038u) +#define TIM1_CCR2_REG *((volatile int32u *)0x4000E038u) +#define TIM1_CCR2_ADDR (0x4000E038u) +#define TIM1_CCR2_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_CCR3 *((volatile int32u *)0x4000E03Cu) +#define TIM1_CCR3_REG *((volatile int32u *)0x4000E03Cu) +#define TIM1_CCR3_ADDR (0x4000E03Cu) +#define TIM1_CCR3_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_CCR4 *((volatile int32u *)0x4000E040u) +#define TIM1_CCR4_REG *((volatile int32u *)0x4000E040u) +#define TIM1_CCR4_ADDR (0x4000E040u) +#define TIM1_CCR4_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_OR *((volatile int32u *)0x4000E050u) +#define TIM1_OR_REG *((volatile int32u *)0x4000E050u) +#define TIM1_OR_ADDR (0x4000E050u) +#define TIM1_OR_RESET (0x00000000u) + /* TIM_ORRSVD field */ + #define TIM_ORRSVD (0x00000008u) + #define TIM_ORRSVD_MASK (0x00000008u) + #define TIM_ORRSVD_BIT (3) + #define TIM_ORRSVD_BITS (1) + /* TIM_CLKMSKEN field */ + #define TIM_CLKMSKEN (0x00000004u) + #define TIM_CLKMSKEN_MASK (0x00000004u) + #define TIM_CLKMSKEN_BIT (2) + #define TIM_CLKMSKEN_BITS (1) + /* TIM1_EXTRIGSEL field */ + #define TIM1_EXTRIGSEL (0x00000003u) + #define TIM1_EXTRIGSEL_MASK (0x00000003u) + #define TIM1_EXTRIGSEL_BIT (0) + #define TIM1_EXTRIGSEL_BITS (2) + +/* TIM2 block */ +#define BLOCK_TIM2_BASE (0x4000F000u) +#define BLOCK_TIM2_END (0x4000F050u) +#define BLOCK_TIM2_SIZE (BLOCK_TIM2_END - BLOCK_TIM2_BASE + 1) + +#define TIM2_CR1 *((volatile int32u *)0x4000F000u) +#define TIM2_CR1_REG *((volatile int32u *)0x4000F000u) +#define TIM2_CR1_ADDR (0x4000F000u) +#define TIM2_CR1_RESET (0x00000000u) + /* TIM_ARBE field */ + #define TIM_ARBE (0x00000080u) + #define TIM_ARBE_MASK (0x00000080u) + #define TIM_ARBE_BIT (7) + #define TIM_ARBE_BITS (1) + /* TIM_CMS field */ + #define TIM_CMS (0x00000060u) + #define TIM_CMS_MASK (0x00000060u) + #define TIM_CMS_BIT (5) + #define TIM_CMS_BITS (2) + /* TIM_DIR field */ + #define TIM_DIR (0x00000010u) + #define TIM_DIR_MASK (0x00000010u) + #define TIM_DIR_BIT (4) + #define TIM_DIR_BITS (1) + /* TIM_OPM field */ + #define TIM_OPM (0x00000008u) + #define TIM_OPM_MASK (0x00000008u) + #define TIM_OPM_BIT (3) + #define TIM_OPM_BITS (1) + /* TIM_URS field */ + #define TIM_URS (0x00000004u) + #define TIM_URS_MASK (0x00000004u) + #define TIM_URS_BIT (2) + #define TIM_URS_BITS (1) + /* TIM_UDIS field */ + #define TIM_UDIS (0x00000002u) + #define TIM_UDIS_MASK (0x00000002u) + #define TIM_UDIS_BIT (1) + #define TIM_UDIS_BITS (1) + /* TIM_CEN field */ + #define TIM_CEN (0x00000001u) + #define TIM_CEN_MASK (0x00000001u) + #define TIM_CEN_BIT (0) + #define TIM_CEN_BITS (1) + +#define TIM2_CR2 *((volatile int32u *)0x4000F004u) +#define TIM2_CR2_REG *((volatile int32u *)0x4000F004u) +#define TIM2_CR2_ADDR (0x4000F004u) +#define TIM2_CR2_RESET (0x00000000u) + /* TIM_TI1S field */ + #define TIM_TI1S (0x00000080u) + #define TIM_TI1S_MASK (0x00000080u) + #define TIM_TI1S_BIT (7) + #define TIM_TI1S_BITS (1) + /* TIM_MMS field */ + #define TIM_MMS (0x00000070u) + #define TIM_MMS_MASK (0x00000070u) + #define TIM_MMS_BIT (4) + #define TIM_MMS_BITS (3) + +#define TIM2_SMCR *((volatile int32u *)0x4000F008u) +#define TIM2_SMCR_REG *((volatile int32u *)0x4000F008u) +#define TIM2_SMCR_ADDR (0x4000F008u) +#define TIM2_SMCR_RESET (0x00000000u) + /* TIM_ETP field */ + #define TIM_ETP (0x00008000u) + #define TIM_ETP_MASK (0x00008000u) + #define TIM_ETP_BIT (15) + #define TIM_ETP_BITS (1) + /* TIM_ECE field */ + #define TIM_ECE (0x00004000u) + #define TIM_ECE_MASK (0x00004000u) + #define TIM_ECE_BIT (14) + #define TIM_ECE_BITS (1) + /* TIM_ETPS field */ + #define TIM_ETPS (0x00003000u) + #define TIM_ETPS_MASK (0x00003000u) + #define TIM_ETPS_BIT (12) + #define TIM_ETPS_BITS (2) + /* TIM_ETF field */ + #define TIM_ETF (0x00000F00u) + #define TIM_ETF_MASK (0x00000F00u) + #define TIM_ETF_BIT (8) + #define TIM_ETF_BITS (4) + /* TIM_MSM field */ + #define TIM_MSM (0x00000080u) + #define TIM_MSM_MASK (0x00000080u) + #define TIM_MSM_BIT (7) + #define TIM_MSM_BITS (1) + /* TIM_TS field */ + #define TIM_TS (0x00000070u) + #define TIM_TS_MASK (0x00000070u) + #define TIM_TS_BIT (4) + #define TIM_TS_BITS (3) + /* TIM_SMS field */ + #define TIM_SMS (0x00000007u) + #define TIM_SMS_MASK (0x00000007u) + #define TIM_SMS_BIT (0) + #define TIM_SMS_BITS (3) + +#define TMR2_DIER *((volatile int32u *)0x4000F00Cu) +#define TMR2_DIER_REG *((volatile int32u *)0x4000F00Cu) +#define TMR2_DIER_ADDR (0x4000F00Cu) +#define TMR2_DIER_RESET (0x00000000u) + /* TIE field */ + #define TMR2_DIER_TIE (0x00000040u) + #define TMR2_DIER_TIE_MASK (0x00000040u) + #define TMR2_DIER_TIE_BIT (6) + #define TMR2_DIER_TIE_BITS (1) + /* CC4IE field */ + #define TMR2_DIER_CC4IE (0x00000010u) + #define TMR2_DIER_CC4IE_MASK (0x00000010u) + #define TMR2_DIER_CC4IE_BIT (4) + #define TMR2_DIER_CC4IE_BITS (1) + /* CC3IE field */ + #define TMR2_DIER_CC3IE (0x00000008u) + #define TMR2_DIER_CC3IE_MASK (0x00000008u) + #define TMR2_DIER_CC3IE_BIT (3) + #define TMR2_DIER_CC3IE_BITS (1) + /* CC2IE field */ + #define TMR2_DIER_CC2IE (0x00000004u) + #define TMR2_DIER_CC2IE_MASK (0x00000004u) + #define TMR2_DIER_CC2IE_BIT (2) + #define TMR2_DIER_CC2IE_BITS (1) + /* CC1IE field */ + #define TMR2_DIER_CC1IE (0x00000002u) + #define TMR2_DIER_CC1IE_MASK (0x00000002u) + #define TMR2_DIER_CC1IE_BIT (1) + #define TMR2_DIER_CC1IE_BITS (1) + /* UIE field */ + #define TMR2_DIER_UIE (0x00000001u) + #define TMR2_DIER_UIE_MASK (0x00000001u) + #define TMR2_DIER_UIE_BIT (0) + #define TMR2_DIER_UIE_BITS (1) + +#define TMR2_SR *((volatile int32u *)0x4000F010u) +#define TMR2_SR_REG *((volatile int32u *)0x4000F010u) +#define TMR2_SR_ADDR (0x4000F010u) +#define TMR2_SR_RESET (0x00000000u) + /* CC4OF field */ + #define TMR2_SR_CC4OF (0x00001000u) + #define TMR2_SR_CC4OF_MASK (0x00001000u) + #define TMR2_SR_CC4OF_BIT (12) + #define TMR2_SR_CC4OF_BITS (1) + /* CC3OF field */ + #define TMR2_SR_CC3OF (0x00000800u) + #define TMR2_SR_CC3OF_MASK (0x00000800u) + #define TMR2_SR_CC3OF_BIT (11) + #define TMR2_SR_CC3OF_BITS (1) + /* CC2OF field */ + #define TMR2_SR_CC2OF (0x00000400u) + #define TMR2_SR_CC2OF_MASK (0x00000400u) + #define TMR2_SR_CC2OF_BIT (10) + #define TMR2_SR_CC2OF_BITS (1) + /* CC1OF field */ + #define TMR2_SR_CC1OF (0x00000200u) + #define TMR2_SR_CC1OF_MASK (0x00000200u) + #define TMR2_SR_CC1OF_BIT (9) + #define TMR2_SR_CC1OF_BITS (1) + /* TIF field */ + #define TMR2_SR_TIF (0x00000040u) + #define TMR2_SR_TIF_MASK (0x00000040u) + #define TMR2_SR_TIF_BIT (6) + #define TMR2_SR_TIF_BITS (1) + /* CC4IF field */ + #define TMR2_SR_CC4IF (0x00000010u) + #define TMR2_SR_CC4IF_MASK (0x00000010u) + #define TMR2_SR_CC4IF_BIT (4) + #define TMR2_SR_CC4IF_BITS (1) + /* CC3IF field */ + #define TMR2_SR_CC3IF (0x00000008u) + #define TMR2_SR_CC3IF_MASK (0x00000008u) + #define TMR2_SR_CC3IF_BIT (3) + #define TMR2_SR_CC3IF_BITS (1) + /* CC2IF field */ + #define TMR2_SR_CC2IF (0x00000004u) + #define TMR2_SR_CC2IF_MASK (0x00000004u) + #define TMR2_SR_CC2IF_BIT (2) + #define TMR2_SR_CC2IF_BITS (1) + /* CC1IF field */ + #define TMR2_SR_CC1IF (0x00000002u) + #define TMR2_SR_CC1IF_MASK (0x00000002u) + #define TMR2_SR_CC1IF_BIT (1) + #define TMR2_SR_CC1IF_BITS (1) + /* UIF field */ + #define TMR2_SR_UIF (0x00000001u) + #define TMR2_SR_UIF_MASK (0x00000001u) + #define TMR2_SR_UIF_BIT (0) + #define TMR2_SR_UIF_BITS (1) + +#define TIM2_EGR *((volatile int32u *)0x4000F014u) +#define TIM2_EGR_REG *((volatile int32u *)0x4000F014u) +#define TIM2_EGR_ADDR (0x4000F014u) +#define TIM2_EGR_RESET (0x00000000u) + /* TIM_TG field */ + #define TIM_TG (0x00000040u) + #define TIM_TG_MASK (0x00000040u) + #define TIM_TG_BIT (6) + #define TIM_TG_BITS (1) + /* TIM_CC4G field */ + #define TIM_CC4G (0x00000010u) + #define TIM_CC4G_MASK (0x00000010u) + #define TIM_CC4G_BIT (4) + #define TIM_CC4G_BITS (1) + /* TIM_CC3G field */ + #define TIM_CC3G (0x00000008u) + #define TIM_CC3G_MASK (0x00000008u) + #define TIM_CC3G_BIT (3) + #define TIM_CC3G_BITS (1) + /* TIM_CC2G field */ + #define TIM_CC2G (0x00000004u) + #define TIM_CC2G_MASK (0x00000004u) + #define TIM_CC2G_BIT (2) + #define TIM_CC2G_BITS (1) + /* TIM_CC1G field */ + #define TIM_CC1G (0x00000002u) + #define TIM_CC1G_MASK (0x00000002u) + #define TIM_CC1G_BIT (1) + #define TIM_CC1G_BITS (1) + /* TIM_UG field */ + #define TIM_UG (0x00000001u) + #define TIM_UG_MASK (0x00000001u) + #define TIM_UG_BIT (0) + #define TIM_UG_BITS (1) + +#define TIM2_CCMR1 *((volatile int32u *)0x4000F018u) +#define TIM2_CCMR1_REG *((volatile int32u *)0x4000F018u) +#define TIM2_CCMR1_ADDR (0x4000F018u) +#define TIM2_CCMR1_RESET (0x00000000u) + /* TIM_IC2F field */ + #define TIM_IC2F (0x0000F000u) + #define TIM_IC2F_MASK (0x0000F000u) + #define TIM_IC2F_BIT (12) + #define TIM_IC2F_BITS (4) + /* TIM_IC2PSC field */ + #define TIM_IC2PSC (0x00000C00u) + #define TIM_IC2PSC_MASK (0x00000C00u) + #define TIM_IC2PSC_BIT (10) + #define TIM_IC2PSC_BITS (2) + /* TIM_IC1F field */ + #define TIM_IC1F (0x000000F0u) + #define TIM_IC1F_MASK (0x000000F0u) + #define TIM_IC1F_BIT (4) + #define TIM_IC1F_BITS (4) + /* TIM_IC1PSC field */ + #define TIM_IC1PSC (0x0000000Cu) + #define TIM_IC1PSC_MASK (0x0000000Cu) + #define TIM_IC1PSC_BIT (2) + #define TIM_IC1PSC_BITS (2) + /* TIM_OC2CE field */ + #define TIM_OC2CE (0x00008000u) + #define TIM_OC2CE_MASK (0x00008000u) + #define TIM_OC2CE_BIT (15) + #define TIM_OC2CE_BITS (1) + /* TIM_OC2M field */ + #define TIM_OC2M (0x00007000u) + #define TIM_OC2M_MASK (0x00007000u) + #define TIM_OC2M_BIT (12) + #define TIM_OC2M_BITS (3) + /* TIM_OC2BE field */ + #define TIM_OC2BE (0x00000800u) + #define TIM_OC2BE_MASK (0x00000800u) + #define TIM_OC2BE_BIT (11) + #define TIM_OC2BE_BITS (1) + /* TIM_OC2FE field */ + #define TIM_OC2FE (0x00000400u) + #define TIM_OC2FE_MASK (0x00000400u) + #define TIM_OC2FE_BIT (10) + #define TIM_OC2FE_BITS (1) + /* TIM_CC2S field */ + #define TIM_CC2S (0x00000300u) + #define TIM_CC2S_MASK (0x00000300u) + #define TIM_CC2S_BIT (8) + #define TIM_CC2S_BITS (2) + /* TIM_OC1CE field */ + #define TIM_OC1CE (0x00000080u) + #define TIM_OC1CE_MASK (0x00000080u) + #define TIM_OC1CE_BIT (7) + #define TIM_OC1CE_BITS (1) + /* TIM_OC1M field */ + #define TIM_OC1M (0x00000070u) + #define TIM_OC1M_MASK (0x00000070u) + #define TIM_OC1M_BIT (4) + #define TIM_OC1M_BITS (3) + /* TIM_OC1PE field */ + #define TIM_OC1PE (0x00000008u) + #define TIM_OC1PE_MASK (0x00000008u) + #define TIM_OC1PE_BIT (3) + #define TIM_OC1PE_BITS (1) + /* TIM_OC1FE field */ + #define TIM_OC1FE (0x00000004u) + #define TIM_OC1FE_MASK (0x00000004u) + #define TIM_OC1FE_BIT (2) + #define TIM_OC1FE_BITS (1) + /* TIM_CC1S field */ + #define TIM_CC1S (0x00000003u) + #define TIM_CC1S_MASK (0x00000003u) + #define TIM_CC1S_BIT (0) + #define TIM_CC1S_BITS (2) + +#define TIM2_CCMR2 *((volatile int32u *)0x4000F01Cu) +#define TIM2_CCMR2_REG *((volatile int32u *)0x4000F01Cu) +#define TIM2_CCMR2_ADDR (0x4000F01Cu) +#define TIM2_CCMR2_RESET (0x00000000u) + /* TIM_IC4F field */ + #define TIM_IC4F (0x0000F000u) + #define TIM_IC4F_MASK (0x0000F000u) + #define TIM_IC4F_BIT (12) + #define TIM_IC4F_BITS (4) + /* TIM_IC4PSC field */ + #define TIM_IC4PSC (0x00000C00u) + #define TIM_IC4PSC_MASK (0x00000C00u) + #define TIM_IC4PSC_BIT (10) + #define TIM_IC4PSC_BITS (2) + /* TIM_IC3F field */ + #define TIM_IC3F (0x000000F0u) + #define TIM_IC3F_MASK (0x000000F0u) + #define TIM_IC3F_BIT (4) + #define TIM_IC3F_BITS (4) + /* TIM_IC3PSC field */ + #define TIM_IC3PSC (0x0000000Cu) + #define TIM_IC3PSC_MASK (0x0000000Cu) + #define TIM_IC3PSC_BIT (2) + #define TIM_IC3PSC_BITS (2) + /* TIM_OC4CE field */ + #define TIM_OC4CE (0x00008000u) + #define TIM_OC4CE_MASK (0x00008000u) + #define TIM_OC4CE_BIT (15) + #define TIM_OC4CE_BITS (1) + /* TIM_OC4M field */ + #define TIM_OC4M (0x00007000u) + #define TIM_OC4M_MASK (0x00007000u) + #define TIM_OC4M_BIT (12) + #define TIM_OC4M_BITS (3) + /* TIM_OC4BE field */ + #define TIM_OC4BE (0x00000800u) + #define TIM_OC4BE_MASK (0x00000800u) + #define TIM_OC4BE_BIT (11) + #define TIM_OC4BE_BITS (1) + /* TIM_OC4FE field */ + #define TIM_OC4FE (0x00000400u) + #define TIM_OC4FE_MASK (0x00000400u) + #define TIM_OC4FE_BIT (10) + #define TIM_OC4FE_BITS (1) + /* TIM_CC4S field */ + #define TIM_CC4S (0x00000300u) + #define TIM_CC4S_MASK (0x00000300u) + #define TIM_CC4S_BIT (8) + #define TIM_CC4S_BITS (2) + /* TIM_OC3CE field */ + #define TIM_OC3CE (0x00000080u) + #define TIM_OC3CE_MASK (0x00000080u) + #define TIM_OC3CE_BIT (7) + #define TIM_OC3CE_BITS (1) + /* TIM_OC3M field */ + #define TIM_OC3M (0x00000070u) + #define TIM_OC3M_MASK (0x00000070u) + #define TIM_OC3M_BIT (4) + #define TIM_OC3M_BITS (3) + /* TIM_OC3BE field */ + #define TIM_OC3BE (0x00000008u) + #define TIM_OC3BE_MASK (0x00000008u) + #define TIM_OC3BE_BIT (3) + #define TIM_OC3BE_BITS (1) + /* TIM_OC3FE field */ + #define TIM_OC3FE (0x00000004u) + #define TIM_OC3FE_MASK (0x00000004u) + #define TIM_OC3FE_BIT (2) + #define TIM_OC3FE_BITS (1) + /* TIM_CC3S field */ + #define TIM_CC3S (0x00000003u) + #define TIM_CC3S_MASK (0x00000003u) + #define TIM_CC3S_BIT (0) + #define TIM_CC3S_BITS (2) + +#define TIM2_CCER *((volatile int32u *)0x4000F020u) +#define TIM2_CCER_REG *((volatile int32u *)0x4000F020u) +#define TIM2_CCER_ADDR (0x4000F020u) +#define TIM2_CCER_RESET (0x00000000u) + /* TIM_CC4P field */ + #define TIM_CC4P (0x00002000u) + #define TIM_CC4P_MASK (0x00002000u) + #define TIM_CC4P_BIT (13) + #define TIM_CC4P_BITS (1) + /* TIM_CC4E field */ + #define TIM_CC4E (0x00001000u) + #define TIM_CC4E_MASK (0x00001000u) + #define TIM_CC4E_BIT (12) + #define TIM_CC4E_BITS (1) + /* TIM_CC3P field */ + #define TIM_CC3P (0x00000200u) + #define TIM_CC3P_MASK (0x00000200u) + #define TIM_CC3P_BIT (9) + #define TIM_CC3P_BITS (1) + /* TIM_CC3E field */ + #define TIM_CC3E (0x00000100u) + #define TIM_CC3E_MASK (0x00000100u) + #define TIM_CC3E_BIT (8) + #define TIM_CC3E_BITS (1) + /* TIM_CC2P field */ + #define TIM_CC2P (0x00000020u) + #define TIM_CC2P_MASK (0x00000020u) + #define TIM_CC2P_BIT (5) + #define TIM_CC2P_BITS (1) + /* TIM_CC2E field */ + #define TIM_CC2E (0x00000010u) + #define TIM_CC2E_MASK (0x00000010u) + #define TIM_CC2E_BIT (4) + #define TIM_CC2E_BITS (1) + /* TIM_CC1P field */ + #define TIM_CC1P (0x00000002u) + #define TIM_CC1P_MASK (0x00000002u) + #define TIM_CC1P_BIT (1) + #define TIM_CC1P_BITS (1) + /* TIM_CC1E field */ + #define TIM_CC1E (0x00000001u) + #define TIM_CC1E_MASK (0x00000001u) + #define TIM_CC1E_BIT (0) + #define TIM_CC1E_BITS (1) + +#define TIM2_CNT *((volatile int32u *)0x4000F024u) +#define TIM2_CNT_REG *((volatile int32u *)0x4000F024u) +#define TIM2_CNT_ADDR (0x4000F024u) +#define TIM2_CNT_RESET (0x00000000u) + /* TIM_CNT field */ + #define TIM_CNT (0x0000FFFFu) + #define TIM_CNT_MASK (0x0000FFFFu) + #define TIM_CNT_BIT (0) + #define TIM_CNT_BITS (16) + +#define TIM2_PSC *((volatile int32u *)0x4000F028u) +#define TIM2_PSC_REG *((volatile int32u *)0x4000F028u) +#define TIM2_PSC_ADDR (0x4000F028u) +#define TIM2_PSC_RESET (0x00000000u) + /* TIM_PSC field */ + #define TIM_PSC (0x0000000Fu) + #define TIM_PSC_MASK (0x0000000Fu) + #define TIM_PSC_BIT (0) + #define TIM_PSC_BITS (4) + +#define TIM2_ARR *((volatile int32u *)0x4000F02Cu) +#define TIM2_ARR_REG *((volatile int32u *)0x4000F02Cu) +#define TIM2_ARR_ADDR (0x4000F02Cu) +#define TIM2_ARR_RESET (0x0000FFFFu) + /* TIM_ARR field */ + #define TIM_ARR (0x0000FFFFu) + #define TIM_ARR_MASK (0x0000FFFFu) + #define TIM_ARR_BIT (0) + #define TIM_ARR_BITS (16) + +#define TIM2_CCR1 *((volatile int32u *)0x4000F034u) +#define TIM2_CCR1_REG *((volatile int32u *)0x4000F034u) +#define TIM2_CCR1_ADDR (0x4000F034u) +#define TIM2_CCR1_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_CCR2 *((volatile int32u *)0x4000F038u) +#define TIM2_CCR2_REG *((volatile int32u *)0x4000F038u) +#define TIM2_CCR2_ADDR (0x4000F038u) +#define TIM2_CCR2_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_CCR3 *((volatile int32u *)0x4000F03Cu) +#define TIM2_CCR3_REG *((volatile int32u *)0x4000F03Cu) +#define TIM2_CCR3_ADDR (0x4000F03Cu) +#define TIM2_CCR3_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_CCR4 *((volatile int32u *)0x4000F040u) +#define TIM2_CCR4_REG *((volatile int32u *)0x4000F040u) +#define TIM2_CCR4_ADDR (0x4000F040u) +#define TIM2_CCR4_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_OR *((volatile int32u *)0x4000F050u) +#define TIM2_OR_REG *((volatile int32u *)0x4000F050u) +#define TIM2_OR_ADDR (0x4000F050u) +#define TIM2_OR_RESET (0x00000000u) + /* TIM_REMAPC4 field */ + #define TIM_REMAPC4 (0x00000080u) + #define TIM_REMAPC4_MASK (0x00000080u) + #define TIM_REMAPC4_BIT (7) + #define TIM_REMAPC4_BITS (1) + /* TIM_REMAPC3 field */ + #define TIM_REMAPC3 (0x00000040u) + #define TIM_REMAPC3_MASK (0x00000040u) + #define TIM_REMAPC3_BIT (6) + #define TIM_REMAPC3_BITS (1) + /* TIM_REMAPC2 field */ + #define TIM_REMAPC2 (0x00000020u) + #define TIM_REMAPC2_MASK (0x00000020u) + #define TIM_REMAPC2_BIT (5) + #define TIM_REMAPC2_BITS (1) + /* TIM_REMAPC1 field */ + #define TIM_REMAPC1 (0x00000010u) + #define TIM_REMAPC1_MASK (0x00000010u) + #define TIM_REMAPC1_BIT (4) + #define TIM_REMAPC1_BITS (1) + /* TIM_ORRSVD field */ + #define TIM_ORRSVD (0x00000008u) + #define TIM_ORRSVD_MASK (0x00000008u) + #define TIM_ORRSVD_BIT (3) + #define TIM_ORRSVD_BITS (1) + /* TIM_CLKMSKEN field */ + #define TIM_CLKMSKEN (0x00000004u) + #define TIM_CLKMSKEN_MASK (0x00000004u) + #define TIM_CLKMSKEN_BIT (2) + #define TIM_CLKMSKEN_BITS (1) + /* TIM1_EXTRIGSEL field */ + #define TIM1_EXTRIGSEL (0x00000003u) + #define TIM1_EXTRIGSEL_MASK (0x00000003u) + #define TIM1_EXTRIGSEL_BIT (0) + #define TIM1_EXTRIGSEL_BITS (2) + +/* EXT_RAM block */ +#define DATA_EXT_RAM_BASE (0x60000000u) +#define DATA_EXT_RAM_END (0x9FFFFFFFu) +#define DATA_EXT_RAM_SIZE (DATA_EXT_RAM_END - DATA_EXT_RAM_BASE + 1) + +/* EXT_DEVICE block */ +#define DATA_EXT_DEVICE_BASE (0xA0000000u) +#define DATA_EXT_DEVICE_END (0xDFFFFFFFu) +#define DATA_EXT_DEVICE_SIZE (DATA_EXT_DEVICE_END - DATA_EXT_DEVICE_BASE + 1) + +/* ITM block */ +#define DATA_ITM_BASE (0xE0000000u) +#define DATA_ITM_END (0xE0000FFFu) +#define DATA_ITM_SIZE (DATA_ITM_END - DATA_ITM_BASE + 1) + +#define ITM_SP0 *((volatile int32u *)0xE0000000u) +#define ITM_SP0_REG *((volatile int32u *)0xE0000000u) +#define ITM_SP0_ADDR (0xE0000000u) +#define ITM_SP0_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP0_FIFOREADY (0x00000001u) + #define ITM_SP0_FIFOREADY_MASK (0x00000001u) + #define ITM_SP0_FIFOREADY_BIT (0) + #define ITM_SP0_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP0_STIMULUS (0xFFFFFFFFu) + #define ITM_SP0_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP0_STIMULUS_BIT (0) + #define ITM_SP0_STIMULUS_BITS (32) + +#define ITM_SP1 *((volatile int32u *)0xE0000004u) +#define ITM_SP1_REG *((volatile int32u *)0xE0000004u) +#define ITM_SP1_ADDR (0xE0000004u) +#define ITM_SP1_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP1_FIFOREADY (0x00000001u) + #define ITM_SP1_FIFOREADY_MASK (0x00000001u) + #define ITM_SP1_FIFOREADY_BIT (0) + #define ITM_SP1_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP1_STIMULUS (0xFFFFFFFFu) + #define ITM_SP1_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP1_STIMULUS_BIT (0) + #define ITM_SP1_STIMULUS_BITS (32) + +#define ITM_SP2 *((volatile int32u *)0xE0000008u) +#define ITM_SP2_REG *((volatile int32u *)0xE0000008u) +#define ITM_SP2_ADDR (0xE0000008u) +#define ITM_SP2_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP2_FIFOREADY (0x00000001u) + #define ITM_SP2_FIFOREADY_MASK (0x00000001u) + #define ITM_SP2_FIFOREADY_BIT (0) + #define ITM_SP2_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP2_STIMULUS (0xFFFFFFFFu) + #define ITM_SP2_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP2_STIMULUS_BIT (0) + #define ITM_SP2_STIMULUS_BITS (32) + +#define ITM_SP3 *((volatile int32u *)0xE000000Cu) +#define ITM_SP3_REG *((volatile int32u *)0xE000000Cu) +#define ITM_SP3_ADDR (0xE000000Cu) +#define ITM_SP3_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP3_FIFOREADY (0x00000001u) + #define ITM_SP3_FIFOREADY_MASK (0x00000001u) + #define ITM_SP3_FIFOREADY_BIT (0) + #define ITM_SP3_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP3_STIMULUS (0xFFFFFFFFu) + #define ITM_SP3_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP3_STIMULUS_BIT (0) + #define ITM_SP3_STIMULUS_BITS (32) + +#define ITM_SP4 *((volatile int32u *)0xE0000010u) +#define ITM_SP4_REG *((volatile int32u *)0xE0000010u) +#define ITM_SP4_ADDR (0xE0000010u) +#define ITM_SP4_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP4_FIFOREADY (0x00000001u) + #define ITM_SP4_FIFOREADY_MASK (0x00000001u) + #define ITM_SP4_FIFOREADY_BIT (0) + #define ITM_SP4_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP4_STIMULUS (0xFFFFFFFFu) + #define ITM_SP4_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP4_STIMULUS_BIT (0) + #define ITM_SP4_STIMULUS_BITS (32) + +#define ITM_SP5 *((volatile int32u *)0xE0000014u) +#define ITM_SP5_REG *((volatile int32u *)0xE0000014u) +#define ITM_SP5_ADDR (0xE0000014u) +#define ITM_SP5_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP5_FIFOREADY (0x00000001u) + #define ITM_SP5_FIFOREADY_MASK (0x00000001u) + #define ITM_SP5_FIFOREADY_BIT (0) + #define ITM_SP5_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP5_STIMULUS (0xFFFFFFFFu) + #define ITM_SP5_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP5_STIMULUS_BIT (0) + #define ITM_SP5_STIMULUS_BITS (32) + +#define ITM_SP6 *((volatile int32u *)0xE0000018u) +#define ITM_SP6_REG *((volatile int32u *)0xE0000018u) +#define ITM_SP6_ADDR (0xE0000018u) +#define ITM_SP6_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP6_FIFOREADY (0x00000001u) + #define ITM_SP6_FIFOREADY_MASK (0x00000001u) + #define ITM_SP6_FIFOREADY_BIT (0) + #define ITM_SP6_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP6_STIMULUS (0xFFFFFFFFu) + #define ITM_SP6_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP6_STIMULUS_BIT (0) + #define ITM_SP6_STIMULUS_BITS (32) + +#define ITM_SP7 *((volatile int32u *)0xE000001Cu) +#define ITM_SP7_REG *((volatile int32u *)0xE000001Cu) +#define ITM_SP7_ADDR (0xE000001Cu) +#define ITM_SP7_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP7_FIFOREADY (0x00000001u) + #define ITM_SP7_FIFOREADY_MASK (0x00000001u) + #define ITM_SP7_FIFOREADY_BIT (0) + #define ITM_SP7_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP7_STIMULUS (0xFFFFFFFFu) + #define ITM_SP7_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP7_STIMULUS_BIT (0) + #define ITM_SP7_STIMULUS_BITS (32) + +#define ITM_SP8 *((volatile int32u *)0xE0000020u) +#define ITM_SP8_REG *((volatile int32u *)0xE0000020u) +#define ITM_SP8_ADDR (0xE0000020u) +#define ITM_SP8_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP8_FIFOREADY (0x00000001u) + #define ITM_SP8_FIFOREADY_MASK (0x00000001u) + #define ITM_SP8_FIFOREADY_BIT (0) + #define ITM_SP8_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP8_STIMULUS (0xFFFFFFFFu) + #define ITM_SP8_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP8_STIMULUS_BIT (0) + #define ITM_SP8_STIMULUS_BITS (32) + +#define ITM_SP9 *((volatile int32u *)0xE0000024u) +#define ITM_SP9_REG *((volatile int32u *)0xE0000024u) +#define ITM_SP9_ADDR (0xE0000024u) +#define ITM_SP9_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP9_FIFOREADY (0x00000001u) + #define ITM_SP9_FIFOREADY_MASK (0x00000001u) + #define ITM_SP9_FIFOREADY_BIT (0) + #define ITM_SP9_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP9_STIMULUS (0xFFFFFFFFu) + #define ITM_SP9_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP9_STIMULUS_BIT (0) + #define ITM_SP9_STIMULUS_BITS (32) + +#define ITM_SP10 *((volatile int32u *)0xE0000028u) +#define ITM_SP10_REG *((volatile int32u *)0xE0000028u) +#define ITM_SP10_ADDR (0xE0000028u) +#define ITM_SP10_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP10_FIFOREADY (0x00000001u) + #define ITM_SP10_FIFOREADY_MASK (0x00000001u) + #define ITM_SP10_FIFOREADY_BIT (0) + #define ITM_SP10_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP10_STIMULUS (0xFFFFFFFFu) + #define ITM_SP10_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP10_STIMULUS_BIT (0) + #define ITM_SP10_STIMULUS_BITS (32) + +#define ITM_SP11 *((volatile int32u *)0xE000002Cu) +#define ITM_SP11_REG *((volatile int32u *)0xE000002Cu) +#define ITM_SP11_ADDR (0xE000002Cu) +#define ITM_SP11_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP11_FIFOREADY (0x00000001u) + #define ITM_SP11_FIFOREADY_MASK (0x00000001u) + #define ITM_SP11_FIFOREADY_BIT (0) + #define ITM_SP11_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP11_STIMULUS (0xFFFFFFFFu) + #define ITM_SP11_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP11_STIMULUS_BIT (0) + #define ITM_SP11_STIMULUS_BITS (32) + +#define ITM_SP12 *((volatile int32u *)0xE0000030u) +#define ITM_SP12_REG *((volatile int32u *)0xE0000030u) +#define ITM_SP12_ADDR (0xE0000030u) +#define ITM_SP12_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP12_FIFOREADY (0x00000001u) + #define ITM_SP12_FIFOREADY_MASK (0x00000001u) + #define ITM_SP12_FIFOREADY_BIT (0) + #define ITM_SP12_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP12_STIMULUS (0xFFFFFFFFu) + #define ITM_SP12_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP12_STIMULUS_BIT (0) + #define ITM_SP12_STIMULUS_BITS (32) + +#define ITM_SP13 *((volatile int32u *)0xE0000034u) +#define ITM_SP13_REG *((volatile int32u *)0xE0000034u) +#define ITM_SP13_ADDR (0xE0000034u) +#define ITM_SP13_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP13_FIFOREADY (0x00000001u) + #define ITM_SP13_FIFOREADY_MASK (0x00000001u) + #define ITM_SP13_FIFOREADY_BIT (0) + #define ITM_SP13_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP13_STIMULUS (0xFFFFFFFFu) + #define ITM_SP13_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP13_STIMULUS_BIT (0) + #define ITM_SP13_STIMULUS_BITS (32) + +#define ITM_SP14 *((volatile int32u *)0xE0000038u) +#define ITM_SP14_REG *((volatile int32u *)0xE0000038u) +#define ITM_SP14_ADDR (0xE0000038u) +#define ITM_SP14_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP14_FIFOREADY (0x00000001u) + #define ITM_SP14_FIFOREADY_MASK (0x00000001u) + #define ITM_SP14_FIFOREADY_BIT (0) + #define ITM_SP14_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP14_STIMULUS (0xFFFFFFFFu) + #define ITM_SP14_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP14_STIMULUS_BIT (0) + #define ITM_SP14_STIMULUS_BITS (32) + +#define ITM_SP15 *((volatile int32u *)0xE000003Cu) +#define ITM_SP15_REG *((volatile int32u *)0xE000003Cu) +#define ITM_SP15_ADDR (0xE000003Cu) +#define ITM_SP15_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP15_FIFOREADY (0x00000001u) + #define ITM_SP15_FIFOREADY_MASK (0x00000001u) + #define ITM_SP15_FIFOREADY_BIT (0) + #define ITM_SP15_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP15_STIMULUS (0xFFFFFFFFu) + #define ITM_SP15_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP15_STIMULUS_BIT (0) + #define ITM_SP15_STIMULUS_BITS (32) + +#define ITM_SP16 *((volatile int32u *)0xE0000040u) +#define ITM_SP16_REG *((volatile int32u *)0xE0000040u) +#define ITM_SP16_ADDR (0xE0000040u) +#define ITM_SP16_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP16_FIFOREADY (0x00000001u) + #define ITM_SP16_FIFOREADY_MASK (0x00000001u) + #define ITM_SP16_FIFOREADY_BIT (0) + #define ITM_SP16_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP16_STIMULUS (0xFFFFFFFFu) + #define ITM_SP16_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP16_STIMULUS_BIT (0) + #define ITM_SP16_STIMULUS_BITS (32) + +#define ITM_SP17 *((volatile int32u *)0xE0000044u) +#define ITM_SP17_REG *((volatile int32u *)0xE0000044u) +#define ITM_SP17_ADDR (0xE0000044u) +#define ITM_SP17_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP17_FIFOREADY (0x00000001u) + #define ITM_SP17_FIFOREADY_MASK (0x00000001u) + #define ITM_SP17_FIFOREADY_BIT (0) + #define ITM_SP17_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP17_STIMULUS (0xFFFFFFFFu) + #define ITM_SP17_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP17_STIMULUS_BIT (0) + #define ITM_SP17_STIMULUS_BITS (32) + +#define ITM_SP18 *((volatile int32u *)0xE0000048u) +#define ITM_SP18_REG *((volatile int32u *)0xE0000048u) +#define ITM_SP18_ADDR (0xE0000048u) +#define ITM_SP18_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP18_FIFOREADY (0x00000001u) + #define ITM_SP18_FIFOREADY_MASK (0x00000001u) + #define ITM_SP18_FIFOREADY_BIT (0) + #define ITM_SP18_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP18_STIMULUS (0xFFFFFFFFu) + #define ITM_SP18_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP18_STIMULUS_BIT (0) + #define ITM_SP18_STIMULUS_BITS (32) + +#define ITM_SP19 *((volatile int32u *)0xE000004Cu) +#define ITM_SP19_REG *((volatile int32u *)0xE000004Cu) +#define ITM_SP19_ADDR (0xE000004Cu) +#define ITM_SP19_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP19_FIFOREADY (0x00000001u) + #define ITM_SP19_FIFOREADY_MASK (0x00000001u) + #define ITM_SP19_FIFOREADY_BIT (0) + #define ITM_SP19_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP19_STIMULUS (0xFFFFFFFFu) + #define ITM_SP19_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP19_STIMULUS_BIT (0) + #define ITM_SP19_STIMULUS_BITS (32) + +#define ITM_SP20 *((volatile int32u *)0xE0000050u) +#define ITM_SP20_REG *((volatile int32u *)0xE0000050u) +#define ITM_SP20_ADDR (0xE0000050u) +#define ITM_SP20_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP20_FIFOREADY (0x00000001u) + #define ITM_SP20_FIFOREADY_MASK (0x00000001u) + #define ITM_SP20_FIFOREADY_BIT (0) + #define ITM_SP20_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP20_STIMULUS (0xFFFFFFFFu) + #define ITM_SP20_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP20_STIMULUS_BIT (0) + #define ITM_SP20_STIMULUS_BITS (32) + +#define ITM_SP21 *((volatile int32u *)0xE0000054u) +#define ITM_SP21_REG *((volatile int32u *)0xE0000054u) +#define ITM_SP21_ADDR (0xE0000054u) +#define ITM_SP21_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP21_FIFOREADY (0x00000001u) + #define ITM_SP21_FIFOREADY_MASK (0x00000001u) + #define ITM_SP21_FIFOREADY_BIT (0) + #define ITM_SP21_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP21_STIMULUS (0xFFFFFFFFu) + #define ITM_SP21_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP21_STIMULUS_BIT (0) + #define ITM_SP21_STIMULUS_BITS (32) + +#define ITM_SP22 *((volatile int32u *)0xE0000058u) +#define ITM_SP22_REG *((volatile int32u *)0xE0000058u) +#define ITM_SP22_ADDR (0xE0000058u) +#define ITM_SP22_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP22_FIFOREADY (0x00000001u) + #define ITM_SP22_FIFOREADY_MASK (0x00000001u) + #define ITM_SP22_FIFOREADY_BIT (0) + #define ITM_SP22_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP22_STIMULUS (0xFFFFFFFFu) + #define ITM_SP22_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP22_STIMULUS_BIT (0) + #define ITM_SP22_STIMULUS_BITS (32) + +#define ITM_SP23 *((volatile int32u *)0xE000005Cu) +#define ITM_SP23_REG *((volatile int32u *)0xE000005Cu) +#define ITM_SP23_ADDR (0xE000005Cu) +#define ITM_SP23_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP23_FIFOREADY (0x00000001u) + #define ITM_SP23_FIFOREADY_MASK (0x00000001u) + #define ITM_SP23_FIFOREADY_BIT (0) + #define ITM_SP23_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP23_STIMULUS (0xFFFFFFFFu) + #define ITM_SP23_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP23_STIMULUS_BIT (0) + #define ITM_SP23_STIMULUS_BITS (32) + +#define ITM_SP24 *((volatile int32u *)0xE0000060u) +#define ITM_SP24_REG *((volatile int32u *)0xE0000060u) +#define ITM_SP24_ADDR (0xE0000060u) +#define ITM_SP24_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP24_FIFOREADY (0x00000001u) + #define ITM_SP24_FIFOREADY_MASK (0x00000001u) + #define ITM_SP24_FIFOREADY_BIT (0) + #define ITM_SP24_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP24_STIMULUS (0xFFFFFFFFu) + #define ITM_SP24_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP24_STIMULUS_BIT (0) + #define ITM_SP24_STIMULUS_BITS (32) + +#define ITM_SP25 *((volatile int32u *)0xE0000064u) +#define ITM_SP25_REG *((volatile int32u *)0xE0000064u) +#define ITM_SP25_ADDR (0xE0000064u) +#define ITM_SP25_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP25_FIFOREADY (0x00000001u) + #define ITM_SP25_FIFOREADY_MASK (0x00000001u) + #define ITM_SP25_FIFOREADY_BIT (0) + #define ITM_SP25_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP25_STIMULUS (0xFFFFFFFFu) + #define ITM_SP25_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP25_STIMULUS_BIT (0) + #define ITM_SP25_STIMULUS_BITS (32) + +#define ITM_SP26 *((volatile int32u *)0xE0000068u) +#define ITM_SP26_REG *((volatile int32u *)0xE0000068u) +#define ITM_SP26_ADDR (0xE0000068u) +#define ITM_SP26_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP26_FIFOREADY (0x00000001u) + #define ITM_SP26_FIFOREADY_MASK (0x00000001u) + #define ITM_SP26_FIFOREADY_BIT (0) + #define ITM_SP26_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP26_STIMULUS (0xFFFFFFFFu) + #define ITM_SP26_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP26_STIMULUS_BIT (0) + #define ITM_SP26_STIMULUS_BITS (32) + +#define ITM_SP27 *((volatile int32u *)0xE000006Cu) +#define ITM_SP27_REG *((volatile int32u *)0xE000006Cu) +#define ITM_SP27_ADDR (0xE000006Cu) +#define ITM_SP27_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP27_FIFOREADY (0x00000001u) + #define ITM_SP27_FIFOREADY_MASK (0x00000001u) + #define ITM_SP27_FIFOREADY_BIT (0) + #define ITM_SP27_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP27_STIMULUS (0xFFFFFFFFu) + #define ITM_SP27_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP27_STIMULUS_BIT (0) + #define ITM_SP27_STIMULUS_BITS (32) + +#define ITM_SP28 *((volatile int32u *)0xE0000070u) +#define ITM_SP28_REG *((volatile int32u *)0xE0000070u) +#define ITM_SP28_ADDR (0xE0000070u) +#define ITM_SP28_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP28_FIFOREADY (0x00000001u) + #define ITM_SP28_FIFOREADY_MASK (0x00000001u) + #define ITM_SP28_FIFOREADY_BIT (0) + #define ITM_SP28_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP28_STIMULUS (0xFFFFFFFFu) + #define ITM_SP28_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP28_STIMULUS_BIT (0) + #define ITM_SP28_STIMULUS_BITS (32) + +#define ITM_SP29 *((volatile int32u *)0xE0000074u) +#define ITM_SP29_REG *((volatile int32u *)0xE0000074u) +#define ITM_SP29_ADDR (0xE0000074u) +#define ITM_SP29_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP29_FIFOREADY (0x00000001u) + #define ITM_SP29_FIFOREADY_MASK (0x00000001u) + #define ITM_SP29_FIFOREADY_BIT (0) + #define ITM_SP29_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP29_STIMULUS (0xFFFFFFFFu) + #define ITM_SP29_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP29_STIMULUS_BIT (0) + #define ITM_SP29_STIMULUS_BITS (32) + +#define ITM_SP30 *((volatile int32u *)0xE0000078u) +#define ITM_SP30_REG *((volatile int32u *)0xE0000078u) +#define ITM_SP30_ADDR (0xE0000078u) +#define ITM_SP30_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP30_FIFOREADY (0x00000001u) + #define ITM_SP30_FIFOREADY_MASK (0x00000001u) + #define ITM_SP30_FIFOREADY_BIT (0) + #define ITM_SP30_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP30_STIMULUS (0xFFFFFFFFu) + #define ITM_SP30_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP30_STIMULUS_BIT (0) + #define ITM_SP30_STIMULUS_BITS (32) + +#define ITM_SP31 *((volatile int32u *)0xE000007Cu) +#define ITM_SP31_REG *((volatile int32u *)0xE000007Cu) +#define ITM_SP31_ADDR (0xE000007Cu) +#define ITM_SP31_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP31_FIFOREADY (0x00000001u) + #define ITM_SP31_FIFOREADY_MASK (0x00000001u) + #define ITM_SP31_FIFOREADY_BIT (0) + #define ITM_SP31_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP31_STIMULUS (0xFFFFFFFFu) + #define ITM_SP31_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP31_STIMULUS_BIT (0) + #define ITM_SP31_STIMULUS_BITS (32) + +#define ITM_TER *((volatile int32u *)0xE0000E00u) +#define ITM_TER_REG *((volatile int32u *)0xE0000E00u) +#define ITM_TER_ADDR (0xE0000E00u) +#define ITM_TER_RESET (0x00000000u) + /* STIMENA field */ + #define ITM_TER_STIMENA (0xFFFFFFFFu) + #define ITM_TER_STIMENA_MASK (0xFFFFFFFFu) + #define ITM_TER_STIMENA_BIT (0) + #define ITM_TER_STIMENA_BITS (32) + +#define ITM_TPR *((volatile int32u *)0xE0000E40u) +#define ITM_TPR_REG *((volatile int32u *)0xE0000E40u) +#define ITM_TPR_ADDR (0xE0000E40u) +#define ITM_TPR_RESET (0x00000000u) + /* PRIVMASK field */ + #define ITM_TPR_PRIVMASK (0x0000000Fu) + #define ITM_TPR_PRIVMASK_MASK (0x0000000Fu) + #define ITM_TPR_PRIVMASK_BIT (0) + #define ITM_TPR_PRIVMASK_BITS (4) + +#define ITM_TCR *((volatile int32u *)0xE0000E80u) +#define ITM_TCR_REG *((volatile int32u *)0xE0000E80u) +#define ITM_TCR_ADDR (0xE0000E80u) +#define ITM_TCR_RESET (0x00000000u) + /* BUSY field */ + #define ITM_TCR_BUSY (0x00800000u) + #define ITM_TCR_BUSY_MASK (0x00800000u) + #define ITM_TCR_BUSY_BIT (23) + #define ITM_TCR_BUSY_BITS (1) + /* ATBID field */ + #define ITM_TCR_ATBID (0x007F0000u) + #define ITM_TCR_ATBID_MASK (0x007F0000u) + #define ITM_TCR_ATBID_BIT (16) + #define ITM_TCR_ATBID_BITS (7) + /* TSPRESCALE field */ + #define ITM_TCR_TSPRESCALE (0x00000300u) + #define ITM_TCR_TSPRESCALE_MASK (0x00000300u) + #define ITM_TCR_TSPRESCALE_BIT (8) + #define ITM_TCR_TSPRESCALE_BITS (2) + /* SWOENA field */ + #define ITM_TCR_SWOENA (0x00000010u) + #define ITM_TCR_SWOENA_MASK (0x00000010u) + #define ITM_TCR_SWOENA_BIT (4) + #define ITM_TCR_SWOENA_BITS (1) + /* DWTENA field */ + #define ITM_TCR_DWTENA (0x00000008u) + #define ITM_TCR_DWTENA_MASK (0x00000008u) + #define ITM_TCR_DWTENA_BIT (3) + #define ITM_TCR_DWTENA_BITS (1) + /* SYNCENA field */ + #define ITM_TCR_SYNCENA (0x00000004u) + #define ITM_TCR_SYNCENA_MASK (0x00000004u) + #define ITM_TCR_SYNCENA_BIT (2) + #define ITM_TCR_SYNCENA_BITS (1) + /* TSENA field */ + #define ITM_TCR_TSENA (0x00000002u) + #define ITM_TCR_TSENA_MASK (0x00000002u) + #define ITM_TCR_TSENA_BIT (1) + #define ITM_TCR_TSENA_BITS (1) + /* ITMEN field */ + #define ITM_TCR_ITMEN (0x00000001u) + #define ITM_TCR_ITMEN_MASK (0x00000001u) + #define ITM_TCR_ITMEN_BIT (0) + #define ITM_TCR_ITMEN_BITS (1) + +#define ITM_IW *((volatile int32u *)0xE0000EF8u) +#define ITM_IW_REG *((volatile int32u *)0xE0000EF8u) +#define ITM_IW_ADDR (0xE0000EF8u) +#define ITM_IW_RESET (0x00000000u) + /* ATVALIDM field */ + #define ITM_IW_ATVALIDM (0x00000001u) + #define ITM_IW_ATVALIDM_MASK (0x00000001u) + #define ITM_IW_ATVALIDM_BIT (0) + #define ITM_IW_ATVALIDM_BITS (1) + +#define ITM_IR *((volatile int32u *)0xE0000EFCu) +#define ITM_IR_REG *((volatile int32u *)0xE0000EFCu) +#define ITM_IR_ADDR (0xE0000EFCu) +#define ITM_IR_RESET (0x00000000u) + /* ATREADYM field */ + #define ITM_IR_ATREADYM (0x00000001u) + #define ITM_IR_ATREADYM_MASK (0x00000001u) + #define ITM_IR_ATREADYM_BIT (0) + #define ITM_IR_ATREADYM_BITS (1) + +#define ITM_IMC *((volatile int32u *)0xE0000F00u) +#define ITM_IMC_REG *((volatile int32u *)0xE0000F00u) +#define ITM_IMC_ADDR (0xE0000F00u) +#define ITM_IMC_RESET (0x00000000u) + /* INTEGRATION field */ + #define ITM_IMC_INTEGRATION (0x00000001u) + #define ITM_IMC_INTEGRATION_MASK (0x00000001u) + #define ITM_IMC_INTEGRATION_BIT (0) + #define ITM_IMC_INTEGRATION_BITS (1) + +#define ITM_LA *((volatile int32u *)0xE0000FB0u) +#define ITM_LA_REG *((volatile int32u *)0xE0000FB0u) +#define ITM_LA_ADDR (0xE0000FB0u) +#define ITM_LA_RESET (0x00000000u) + /* LOCKACC field */ + #define ITM_LA_LOCKACC (0xFFFFFFFFu) + #define ITM_LA_LOCKACC_MASK (0xFFFFFFFFu) + #define ITM_LA_LOCKACC_BIT (0) + #define ITM_LA_LOCKACC_BITS (32) + +#define ITM_LS *((volatile int32u *)0xE0000FB4u) +#define ITM_LS_REG *((volatile int32u *)0xE0000FB4u) +#define ITM_LS_ADDR (0xE0000FB4u) +#define ITM_LS_RESET (0x00000000u) + /* BYTEACC field */ + #define ITM_LS_BYTEACC (0x00000004u) + #define ITM_LS_BYTEACC_MASK (0x00000004u) + #define ITM_LS_BYTEACC_BIT (2) + #define ITM_LS_BYTEACC_BITS (1) + /* ACCESS field */ + #define ITM_LS_ACCESS (0x00000002u) + #define ITM_LS_ACCESS_MASK (0x00000002u) + #define ITM_LS_ACCESS_BIT (1) + #define ITM_LS_ACCESS_BITS (1) + /* PRESENT field */ + #define ITM_LS_PRESENT (0x00000001u) + #define ITM_LS_PRESENT_MASK (0x00000001u) + #define ITM_LS_PRESENT_BIT (0) + #define ITM_LS_PRESENT_BITS (1) + +#define ITM_PERIPHID4 *((volatile int32u *)0xE0000FD0u) +#define ITM_PERIPHID4_REG *((volatile int32u *)0xE0000FD0u) +#define ITM_PERIPHID4_ADDR (0xE0000FD0u) +#define ITM_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define ITM_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID4_PERIPHID_BIT (0) + #define ITM_PERIPHID4_PERIPHID_BITS (32) + +#define ITM_PERIPHID5 *((volatile int32u *)0xE0000FD4u) +#define ITM_PERIPHID5_REG *((volatile int32u *)0xE0000FD4u) +#define ITM_PERIPHID5_ADDR (0xE0000FD4u) +#define ITM_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID5_PERIPHID_BIT (0) + #define ITM_PERIPHID5_PERIPHID_BITS (32) + +#define ITM_PERIPHID6 *((volatile int32u *)0xE0000FD8u) +#define ITM_PERIPHID6_REG *((volatile int32u *)0xE0000FD8u) +#define ITM_PERIPHID6_ADDR (0xE0000FD8u) +#define ITM_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID6_PERIPHID_BIT (0) + #define ITM_PERIPHID6_PERIPHID_BITS (32) + +#define ITM_PERIPHID7 *((volatile int32u *)0xE0000FDCu) +#define ITM_PERIPHID7_REG *((volatile int32u *)0xE0000FDCu) +#define ITM_PERIPHID7_ADDR (0xE0000FDCu) +#define ITM_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID7_PERIPHID_BIT (0) + #define ITM_PERIPHID7_PERIPHID_BITS (32) + +#define ITM_PERIPHID0 *((volatile int32u *)0xE0000FE0u) +#define ITM_PERIPHID0_REG *((volatile int32u *)0xE0000FE0u) +#define ITM_PERIPHID0_ADDR (0xE0000FE0u) +#define ITM_PERIPHID0_RESET (0x00000001u) + /* PERIPHID field */ + #define ITM_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID0_PERIPHID_BIT (0) + #define ITM_PERIPHID0_PERIPHID_BITS (32) + +#define ITM_PERIPHID1 *((volatile int32u *)0xE0000FE4u) +#define ITM_PERIPHID1_REG *((volatile int32u *)0xE0000FE4u) +#define ITM_PERIPHID1_ADDR (0xE0000FE4u) +#define ITM_PERIPHID1_RESET (0x000000B0u) + /* PERIPHID field */ + #define ITM_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID1_PERIPHID_BIT (0) + #define ITM_PERIPHID1_PERIPHID_BITS (32) + +#define ITM_PERIPHID2 *((volatile int32u *)0xE0000FE8u) +#define ITM_PERIPHID2_REG *((volatile int32u *)0xE0000FE8u) +#define ITM_PERIPHID2_ADDR (0xE0000FE8u) +#define ITM_PERIPHID2_RESET (0x0000001Bu) + /* PERIPHID field */ + #define ITM_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID2_PERIPHID_BIT (0) + #define ITM_PERIPHID2_PERIPHID_BITS (32) + +#define ITM_PERIPHID3 *((volatile int32u *)0xE0000FECu) +#define ITM_PERIPHID3_REG *((volatile int32u *)0xE0000FECu) +#define ITM_PERIPHID3_ADDR (0xE0000FECu) +#define ITM_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID3_PERIPHID_BIT (0) + #define ITM_PERIPHID3_PERIPHID_BITS (32) + +#define ITM_CELLID0 *((volatile int32u *)0xE0000FF0u) +#define ITM_CELLID0_REG *((volatile int32u *)0xE0000FF0u) +#define ITM_CELLID0_ADDR (0xE0000FF0u) +#define ITM_CELLID0_RESET (0x0000000Du) + /* PERIPHID field */ + #define ITM_CELLID0_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID0_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID0_PERIPHID_BIT (0) + #define ITM_CELLID0_PERIPHID_BITS (32) + +#define ITM_CELLID1 *((volatile int32u *)0xE0000FF4u) +#define ITM_CELLID1_REG *((volatile int32u *)0xE0000FF4u) +#define ITM_CELLID1_ADDR (0xE0000FF4u) +#define ITM_CELLID1_RESET (0x000000E0u) + /* PERIPHID field */ + #define ITM_CELLID1_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID1_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID1_PERIPHID_BIT (0) + #define ITM_CELLID1_PERIPHID_BITS (32) + +#define ITM_CELLID2 *((volatile int32u *)0xE0000FF8u) +#define ITM_CELLID2_REG *((volatile int32u *)0xE0000FF8u) +#define ITM_CELLID2_ADDR (0xE0000FF8u) +#define ITM_CELLID2_RESET (0x00000005u) + /* PERIPHID field */ + #define ITM_CELLID2_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID2_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID2_PERIPHID_BIT (0) + #define ITM_CELLID2_PERIPHID_BITS (32) + +#define ITM_CELLID3 *((volatile int32u *)0xE0000FFCu) +#define ITM_CELLID3_REG *((volatile int32u *)0xE0000FFCu) +#define ITM_CELLID3_ADDR (0xE0000FFCu) +#define ITM_CELLID3_RESET (0x000000B1u) + /* PERIPHID field */ + #define ITM_CELLID3_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID3_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID3_PERIPHID_BIT (0) + #define ITM_CELLID3_PERIPHID_BITS (32) + +/* DWT block */ +#define DATA_DWT_BASE (0xE0001000u) +#define DATA_DWT_END (0xE0001FFFu) +#define DATA_DWT_SIZE (DATA_DWT_END - DATA_DWT_BASE + 1) + +#define DWT_CTRL *((volatile int32u *)0xE0001000u) +#define DWT_CTRL_REG *((volatile int32u *)0xE0001000u) +#define DWT_CTRL_ADDR (0xE0001000u) +#define DWT_CTRL_RESET (0x40000000u) + /* NUMCOMP field */ + #define DWT_CTRL_NUMCOMP (0xF0000000u) + #define DWT_CTRL_NUMCOMP_MASK (0xF0000000u) + #define DWT_CTRL_NUMCOMP_BIT (28) + #define DWT_CTRL_NUMCOMP_BITS (4) + /* CYCEVTENA field */ + #define DWT_CTRL_CYCEVTENA (0x00400000u) + #define DWT_CTRL_CYCEVTENA_MASK (0x00400000u) + #define DWT_CTRL_CYCEVTENA_BIT (22) + #define DWT_CTRL_CYCEVTENA_BITS (1) + /* FOLDEVTENA field */ + #define DWT_CTRL_FOLDEVTENA (0x00200000u) + #define DWT_CTRL_FOLDEVTENA_MASK (0x00200000u) + #define DWT_CTRL_FOLDEVTENA_BIT (21) + #define DWT_CTRL_FOLDEVTENA_BITS (1) + /* LSUEVTENA field */ + #define DWT_CTRL_LSUEVTENA (0x00100000u) + #define DWT_CTRL_LSUEVTENA_MASK (0x00100000u) + #define DWT_CTRL_LSUEVTENA_BIT (20) + #define DWT_CTRL_LSUEVTENA_BITS (1) + /* SLEEPEVTENA field */ + #define DWT_CTRL_SLEEPEVTENA (0x00080000u) + #define DWT_CTRL_SLEEPEVTENA_MASK (0x00080000u) + #define DWT_CTRL_SLEEPEVTENA_BIT (19) + #define DWT_CTRL_SLEEPEVTENA_BITS (1) + /* EXCEVTENA field */ + #define DWT_CTRL_EXCEVTENA (0x00040000u) + #define DWT_CTRL_EXCEVTENA_MASK (0x00040000u) + #define DWT_CTRL_EXCEVTENA_BIT (18) + #define DWT_CTRL_EXCEVTENA_BITS (1) + /* CPIEVTENA field */ + #define DWT_CTRL_CPIEVTENA (0x00020000u) + #define DWT_CTRL_CPIEVTENA_MASK (0x00020000u) + #define DWT_CTRL_CPIEVTENA_BIT (17) + #define DWT_CTRL_CPIEVTENA_BITS (1) + /* EXCTRCENA field */ + #define DWT_CTRL_EXCTRCENA (0x00010000u) + #define DWT_CTRL_EXCTRCENA_MASK (0x00010000u) + #define DWT_CTRL_EXCTRCENA_BIT (16) + #define DWT_CTRL_EXCTRCENA_BITS (1) + /* PCSAMPLEENA field */ + #define DWT_CTRL_PCSAMPLEENA (0x00001000u) + #define DWT_CTRL_PCSAMPLEENA_MASK (0x00001000u) + #define DWT_CTRL_PCSAMPLEENA_BIT (12) + #define DWT_CTRL_PCSAMPLEENA_BITS (1) + /* SYNCTAP field */ + #define DWT_CTRL_SYNCTAP (0x00000C00u) + #define DWT_CTRL_SYNCTAP_MASK (0x00000C00u) + #define DWT_CTRL_SYNCTAP_BIT (10) + #define DWT_CTRL_SYNCTAP_BITS (2) + /* CYCTAP field */ + #define DWT_CTRL_CYCTAP (0x00000200u) + #define DWT_CTRL_CYCTAP_MASK (0x00000200u) + #define DWT_CTRL_CYCTAP_BIT (9) + #define DWT_CTRL_CYCTAP_BITS (1) + /* POSTCNT field */ + #define DWT_CTRL_POSTCNT (0x000001E0u) + #define DWT_CTRL_POSTCNT_MASK (0x000001E0u) + #define DWT_CTRL_POSTCNT_BIT (5) + #define DWT_CTRL_POSTCNT_BITS (4) + /* POSTPRESET field */ + #define DWT_CTRL_POSTPRESET (0x0000001Eu) + #define DWT_CTRL_POSTPRESET_MASK (0x0000001Eu) + #define DWT_CTRL_POSTPRESET_BIT (1) + #define DWT_CTRL_POSTPRESET_BITS (4) + /* CYCCNTENA field */ + #define DWT_CTRL_CYCCNTENA (0x00000001u) + #define DWT_CTRL_CYCCNTENA_MASK (0x00000001u) + #define DWT_CTRL_CYCCNTENA_BIT (0) + #define DWT_CTRL_CYCCNTENA_BITS (1) + +#define DWT_CYCCNT *((volatile int32u *)0xE0001004u) +#define DWT_CYCCNT_REG *((volatile int32u *)0xE0001004u) +#define DWT_CYCCNT_ADDR (0xE0001004u) +#define DWT_CYCCNT_RESET (0x00000000u) + /* CYCCNT field */ + #define DWT_CYCCNT_CYCCNT (0xFFFFFFFFu) + #define DWT_CYCCNT_CYCCNT_MASK (0xFFFFFFFFu) + #define DWT_CYCCNT_CYCCNT_BIT (0) + #define DWT_CYCCNT_CYCCNT_BITS (32) + +#define DWT_CPICNT *((volatile int32u *)0xE0001008u) +#define DWT_CPICNT_REG *((volatile int32u *)0xE0001008u) +#define DWT_CPICNT_ADDR (0xE0001008u) +#define DWT_CPICNT_RESET (0x00000000u) + /* CPICNT field */ + #define DWT_CPICNT_CPICNT (0x000000FFu) + #define DWT_CPICNT_CPICNT_MASK (0x000000FFu) + #define DWT_CPICNT_CPICNT_BIT (0) + #define DWT_CPICNT_CPICNT_BITS (8) + +#define DWT_EXCCNT *((volatile int32u *)0xE000100Cu) +#define DWT_EXCCNT_REG *((volatile int32u *)0xE000100Cu) +#define DWT_EXCCNT_ADDR (0xE000100Cu) +#define DWT_EXCCNT_RESET (0x00000000u) + /* EXCCNT field */ + #define DWT_EXCCNT_EXCCNT (0x000000FFu) + #define DWT_EXCCNT_EXCCNT_MASK (0x000000FFu) + #define DWT_EXCCNT_EXCCNT_BIT (0) + #define DWT_EXCCNT_EXCCNT_BITS (8) + +#define DWT_SLEEPCNT *((volatile int32u *)0xE0001010u) +#define DWT_SLEEPCNT_REG *((volatile int32u *)0xE0001010u) +#define DWT_SLEEPCNT_ADDR (0xE0001010u) +#define DWT_SLEEPCNT_RESET (0x00000000u) + /* SLEEPCNT field */ + #define DWT_SLEEPCNT_SLEEPCNT (0x000000FFu) + #define DWT_SLEEPCNT_SLEEPCNT_MASK (0x000000FFu) + #define DWT_SLEEPCNT_SLEEPCNT_BIT (0) + #define DWT_SLEEPCNT_SLEEPCNT_BITS (8) + +#define DWT_LSUCNT *((volatile int32u *)0xE0001014u) +#define DWT_LSUCNT_REG *((volatile int32u *)0xE0001014u) +#define DWT_LSUCNT_ADDR (0xE0001014u) +#define DWT_LSUCNT_RESET (0x00000000u) + /* CPICNT field */ + #define DWT_LSUCNT_CPICNT (0x000000FFu) + #define DWT_LSUCNT_CPICNT_MASK (0x000000FFu) + #define DWT_LSUCNT_CPICNT_BIT (0) + #define DWT_LSUCNT_CPICNT_BITS (8) + +#define DWT_FOLDCNT *((volatile int32u *)0xE0001018u) +#define DWT_FOLDCNT_REG *((volatile int32u *)0xE0001018u) +#define DWT_FOLDCNT_ADDR (0xE0001018u) +#define DWT_FOLDCNT_RESET (0x00000000u) + /* CPICNT field */ + #define DWT_FOLDCNT_CPICNT (0x000000FFu) + #define DWT_FOLDCNT_CPICNT_MASK (0x000000FFu) + #define DWT_FOLDCNT_CPICNT_BIT (0) + #define DWT_FOLDCNT_CPICNT_BITS (8) + +#define DWT_PCSR *((volatile int32u *)0xE000101Cu) +#define DWT_PCSR_REG *((volatile int32u *)0xE000101Cu) +#define DWT_PCSR_ADDR (0xE000101Cu) +#define DWT_PCSR_RESET (0x00000000u) + /* EIASAMPLE field */ + #define DWT_PCSR_EIASAMPLE (0xFFFFFFFFu) + #define DWT_PCSR_EIASAMPLE_MASK (0xFFFFFFFFu) + #define DWT_PCSR_EIASAMPLE_BIT (0) + #define DWT_PCSR_EIASAMPLE_BITS (32) + +#define DWT_COMP0 *((volatile int32u *)0xE0001020u) +#define DWT_COMP0_REG *((volatile int32u *)0xE0001020u) +#define DWT_COMP0_ADDR (0xE0001020u) +#define DWT_COMP0_RESET (0x00000000u) + /* COMP0 field */ + #define DWT_COMP0_COMP0 (0xFFFFFFFFu) + #define DWT_COMP0_COMP0_MASK (0xFFFFFFFFu) + #define DWT_COMP0_COMP0_BIT (0) + #define DWT_COMP0_COMP0_BITS (32) + +#define DWT_MASK0 *((volatile int32u *)0xE0001024u) +#define DWT_MASK0_REG *((volatile int32u *)0xE0001024u) +#define DWT_MASK0_ADDR (0xE0001024u) +#define DWT_MASK0_RESET (0x00000000u) + /* MASK0 field */ + #define DWT_MASK0_MASK0 (0x0000001Fu) + #define DWT_MASK0_MASK0_MASK (0x0000001Fu) + #define DWT_MASK0_MASK0_BIT (0) + #define DWT_MASK0_MASK0_BITS (5) + +#define DWT_FUNCTION0 *((volatile int32u *)0xE0001028u) +#define DWT_FUNCTION0_REG *((volatile int32u *)0xE0001028u) +#define DWT_FUNCTION0_ADDR (0xE0001028u) +#define DWT_FUNCTION0_RESET (0x00000000u) + /* MATCHED field */ + #define DWT_FUNCTION0_MATCHED (0x01000000u) + #define DWT_FUNCTION0_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION0_MATCHED_BIT (24) + #define DWT_FUNCTION0_MATCHED_BITS (1) + /* CYCMATCH field */ + #define DWT_FUNCTION0_CYCMATCH (0x00000080u) + #define DWT_FUNCTION0_CYCMATCH_MASK (0x00000080u) + #define DWT_FUNCTION0_CYCMATCH_BIT (7) + #define DWT_FUNCTION0_CYCMATCH_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION0_EMITRANGE (0x00000020u) + #define DWT_FUNCTION0_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION0_EMITRANGE_BIT (5) + #define DWT_FUNCTION0_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION0_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION0_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION0_FUNCTION_BIT (0) + #define DWT_FUNCTION0_FUNCTION_BITS (4) + +#define DWT_COMP1 *((volatile int32u *)0xE0001030u) +#define DWT_COMP1_REG *((volatile int32u *)0xE0001030u) +#define DWT_COMP1_ADDR (0xE0001030u) +#define DWT_COMP1_RESET (0x00000000u) + /* COMP1 field */ + #define DWT_COMP1_COMP1 (0xFFFFFFFFu) + #define DWT_COMP1_COMP1_MASK (0xFFFFFFFFu) + #define DWT_COMP1_COMP1_BIT (0) + #define DWT_COMP1_COMP1_BITS (32) + +#define DWT_MASK1 *((volatile int32u *)0xE0001034u) +#define DWT_MASK1_REG *((volatile int32u *)0xE0001034u) +#define DWT_MASK1_ADDR (0xE0001034u) +#define DWT_MASK1_RESET (0x00000000u) + /* MASK1 field */ + #define DWT_MASK1_MASK1 (0x0000001Fu) + #define DWT_MASK1_MASK1_MASK (0x0000001Fu) + #define DWT_MASK1_MASK1_BIT (0) + #define DWT_MASK1_MASK1_BITS (5) + +#define DWT_FUNCTION1 *((volatile int32u *)0xE0001038u) +#define DWT_FUNCTION1_REG *((volatile int32u *)0xE0001038u) +#define DWT_FUNCTION1_ADDR (0xE0001038u) +#define DWT_FUNCTION1_RESET (0x00000200u) + /* MATCHED field */ + #define DWT_FUNCTION1_MATCHED (0x01000000u) + #define DWT_FUNCTION1_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION1_MATCHED_BIT (24) + #define DWT_FUNCTION1_MATCHED_BITS (1) + /* DATAVADDR1 field */ + #define DWT_FUNCTION1_DATAVADDR1 (0x000F0000u) + #define DWT_FUNCTION1_DATAVADDR1_MASK (0x000F0000u) + #define DWT_FUNCTION1_DATAVADDR1_BIT (16) + #define DWT_FUNCTION1_DATAVADDR1_BITS (4) + /* DATAVADDR0 field */ + #define DWT_FUNCTION1_DATAVADDR0 (0x0000F000u) + #define DWT_FUNCTION1_DATAVADDR0_MASK (0x0000F000u) + #define DWT_FUNCTION1_DATAVADDR0_BIT (12) + #define DWT_FUNCTION1_DATAVADDR0_BITS (4) + /* DATAVSIZE field */ + #define DWT_FUNCTION1_DATAVSIZE (0x00000C00u) + #define DWT_FUNCTION1_DATAVSIZE_MASK (0x00000C00u) + #define DWT_FUNCTION1_DATAVSIZE_BIT (10) + #define DWT_FUNCTION1_DATAVSIZE_BITS (2) + /* LNK1ENA field */ + #define DWT_FUNCTION1_LNK1ENA (0x00000200u) + #define DWT_FUNCTION1_LNK1ENA_MASK (0x00000200u) + #define DWT_FUNCTION1_LNK1ENA_BIT (9) + #define DWT_FUNCTION1_LNK1ENA_BITS (1) + /* DATAVMATCH field */ + #define DWT_FUNCTION1_DATAVMATCH (0x00000100u) + #define DWT_FUNCTION1_DATAVMATCH_MASK (0x00000100u) + #define DWT_FUNCTION1_DATAVMATCH_BIT (8) + #define DWT_FUNCTION1_DATAVMATCH_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION1_EMITRANGE (0x00000020u) + #define DWT_FUNCTION1_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION1_EMITRANGE_BIT (5) + #define DWT_FUNCTION1_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION1_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION1_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION1_FUNCTION_BIT (0) + #define DWT_FUNCTION1_FUNCTION_BITS (4) + +#define DWT_COMP2 *((volatile int32u *)0xE0001040u) +#define DWT_COMP2_REG *((volatile int32u *)0xE0001040u) +#define DWT_COMP2_ADDR (0xE0001040u) +#define DWT_COMP2_RESET (0x00000000u) + /* COMP2 field */ + #define DWT_COMP2_COMP2 (0xFFFFFFFFu) + #define DWT_COMP2_COMP2_MASK (0xFFFFFFFFu) + #define DWT_COMP2_COMP2_BIT (0) + #define DWT_COMP2_COMP2_BITS (32) + +#define DWT_MASK2 *((volatile int32u *)0xE0001044u) +#define DWT_MASK2_REG *((volatile int32u *)0xE0001044u) +#define DWT_MASK2_ADDR (0xE0001044u) +#define DWT_MASK2_RESET (0x00000000u) + /* MASK2 field */ + #define DWT_MASK2_MASK2 (0x0000001Fu) + #define DWT_MASK2_MASK2_MASK (0x0000001Fu) + #define DWT_MASK2_MASK2_BIT (0) + #define DWT_MASK2_MASK2_BITS (5) + +#define DWT_FUNCTION2 *((volatile int32u *)0xE0001048u) +#define DWT_FUNCTION2_REG *((volatile int32u *)0xE0001048u) +#define DWT_FUNCTION2_ADDR (0xE0001048u) +#define DWT_FUNCTION2_RESET (0x00000000u) + /* MATCHED field */ + #define DWT_FUNCTION2_MATCHED (0x01000000u) + #define DWT_FUNCTION2_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION2_MATCHED_BIT (24) + #define DWT_FUNCTION2_MATCHED_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION2_EMITRANGE (0x00000020u) + #define DWT_FUNCTION2_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION2_EMITRANGE_BIT (5) + #define DWT_FUNCTION2_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION2_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION2_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION2_FUNCTION_BIT (0) + #define DWT_FUNCTION2_FUNCTION_BITS (4) + +#define DWT_COMP3 *((volatile int32u *)0xE0001050u) +#define DWT_COMP3_REG *((volatile int32u *)0xE0001050u) +#define DWT_COMP3_ADDR (0xE0001050u) +#define DWT_COMP3_RESET (0x00000000u) + /* COMP3 field */ + #define DWT_COMP3_COMP3 (0xFFFFFFFFu) + #define DWT_COMP3_COMP3_MASK (0xFFFFFFFFu) + #define DWT_COMP3_COMP3_BIT (0) + #define DWT_COMP3_COMP3_BITS (32) + +#define DWT_MASK3 *((volatile int32u *)0xE0001054u) +#define DWT_MASK3_REG *((volatile int32u *)0xE0001054u) +#define DWT_MASK3_ADDR (0xE0001054u) +#define DWT_MASK3_RESET (0x00000000u) + /* MASK3 field */ + #define DWT_MASK3_MASK3 (0x0000001Fu) + #define DWT_MASK3_MASK3_MASK (0x0000001Fu) + #define DWT_MASK3_MASK3_BIT (0) + #define DWT_MASK3_MASK3_BITS (5) + +#define DWT_FUNCTION3 *((volatile int32u *)0xE0001058u) +#define DWT_FUNCTION3_REG *((volatile int32u *)0xE0001058u) +#define DWT_FUNCTION3_ADDR (0xE0001058u) +#define DWT_FUNCTION3_RESET (0x00000000u) + /* MATCHED field */ + #define DWT_FUNCTION3_MATCHED (0x01000000u) + #define DWT_FUNCTION3_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION3_MATCHED_BIT (24) + #define DWT_FUNCTION3_MATCHED_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION3_EMITRANGE (0x00000020u) + #define DWT_FUNCTION3_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION3_EMITRANGE_BIT (5) + #define DWT_FUNCTION3_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION3_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION3_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION3_FUNCTION_BIT (0) + #define DWT_FUNCTION3_FUNCTION_BITS (4) + +#define DWT_PERIPHID4 *((volatile int32u *)0xE0001FD0u) +#define DWT_PERIPHID4_REG *((volatile int32u *)0xE0001FD0u) +#define DWT_PERIPHID4_ADDR (0xE0001FD0u) +#define DWT_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define DWT_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID4_PERIPHID_BIT (0) + #define DWT_PERIPHID4_PERIPHID_BITS (32) + +#define DWT_PERIPHID5 *((volatile int32u *)0xE0001FD4u) +#define DWT_PERIPHID5_REG *((volatile int32u *)0xE0001FD4u) +#define DWT_PERIPHID5_ADDR (0xE0001FD4u) +#define DWT_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID5_PERIPHID_BIT (0) + #define DWT_PERIPHID5_PERIPHID_BITS (32) + +#define DWT_PERIPHID6 *((volatile int32u *)0xE0001FD8u) +#define DWT_PERIPHID6_REG *((volatile int32u *)0xE0001FD8u) +#define DWT_PERIPHID6_ADDR (0xE0001FD8u) +#define DWT_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID6_PERIPHID_BIT (0) + #define DWT_PERIPHID6_PERIPHID_BITS (32) + +#define DWT_PERIPHID7 *((volatile int32u *)0xE0001FDCu) +#define DWT_PERIPHID7_REG *((volatile int32u *)0xE0001FDCu) +#define DWT_PERIPHID7_ADDR (0xE0001FDCu) +#define DWT_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID7_PERIPHID_BIT (0) + #define DWT_PERIPHID7_PERIPHID_BITS (32) + +#define DWT_PERIPHID0 *((volatile int32u *)0xE0001FE0u) +#define DWT_PERIPHID0_REG *((volatile int32u *)0xE0001FE0u) +#define DWT_PERIPHID0_ADDR (0xE0001FE0u) +#define DWT_PERIPHID0_RESET (0x00000002u) + /* PERIPHID field */ + #define DWT_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID0_PERIPHID_BIT (0) + #define DWT_PERIPHID0_PERIPHID_BITS (32) + +#define DWT_PERIPHID1 *((volatile int32u *)0xE0001FE4u) +#define DWT_PERIPHID1_REG *((volatile int32u *)0xE0001FE4u) +#define DWT_PERIPHID1_ADDR (0xE0001FE4u) +#define DWT_PERIPHID1_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID1_PERIPHID_BIT (0) + #define DWT_PERIPHID1_PERIPHID_BITS (32) + +#define DWT_PERIPHID2 *((volatile int32u *)0xE0001FE8u) +#define DWT_PERIPHID2_REG *((volatile int32u *)0xE0001FE8u) +#define DWT_PERIPHID2_ADDR (0xE0001FE8u) +#define DWT_PERIPHID2_RESET (0x0000001Bu) + /* PERIPHID field */ + #define DWT_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID2_PERIPHID_BIT (0) + #define DWT_PERIPHID2_PERIPHID_BITS (32) + +#define DWT_PERIPHID3 *((volatile int32u *)0xE0001FECu) +#define DWT_PERIPHID3_REG *((volatile int32u *)0xE0001FECu) +#define DWT_PERIPHID3_ADDR (0xE0001FECu) +#define DWT_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID3_PERIPHID_BIT (0) + #define DWT_PERIPHID3_PERIPHID_BITS (32) + +#define DWT_CELLID0 *((volatile int32u *)0xE0001FF0u) +#define DWT_CELLID0_REG *((volatile int32u *)0xE0001FF0u) +#define DWT_CELLID0_ADDR (0xE0001FF0u) +#define DWT_CELLID0_RESET (0x0000000Du) + /* CELLID field */ + #define DWT_CELLID0_CELLID (0xFFFFFFFFu) + #define DWT_CELLID0_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID0_CELLID_BIT (0) + #define DWT_CELLID0_CELLID_BITS (32) + +#define DWT_CELLID1 *((volatile int32u *)0xE0001FF4u) +#define DWT_CELLID1_REG *((volatile int32u *)0xE0001FF4u) +#define DWT_CELLID1_ADDR (0xE0001FF4u) +#define DWT_CELLID1_RESET (0x000000E0u) + /* CELLID field */ + #define DWT_CELLID1_CELLID (0xFFFFFFFFu) + #define DWT_CELLID1_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID1_CELLID_BIT (0) + #define DWT_CELLID1_CELLID_BITS (32) + +#define DWT_CELLID2 *((volatile int32u *)0xE0001FF8u) +#define DWT_CELLID2_REG *((volatile int32u *)0xE0001FF8u) +#define DWT_CELLID2_ADDR (0xE0001FF8u) +#define DWT_CELLID2_RESET (0x00000005u) + /* CELLID field */ + #define DWT_CELLID2_CELLID (0xFFFFFFFFu) + #define DWT_CELLID2_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID2_CELLID_BIT (0) + #define DWT_CELLID2_CELLID_BITS (32) + +#define DWT_CELLID3 *((volatile int32u *)0xE0001FFCu) +#define DWT_CELLID3_REG *((volatile int32u *)0xE0001FFCu) +#define DWT_CELLID3_ADDR (0xE0001FFCu) +#define DWT_CELLID3_RESET (0x000000B1u) + /* CELLID field */ + #define DWT_CELLID3_CELLID (0xFFFFFFFFu) + #define DWT_CELLID3_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID3_CELLID_BIT (0) + #define DWT_CELLID3_CELLID_BITS (32) + +/* FPB block */ +#define DATA_FPB_BASE (0xE0002000u) +#define DATA_FPB_END (0xE0002FFFu) +#define DATA_FPB_SIZE (DATA_FPB_END - DATA_FPB_BASE + 1) + +#define FPB_CTRL *((volatile int32u *)0xE0002000u) +#define FPB_CTRL_REG *((volatile int32u *)0xE0002000u) +#define FPB_CTRL_ADDR (0xE0002000u) +#define FPB_CTRL_RESET (0x00000000u) + /* NUM_LIT field */ + #define FPB_CTRL_NUM_LIT (0x00000F00u) + #define FPB_CTRL_NUM_LIT_MASK (0x00000F00u) + #define FPB_CTRL_NUM_LIT_BIT (8) + #define FPB_CTRL_NUM_LIT_BITS (4) + /* NUM_CODE field */ + #define FPB_CTRL_NUM_CODE (0x000000F0u) + #define FPB_CTRL_NUM_CODE_MASK (0x000000F0u) + #define FPB_CTRL_NUM_CODE_BIT (4) + #define FPB_CTRL_NUM_CODE_BITS (4) + /* KEY field */ + #define FPB_CTRL_KEY (0x00000002u) + #define FPB_CTRL_KEY_MASK (0x00000002u) + #define FPB_CTRL_KEY_BIT (1) + #define FPB_CTRL_KEY_BITS (1) + /* enable field */ + #define FPB_CTRL_enable (0x00000001u) + #define FPB_CTRL_enable_MASK (0x00000001u) + #define FPB_CTRL_enable_BIT (0) + #define FPB_CTRL_enable_BITS (1) + +#define FPB_REMAP *((volatile int32u *)0xE0002004u) +#define FPB_REMAP_REG *((volatile int32u *)0xE0002004u) +#define FPB_REMAP_ADDR (0xE0002004u) +#define FPB_REMAP_RESET (0x20000000u) + /* REMAP field */ + #define FPB_REMAP_REMAP (0x1FFFFFE0u) + #define FPB_REMAP_REMAP_MASK (0x1FFFFFE0u) + #define FPB_REMAP_REMAP_BIT (5) + #define FPB_REMAP_REMAP_BITS (24) + +#define FPB_COMP0 *((volatile int32u *)0xE0002008u) +#define FPB_COMP0_REG *((volatile int32u *)0xE0002008u) +#define FPB_COMP0_ADDR (0xE0002008u) +#define FPB_COMP0_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP0_REPLACE (0xC0000000u) + #define FPB_COMP0_REPLACE_MASK (0xC0000000u) + #define FPB_COMP0_REPLACE_BIT (30) + #define FPB_COMP0_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP0_COMP (0x1FFFFFFCu) + #define FPB_COMP0_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP0_COMP_BIT (2) + #define FPB_COMP0_COMP_BITS (27) + /* enable field */ + #define FPB_COMP0_enable (0x00000001u) + #define FPB_COMP0_enable_MASK (0x00000001u) + #define FPB_COMP0_enable_BIT (0) + #define FPB_COMP0_enable_BITS (1) + +#define FPB_COMP1 *((volatile int32u *)0xE000200Cu) +#define FPB_COMP1_REG *((volatile int32u *)0xE000200Cu) +#define FPB_COMP1_ADDR (0xE000200Cu) +#define FPB_COMP1_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP1_REPLACE (0xC0000000u) + #define FPB_COMP1_REPLACE_MASK (0xC0000000u) + #define FPB_COMP1_REPLACE_BIT (30) + #define FPB_COMP1_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP1_COMP (0x1FFFFFFCu) + #define FPB_COMP1_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP1_COMP_BIT (2) + #define FPB_COMP1_COMP_BITS (27) + /* enable field */ + #define FPB_COMP1_enable (0x00000001u) + #define FPB_COMP1_enable_MASK (0x00000001u) + #define FPB_COMP1_enable_BIT (0) + #define FPB_COMP1_enable_BITS (1) + +#define FPB_COMP2 *((volatile int32u *)0xE0002010u) +#define FPB_COMP2_REG *((volatile int32u *)0xE0002010u) +#define FPB_COMP2_ADDR (0xE0002010u) +#define FPB_COMP2_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP2_REPLACE (0xC0000000u) + #define FPB_COMP2_REPLACE_MASK (0xC0000000u) + #define FPB_COMP2_REPLACE_BIT (30) + #define FPB_COMP2_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP2_COMP (0x1FFFFFFCu) + #define FPB_COMP2_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP2_COMP_BIT (2) + #define FPB_COMP2_COMP_BITS (27) + /* enable field */ + #define FPB_COMP2_enable (0x00000001u) + #define FPB_COMP2_enable_MASK (0x00000001u) + #define FPB_COMP2_enable_BIT (0) + #define FPB_COMP2_enable_BITS (1) + +#define FPB_COMP3 *((volatile int32u *)0xE0002014u) +#define FPB_COMP3_REG *((volatile int32u *)0xE0002014u) +#define FPB_COMP3_ADDR (0xE0002014u) +#define FPB_COMP3_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP3_REPLACE (0xC0000000u) + #define FPB_COMP3_REPLACE_MASK (0xC0000000u) + #define FPB_COMP3_REPLACE_BIT (30) + #define FPB_COMP3_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP3_COMP (0x1FFFFFFCu) + #define FPB_COMP3_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP3_COMP_BIT (2) + #define FPB_COMP3_COMP_BITS (27) + /* enable field */ + #define FPB_COMP3_enable (0x00000001u) + #define FPB_COMP3_enable_MASK (0x00000001u) + #define FPB_COMP3_enable_BIT (0) + #define FPB_COMP3_enable_BITS (1) + +#define FPB_COMP4 *((volatile int32u *)0xE0002018u) +#define FPB_COMP4_REG *((volatile int32u *)0xE0002018u) +#define FPB_COMP4_ADDR (0xE0002018u) +#define FPB_COMP4_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP4_REPLACE (0xC0000000u) + #define FPB_COMP4_REPLACE_MASK (0xC0000000u) + #define FPB_COMP4_REPLACE_BIT (30) + #define FPB_COMP4_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP4_COMP (0x1FFFFFFCu) + #define FPB_COMP4_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP4_COMP_BIT (2) + #define FPB_COMP4_COMP_BITS (27) + /* enable field */ + #define FPB_COMP4_enable (0x00000001u) + #define FPB_COMP4_enable_MASK (0x00000001u) + #define FPB_COMP4_enable_BIT (0) + #define FPB_COMP4_enable_BITS (1) + +#define FPB_COMP5 *((volatile int32u *)0xE000201Cu) +#define FPB_COMP5_REG *((volatile int32u *)0xE000201Cu) +#define FPB_COMP5_ADDR (0xE000201Cu) +#define FPB_COMP5_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP5_REPLACE (0xC0000000u) + #define FPB_COMP5_REPLACE_MASK (0xC0000000u) + #define FPB_COMP5_REPLACE_BIT (30) + #define FPB_COMP5_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP5_COMP (0x1FFFFFFCu) + #define FPB_COMP5_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP5_COMP_BIT (2) + #define FPB_COMP5_COMP_BITS (27) + /* enable field */ + #define FPB_COMP5_enable (0x00000001u) + #define FPB_COMP5_enable_MASK (0x00000001u) + #define FPB_COMP5_enable_BIT (0) + #define FPB_COMP5_enable_BITS (1) + +#define FPB_COMP6 *((volatile int32u *)0xE0002020u) +#define FPB_COMP6_REG *((volatile int32u *)0xE0002020u) +#define FPB_COMP6_ADDR (0xE0002020u) +#define FPB_COMP6_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP6_REPLACE (0xC0000000u) + #define FPB_COMP6_REPLACE_MASK (0xC0000000u) + #define FPB_COMP6_REPLACE_BIT (30) + #define FPB_COMP6_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP6_COMP (0x1FFFFFFCu) + #define FPB_COMP6_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP6_COMP_BIT (2) + #define FPB_COMP6_COMP_BITS (27) + /* enable field */ + #define FPB_COMP6_enable (0x00000001u) + #define FPB_COMP6_enable_MASK (0x00000001u) + #define FPB_COMP6_enable_BIT (0) + #define FPB_COMP6_enable_BITS (1) + +#define FPB_COMP7 *((volatile int32u *)0xE0002024u) +#define FPB_COMP7_REG *((volatile int32u *)0xE0002024u) +#define FPB_COMP7_ADDR (0xE0002024u) +#define FPB_COMP7_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP7_REPLACE (0xC0000000u) + #define FPB_COMP7_REPLACE_MASK (0xC0000000u) + #define FPB_COMP7_REPLACE_BIT (30) + #define FPB_COMP7_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP7_COMP (0x1FFFFFFCu) + #define FPB_COMP7_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP7_COMP_BIT (2) + #define FPB_COMP7_COMP_BITS (27) + /* enable field */ + #define FPB_COMP7_enable (0x00000001u) + #define FPB_COMP7_enable_MASK (0x00000001u) + #define FPB_COMP7_enable_BIT (0) + #define FPB_COMP7_enable_BITS (1) + +#define FPB_PERIPHID4 *((volatile int32u *)0xE0002FD0u) +#define FPB_PERIPHID4_REG *((volatile int32u *)0xE0002FD0u) +#define FPB_PERIPHID4_ADDR (0xE0002FD0u) +#define FPB_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define FPB_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID4_PERIPHID_BIT (0) + #define FPB_PERIPHID4_PERIPHID_BITS (32) + +#define FPB_PERIPHID5 *((volatile int32u *)0xE0002FD4u) +#define FPB_PERIPHID5_REG *((volatile int32u *)0xE0002FD4u) +#define FPB_PERIPHID5_ADDR (0xE0002FD4u) +#define FPB_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID5_PERIPHID_BIT (0) + #define FPB_PERIPHID5_PERIPHID_BITS (32) + +#define FPB_PERIPHID6 *((volatile int32u *)0xE0002FD8u) +#define FPB_PERIPHID6_REG *((volatile int32u *)0xE0002FD8u) +#define FPB_PERIPHID6_ADDR (0xE0002FD8u) +#define FPB_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID6_PERIPHID_BIT (0) + #define FPB_PERIPHID6_PERIPHID_BITS (32) + +#define FPB_PERIPHID7 *((volatile int32u *)0xE0002FDCu) +#define FPB_PERIPHID7_REG *((volatile int32u *)0xE0002FDCu) +#define FPB_PERIPHID7_ADDR (0xE0002FDCu) +#define FPB_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID7_PERIPHID_BIT (0) + #define FPB_PERIPHID7_PERIPHID_BITS (32) + +#define FPB_PERIPHID0 *((volatile int32u *)0xE0002FE0u) +#define FPB_PERIPHID0_REG *((volatile int32u *)0xE0002FE0u) +#define FPB_PERIPHID0_ADDR (0xE0002FE0u) +#define FPB_PERIPHID0_RESET (0x00000003u) + /* PERIPHID field */ + #define FPB_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID0_PERIPHID_BIT (0) + #define FPB_PERIPHID0_PERIPHID_BITS (32) + +#define FPB_PERIPHID1 *((volatile int32u *)0xE0002FE4u) +#define FPB_PERIPHID1_REG *((volatile int32u *)0xE0002FE4u) +#define FPB_PERIPHID1_ADDR (0xE0002FE4u) +#define FPB_PERIPHID1_RESET (0x000000B0u) + /* PERIPHID field */ + #define FPB_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID1_PERIPHID_BIT (0) + #define FPB_PERIPHID1_PERIPHID_BITS (32) + +#define FPB_PERIPHID2 *((volatile int32u *)0xE0002FE8u) +#define FPB_PERIPHID2_REG *((volatile int32u *)0xE0002FE8u) +#define FPB_PERIPHID2_ADDR (0xE0002FE8u) +#define FPB_PERIPHID2_RESET (0x0000000Bu) + /* PERIPHID field */ + #define FPB_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID2_PERIPHID_BIT (0) + #define FPB_PERIPHID2_PERIPHID_BITS (32) + +#define FPB_PERIPHID3 *((volatile int32u *)0xE0002FECu) +#define FPB_PERIPHID3_REG *((volatile int32u *)0xE0002FECu) +#define FPB_PERIPHID3_ADDR (0xE0002FECu) +#define FPB_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID3_PERIPHID_BIT (0) + #define FPB_PERIPHID3_PERIPHID_BITS (32) + +#define FPB_CELLID0 *((volatile int32u *)0xE0002FF0u) +#define FPB_CELLID0_REG *((volatile int32u *)0xE0002FF0u) +#define FPB_CELLID0_ADDR (0xE0002FF0u) +#define FPB_CELLID0_RESET (0x0000000Du) + /* CELLID field */ + #define FPB_CELLID0_CELLID (0xFFFFFFFFu) + #define FPB_CELLID0_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID0_CELLID_BIT (0) + #define FPB_CELLID0_CELLID_BITS (32) + +#define FPB_CELLID1 *((volatile int32u *)0xE0002FF4u) +#define FPB_CELLID1_REG *((volatile int32u *)0xE0002FF4u) +#define FPB_CELLID1_ADDR (0xE0002FF4u) +#define FPB_CELLID1_RESET (0x000000E0u) + /* CELLID field */ + #define FPB_CELLID1_CELLID (0xFFFFFFFFu) + #define FPB_CELLID1_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID1_CELLID_BIT (0) + #define FPB_CELLID1_CELLID_BITS (32) + +#define FPB_CELLID2 *((volatile int32u *)0xE0002FF8u) +#define FPB_CELLID2_REG *((volatile int32u *)0xE0002FF8u) +#define FPB_CELLID2_ADDR (0xE0002FF8u) +#define FPB_CELLID2_RESET (0x00000005u) + /* CELLID field */ + #define FPB_CELLID2_CELLID (0xFFFFFFFFu) + #define FPB_CELLID2_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID2_CELLID_BIT (0) + #define FPB_CELLID2_CELLID_BITS (32) + +#define FPB_CELLID3 *((volatile int32u *)0xE0002FFCu) +#define FPB_CELLID3_REG *((volatile int32u *)0xE0002FFCu) +#define FPB_CELLID3_ADDR (0xE0002FFCu) +#define FPB_CELLID3_RESET (0x000000B1u) + /* CELLID field */ + #define FPB_CELLID3_CELLID (0xFFFFFFFFu) + #define FPB_CELLID3_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID3_CELLID_BIT (0) + #define FPB_CELLID3_CELLID_BITS (32) + +/* NVIC block */ +#define BLOCK_NVIC_BASE (0xE000E000u) +#define BLOCK_NVIC_END (0xE000EFFFu) +#define BLOCK_NVIC_SIZE (BLOCK_NVIC_END - BLOCK_NVIC_BASE + 1) + +#define NVIC_MCR *((volatile int32u *)0xE000E000u) +#define NVIC_MCR_REG *((volatile int32u *)0xE000E000u) +#define NVIC_MCR_ADDR (0xE000E000u) +#define NVIC_MCR_RESET (0x00000000u) + +#define NVIC_ICTR *((volatile int32u *)0xE000E004u) +#define NVIC_ICTR_REG *((volatile int32u *)0xE000E004u) +#define NVIC_ICTR_ADDR (0xE000E004u) +#define NVIC_ICTR_RESET (0x00000000u) + /* INTLINESNUM field */ + #define NVIC_ICTR_INTLINESNUM (0x0000001Fu) + #define NVIC_ICTR_INTLINESNUM_MASK (0x0000001Fu) + #define NVIC_ICTR_INTLINESNUM_BIT (0) + #define NVIC_ICTR_INTLINESNUM_BITS (5) + +#define ST_CSR *((volatile int32u *)0xE000E010u) +#define ST_CSR_REG *((volatile int32u *)0xE000E010u) +#define ST_CSR_ADDR (0xE000E010u) +#define ST_CSR_RESET (0x00000000u) + /* COUNTFLAG field */ + #define ST_CSR_COUNTFLAG (0x00010000u) + #define ST_CSR_COUNTFLAG_MASK (0x00010000u) + #define ST_CSR_COUNTFLAG_BIT (16) + #define ST_CSR_COUNTFLAG_BITS (1) + /* CLKSOURCE field */ + #define ST_CSR_CLKSOURCE (0x00000004u) + #define ST_CSR_CLKSOURCE_MASK (0x00000004u) + #define ST_CSR_CLKSOURCE_BIT (2) + #define ST_CSR_CLKSOURCE_BITS (1) + /* TICKINT field */ + #define ST_CSR_TICKINT (0x00000002u) + #define ST_CSR_TICKINT_MASK (0x00000002u) + #define ST_CSR_TICKINT_BIT (1) + #define ST_CSR_TICKINT_BITS (1) + /* ENABLE field */ + #define ST_CSR_ENABLE (0x00000001u) + #define ST_CSR_ENABLE_MASK (0x00000001u) + #define ST_CSR_ENABLE_BIT (0) + #define ST_CSR_ENABLE_BITS (1) + +#define ST_RVR *((volatile int32u *)0xE000E014u) +#define ST_RVR_REG *((volatile int32u *)0xE000E014u) +#define ST_RVR_ADDR (0xE000E014u) +#define ST_RVR_RESET (0x00000000u) + /* RELOAD field */ + #define ST_RVR_RELOAD (0x00FFFFFFu) + #define ST_RVR_RELOAD_MASK (0x00FFFFFFu) + #define ST_RVR_RELOAD_BIT (0) + #define ST_RVR_RELOAD_BITS (24) + +#define ST_CVR *((volatile int32u *)0xE000E018u) +#define ST_CVR_REG *((volatile int32u *)0xE000E018u) +#define ST_CVR_ADDR (0xE000E018u) +#define ST_CVR_RESET (0x00000000u) + /* CURRENT field */ + #define ST_CVR_CURRENT (0xFFFFFFFFu) + #define ST_CVR_CURRENT_MASK (0xFFFFFFFFu) + #define ST_CVR_CURRENT_BIT (0) + #define ST_CVR_CURRENT_BITS (32) + +#define ST_CALVR *((volatile int32u *)0xE000E01Cu) +#define ST_CALVR_REG *((volatile int32u *)0xE000E01Cu) +#define ST_CALVR_ADDR (0xE000E01Cu) +#define ST_CALVR_RESET (0x00000000u) + /* NOREF field */ + #define ST_CALVR_NOREF (0x80000000u) + #define ST_CALVR_NOREF_MASK (0x80000000u) + #define ST_CALVR_NOREF_BIT (31) + #define ST_CALVR_NOREF_BITS (1) + /* SKEW field */ + #define ST_CALVR_SKEW (0x40000000u) + #define ST_CALVR_SKEW_MASK (0x40000000u) + #define ST_CALVR_SKEW_BIT (30) + #define ST_CALVR_SKEW_BITS (1) + /* TENMS field */ + #define ST_CALVR_TENMS (0x00FFFFFFu) + #define ST_CALVR_TENMS_MASK (0x00FFFFFFu) + #define ST_CALVR_TENMS_BIT (0) + #define ST_CALVR_TENMS_BITS (24) + +#define INT_CFGSET *((volatile int32u *)0xE000E100u) +#define INT_CFGSET_REG *((volatile int32u *)0xE000E100u) +#define INT_CFGSET_ADDR (0xE000E100u) +#define INT_CFGSET_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_CFGCLR *((volatile int32u *)0xE000E180u) +#define INT_CFGCLR_REG *((volatile int32u *)0xE000E180u) +#define INT_CFGCLR_ADDR (0xE000E180u) +#define INT_CFGCLR_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_PENDSET *((volatile int32u *)0xE000E200u) +#define INT_PENDSET_REG *((volatile int32u *)0xE000E200u) +#define INT_PENDSET_ADDR (0xE000E200u) +#define INT_PENDSET_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_PENDCLR *((volatile int32u *)0xE000E280u) +#define INT_PENDCLR_REG *((volatile int32u *)0xE000E280u) +#define INT_PENDCLR_ADDR (0xE000E280u) +#define INT_PENDCLR_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_ACTIVE *((volatile int32u *)0xE000E300u) +#define INT_ACTIVE_REG *((volatile int32u *)0xE000E300u) +#define INT_ACTIVE_ADDR (0xE000E300u) +#define INT_ACTIVE_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define NVIC_IPR_3to0 *((volatile int32u *)0xE000E400u) +#define NVIC_IPR_3to0_REG *((volatile int32u *)0xE000E400u) +#define NVIC_IPR_3to0_ADDR (0xE000E400u) +#define NVIC_IPR_3to0_RESET (0x00000000u) + /* PRI_3 field */ + #define NVIC_IPR_3to0_PRI_3 (0xFF000000u) + #define NVIC_IPR_3to0_PRI_3_MASK (0xFF000000u) + #define NVIC_IPR_3to0_PRI_3_BIT (24) + #define NVIC_IPR_3to0_PRI_3_BITS (8) + /* PRI_2 field */ + #define NVIC_IPR_3to0_PRI_2 (0x00FF0000u) + #define NVIC_IPR_3to0_PRI_2_MASK (0x00FF0000u) + #define NVIC_IPR_3to0_PRI_2_BIT (16) + #define NVIC_IPR_3to0_PRI_2_BITS (8) + /* PRI_1 field */ + #define NVIC_IPR_3to0_PRI_1 (0x0000FF00u) + #define NVIC_IPR_3to0_PRI_1_MASK (0x0000FF00u) + #define NVIC_IPR_3to0_PRI_1_BIT (8) + #define NVIC_IPR_3to0_PRI_1_BITS (8) + /* PRI_0 field */ + #define NVIC_IPR_3to0_PRI_0 (0x000000FFu) + #define NVIC_IPR_3to0_PRI_0_MASK (0x000000FFu) + #define NVIC_IPR_3to0_PRI_0_BIT (0) + #define NVIC_IPR_3to0_PRI_0_BITS (8) + +#define NVIC_IPR_7to4 *((volatile int32u *)0xE000E404u) +#define NVIC_IPR_7to4_REG *((volatile int32u *)0xE000E404u) +#define NVIC_IPR_7to4_ADDR (0xE000E404u) +#define NVIC_IPR_7to4_RESET (0x00000000u) + /* PRI_7 field */ + #define NVIC_IPR_7to4_PRI_7 (0xFF000000u) + #define NVIC_IPR_7to4_PRI_7_MASK (0xFF000000u) + #define NVIC_IPR_7to4_PRI_7_BIT (24) + #define NVIC_IPR_7to4_PRI_7_BITS (8) + /* PRI_6 field */ + #define NVIC_IPR_7to4_PRI_6 (0x00FF0000u) + #define NVIC_IPR_7to4_PRI_6_MASK (0x00FF0000u) + #define NVIC_IPR_7to4_PRI_6_BIT (16) + #define NVIC_IPR_7to4_PRI_6_BITS (8) + /* PRI_5 field */ + #define NVIC_IPR_7to4_PRI_5 (0x0000FF00u) + #define NVIC_IPR_7to4_PRI_5_MASK (0x0000FF00u) + #define NVIC_IPR_7to4_PRI_5_BIT (8) + #define NVIC_IPR_7to4_PRI_5_BITS (8) + /* PRI_4 field */ + #define NVIC_IPR_7to4_PRI_4 (0x000000FFu) + #define NVIC_IPR_7to4_PRI_4_MASK (0x000000FFu) + #define NVIC_IPR_7to4_PRI_4_BIT (0) + #define NVIC_IPR_7to4_PRI_4_BITS (8) + +#define NVIC_IPR_11to8 *((volatile int32u *)0xE000E408u) +#define NVIC_IPR_11to8_REG *((volatile int32u *)0xE000E408u) +#define NVIC_IPR_11to8_ADDR (0xE000E408u) +#define NVIC_IPR_11to8_RESET (0x00000000u) + /* PRI_11 field */ + #define NVIC_IPR_11to8_PRI_11 (0xFF000000u) + #define NVIC_IPR_11to8_PRI_11_MASK (0xFF000000u) + #define NVIC_IPR_11to8_PRI_11_BIT (24) + #define NVIC_IPR_11to8_PRI_11_BITS (8) + /* PRI_10 field */ + #define NVIC_IPR_11to8_PRI_10 (0x00FF0000u) + #define NVIC_IPR_11to8_PRI_10_MASK (0x00FF0000u) + #define NVIC_IPR_11to8_PRI_10_BIT (16) + #define NVIC_IPR_11to8_PRI_10_BITS (8) + /* PRI_9 field */ + #define NVIC_IPR_11to8_PRI_9 (0x0000FF00u) + #define NVIC_IPR_11to8_PRI_9_MASK (0x0000FF00u) + #define NVIC_IPR_11to8_PRI_9_BIT (8) + #define NVIC_IPR_11to8_PRI_9_BITS (8) + /* PRI_8 field */ + #define NVIC_IPR_11to8_PRI_8 (0x000000FFu) + #define NVIC_IPR_11to8_PRI_8_MASK (0x000000FFu) + #define NVIC_IPR_11to8_PRI_8_BIT (0) + #define NVIC_IPR_11to8_PRI_8_BITS (8) + +#define NVIC_IPR_15to12 *((volatile int32u *)0xE000E40Cu) +#define NVIC_IPR_15to12_REG *((volatile int32u *)0xE000E40Cu) +#define NVIC_IPR_15to12_ADDR (0xE000E40Cu) +#define NVIC_IPR_15to12_RESET (0x00000000u) + /* PRI_15 field */ + #define NVIC_IPR_15to12_PRI_15 (0xFF000000u) + #define NVIC_IPR_15to12_PRI_15_MASK (0xFF000000u) + #define NVIC_IPR_15to12_PRI_15_BIT (24) + #define NVIC_IPR_15to12_PRI_15_BITS (8) + /* PRI_14 field */ + #define NVIC_IPR_15to12_PRI_14 (0x00FF0000u) + #define NVIC_IPR_15to12_PRI_14_MASK (0x00FF0000u) + #define NVIC_IPR_15to12_PRI_14_BIT (16) + #define NVIC_IPR_15to12_PRI_14_BITS (8) + /* PRI_13 field */ + #define NVIC_IPR_15to12_PRI_13 (0x0000FF00u) + #define NVIC_IPR_15to12_PRI_13_MASK (0x0000FF00u) + #define NVIC_IPR_15to12_PRI_13_BIT (8) + #define NVIC_IPR_15to12_PRI_13_BITS (8) + /* PRI_12 field */ + #define NVIC_IPR_15to12_PRI_12 (0x000000FFu) + #define NVIC_IPR_15to12_PRI_12_MASK (0x000000FFu) + #define NVIC_IPR_15to12_PRI_12_BIT (0) + #define NVIC_IPR_15to12_PRI_12_BITS (8) + +#define NVIC_IPR_19to16 *((volatile int32u *)0xE000E410u) +#define NVIC_IPR_19to16_REG *((volatile int32u *)0xE000E410u) +#define NVIC_IPR_19to16_ADDR (0xE000E410u) +#define NVIC_IPR_19to16_RESET (0x00000000u) + /* PRI_19 field */ + #define NVIC_IPR_19to16_PRI_19 (0xFF000000u) + #define NVIC_IPR_19to16_PRI_19_MASK (0xFF000000u) + #define NVIC_IPR_19to16_PRI_19_BIT (24) + #define NVIC_IPR_19to16_PRI_19_BITS (8) + /* PRI_18 field */ + #define NVIC_IPR_19to16_PRI_18 (0x00FF0000u) + #define NVIC_IPR_19to16_PRI_18_MASK (0x00FF0000u) + #define NVIC_IPR_19to16_PRI_18_BIT (16) + #define NVIC_IPR_19to16_PRI_18_BITS (8) + /* PRI_17 field */ + #define NVIC_IPR_19to16_PRI_17 (0x0000FF00u) + #define NVIC_IPR_19to16_PRI_17_MASK (0x0000FF00u) + #define NVIC_IPR_19to16_PRI_17_BIT (8) + #define NVIC_IPR_19to16_PRI_17_BITS (8) + /* PRI_16 field */ + #define NVIC_IPR_19to16_PRI_16 (0x000000FFu) + #define NVIC_IPR_19to16_PRI_16_MASK (0x000000FFu) + #define NVIC_IPR_19to16_PRI_16_BIT (0) + #define NVIC_IPR_19to16_PRI_16_BITS (8) + +#define SCS_CPUID *((volatile int32u *)0xE000ED00u) +#define SCS_CPUID_REG *((volatile int32u *)0xE000ED00u) +#define SCS_CPUID_ADDR (0xE000ED00u) +#define SCS_CPUID_RESET (0x411FC231u) + /* IMPLEMENTER field */ + #define SCS_CPUID_IMPLEMENTER (0xFF000000u) + #define SCS_CPUID_IMPLEMENTER_MASK (0xFF000000u) + #define SCS_CPUID_IMPLEMENTER_BIT (24) + #define SCS_CPUID_IMPLEMENTER_BITS (8) + /* VARIANT field */ + #define SCS_CPUID_VARIANT (0x00F00000u) + #define SCS_CPUID_VARIANT_MASK (0x00F00000u) + #define SCS_CPUID_VARIANT_BIT (20) + #define SCS_CPUID_VARIANT_BITS (4) + /* CONSTANT field */ + #define SCS_CPUID_CONSTANT (0x000F0000u) + #define SCS_CPUID_CONSTANT_MASK (0x000F0000u) + #define SCS_CPUID_CONSTANT_BIT (16) + #define SCS_CPUID_CONSTANT_BITS (4) + /* PARTNO field */ + #define SCS_CPUID_PARTNO (0x0000FFF0u) + #define SCS_CPUID_PARTNO_MASK (0x0000FFF0u) + #define SCS_CPUID_PARTNO_BIT (4) + #define SCS_CPUID_PARTNO_BITS (12) + /* REVISION field */ + #define SCS_CPUID_REVISION (0x0000000Fu) + #define SCS_CPUID_REVISION_MASK (0x0000000Fu) + #define SCS_CPUID_REVISION_BIT (0) + #define SCS_CPUID_REVISION_BITS (4) + +#define SCS_ICSR *((volatile int32u *)0xE000ED04u) +#define SCS_ICSR_REG *((volatile int32u *)0xE000ED04u) +#define SCS_ICSR_ADDR (0xE000ED04u) +#define SCS_ICSR_RESET (0x00000000u) + /* NMIPENDSET field */ + #define SCS_ICSR_NMIPENDSET (0x80000000u) + #define SCS_ICSR_NMIPENDSET_MASK (0x80000000u) + #define SCS_ICSR_NMIPENDSET_BIT (31) + #define SCS_ICSR_NMIPENDSET_BITS (1) + /* PENDSVSET field */ + #define SCS_ICSR_PENDSVSET (0x10000000u) + #define SCS_ICSR_PENDSVSET_MASK (0x10000000u) + #define SCS_ICSR_PENDSVSET_BIT (28) + #define SCS_ICSR_PENDSVSET_BITS (1) + /* PENDSVCLR field */ + #define SCS_ICSR_PENDSVCLR (0x08000000u) + #define SCS_ICSR_PENDSVCLR_MASK (0x08000000u) + #define SCS_ICSR_PENDSVCLR_BIT (27) + #define SCS_ICSR_PENDSVCLR_BITS (1) + /* PENDSTSET field */ + #define SCS_ICSR_PENDSTSET (0x04000000u) + #define SCS_ICSR_PENDSTSET_MASK (0x04000000u) + #define SCS_ICSR_PENDSTSET_BIT (26) + #define SCS_ICSR_PENDSTSET_BITS (1) + /* PENDSTCLR field */ + #define SCS_ICSR_PENDSTCLR (0x02000000u) + #define SCS_ICSR_PENDSTCLR_MASK (0x02000000u) + #define SCS_ICSR_PENDSTCLR_BIT (25) + #define SCS_ICSR_PENDSTCLR_BITS (1) + /* ISRPREEMPT field */ + #define SCS_ICSR_ISRPREEMPT (0x00800000u) + #define SCS_ICSR_ISRPREEMPT_MASK (0x00800000u) + #define SCS_ICSR_ISRPREEMPT_BIT (23) + #define SCS_ICSR_ISRPREEMPT_BITS (1) + /* ISRPENDING field */ + #define SCS_ICSR_ISRPENDING (0x00400000u) + #define SCS_ICSR_ISRPENDING_MASK (0x00400000u) + #define SCS_ICSR_ISRPENDING_BIT (22) + #define SCS_ICSR_ISRPENDING_BITS (1) + /* VECTPENDING field */ + #define SCS_ICSR_VECTPENDING (0x001FF000u) + #define SCS_ICSR_VECTPENDING_MASK (0x001FF000u) + #define SCS_ICSR_VECTPENDING_BIT (12) + #define SCS_ICSR_VECTPENDING_BITS (9) + /* RETTOBASE field */ + #define SCS_ICSR_RETTOBASE (0x00000800u) + #define SCS_ICSR_RETTOBASE_MASK (0x00000800u) + #define SCS_ICSR_RETTOBASE_BIT (11) + #define SCS_ICSR_RETTOBASE_BITS (1) + /* VECACTIVE field */ + #define SCS_ICSR_VECACTIVE (0x000001FFu) + #define SCS_ICSR_VECACTIVE_MASK (0x000001FFu) + #define SCS_ICSR_VECACTIVE_BIT (0) + #define SCS_ICSR_VECACTIVE_BITS (9) + +#define SCS_VTOR *((volatile int32u *)0xE000ED08u) +#define SCS_VTOR_REG *((volatile int32u *)0xE000ED08u) +#define SCS_VTOR_ADDR (0xE000ED08u) +#define SCS_VTOR_RESET (0x00000000u) + /* TBLBASE field */ + #define SCS_VTOR_TBLBASE (0x20000000u) + #define SCS_VTOR_TBLBASE_MASK (0x20000000u) + #define SCS_VTOR_TBLBASE_BIT (29) + #define SCS_VTOR_TBLBASE_BITS (1) + /* TBLOFF field */ + #define SCS_VTOR_TBLOFF (0x1FFFFF00u) + #define SCS_VTOR_TBLOFF_MASK (0x1FFFFF00u) + #define SCS_VTOR_TBLOFF_BIT (8) + #define SCS_VTOR_TBLOFF_BITS (21) + +#define SCS_AIRCR *((volatile int32u *)0xE000ED0Cu) +#define SCS_AIRCR_REG *((volatile int32u *)0xE000ED0Cu) +#define SCS_AIRCR_ADDR (0xE000ED0Cu) +#define SCS_AIRCR_RESET (0x00000000u) + /* VECTKEYSTAT field */ + #define SCS_AIRCR_VECTKEYSTAT (0xFFFF0000u) + #define SCS_AIRCR_VECTKEYSTAT_MASK (0xFFFF0000u) + #define SCS_AIRCR_VECTKEYSTAT_BIT (16) + #define SCS_AIRCR_VECTKEYSTAT_BITS (16) + /* VECTKEY field */ + #define SCS_AIRCR_VECTKEY (0xFFFF0000u) + #define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) + #define SCS_AIRCR_VECTKEY_BIT (16) + #define SCS_AIRCR_VECTKEY_BITS (16) + /* ENDIANESS field */ + #define SCS_AIRCR_ENDIANESS (0x00008000u) + #define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) + #define SCS_AIRCR_ENDIANESS_BIT (15) + #define SCS_AIRCR_ENDIANESS_BITS (1) + /* PRIGROUP field */ + #define SCS_AIRCR_PRIGROUP (0x00000700u) + #define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) + #define SCS_AIRCR_PRIGROUP_BIT (8) + #define SCS_AIRCR_PRIGROUP_BITS (3) + /* SYSRESETREQ field */ + #define SCS_AIRCR_SYSRESETREQ (0x00000004u) + #define SCS_AIRCR_SYSRESETREQ_MASK (0x00000004u) + #define SCS_AIRCR_SYSRESETREQ_BIT (2) + #define SCS_AIRCR_SYSRESETREQ_BITS (1) + /* VECTCLRACTIVE field */ + #define SCS_AIRCR_VECTCLRACTIVE (0x00000002u) + #define SCS_AIRCR_VECTCLRACTIVE_MASK (0x00000002u) + #define SCS_AIRCR_VECTCLRACTIVE_BIT (1) + #define SCS_AIRCR_VECTCLRACTIVE_BITS (1) + /* VECTRESET field */ + #define SCS_AIRCR_VECTRESET (0x00000001u) + #define SCS_AIRCR_VECTRESET_MASK (0x00000001u) + #define SCS_AIRCR_VECTRESET_BIT (0) + #define SCS_AIRCR_VECTRESET_BITS (1) + +#define SCS_SCR *((volatile int32u *)0xE000ED10u) +#define SCS_SCR_REG *((volatile int32u *)0xE000ED10u) +#define SCS_SCR_ADDR (0xE000ED10u) +#define SCS_SCR_RESET (0x00000000u) + /* SEVONPEND field */ + #define SCS_SCR_SEVONPEND (0x00000010u) + #define SCS_SCR_SEVONPEND_MASK (0x00000010u) + #define SCS_SCR_SEVONPEND_BIT (4) + #define SCS_SCR_SEVONPEND_BITS (1) + /* SLEEPDEEP field */ + #define SCS_SCR_SLEEPDEEP (0x00000004u) + #define SCS_SCR_SLEEPDEEP_MASK (0x00000004u) + #define SCS_SCR_SLEEPDEEP_BIT (2) + #define SCS_SCR_SLEEPDEEP_BITS (1) + /* SLEEPONEXIT field */ + #define SCS_SCR_SLEEPONEXIT (0x00000002u) + #define SCS_SCR_SLEEPONEXIT_MASK (0x00000002u) + #define SCS_SCR_SLEEPONEXIT_BIT (1) + #define SCS_SCR_SLEEPONEXIT_BITS (1) + +#define SCS_CCR *((volatile int32u *)0xE000ED14u) +#define SCS_CCR_REG *((volatile int32u *)0xE000ED14u) +#define SCS_CCR_ADDR (0xE000ED14u) +#define SCS_CCR_RESET (0x00000000u) + /* STKALIGN field */ + #define SCS_CCR_STKALIGN (0x00000200u) + #define SCS_CCR_STKALIGN_MASK (0x00000200u) + #define SCS_CCR_STKALIGN_BIT (9) + #define SCS_CCR_STKALIGN_BITS (1) + /* BFHFNMIGN field */ + #define SCS_CCR_BFHFNMIGN (0x00000100u) + #define SCS_CCR_BFHFNMIGN_MASK (0x00000100u) + #define SCS_CCR_BFHFNMIGN_BIT (8) + #define SCS_CCR_BFHFNMIGN_BITS (1) + /* DIV_0_TRP field */ + #define SCS_CCR_DIV_0_TRP (0x00000010u) + #define SCS_CCR_DIV_0_TRP_MASK (0x00000010u) + #define SCS_CCR_DIV_0_TRP_BIT (4) + #define SCS_CCR_DIV_0_TRP_BITS (1) + /* UNALIGN_TRP field */ + #define SCS_CCR_UNALIGN_TRP (0x00000008u) + #define SCS_CCR_UNALIGN_TRP_MASK (0x00000008u) + #define SCS_CCR_UNALIGN_TRP_BIT (3) + #define SCS_CCR_UNALIGN_TRP_BITS (1) + /* USERSETMPEND field */ + #define SCS_CCR_USERSETMPEND (0x00000002u) + #define SCS_CCR_USERSETMPEND_MASK (0x00000002u) + #define SCS_CCR_USERSETMPEND_BIT (1) + #define SCS_CCR_USERSETMPEND_BITS (1) + /* NONBASETHRDENA field */ + #define SCS_CCR_NONBASETHRDENA (0x00000001u) + #define SCS_CCR_NONBASETHRDENA_MASK (0x00000001u) + #define SCS_CCR_NONBASETHRDENA_BIT (0) + #define SCS_CCR_NONBASETHRDENA_BITS (1) + +#define SCS_SHPR_7to4 *((volatile int32u *)0xE000ED18u) +#define SCS_SHPR_7to4_REG *((volatile int32u *)0xE000ED18u) +#define SCS_SHPR_7to4_ADDR (0xE000ED18u) +#define SCS_SHPR_7to4_RESET (0x00000000u) + /* PRI_7 field */ + #define SCS_SHPR_7to4_PRI_7 (0xFF000000u) + #define SCS_SHPR_7to4_PRI_7_MASK (0xFF000000u) + #define SCS_SHPR_7to4_PRI_7_BIT (24) + #define SCS_SHPR_7to4_PRI_7_BITS (8) + /* PRI_6 field */ + #define SCS_SHPR_7to4_PRI_6 (0x00FF0000u) + #define SCS_SHPR_7to4_PRI_6_MASK (0x00FF0000u) + #define SCS_SHPR_7to4_PRI_6_BIT (16) + #define SCS_SHPR_7to4_PRI_6_BITS (8) + /* PRI_5 field */ + #define SCS_SHPR_7to4_PRI_5 (0x0000FF00u) + #define SCS_SHPR_7to4_PRI_5_MASK (0x0000FF00u) + #define SCS_SHPR_7to4_PRI_5_BIT (8) + #define SCS_SHPR_7to4_PRI_5_BITS (8) + /* PRI_4 field */ + #define SCS_SHPR_7to4_PRI_4 (0x000000FFu) + #define SCS_SHPR_7to4_PRI_4_MASK (0x000000FFu) + #define SCS_SHPR_7to4_PRI_4_BIT (0) + #define SCS_SHPR_7to4_PRI_4_BITS (8) + +#define SCS_SHPR_11to8 *((volatile int32u *)0xE000ED1Cu) +#define SCS_SHPR_11to8_REG *((volatile int32u *)0xE000ED1Cu) +#define SCS_SHPR_11to8_ADDR (0xE000ED1Cu) +#define SCS_SHPR_11to8_RESET (0x00000000u) + /* PRI_11 field */ + #define SCS_SHPR_11to8_PRI_11 (0xFF000000u) + #define SCS_SHPR_11to8_PRI_11_MASK (0xFF000000u) + #define SCS_SHPR_11to8_PRI_11_BIT (24) + #define SCS_SHPR_11to8_PRI_11_BITS (8) + /* PRI_10 field */ + #define SCS_SHPR_11to8_PRI_10 (0x00FF0000u) + #define SCS_SHPR_11to8_PRI_10_MASK (0x00FF0000u) + #define SCS_SHPR_11to8_PRI_10_BIT (16) + #define SCS_SHPR_11to8_PRI_10_BITS (8) + /* PRI_9 field */ + #define SCS_SHPR_11to8_PRI_9 (0x0000FF00u) + #define SCS_SHPR_11to8_PRI_9_MASK (0x0000FF00u) + #define SCS_SHPR_11to8_PRI_9_BIT (8) + #define SCS_SHPR_11to8_PRI_9_BITS (8) + /* PRI_8 field */ + #define SCS_SHPR_11to8_PRI_8 (0x000000FFu) + #define SCS_SHPR_11to8_PRI_8_MASK (0x000000FFu) + #define SCS_SHPR_11to8_PRI_8_BIT (0) + #define SCS_SHPR_11to8_PRI_8_BITS (8) + +#define SCS_SHPR_15to12 *((volatile int32u *)0xE000ED20u) +#define SCS_SHPR_15to12_REG *((volatile int32u *)0xE000ED20u) +#define SCS_SHPR_15to12_ADDR (0xE000ED20u) +#define SCS_SHPR_15to12_RESET (0x00000000u) + /* PRI_15 field */ + #define SCS_SHPR_15to12_PRI_15 (0xFF000000u) + #define SCS_SHPR_15to12_PRI_15_MASK (0xFF000000u) + #define SCS_SHPR_15to12_PRI_15_BIT (24) + #define SCS_SHPR_15to12_PRI_15_BITS (8) + /* PRI_14 field */ + #define SCS_SHPR_15to12_PRI_14 (0x00FF0000u) + #define SCS_SHPR_15to12_PRI_14_MASK (0x00FF0000u) + #define SCS_SHPR_15to12_PRI_14_BIT (16) + #define SCS_SHPR_15to12_PRI_14_BITS (8) + /* PRI_13 field */ + #define SCS_SHPR_15to12_PRI_13 (0x0000FF00u) + #define SCS_SHPR_15to12_PRI_13_MASK (0x0000FF00u) + #define SCS_SHPR_15to12_PRI_13_BIT (8) + #define SCS_SHPR_15to12_PRI_13_BITS (8) + /* PRI_12 field */ + #define SCS_SHPR_15to12_PRI_12 (0x000000FFu) + #define SCS_SHPR_15to12_PRI_12_MASK (0x000000FFu) + #define SCS_SHPR_15to12_PRI_12_BIT (0) + #define SCS_SHPR_15to12_PRI_12_BITS (8) + +#define SCS_SHCSR *((volatile int32u *)0xE000ED24u) +#define SCS_SHCSR_REG *((volatile int32u *)0xE000ED24u) +#define SCS_SHCSR_ADDR (0xE000ED24u) +#define SCS_SHCSR_RESET (0x00000000u) + /* USGFAULTENA field */ + #define SCS_SHCSR_USGFAULTENA (0x00040000u) + #define SCS_SHCSR_USGFAULTENA_MASK (0x00040000u) + #define SCS_SHCSR_USGFAULTENA_BIT (18) + #define SCS_SHCSR_USGFAULTENA_BITS (1) + /* BUSFAULTENA field */ + #define SCS_SHCSR_BUSFAULTENA (0x00020000u) + #define SCS_SHCSR_BUSFAULTENA_MASK (0x00020000u) + #define SCS_SHCSR_BUSFAULTENA_BIT (17) + #define SCS_SHCSR_BUSFAULTENA_BITS (1) + /* MEMFAULTENA field */ + #define SCS_SHCSR_MEMFAULTENA (0x00010000u) + #define SCS_SHCSR_MEMFAULTENA_MASK (0x00010000u) + #define SCS_SHCSR_MEMFAULTENA_BIT (16) + #define SCS_SHCSR_MEMFAULTENA_BITS (1) + /* SVCALLPENDED field */ + #define SCS_SHCSR_SVCALLPENDED (0x00008000u) + #define SCS_SHCSR_SVCALLPENDED_MASK (0x00008000u) + #define SCS_SHCSR_SVCALLPENDED_BIT (15) + #define SCS_SHCSR_SVCALLPENDED_BITS (1) + /* BUSFAULTPENDED field */ + #define SCS_SHCSR_BUSFAULTPENDED (0x00004000u) + #define SCS_SHCSR_BUSFAULTPENDED_MASK (0x00004000u) + #define SCS_SHCSR_BUSFAULTPENDED_BIT (14) + #define SCS_SHCSR_BUSFAULTPENDED_BITS (1) + /* MEMFAULTPENDED field */ + #define SCS_SHCSR_MEMFAULTPENDED (0x00002000u) + #define SCS_SHCSR_MEMFAULTPENDED_MASK (0x00002000u) + #define SCS_SHCSR_MEMFAULTPENDED_BIT (13) + #define SCS_SHCSR_MEMFAULTPENDED_BITS (1) + /* USGFAULTPENDED field */ + #define SCS_SHCSR_USGFAULTPENDED (0x00001000u) + #define SCS_SHCSR_USGFAULTPENDED_MASK (0x00001000u) + #define SCS_SHCSR_USGFAULTPENDED_BIT (12) + #define SCS_SHCSR_USGFAULTPENDED_BITS (1) + /* SYSTICKACT field */ + #define SCS_SHCSR_SYSTICKACT (0x00000800u) + #define SCS_SHCSR_SYSTICKACT_MASK (0x00000800u) + #define SCS_SHCSR_SYSTICKACT_BIT (11) + #define SCS_SHCSR_SYSTICKACT_BITS (1) + /* PENDSVACT field */ + #define SCS_SHCSR_PENDSVACT (0x00000400u) + #define SCS_SHCSR_PENDSVACT_MASK (0x00000400u) + #define SCS_SHCSR_PENDSVACT_BIT (10) + #define SCS_SHCSR_PENDSVACT_BITS (1) + /* MONITORACT field */ + #define SCS_SHCSR_MONITORACT (0x00000100u) + #define SCS_SHCSR_MONITORACT_MASK (0x00000100u) + #define SCS_SHCSR_MONITORACT_BIT (8) + #define SCS_SHCSR_MONITORACT_BITS (1) + /* SVCALLACT field */ + #define SCS_SHCSR_SVCALLACT (0x00000080u) + #define SCS_SHCSR_SVCALLACT_MASK (0x00000080u) + #define SCS_SHCSR_SVCALLACT_BIT (7) + #define SCS_SHCSR_SVCALLACT_BITS (1) + /* USGFAULTACT field */ + #define SCS_SHCSR_USGFAULTACT (0x00000008u) + #define SCS_SHCSR_USGFAULTACT_MASK (0x00000008u) + #define SCS_SHCSR_USGFAULTACT_BIT (3) + #define SCS_SHCSR_USGFAULTACT_BITS (1) + /* BUSFAULTACT field */ + #define SCS_SHCSR_BUSFAULTACT (0x00000002u) + #define SCS_SHCSR_BUSFAULTACT_MASK (0x00000002u) + #define SCS_SHCSR_BUSFAULTACT_BIT (1) + #define SCS_SHCSR_BUSFAULTACT_BITS (1) + /* MEMFAULTACT field */ + #define SCS_SHCSR_MEMFAULTACT (0x00000001u) + #define SCS_SHCSR_MEMFAULTACT_MASK (0x00000001u) + #define SCS_SHCSR_MEMFAULTACT_BIT (0) + #define SCS_SHCSR_MEMFAULTACT_BITS (1) + +#define SCS_CFSR *((volatile int32u *)0xE000ED28u) +#define SCS_CFSR_REG *((volatile int32u *)0xE000ED28u) +#define SCS_CFSR_ADDR (0xE000ED28u) +#define SCS_CFSR_RESET (0x00000000u) + /* DIVBYZERO field */ + #define SCS_CFSR_DIVBYZERO (0x02000000u) + #define SCS_CFSR_DIVBYZERO_MASK (0x02000000u) + #define SCS_CFSR_DIVBYZERO_BIT (25) + #define SCS_CFSR_DIVBYZERO_BITS (1) + /* UNALIGNED field */ + #define SCS_CFSR_UNALIGNED (0x01000000u) + #define SCS_CFSR_UNALIGNED_MASK (0x01000000u) + #define SCS_CFSR_UNALIGNED_BIT (24) + #define SCS_CFSR_UNALIGNED_BITS (1) + /* NOCP field */ + #define SCS_CFSR_NOCP (0x00080000u) + #define SCS_CFSR_NOCP_MASK (0x00080000u) + #define SCS_CFSR_NOCP_BIT (19) + #define SCS_CFSR_NOCP_BITS (1) + /* INVPC field */ + #define SCS_CFSR_INVPC (0x00040000u) + #define SCS_CFSR_INVPC_MASK (0x00040000u) + #define SCS_CFSR_INVPC_BIT (18) + #define SCS_CFSR_INVPC_BITS (1) + /* INVSTATE field */ + #define SCS_CFSR_INVSTATE (0x00020000u) + #define SCS_CFSR_INVSTATE_MASK (0x00020000u) + #define SCS_CFSR_INVSTATE_BIT (17) + #define SCS_CFSR_INVSTATE_BITS (1) + /* UNDEFINSTR field */ + #define SCS_CFSR_UNDEFINSTR (0x00010000u) + #define SCS_CFSR_UNDEFINSTR_MASK (0x00010000u) + #define SCS_CFSR_UNDEFINSTR_BIT (16) + #define SCS_CFSR_UNDEFINSTR_BITS (1) + /* BFARVALID field */ + #define SCS_CFSR_BFARVALID (0x00008000u) + #define SCS_CFSR_BFARVALID_MASK (0x00008000u) + #define SCS_CFSR_BFARVALID_BIT (15) + #define SCS_CFSR_BFARVALID_BITS (1) + /* STKERR field */ + #define SCS_CFSR_STKERR (0x00001000u) + #define SCS_CFSR_STKERR_MASK (0x00001000u) + #define SCS_CFSR_STKERR_BIT (12) + #define SCS_CFSR_STKERR_BITS (1) + /* UNSTKERR field */ + #define SCS_CFSR_UNSTKERR (0x00000800u) + #define SCS_CFSR_UNSTKERR_MASK (0x00000800u) + #define SCS_CFSR_UNSTKERR_BIT (11) + #define SCS_CFSR_UNSTKERR_BITS (1) + /* IMPRECISERR field */ + #define SCS_CFSR_IMPRECISERR (0x00000400u) + #define SCS_CFSR_IMPRECISERR_MASK (0x00000400u) + #define SCS_CFSR_IMPRECISERR_BIT (10) + #define SCS_CFSR_IMPRECISERR_BITS (1) + /* PRECISERR field */ + #define SCS_CFSR_PRECISERR (0x00000200u) + #define SCS_CFSR_PRECISERR_MASK (0x00000200u) + #define SCS_CFSR_PRECISERR_BIT (9) + #define SCS_CFSR_PRECISERR_BITS (1) + /* IBUSERR field */ + #define SCS_CFSR_IBUSERR (0x00000100u) + #define SCS_CFSR_IBUSERR_MASK (0x00000100u) + #define SCS_CFSR_IBUSERR_BIT (8) + #define SCS_CFSR_IBUSERR_BITS (1) + /* MMARVALID field */ + #define SCS_CFSR_MMARVALID (0x00000080u) + #define SCS_CFSR_MMARVALID_MASK (0x00000080u) + #define SCS_CFSR_MMARVALID_BIT (7) + #define SCS_CFSR_MMARVALID_BITS (1) + /* MSTKERR field */ + #define SCS_CFSR_MSTKERR (0x00000010u) + #define SCS_CFSR_MSTKERR_MASK (0x00000010u) + #define SCS_CFSR_MSTKERR_BIT (4) + #define SCS_CFSR_MSTKERR_BITS (1) + /* MUNSTKERR field */ + #define SCS_CFSR_MUNSTKERR (0x00000008u) + #define SCS_CFSR_MUNSTKERR_MASK (0x00000008u) + #define SCS_CFSR_MUNSTKERR_BIT (3) + #define SCS_CFSR_MUNSTKERR_BITS (1) + /* DACCVIOL field */ + #define SCS_CFSR_DACCVIOL (0x00000002u) + #define SCS_CFSR_DACCVIOL_MASK (0x00000002u) + #define SCS_CFSR_DACCVIOL_BIT (1) + #define SCS_CFSR_DACCVIOL_BITS (1) + /* IACCVIOL field */ + #define SCS_CFSR_IACCVIOL (0x00000001u) + #define SCS_CFSR_IACCVIOL_MASK (0x00000001u) + #define SCS_CFSR_IACCVIOL_BIT (0) + #define SCS_CFSR_IACCVIOL_BITS (1) + +#define SCS_HFSR *((volatile int32u *)0xE000ED2Cu) +#define SCS_HFSR_REG *((volatile int32u *)0xE000ED2Cu) +#define SCS_HFSR_ADDR (0xE000ED2Cu) +#define SCS_HFSR_RESET (0x00000000u) + /* DEBUGEVT field */ + #define SCS_HFSR_DEBUGEVT (0x80000000u) + #define SCS_HFSR_DEBUGEVT_MASK (0x80000000u) + #define SCS_HFSR_DEBUGEVT_BIT (31) + #define SCS_HFSR_DEBUGEVT_BITS (1) + /* FORCED field */ + #define SCS_HFSR_FORCED (0x40000000u) + #define SCS_HFSR_FORCED_MASK (0x40000000u) + #define SCS_HFSR_FORCED_BIT (30) + #define SCS_HFSR_FORCED_BITS (1) + /* VECTTBL field */ + #define SCS_HFSR_VECTTBL (0x00000002u) + #define SCS_HFSR_VECTTBL_MASK (0x00000002u) + #define SCS_HFSR_VECTTBL_BIT (1) + #define SCS_HFSR_VECTTBL_BITS (1) + +#define SCS_DFSR *((volatile int32u *)0xE000ED30u) +#define SCS_DFSR_REG *((volatile int32u *)0xE000ED30u) +#define SCS_DFSR_ADDR (0xE000ED30u) +#define SCS_DFSR_RESET (0x00000000u) + /* EXTERNAL field */ + #define SCS_DFSR_EXTERNAL (0x00000010u) + #define SCS_DFSR_EXTERNAL_MASK (0x00000010u) + #define SCS_DFSR_EXTERNAL_BIT (4) + #define SCS_DFSR_EXTERNAL_BITS (1) + /* VCATCH field */ + #define SCS_DFSR_VCATCH (0x00000008u) + #define SCS_DFSR_VCATCH_MASK (0x00000008u) + #define SCS_DFSR_VCATCH_BIT (3) + #define SCS_DFSR_VCATCH_BITS (1) + /* DWTTRAP field */ + #define SCS_DFSR_DWTTRAP (0x00000004u) + #define SCS_DFSR_DWTTRAP_MASK (0x00000004u) + #define SCS_DFSR_DWTTRAP_BIT (2) + #define SCS_DFSR_DWTTRAP_BITS (1) + /* BKPT field */ + #define SCS_DFSR_BKPT (0x00000002u) + #define SCS_DFSR_BKPT_MASK (0x00000002u) + #define SCS_DFSR_BKPT_BIT (1) + #define SCS_DFSR_BKPT_BITS (1) + /* HALTED field */ + #define SCS_DFSR_HALTED (0x00000001u) + #define SCS_DFSR_HALTED_MASK (0x00000001u) + #define SCS_DFSR_HALTED_BIT (0) + #define SCS_DFSR_HALTED_BITS (1) + +#define SCS_MMAR *((volatile int32u *)0xE000ED34u) +#define SCS_MMAR_REG *((volatile int32u *)0xE000ED34u) +#define SCS_MMAR_ADDR (0xE000ED34u) +#define SCS_MMAR_RESET (0x00000000u) + /* ADDRESS field */ + #define SCS_MMAR_ADDRESS (0xFFFFFFFFu) + #define SCS_MMAR_ADDRESS_MASK (0xFFFFFFFFu) + #define SCS_MMAR_ADDRESS_BIT (0) + #define SCS_MMAR_ADDRESS_BITS (32) + +#define SCS_BFAR *((volatile int32u *)0xE000ED38u) +#define SCS_BFAR_REG *((volatile int32u *)0xE000ED38u) +#define SCS_BFAR_ADDR (0xE000ED38u) +#define SCS_BFAR_RESET (0x00000000u) + /* ADDRESS field */ + #define SCS_BFAR_ADDRESS (0xFFFFFFFFu) + #define SCS_BFAR_ADDRESS_MASK (0xFFFFFFFFu) + #define SCS_BFAR_ADDRESS_BIT (0) + #define SCS_BFAR_ADDRESS_BITS (32) + +#define SCS_AFSR *((volatile int32u *)0xE000ED3Cu) +#define SCS_AFSR_REG *((volatile int32u *)0xE000ED3Cu) +#define SCS_AFSR_ADDR (0xE000ED3Cu) +#define SCS_AFSR_RESET (0x00000000u) + /* WRONGSIZE field */ + #define SCS_AFSR_WRONGSIZE (0x00000008u) + #define SCS_AFSR_WRONGSIZE_MASK (0x00000008u) + #define SCS_AFSR_WRONGSIZE_BIT (3) + #define SCS_AFSR_WRONGSIZE_BITS (1) + /* PROTECTED field */ + #define SCS_AFSR_PROTECTED (0x00000004u) + #define SCS_AFSR_PROTECTED_MASK (0x00000004u) + #define SCS_AFSR_PROTECTED_BIT (2) + #define SCS_AFSR_PROTECTED_BITS (1) + /* RESERVED field */ + #define SCS_AFSR_RESERVED (0x00000002u) + #define SCS_AFSR_RESERVED_MASK (0x00000002u) + #define SCS_AFSR_RESERVED_BIT (1) + #define SCS_AFSR_RESERVED_BITS (1) + /* MISSED field */ + #define SCS_AFSR_MISSED (0x00000001u) + #define SCS_AFSR_MISSED_MASK (0x00000001u) + #define SCS_AFSR_MISSED_BIT (0) + #define SCS_AFSR_MISSED_BITS (1) + +#define SCS_PFR0 *((volatile int32u *)0xE000ED40u) +#define SCS_PFR0_REG *((volatile int32u *)0xE000ED40u) +#define SCS_PFR0_ADDR (0xE000ED40u) +#define SCS_PFR0_RESET (0x00000030u) + /* FEATURE field */ + #define SCS_PFR0_FEATURE (0xFFFFFFFFu) + #define SCS_PFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_PFR0_FEATURE_BIT (0) + #define SCS_PFR0_FEATURE_BITS (32) + +#define SCS_PFR1 *((volatile int32u *)0xE000ED44u) +#define SCS_PFR1_REG *((volatile int32u *)0xE000ED44u) +#define SCS_PFR1_ADDR (0xE000ED44u) +#define SCS_PFR1_RESET (0x00000200u) + /* FEATURE field */ + #define SCS_PFR1_FEATURE (0xFFFFFFFFu) + #define SCS_PFR1_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_PFR1_FEATURE_BIT (0) + #define SCS_PFR1_FEATURE_BITS (32) + +#define SCS_DFR0 *((volatile int32u *)0xE000ED48u) +#define SCS_DFR0_REG *((volatile int32u *)0xE000ED48u) +#define SCS_DFR0_ADDR (0xE000ED48u) +#define SCS_DFR0_RESET (0x00100000u) + /* FEATURE field */ + #define SCS_DFR0_FEATURE (0xFFFFFFFFu) + #define SCS_DFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_DFR0_FEATURE_BIT (0) + #define SCS_DFR0_FEATURE_BITS (32) + +#define SCS_AFR0 *((volatile int32u *)0xE000ED4Cu) +#define SCS_AFR0_REG *((volatile int32u *)0xE000ED4Cu) +#define SCS_AFR0_ADDR (0xE000ED4Cu) +#define SCS_AFR0_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_AFR0_FEATURE (0xFFFFFFFFu) + #define SCS_AFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_AFR0_FEATURE_BIT (0) + #define SCS_AFR0_FEATURE_BITS (32) + +#define SCS_MMFR0 *((volatile int32u *)0xE000ED50u) +#define SCS_MMFR0_REG *((volatile int32u *)0xE000ED50u) +#define SCS_MMFR0_ADDR (0xE000ED50u) +#define SCS_MMFR0_RESET (0x00000030u) + /* FEATURE field */ + #define SCS_MMFR0_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR0_FEATURE_BIT (0) + #define SCS_MMFR0_FEATURE_BITS (32) + +#define SCS_MMFR1 *((volatile int32u *)0xE000ED54u) +#define SCS_MMFR1_REG *((volatile int32u *)0xE000ED54u) +#define SCS_MMFR1_ADDR (0xE000ED54u) +#define SCS_MMFR1_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_MMFR1_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR1_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR1_FEATURE_BIT (0) + #define SCS_MMFR1_FEATURE_BITS (32) + +#define SCS_MMFR2 *((volatile int32u *)0xE000ED58u) +#define SCS_MMFR2_REG *((volatile int32u *)0xE000ED58u) +#define SCS_MMFR2_ADDR (0xE000ED58u) +#define SCS_MMFR2_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_MMFR2_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR2_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR2_FEATURE_BIT (0) + #define SCS_MMFR2_FEATURE_BITS (32) + +#define SCS_MMFR3 *((volatile int32u *)0xE000ED5Cu) +#define SCS_MMFR3_REG *((volatile int32u *)0xE000ED5Cu) +#define SCS_MMFR3_ADDR (0xE000ED5Cu) +#define SCS_MMFR3_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_MMFR3_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR3_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR3_FEATURE_BIT (0) + #define SCS_MMFR3_FEATURE_BITS (32) + +#define SCS_ISAFR0 *((volatile int32u *)0xE000ED60u) +#define SCS_ISAFR0_REG *((volatile int32u *)0xE000ED60u) +#define SCS_ISAFR0_ADDR (0xE000ED60u) +#define SCS_ISAFR0_RESET (0x01141110u) + /* FEATURE field */ + #define SCS_ISAFR0_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR0_FEATURE_BIT (0) + #define SCS_ISAFR0_FEATURE_BITS (32) + +#define SCS_ISAFR1 *((volatile int32u *)0xE000ED64u) +#define SCS_ISAFR1_REG *((volatile int32u *)0xE000ED64u) +#define SCS_ISAFR1_ADDR (0xE000ED64u) +#define SCS_ISAFR1_RESET (0x02111000u) + /* FEATURE field */ + #define SCS_ISAFR1_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR1_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR1_FEATURE_BIT (0) + #define SCS_ISAFR1_FEATURE_BITS (32) + +#define SCS_ISAFR2 *((volatile int32u *)0xE000ED68u) +#define SCS_ISAFR2_REG *((volatile int32u *)0xE000ED68u) +#define SCS_ISAFR2_ADDR (0xE000ED68u) +#define SCS_ISAFR2_RESET (0x21112231u) + /* FEATURE field */ + #define SCS_ISAFR2_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR2_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR2_FEATURE_BIT (0) + #define SCS_ISAFR2_FEATURE_BITS (32) + +#define SCS_ISAFR3 *((volatile int32u *)0xE000ED6Cu) +#define SCS_ISAFR3_REG *((volatile int32u *)0xE000ED6Cu) +#define SCS_ISAFR3_ADDR (0xE000ED6Cu) +#define SCS_ISAFR3_RESET (0x11111110u) + /* FEATURE field */ + #define SCS_ISAFR3_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR3_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR3_FEATURE_BIT (0) + #define SCS_ISAFR3_FEATURE_BITS (32) + +#define SCS_ISAFR4 *((volatile int32u *)0xE000ED70u) +#define SCS_ISAFR4_REG *((volatile int32u *)0xE000ED70u) +#define SCS_ISAFR4_ADDR (0xE000ED70u) +#define SCS_ISAFR4_RESET (0x01310102u) + /* FEATURE field */ + #define SCS_ISAFR4_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR4_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR4_FEATURE_BIT (0) + #define SCS_ISAFR4_FEATURE_BITS (32) + +#define MPU_TYPE *((volatile int32u *)0xE000ED90u) +#define MPU_TYPE_REG *((volatile int32u *)0xE000ED90u) +#define MPU_TYPE_ADDR (0xE000ED90u) +#define MPU_TYPE_RESET (0x00000800u) + /* IREGION field */ + #define MPU_TYPE_IREGION (0x00FF0000u) + #define MPU_TYPE_IREGION_MASK (0x00FF0000u) + #define MPU_TYPE_IREGION_BIT (16) + #define MPU_TYPE_IREGION_BITS (8) + /* DREGION field */ + #define MPU_TYPE_DREGION (0x0000FF00u) + #define MPU_TYPE_DREGION_MASK (0x0000FF00u) + #define MPU_TYPE_DREGION_BIT (8) + #define MPU_TYPE_DREGION_BITS (8) + +#define MPU_CTRL *((volatile int32u *)0xE000ED94u) +#define MPU_CTRL_REG *((volatile int32u *)0xE000ED94u) +#define MPU_CTRL_ADDR (0xE000ED94u) +#define MPU_CTRL_RESET (0x00000000u) + /* PRIVDEFENA field */ + #define MPU_CTRL_PRIVDEFENA (0x00000004u) + #define MPU_CTRL_PRIVDEFENA_MASK (0x00000004u) + #define MPU_CTRL_PRIVDEFENA_BIT (2) + #define MPU_CTRL_PRIVDEFENA_BITS (1) + /* HFNMIENA field */ + #define MPU_CTRL_HFNMIENA (0x00000002u) + #define MPU_CTRL_HFNMIENA_MASK (0x00000002u) + #define MPU_CTRL_HFNMIENA_BIT (1) + #define MPU_CTRL_HFNMIENA_BITS (1) + /* ENABLE field */ + #define MPU_CTRL_ENABLE (0x00000001u) + #define MPU_CTRL_ENABLE_MASK (0x00000001u) + #define MPU_CTRL_ENABLE_BIT (0) + #define MPU_CTRL_ENABLE_BITS (1) + +#define MPU_REGION *((volatile int32u *)0xE000ED98u) +#define MPU_REGION_REG *((volatile int32u *)0xE000ED98u) +#define MPU_REGION_ADDR (0xE000ED98u) +#define MPU_REGION_RESET (0x00000000u) + /* REGION field */ + #define MPU_REGION_REGION (0x000000FFu) + #define MPU_REGION_REGION_MASK (0x000000FFu) + #define MPU_REGION_REGION_BIT (0) + #define MPU_REGION_REGION_BITS (8) + +#define MPU_BASE *((volatile int32u *)0xE000ED9Cu) +#define MPU_BASE_REG *((volatile int32u *)0xE000ED9Cu) +#define MPU_BASE_ADDR (0xE000ED9Cu) +#define MPU_BASE_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE_ADDRESS_BIT (5) + #define MPU_BASE_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE_VALID (0x00000010u) + #define MPU_BASE_VALID_MASK (0x00000010u) + #define MPU_BASE_VALID_BIT (4) + #define MPU_BASE_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE_REGION (0x0000000Fu) + #define MPU_BASE_REGION_MASK (0x0000000Fu) + #define MPU_BASE_REGION_BIT (0) + #define MPU_BASE_REGION_BITS (4) + +#define MPU_ATTR *((volatile int32u *)0xE000EDA0u) +#define MPU_ATTR_REG *((volatile int32u *)0xE000EDA0u) +#define MPU_ATTR_ADDR (0xE000EDA0u) +#define MPU_ATTR_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR_XN (0x10000000u) + #define MPU_ATTR_XN_MASK (0x10000000u) + #define MPU_ATTR_XN_BIT (28) + #define MPU_ATTR_XN_BITS (1) + /* AP field */ + #define MPU_ATTR_AP (0x07000000u) + #define MPU_ATTR_AP_MASK (0x07000000u) + #define MPU_ATTR_AP_BIT (24) + #define MPU_ATTR_AP_BITS (3) + /* TEX field */ + #define MPU_ATTR_TEX (0x00380000u) + #define MPU_ATTR_TEX_MASK (0x00380000u) + #define MPU_ATTR_TEX_BIT (19) + #define MPU_ATTR_TEX_BITS (3) + /* S field */ + #define MPU_ATTR_S (0x00040000u) + #define MPU_ATTR_S_MASK (0x00040000u) + #define MPU_ATTR_S_BIT (18) + #define MPU_ATTR_S_BITS (1) + /* C field */ + #define MPU_ATTR_C (0x00020000u) + #define MPU_ATTR_C_MASK (0x00020000u) + #define MPU_ATTR_C_BIT (17) + #define MPU_ATTR_C_BITS (1) + /* B field */ + #define MPU_ATTR_B (0x00010000u) + #define MPU_ATTR_B_MASK (0x00010000u) + #define MPU_ATTR_B_BIT (16) + #define MPU_ATTR_B_BITS (1) + /* SRD field */ + #define MPU_ATTR_SRD (0x0000FF00u) + #define MPU_ATTR_SRD_MASK (0x0000FF00u) + #define MPU_ATTR_SRD_BIT (8) + #define MPU_ATTR_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR_SIZE (0x0000003Eu) + #define MPU_ATTR_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR_SIZE_BIT (1) + #define MPU_ATTR_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR_ENABLE (0x00000001u) + #define MPU_ATTR_ENABLE_MASK (0x00000001u) + #define MPU_ATTR_ENABLE_BIT (0) + #define MPU_ATTR_ENABLE_BITS (1) + +#define MPU_BASE1 *((volatile int32u *)0xE000EDA4u) +#define MPU_BASE1_REG *((volatile int32u *)0xE000EDA4u) +#define MPU_BASE1_ADDR (0xE000EDA4u) +#define MPU_BASE1_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE1_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE1_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE1_ADDRESS_BIT (5) + #define MPU_BASE1_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE1_VALID (0x00000010u) + #define MPU_BASE1_VALID_MASK (0x00000010u) + #define MPU_BASE1_VALID_BIT (4) + #define MPU_BASE1_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE1_REGION (0x0000000Fu) + #define MPU_BASE1_REGION_MASK (0x0000000Fu) + #define MPU_BASE1_REGION_BIT (0) + #define MPU_BASE1_REGION_BITS (4) + +#define MPU_ATTR1 *((volatile int32u *)0xE000EDA8u) +#define MPU_ATTR1_REG *((volatile int32u *)0xE000EDA8u) +#define MPU_ATTR1_ADDR (0xE000EDA8u) +#define MPU_ATTR1_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR1_XN (0x10000000u) + #define MPU_ATTR1_XN_MASK (0x10000000u) + #define MPU_ATTR1_XN_BIT (28) + #define MPU_ATTR1_XN_BITS (1) + /* AP field */ + #define MPU_ATTR1_AP (0x07000000u) + #define MPU_ATTR1_AP_MASK (0x07000000u) + #define MPU_ATTR1_AP_BIT (24) + #define MPU_ATTR1_AP_BITS (3) + /* TEX field */ + #define MPU_ATTR1_TEX (0x00380000u) + #define MPU_ATTR1_TEX_MASK (0x00380000u) + #define MPU_ATTR1_TEX_BIT (19) + #define MPU_ATTR1_TEX_BITS (3) + /* S field */ + #define MPU_ATTR1_S (0x00040000u) + #define MPU_ATTR1_S_MASK (0x00040000u) + #define MPU_ATTR1_S_BIT (18) + #define MPU_ATTR1_S_BITS (1) + /* C field */ + #define MPU_ATTR1_C (0x00020000u) + #define MPU_ATTR1_C_MASK (0x00020000u) + #define MPU_ATTR1_C_BIT (17) + #define MPU_ATTR1_C_BITS (1) + /* B field */ + #define MPU_ATTR1_B (0x00010000u) + #define MPU_ATTR1_B_MASK (0x00010000u) + #define MPU_ATTR1_B_BIT (16) + #define MPU_ATTR1_B_BITS (1) + /* SRD field */ + #define MPU_ATTR1_SRD (0x0000FF00u) + #define MPU_ATTR1_SRD_MASK (0x0000FF00u) + #define MPU_ATTR1_SRD_BIT (8) + #define MPU_ATTR1_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR1_SIZE (0x0000003Eu) + #define MPU_ATTR1_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR1_SIZE_BIT (1) + #define MPU_ATTR1_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR1_ENABLE (0x00000001u) + #define MPU_ATTR1_ENABLE_MASK (0x00000001u) + #define MPU_ATTR1_ENABLE_BIT (0) + #define MPU_ATTR1_ENABLE_BITS (1) + +#define MPU_BASE2 *((volatile int32u *)0xE000EDACu) +#define MPU_BASE2_REG *((volatile int32u *)0xE000EDACu) +#define MPU_BASE2_ADDR (0xE000EDACu) +#define MPU_BASE2_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE2_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE2_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE2_ADDRESS_BIT (5) + #define MPU_BASE2_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE2_VALID (0x00000010u) + #define MPU_BASE2_VALID_MASK (0x00000010u) + #define MPU_BASE2_VALID_BIT (4) + #define MPU_BASE2_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE2_REGION (0x0000000Fu) + #define MPU_BASE2_REGION_MASK (0x0000000Fu) + #define MPU_BASE2_REGION_BIT (0) + #define MPU_BASE2_REGION_BITS (4) + +#define MPU_ATTR2 *((volatile int32u *)0xE000EDB0u) +#define MPU_ATTR2_REG *((volatile int32u *)0xE000EDB0u) +#define MPU_ATTR2_ADDR (0xE000EDB0u) +#define MPU_ATTR2_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR2_XN (0x10000000u) + #define MPU_ATTR2_XN_MASK (0x10000000u) + #define MPU_ATTR2_XN_BIT (28) + #define MPU_ATTR2_XN_BITS (1) + /* AP field */ + #define MPU_ATTR2_AP (0x1F000000u) + #define MPU_ATTR2_AP_MASK (0x1F000000u) + #define MPU_ATTR2_AP_BIT (24) + #define MPU_ATTR2_AP_BITS (5) + /* TEX field */ + #define MPU_ATTR2_TEX (0x00380000u) + #define MPU_ATTR2_TEX_MASK (0x00380000u) + #define MPU_ATTR2_TEX_BIT (19) + #define MPU_ATTR2_TEX_BITS (3) + /* S field */ + #define MPU_ATTR2_S (0x00040000u) + #define MPU_ATTR2_S_MASK (0x00040000u) + #define MPU_ATTR2_S_BIT (18) + #define MPU_ATTR2_S_BITS (1) + /* C field */ + #define MPU_ATTR2_C (0x00020000u) + #define MPU_ATTR2_C_MASK (0x00020000u) + #define MPU_ATTR2_C_BIT (17) + #define MPU_ATTR2_C_BITS (1) + /* B field */ + #define MPU_ATTR2_B (0x00010000u) + #define MPU_ATTR2_B_MASK (0x00010000u) + #define MPU_ATTR2_B_BIT (16) + #define MPU_ATTR2_B_BITS (1) + /* SRD field */ + #define MPU_ATTR2_SRD (0x0000FF00u) + #define MPU_ATTR2_SRD_MASK (0x0000FF00u) + #define MPU_ATTR2_SRD_BIT (8) + #define MPU_ATTR2_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR2_SIZE (0x0000003Eu) + #define MPU_ATTR2_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR2_SIZE_BIT (1) + #define MPU_ATTR2_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR2_ENABLE (0x00000003u) + #define MPU_ATTR2_ENABLE_MASK (0x00000003u) + #define MPU_ATTR2_ENABLE_BIT (0) + #define MPU_ATTR2_ENABLE_BITS (2) + +#define MPU_BASE3 *((volatile int32u *)0xE000EDB4u) +#define MPU_BASE3_REG *((volatile int32u *)0xE000EDB4u) +#define MPU_BASE3_ADDR (0xE000EDB4u) +#define MPU_BASE3_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE3_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE3_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE3_ADDRESS_BIT (5) + #define MPU_BASE3_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE3_VALID (0x00000010u) + #define MPU_BASE3_VALID_MASK (0x00000010u) + #define MPU_BASE3_VALID_BIT (4) + #define MPU_BASE3_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE3_REGION (0x0000000Fu) + #define MPU_BASE3_REGION_MASK (0x0000000Fu) + #define MPU_BASE3_REGION_BIT (0) + #define MPU_BASE3_REGION_BITS (4) + +#define MPU_ATTR3 *((volatile int32u *)0xE000EDBCu) +#define MPU_ATTR3_REG *((volatile int32u *)0xE000EDBCu) +#define MPU_ATTR3_ADDR (0xE000EDBCu) +#define MPU_ATTR3_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR3_XN (0x10000000u) + #define MPU_ATTR3_XN_MASK (0x10000000u) + #define MPU_ATTR3_XN_BIT (28) + #define MPU_ATTR3_XN_BITS (1) + /* AP field */ + #define MPU_ATTR3_AP (0x1F000000u) + #define MPU_ATTR3_AP_MASK (0x1F000000u) + #define MPU_ATTR3_AP_BIT (24) + #define MPU_ATTR3_AP_BITS (5) + /* TEX field */ + #define MPU_ATTR3_TEX (0x00380000u) + #define MPU_ATTR3_TEX_MASK (0x00380000u) + #define MPU_ATTR3_TEX_BIT (19) + #define MPU_ATTR3_TEX_BITS (3) + /* S field */ + #define MPU_ATTR3_S (0x00040000u) + #define MPU_ATTR3_S_MASK (0x00040000u) + #define MPU_ATTR3_S_BIT (18) + #define MPU_ATTR3_S_BITS (1) + /* C field */ + #define MPU_ATTR3_C (0x00020000u) + #define MPU_ATTR3_C_MASK (0x00020000u) + #define MPU_ATTR3_C_BIT (17) + #define MPU_ATTR3_C_BITS (1) + /* B field */ + #define MPU_ATTR3_B (0x00010000u) + #define MPU_ATTR3_B_MASK (0x00010000u) + #define MPU_ATTR3_B_BIT (16) + #define MPU_ATTR3_B_BITS (1) + /* SRD field */ + #define MPU_ATTR3_SRD (0x0000FF00u) + #define MPU_ATTR3_SRD_MASK (0x0000FF00u) + #define MPU_ATTR3_SRD_BIT (8) + #define MPU_ATTR3_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR3_SIZE (0x0000003Eu) + #define MPU_ATTR3_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR3_SIZE_BIT (1) + #define MPU_ATTR3_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR3_ENABLE (0x00000003u) + #define MPU_ATTR3_ENABLE_MASK (0x00000003u) + #define MPU_ATTR3_ENABLE_BIT (0) + #define MPU_ATTR3_ENABLE_BITS (2) + +#define DEBUG_HCSR *((volatile int32u *)0xE000EDF0u) +#define DEBUG_HCSR_REG *((volatile int32u *)0xE000EDF0u) +#define DEBUG_HCSR_ADDR (0xE000EDF0u) +#define DEBUG_HCSR_RESET (0x00000000u) + /* S_RESET_ST field */ + #define DEBUG_HCSR_S_RESET_ST (0x02000000u) + #define DEBUG_HCSR_S_RESET_ST_MASK (0x02000000u) + #define DEBUG_HCSR_S_RESET_ST_BIT (25) + #define DEBUG_HCSR_S_RESET_ST_BITS (1) + /* S_RETIRE_ST field */ + #define DEBUG_HCSR_S_RETIRE_ST (0x01000000u) + #define DEBUG_HCSR_S_RETIRE_ST_MASK (0x01000000u) + #define DEBUG_HCSR_S_RETIRE_ST_BIT (24) + #define DEBUG_HCSR_S_RETIRE_ST_BITS (1) + /* S_LOCKUP field */ + #define DEBUG_HCSR_S_LOCKUP (0x00080000u) + #define DEBUG_HCSR_S_LOCKUP_MASK (0x00080000u) + #define DEBUG_HCSR_S_LOCKUP_BIT (19) + #define DEBUG_HCSR_S_LOCKUP_BITS (1) + /* S_SLEEP field */ + #define DEBUG_HCSR_S_SLEEP (0x00040000u) + #define DEBUG_HCSR_S_SLEEP_MASK (0x00040000u) + #define DEBUG_HCSR_S_SLEEP_BIT (18) + #define DEBUG_HCSR_S_SLEEP_BITS (1) + /* S_HALT field */ + #define DEBUG_HCSR_S_HALT (0x00020000u) + #define DEBUG_HCSR_S_HALT_MASK (0x00020000u) + #define DEBUG_HCSR_S_HALT_BIT (17) + #define DEBUG_HCSR_S_HALT_BITS (1) + /* S_REGRDY field */ + #define DEBUG_HCSR_S_REGRDY (0x00010000u) + #define DEBUG_HCSR_S_REGRDY_MASK (0x00010000u) + #define DEBUG_HCSR_S_REGRDY_BIT (16) + #define DEBUG_HCSR_S_REGRDY_BITS (1) + /* DBGKEY field */ + #define DEBUG_HCSR_DBGKEY (0xFFFF0000u) + #define DEBUG_HCSR_DBGKEY_MASK (0xFFFF0000u) + #define DEBUG_HCSR_DBGKEY_BIT (16) + #define DEBUG_HCSR_DBGKEY_BITS (16) + /* C_SNAPSTALL field */ + #define DEBUG_HCSR_C_SNAPSTALL (0x00000020u) + #define DEBUG_HCSR_C_SNAPSTALL_MASK (0x00000020u) + #define DEBUG_HCSR_C_SNAPSTALL_BIT (5) + #define DEBUG_HCSR_C_SNAPSTALL_BITS (1) + /* C_MASKINTS field */ + #define DEBUG_HCSR_C_MASKINTS (0x00000008u) + #define DEBUG_HCSR_C_MASKINTS_MASK (0x00000008u) + #define DEBUG_HCSR_C_MASKINTS_BIT (3) + #define DEBUG_HCSR_C_MASKINTS_BITS (1) + /* C_STEP field */ + #define DEBUG_HCSR_C_STEP (0x00000004u) + #define DEBUG_HCSR_C_STEP_MASK (0x00000004u) + #define DEBUG_HCSR_C_STEP_BIT (2) + #define DEBUG_HCSR_C_STEP_BITS (1) + /* C_HALT field */ + #define DEBUG_HCSR_C_HALT (0x00000002u) + #define DEBUG_HCSR_C_HALT_MASK (0x00000002u) + #define DEBUG_HCSR_C_HALT_BIT (1) + #define DEBUG_HCSR_C_HALT_BITS (1) + /* C_DEBUGEN field */ + #define DEBUG_HCSR_C_DEBUGEN (0x00000001u) + #define DEBUG_HCSR_C_DEBUGEN_MASK (0x00000001u) + #define DEBUG_HCSR_C_DEBUGEN_BIT (0) + #define DEBUG_HCSR_C_DEBUGEN_BITS (1) + +#define DEBUG_CRSR *((volatile int32u *)0xE000EDF4u) +#define DEBUG_CRSR_REG *((volatile int32u *)0xE000EDF4u) +#define DEBUG_CRSR_ADDR (0xE000EDF4u) +#define DEBUG_CRSR_RESET (0x00000000u) + /* REGWnR field */ + #define DEBUG_CRSR_REGWnR (0x00010000u) + #define DEBUG_CRSR_REGWnR_MASK (0x00010000u) + #define DEBUG_CRSR_REGWnR_BIT (16) + #define DEBUG_CRSR_REGWnR_BITS (1) + /* REGSEL field */ + #define DEBUG_CRSR_REGSEL (0x0000001Fu) + #define DEBUG_CRSR_REGSEL_MASK (0x0000001Fu) + #define DEBUG_CRSR_REGSEL_BIT (0) + #define DEBUG_CRSR_REGSEL_BITS (5) + +#define DEBUG_CRDR *((volatile int32u *)0xE000EDF8u) +#define DEBUG_CRDR_REG *((volatile int32u *)0xE000EDF8u) +#define DEBUG_CRDR_ADDR (0xE000EDF8u) +#define DEBUG_CRDR_RESET (0x00000000u) + /* DBGTMP field */ + #define DEBUG_CRDR_DBGTMP (0xFFFFFFFFu) + #define DEBUG_CRDR_DBGTMP_MASK (0xFFFFFFFFu) + #define DEBUG_CRDR_DBGTMP_BIT (0) + #define DEBUG_CRDR_DBGTMP_BITS (32) + +#define DEBUG_EMCR *((volatile int32u *)0xE000EDFCu) +#define DEBUG_EMCR_REG *((volatile int32u *)0xE000EDFCu) +#define DEBUG_EMCR_ADDR (0xE000EDFCu) +#define DEBUG_EMCR_RESET (0x00000000u) + /* TRCENA field */ + #define DEBUG_EMCR_TRCENA (0x01000000u) + #define DEBUG_EMCR_TRCENA_MASK (0x01000000u) + #define DEBUG_EMCR_TRCENA_BIT (24) + #define DEBUG_EMCR_TRCENA_BITS (1) + /* MON_REQ field */ + #define DEBUG_EMCR_MON_REQ (0x00080000u) + #define DEBUG_EMCR_MON_REQ_MASK (0x00080000u) + #define DEBUG_EMCR_MON_REQ_BIT (19) + #define DEBUG_EMCR_MON_REQ_BITS (1) + /* MON_STEP field */ + #define DEBUG_EMCR_MON_STEP (0x00040000u) + #define DEBUG_EMCR_MON_STEP_MASK (0x00040000u) + #define DEBUG_EMCR_MON_STEP_BIT (18) + #define DEBUG_EMCR_MON_STEP_BITS (1) + /* MON_PEND field */ + #define DEBUG_EMCR_MON_PEND (0x00020000u) + #define DEBUG_EMCR_MON_PEND_MASK (0x00020000u) + #define DEBUG_EMCR_MON_PEND_BIT (17) + #define DEBUG_EMCR_MON_PEND_BITS (1) + /* MON_EN field */ + #define DEBUG_EMCR_MON_EN (0x00010000u) + #define DEBUG_EMCR_MON_EN_MASK (0x00010000u) + #define DEBUG_EMCR_MON_EN_BIT (16) + #define DEBUG_EMCR_MON_EN_BITS (1) + /* VC_HARDERR field */ + #define DEBUG_EMCR_VC_HARDERR (0x00000400u) + #define DEBUG_EMCR_VC_HARDERR_MASK (0x00000400u) + #define DEBUG_EMCR_VC_HARDERR_BIT (10) + #define DEBUG_EMCR_VC_HARDERR_BITS (1) + /* VC_INTERR field */ + #define DEBUG_EMCR_VC_INTERR (0x00000200u) + #define DEBUG_EMCR_VC_INTERR_MASK (0x00000200u) + #define DEBUG_EMCR_VC_INTERR_BIT (9) + #define DEBUG_EMCR_VC_INTERR_BITS (1) + /* VC_BUSERR field */ + #define DEBUG_EMCR_VC_BUSERR (0x00000100u) + #define DEBUG_EMCR_VC_BUSERR_MASK (0x00000100u) + #define DEBUG_EMCR_VC_BUSERR_BIT (8) + #define DEBUG_EMCR_VC_BUSERR_BITS (1) + /* VC_STATERR field */ + #define DEBUG_EMCR_VC_STATERR (0x00000080u) + #define DEBUG_EMCR_VC_STATERR_MASK (0x00000080u) + #define DEBUG_EMCR_VC_STATERR_BIT (7) + #define DEBUG_EMCR_VC_STATERR_BITS (1) + /* VC_CHKERR field */ + #define DEBUG_EMCR_VC_CHKERR (0x00000040u) + #define DEBUG_EMCR_VC_CHKERR_MASK (0x00000040u) + #define DEBUG_EMCR_VC_CHKERR_BIT (6) + #define DEBUG_EMCR_VC_CHKERR_BITS (1) + /* VC_NOCPERR field */ + #define DEBUG_EMCR_VC_NOCPERR (0x00000020u) + #define DEBUG_EMCR_VC_NOCPERR_MASK (0x00000020u) + #define DEBUG_EMCR_VC_NOCPERR_BIT (5) + #define DEBUG_EMCR_VC_NOCPERR_BITS (1) + /* VC_MMERR field */ + #define DEBUG_EMCR_VC_MMERR (0x00000010u) + #define DEBUG_EMCR_VC_MMERR_MASK (0x00000010u) + #define DEBUG_EMCR_VC_MMERR_BIT (4) + #define DEBUG_EMCR_VC_MMERR_BITS (1) + /* VC_CORERESET field */ + #define DEBUG_EMCR_VC_CORERESET (0x00000001u) + #define DEBUG_EMCR_VC_CORERESET_MASK (0x00000001u) + #define DEBUG_EMCR_VC_CORERESET_BIT (0) + #define DEBUG_EMCR_VC_CORERESET_BITS (1) + +#define NVIC_STIR *((volatile int32u *)0xE000EF00u) +#define NVIC_STIR_REG *((volatile int32u *)0xE000EF00u) +#define NVIC_STIR_ADDR (0xE000EF00u) +#define NVIC_STIR_RESET (0x00000000u) + /* INTID field */ + #define NVIC_STIR_INTID (0x000003FFu) + #define NVIC_STIR_INTID_MASK (0x000003FFu) + #define NVIC_STIR_INTID_BIT (0) + #define NVIC_STIR_INTID_BITS (10) + +#define NVIC_PERIPHID4 *((volatile int32u *)0xE000EFD0u) +#define NVIC_PERIPHID4_REG *((volatile int32u *)0xE000EFD0u) +#define NVIC_PERIPHID4_ADDR (0xE000EFD0u) +#define NVIC_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define NVIC_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID4_PERIPHID_BIT (0) + #define NVIC_PERIPHID4_PERIPHID_BITS (32) + +#define NVIC_PERIPHID5 *((volatile int32u *)0xE000EFD4u) +#define NVIC_PERIPHID5_REG *((volatile int32u *)0xE000EFD4u) +#define NVIC_PERIPHID5_ADDR (0xE000EFD4u) +#define NVIC_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID5_PERIPHID_BIT (0) + #define NVIC_PERIPHID5_PERIPHID_BITS (32) + +#define NVIC_PERIPHID6 *((volatile int32u *)0xE000EFD8u) +#define NVIC_PERIPHID6_REG *((volatile int32u *)0xE000EFD8u) +#define NVIC_PERIPHID6_ADDR (0xE000EFD8u) +#define NVIC_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID6_PERIPHID_BIT (0) + #define NVIC_PERIPHID6_PERIPHID_BITS (32) + +#define NVIC_PERIPHID7 *((volatile int32u *)0xE000EFDCu) +#define NVIC_PERIPHID7_REG *((volatile int32u *)0xE000EFDCu) +#define NVIC_PERIPHID7_ADDR (0xE000EFDCu) +#define NVIC_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID7_PERIPHID_BIT (0) + #define NVIC_PERIPHID7_PERIPHID_BITS (32) + +#define NVIC_PERIPHID0 *((volatile int32u *)0xE000EFE0u) +#define NVIC_PERIPHID0_REG *((volatile int32u *)0xE000EFE0u) +#define NVIC_PERIPHID0_ADDR (0xE000EFE0u) +#define NVIC_PERIPHID0_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID0_PERIPHID_BIT (0) + #define NVIC_PERIPHID0_PERIPHID_BITS (32) + +#define NVIC_PERIPHID1 *((volatile int32u *)0xE000EFE4u) +#define NVIC_PERIPHID1_REG *((volatile int32u *)0xE000EFE4u) +#define NVIC_PERIPHID1_ADDR (0xE000EFE4u) +#define NVIC_PERIPHID1_RESET (0x000000B0u) + /* PERIPHID field */ + #define NVIC_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID1_PERIPHID_BIT (0) + #define NVIC_PERIPHID1_PERIPHID_BITS (32) + +#define NVIC_PERIPHID2 *((volatile int32u *)0xE000EFE8u) +#define NVIC_PERIPHID2_REG *((volatile int32u *)0xE000EFE8u) +#define NVIC_PERIPHID2_ADDR (0xE000EFE8u) +#define NVIC_PERIPHID2_RESET (0x0000001Bu) + /* PERIPHID field */ + #define NVIC_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID2_PERIPHID_BIT (0) + #define NVIC_PERIPHID2_PERIPHID_BITS (32) + +#define NVIC_PERIPHID3 *((volatile int32u *)0xE000EFECu) +#define NVIC_PERIPHID3_REG *((volatile int32u *)0xE000EFECu) +#define NVIC_PERIPHID3_ADDR (0xE000EFECu) +#define NVIC_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID3_PERIPHID_BIT (0) + #define NVIC_PERIPHID3_PERIPHID_BITS (32) + +#define NVIC_PCELLID0 *((volatile int32u *)0xE000EFF0u) +#define NVIC_PCELLID0_REG *((volatile int32u *)0xE000EFF0u) +#define NVIC_PCELLID0_ADDR (0xE000EFF0u) +#define NVIC_PCELLID0_RESET (0x0000000Du) + /* PCELLID field */ + #define NVIC_PCELLID0_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID0_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID0_PCELLID_BIT (0) + #define NVIC_PCELLID0_PCELLID_BITS (32) + +#define NVIC_PCELLID1 *((volatile int32u *)0xE000EFF4u) +#define NVIC_PCELLID1_REG *((volatile int32u *)0xE000EFF4u) +#define NVIC_PCELLID1_ADDR (0xE000EFF4u) +#define NVIC_PCELLID1_RESET (0x000000E0u) + /* PCELLID field */ + #define NVIC_PCELLID1_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID1_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID1_PCELLID_BIT (0) + #define NVIC_PCELLID1_PCELLID_BITS (32) + +#define NVIC_PCELLID2 *((volatile int32u *)0xE000EFF8u) +#define NVIC_PCELLID2_REG *((volatile int32u *)0xE000EFF8u) +#define NVIC_PCELLID2_ADDR (0xE000EFF8u) +#define NVIC_PCELLID2_RESET (0x00000005u) + /* PCELLID field */ + #define NVIC_PCELLID2_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID2_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID2_PCELLID_BIT (0) + #define NVIC_PCELLID2_PCELLID_BITS (32) + +#define NVIC_PCELLID3 *((volatile int32u *)0xE000EFFCu) +#define NVIC_PCELLID3_REG *((volatile int32u *)0xE000EFFCu) +#define NVIC_PCELLID3_ADDR (0xE000EFFCu) +#define NVIC_PCELLID3_RESET (0x000000B1u) + /* PCELLID field */ + #define NVIC_PCELLID3_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID3_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID3_PCELLID_BIT (0) + #define NVIC_PCELLID3_PCELLID_BITS (32) + +/* TPIU block */ +#define DATA_TPIU_BASE (0xE0040000u) +#define DATA_TPIU_END (0xE0040EF8u) +#define DATA_TPIU_SIZE (DATA_TPIU_END - DATA_TPIU_BASE + 1) + +#define TPIU_SPS *((volatile int32u *)0xE0040000u) +#define TPIU_SPS_REG *((volatile int32u *)0xE0040000u) +#define TPIU_SPS_ADDR (0xE0040000u) +#define TPIU_SPS_RESET (0x00000000u) + /* SPS_04 field */ + #define TPIU_SPS_SPS_04 (0x00000008u) + #define TPIU_SPS_SPS_04_MASK (0x00000008u) + #define TPIU_SPS_SPS_04_BIT (3) + #define TPIU_SPS_SPS_04_BITS (1) + /* SPS_03 field */ + #define TPIU_SPS_SPS_03 (0x00000004u) + #define TPIU_SPS_SPS_03_MASK (0x00000004u) + #define TPIU_SPS_SPS_03_BIT (2) + #define TPIU_SPS_SPS_03_BITS (1) + /* SPS_02 field */ + #define TPIU_SPS_SPS_02 (0x00000002u) + #define TPIU_SPS_SPS_02_MASK (0x00000002u) + #define TPIU_SPS_SPS_02_BIT (1) + #define TPIU_SPS_SPS_02_BITS (1) + /* SPS_01 field */ + #define TPIU_SPS_SPS_01 (0x00000001u) + #define TPIU_SPS_SPS_01_MASK (0x00000001u) + #define TPIU_SPS_SPS_01_BIT (0) + #define TPIU_SPS_SPS_01_BITS (1) + +#define TPIU_CPS *((volatile int32u *)0xE0040004u) +#define TPIU_CPS_REG *((volatile int32u *)0xE0040004u) +#define TPIU_CPS_ADDR (0xE0040004u) +#define TPIU_CPS_RESET (0x00000001u) + /* CPS_04 field */ + #define TPIU_CPS_CPS_04 (0x00000008u) + #define TPIU_CPS_CPS_04_MASK (0x00000008u) + #define TPIU_CPS_CPS_04_BIT (3) + #define TPIU_CPS_CPS_04_BITS (1) + /* CPS_03 field */ + #define TPIU_CPS_CPS_03 (0x00000004u) + #define TPIU_CPS_CPS_03_MASK (0x00000004u) + #define TPIU_CPS_CPS_03_BIT (2) + #define TPIU_CPS_CPS_03_BITS (1) + /* CPS_02 field */ + #define TPIU_CPS_CPS_02 (0x00000002u) + #define TPIU_CPS_CPS_02_MASK (0x00000002u) + #define TPIU_CPS_CPS_02_BIT (1) + #define TPIU_CPS_CPS_02_BITS (1) + /* CPS_01 field */ + #define TPIU_CPS_CPS_01 (0x00000001u) + #define TPIU_CPS_CPS_01_MASK (0x00000001u) + #define TPIU_CPS_CPS_01_BIT (0) + #define TPIU_CPS_CPS_01_BITS (1) + +#define TPIU_COSD *((volatile int32u *)0xE0040010u) +#define TPIU_COSD_REG *((volatile int32u *)0xE0040010u) +#define TPIU_COSD_ADDR (0xE0040010u) +#define TPIU_COSD_RESET (0x00000000u) + /* PRESCALER field */ + #define TPIU_COSD_PRESCALER (0x00001FFFu) + #define TPIU_COSD_PRESCALER_MASK (0x00001FFFu) + #define TPIU_COSD_PRESCALER_BIT (0) + #define TPIU_COSD_PRESCALER_BITS (13) + +#define TPIU_SPP *((volatile int32u *)0xE00400F0u) +#define TPIU_SPP_REG *((volatile int32u *)0xE00400F0u) +#define TPIU_SPP_ADDR (0xE00400F0u) +#define TPIU_SPP_RESET (0x00000001u) + /* PROTOCOL field */ + #define TPIU_SPP_PROTOCOL (0x00000003u) + #define TPIU_SPP_PROTOCOL_MASK (0x00000003u) + #define TPIU_SPP_PROTOCOL_BIT (0) + #define TPIU_SPP_PROTOCOL_BITS (2) + +#define TPIU_FFS *((volatile int32u *)0xE0040300u) +#define TPIU_FFS_REG *((volatile int32u *)0xE0040300u) +#define TPIU_FFS_ADDR (0xE0040300u) +#define TPIU_FFS_RESET (0x00000008u) + /* FTNONSTOP field */ + #define TPIU_FFS_FTNONSTOP (0x00000008u) + #define TPIU_FFS_FTNONSTOP_MASK (0x00000008u) + #define TPIU_FFS_FTNONSTOP_BIT (3) + #define TPIU_FFS_FTNONSTOP_BITS (1) + /* TCPRESENT field */ + #define TPIU_FFS_TCPRESENT (0x00000004u) + #define TPIU_FFS_TCPRESENT_MASK (0x00000004u) + #define TPIU_FFS_TCPRESENT_BIT (2) + #define TPIU_FFS_TCPRESENT_BITS (1) + /* FTSTOPPED field */ + #define TPIU_FFS_FTSTOPPED (0x00000002u) + #define TPIU_FFS_FTSTOPPED_MASK (0x00000002u) + #define TPIU_FFS_FTSTOPPED_BIT (1) + #define TPIU_FFS_FTSTOPPED_BITS (1) + /* FLINPROG field */ + #define TPIU_FFS_FLINPROG (0x00000001u) + #define TPIU_FFS_FLINPROG_MASK (0x00000001u) + #define TPIU_FFS_FLINPROG_BIT (0) + #define TPIU_FFS_FLINPROG_BITS (1) + +#define TPIU_FFC *((volatile int32u *)0xE0040304u) +#define TPIU_FFC_REG *((volatile int32u *)0xE0040304u) +#define TPIU_FFC_ADDR (0xE0040304u) +#define TPIU_FFC_RESET (0x00000102u) + /* TRIGIN field */ + #define TPIU_FFC_TRIGIN (0x00000100u) + #define TPIU_FFC_TRIGIN_MASK (0x00000100u) + #define TPIU_FFC_TRIGIN_BIT (8) + #define TPIU_FFC_TRIGIN_BITS (1) + /* ENFCONT field */ + #define TPIU_FFC_ENFCONT (0x00000002u) + #define TPIU_FFC_ENFCONT_MASK (0x00000002u) + #define TPIU_FFC_ENFCONT_BIT (1) + #define TPIU_FFC_ENFCONT_BITS (1) + +#define TPIU_FSC *((volatile int32u *)0xE0040308u) +#define TPIU_FSC_REG *((volatile int32u *)0xE0040308u) +#define TPIU_FSC_ADDR (0xE0040308u) +#define TPIU_FSC_RESET (0x00000000u) + /* FSC field */ + #define TPIU_FSC_FSC (0xFFFFFFFFu) + #define TPIU_FSC_FSC_MASK (0xFFFFFFFFu) + #define TPIU_FSC_FSC_BIT (0) + #define TPIU_FSC_FSC_BITS (32) + +#define TPIU_ITATBCTR2 *((volatile int32u *)0xE0040EF0u) +#define TPIU_ITATBCTR2_REG *((volatile int32u *)0xE0040EF0u) +#define TPIU_ITATBCTR2_ADDR (0xE0040EF0u) +#define TPIU_ITATBCTR2_RESET (0x00000000u) + /* ATREADY1 field */ + #define TPIU_ITATBCTR2_ATREADY1 (0x00000001u) + #define TPIU_ITATBCTR2_ATREADY1_MASK (0x00000001u) + #define TPIU_ITATBCTR2_ATREADY1_BIT (0) + #define TPIU_ITATBCTR2_ATREADY1_BITS (1) + +#define TPIU_ITATBCTR0 *((volatile int32u *)0xE0040EF8u) +#define TPIU_ITATBCTR0_REG *((volatile int32u *)0xE0040EF8u) +#define TPIU_ITATBCTR0_ADDR (0xE0040EF8u) +#define TPIU_ITATBCTR0_RESET (0x00000000u) + /* ATREADY1 field */ + #define TPIU_ITATBCTR0_ATREADY1 (0x00000001u) + #define TPIU_ITATBCTR0_ATREADY1_MASK (0x00000001u) + #define TPIU_ITATBCTR0_ATREADY1_BIT (0) + #define TPIU_ITATBCTR0_ATREADY1_BITS (1) + +/* ETM block */ +#define DATA_ETM_BASE (0xE0041000u) +#define DATA_ETM_END (0xE0041FFFu) +#define DATA_ETM_SIZE (DATA_ETM_END - DATA_ETM_BASE + 1) + +/* ROM_TAB block */ +#define DATA_ROM_TAB_BASE (0xE00FF000u) +#define DATA_ROM_TAB_END (0xE00FFFFFu) +#define DATA_ROM_TAB_SIZE (DATA_ROM_TAB_END - DATA_ROM_TAB_BASE + 1) + +#define ROM_SCS *((volatile int32u *)0xE00FF000u) +#define ROM_SCS_REG *((volatile int32u *)0xE00FF000u) +#define ROM_SCS_ADDR (0xE00FF000u) +#define ROM_SCS_RESET (0xFFF0F003u) + /* ADDR_OFF field */ + #define ROM_SCS_ADDR_OFF (0xFFFFF000u) + #define ROM_SCS_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_SCS_ADDR_OFF_BIT (12) + #define ROM_SCS_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_SCS_FORMAT (0x00000002u) + #define ROM_SCS_FORMAT_MASK (0x00000002u) + #define ROM_SCS_FORMAT_BIT (1) + #define ROM_SCS_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_SCS_ENTRY_PRES (0x00000001u) + #define ROM_SCS_ENTRY_PRES_MASK (0x00000001u) + #define ROM_SCS_ENTRY_PRES_BIT (0) + #define ROM_SCS_ENTRY_PRES_BITS (1) + +#define ROM_DWT *((volatile int32u *)0xE00FF004u) +#define ROM_DWT_REG *((volatile int32u *)0xE00FF004u) +#define ROM_DWT_ADDR (0xE00FF004u) +#define ROM_DWT_RESET (0xFFF02003u) + /* ADDR_OFF field */ + #define ROM_DWT_ADDR_OFF (0xFFFFF000u) + #define ROM_DWT_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_DWT_ADDR_OFF_BIT (12) + #define ROM_DWT_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_DWT_FORMAT (0x00000002u) + #define ROM_DWT_FORMAT_MASK (0x00000002u) + #define ROM_DWT_FORMAT_BIT (1) + #define ROM_DWT_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_DWT_ENTRY_PRES (0x00000001u) + #define ROM_DWT_ENTRY_PRES_MASK (0x00000001u) + #define ROM_DWT_ENTRY_PRES_BIT (0) + #define ROM_DWT_ENTRY_PRES_BITS (1) + +#define ROM_FPB *((volatile int32u *)0xE00FF008u) +#define ROM_FPB_REG *((volatile int32u *)0xE00FF008u) +#define ROM_FPB_ADDR (0xE00FF008u) +#define ROM_FPB_RESET (0xFFF03003u) + /* ADDR_OFF field */ + #define ROM_FPB_ADDR_OFF (0xFFFFF000u) + #define ROM_FPB_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_FPB_ADDR_OFF_BIT (12) + #define ROM_FPB_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_FPB_FORMAT (0x00000002u) + #define ROM_FPB_FORMAT_MASK (0x00000002u) + #define ROM_FPB_FORMAT_BIT (1) + #define ROM_FPB_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_FPB_ENTRY_PRES (0x00000001u) + #define ROM_FPB_ENTRY_PRES_MASK (0x00000001u) + #define ROM_FPB_ENTRY_PRES_BIT (0) + #define ROM_FPB_ENTRY_PRES_BITS (1) + +#define ROM_ITM *((volatile int32u *)0xE00FF00Cu) +#define ROM_ITM_REG *((volatile int32u *)0xE00FF00Cu) +#define ROM_ITM_ADDR (0xE00FF00Cu) +#define ROM_ITM_RESET (0xFFF01003u) + /* ADDR_OFF field */ + #define ROM_ITM_ADDR_OFF (0xFFFFF000u) + #define ROM_ITM_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_ITM_ADDR_OFF_BIT (12) + #define ROM_ITM_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_ITM_FORMAT (0x00000002u) + #define ROM_ITM_FORMAT_MASK (0x00000002u) + #define ROM_ITM_FORMAT_BIT (1) + #define ROM_ITM_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_ITM_ENTRY_PRES (0x00000001u) + #define ROM_ITM_ENTRY_PRES_MASK (0x00000001u) + #define ROM_ITM_ENTRY_PRES_BIT (0) + #define ROM_ITM_ENTRY_PRES_BITS (1) + +#define ROM_TPIU *((volatile int32u *)0xE00FF010u) +#define ROM_TPIU_REG *((volatile int32u *)0xE00FF010u) +#define ROM_TPIU_ADDR (0xE00FF010u) +#define ROM_TPIU_RESET (0xFFF0F003u) + /* ADDR_OFF field */ + #define ROM_TPIU_ADDR_OFF (0xFFFFF000u) + #define ROM_TPIU_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_TPIU_ADDR_OFF_BIT (12) + #define ROM_TPIU_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_TPIU_FORMAT (0x00000002u) + #define ROM_TPIU_FORMAT_MASK (0x00000002u) + #define ROM_TPIU_FORMAT_BIT (1) + #define ROM_TPIU_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_TPIU_ENTRY_PRES (0x00000001u) + #define ROM_TPIU_ENTRY_PRES_MASK (0x00000001u) + #define ROM_TPIU_ENTRY_PRES_BIT (0) + #define ROM_TPIU_ENTRY_PRES_BITS (1) + +#define ROM_ETM *((volatile int32u *)0xE00FF014u) +#define ROM_ETM_REG *((volatile int32u *)0xE00FF014u) +#define ROM_ETM_ADDR (0xE00FF014u) +#define ROM_ETM_RESET (0xFFF0F002u) + /* ADDR_OFF field */ + #define ROM_ETM_ADDR_OFF (0xFFFFF000u) + #define ROM_ETM_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_ETM_ADDR_OFF_BIT (12) + #define ROM_ETM_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_ETM_FORMAT (0x00000002u) + #define ROM_ETM_FORMAT_MASK (0x00000002u) + #define ROM_ETM_FORMAT_BIT (1) + #define ROM_ETM_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_ETM_ENTRY_PRES (0x00000001u) + #define ROM_ETM_ENTRY_PRES_MASK (0x00000001u) + #define ROM_ETM_ENTRY_PRES_BIT (0) + #define ROM_ETM_ENTRY_PRES_BITS (1) + +#define ROM_END *((volatile int32u *)0xE00FF018u) +#define ROM_END_REG *((volatile int32u *)0xE00FF018u) +#define ROM_END_ADDR (0xE00FF018u) +#define ROM_END_RESET (0x00000000u) + /* END field */ + #define ROM_END_END (0xFFFFFFFFu) + #define ROM_END_END_MASK (0xFFFFFFFFu) + #define ROM_END_END_BIT (0) + #define ROM_END_END_BITS (32) + +#define ROM_MEMTYPE *((volatile int32u *)0xE00FFFCCu) +#define ROM_MEMTYPE_REG *((volatile int32u *)0xE00FFFCCu) +#define ROM_MEMTYPE_ADDR (0xE00FFFCCu) +#define ROM_MEMTYPE_RESET (0x00000001u) + /* MEMTYPE field */ + #define ROM_MEMTYPE_MEMTYPE (0x00000001u) + #define ROM_MEMTYPE_MEMTYPE_MASK (0x00000001u) + #define ROM_MEMTYPE_MEMTYPE_BIT (0) + #define ROM_MEMTYPE_MEMTYPE_BITS (1) + +#define ROM_PID4 *((volatile int32u *)0xE00FFFD0u) +#define ROM_PID4_REG *((volatile int32u *)0xE00FFFD0u) +#define ROM_PID4_ADDR (0xE00FFFD0u) +#define ROM_PID4_RESET (0x00000000u) + /* PID field */ + #define ROM_PID4_PID (0x0000000Fu) + #define ROM_PID4_PID_MASK (0x0000000Fu) + #define ROM_PID4_PID_BIT (0) + #define ROM_PID4_PID_BITS (4) + +#define ROM_PID5 *((volatile int32u *)0xE00FFFD4u) +#define ROM_PID5_REG *((volatile int32u *)0xE00FFFD4u) +#define ROM_PID5_ADDR (0xE00FFFD4u) +#define ROM_PID5_RESET (0x00000000u) + /* PID field */ + #define ROM_PID5_PID (0x0000000Fu) + #define ROM_PID5_PID_MASK (0x0000000Fu) + #define ROM_PID5_PID_BIT (0) + #define ROM_PID5_PID_BITS (4) + +#define ROM_PID6 *((volatile int32u *)0xE00FFFD8u) +#define ROM_PID6_REG *((volatile int32u *)0xE00FFFD8u) +#define ROM_PID6_ADDR (0xE00FFFD8u) +#define ROM_PID6_RESET (0x00000000u) + /* PID field */ + #define ROM_PID6_PID (0x0000000Fu) + #define ROM_PID6_PID_MASK (0x0000000Fu) + #define ROM_PID6_PID_BIT (0) + #define ROM_PID6_PID_BITS (4) + +#define ROM_PID7 *((volatile int32u *)0xE00FFFDCu) +#define ROM_PID7_REG *((volatile int32u *)0xE00FFFDCu) +#define ROM_PID7_ADDR (0xE00FFFDCu) +#define ROM_PID7_RESET (0x00000000u) + /* PID field */ + #define ROM_PID7_PID (0x0000000Fu) + #define ROM_PID7_PID_MASK (0x0000000Fu) + #define ROM_PID7_PID_BIT (0) + #define ROM_PID7_PID_BITS (4) + +#define ROM_PID0 *((volatile int32u *)0xE00FFFE0u) +#define ROM_PID0_REG *((volatile int32u *)0xE00FFFE0u) +#define ROM_PID0_ADDR (0xE00FFFE0u) +#define ROM_PID0_RESET (0x00000000u) + /* PID field */ + #define ROM_PID0_PID (0x0000000Fu) + #define ROM_PID0_PID_MASK (0x0000000Fu) + #define ROM_PID0_PID_BIT (0) + #define ROM_PID0_PID_BITS (4) + +#define ROM_PID1 *((volatile int32u *)0xE00FFFE4u) +#define ROM_PID1_REG *((volatile int32u *)0xE00FFFE4u) +#define ROM_PID1_ADDR (0xE00FFFE4u) +#define ROM_PID1_RESET (0x00000000u) + /* PID field */ + #define ROM_PID1_PID (0x0000000Fu) + #define ROM_PID1_PID_MASK (0x0000000Fu) + #define ROM_PID1_PID_BIT (0) + #define ROM_PID1_PID_BITS (4) + +#define ROM_PID2 *((volatile int32u *)0xE00FFFE8u) +#define ROM_PID2_REG *((volatile int32u *)0xE00FFFE8u) +#define ROM_PID2_ADDR (0xE00FFFE8u) +#define ROM_PID2_RESET (0x00000000u) + /* PID field */ + #define ROM_PID2_PID (0x0000000Fu) + #define ROM_PID2_PID_MASK (0x0000000Fu) + #define ROM_PID2_PID_BIT (0) + #define ROM_PID2_PID_BITS (4) + +#define ROM_PID3 *((volatile int32u *)0xE00FFFECu) +#define ROM_PID3_REG *((volatile int32u *)0xE00FFFECu) +#define ROM_PID3_ADDR (0xE00FFFECu) +#define ROM_PID3_RESET (0x00000000u) + /* PID field */ + #define ROM_PID3_PID (0x0000000Fu) + #define ROM_PID3_PID_MASK (0x0000000Fu) + #define ROM_PID3_PID_BIT (0) + #define ROM_PID3_PID_BITS (4) + +#define ROM_CID0 *((volatile int32u *)0xE00FFFF0u) +#define ROM_CID0_REG *((volatile int32u *)0xE00FFFF0u) +#define ROM_CID0_ADDR (0xE00FFFF0u) +#define ROM_CID0_RESET (0x0000000Du) + /* CID field */ + #define ROM_CID0_CID (0x000000FFu) + #define ROM_CID0_CID_MASK (0x000000FFu) + #define ROM_CID0_CID_BIT (0) + #define ROM_CID0_CID_BITS (8) + +#define ROM_CID1 *((volatile int32u *)0xE00FFFF4u) +#define ROM_CID1_REG *((volatile int32u *)0xE00FFFF4u) +#define ROM_CID1_ADDR (0xE00FFFF4u) +#define ROM_CID1_RESET (0x00000010u) + /* CID field */ + #define ROM_CID1_CID (0x000000FFu) + #define ROM_CID1_CID_MASK (0x000000FFu) + #define ROM_CID1_CID_BIT (0) + #define ROM_CID1_CID_BITS (8) + +#define ROM_CID2 *((volatile int32u *)0xE00FFFF8u) +#define ROM_CID2_REG *((volatile int32u *)0xE00FFFF8u) +#define ROM_CID2_ADDR (0xE00FFFF8u) +#define ROM_CID2_RESET (0x00000005u) + /* CID field */ + #define ROM_CID2_CID (0x000000FFu) + #define ROM_CID2_CID_MASK (0x000000FFu) + #define ROM_CID2_CID_BIT (0) + #define ROM_CID2_CID_BITS (8) + +#define ROM_CID3 *((volatile int32u *)0xE00FFFFCu) +#define ROM_CID3_REG *((volatile int32u *)0xE00FFFFCu) +#define ROM_CID3_ADDR (0xE00FFFFCu) +#define ROM_CID3_RESET (0x000000B1u) + /* CID field */ + #define ROM_CID3_CID (0x000000FFu) + #define ROM_CID3_CID_MASK (0x000000FFu) + #define ROM_CID3_CID_BIT (0) + #define ROM_CID3_CID_BITS (8) + +/* VENDOR block */ +#define DATA_VENDOR_BASE (0xE0100000u) +#define DATA_VENDOR_END (0xFFFFFFFFu) +#define DATA_VENDOR_SIZE (DATA_VENDOR_END - DATA_VENDOR_BASE + 1) + + +#endif /*__REGS_H__*/ diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h new file mode 100644 index 000000000..bddd90f34 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32w108_type.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2009 +* Description : This file contains all the common data types used for the +* STM32W108 firmware library. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32W108_TYPE_H +#define __STM32W108_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +//typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)2147483648uL) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32W108_TYPE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/hal/micro/cortexm3/system-timer.c b/cpu/stm32w108/hal/micro/cortexm3/system-timer.c new file mode 100644 index 000000000..12efe92f5 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/system-timer.c @@ -0,0 +1,172 @@ +/** @file hal/micro/cortexm3/system-timer.c + * @brief STM32W108 System Timer HAL functions. + * + * \b NOTE: The Sleep Timer count and compare registers are only 16 bits, but + * the counter and comparators themselves are actually 32bits. To deal with + * this, there are High ("H") and Low ("L") registers. The High register is + * the "action" register. When working with SLEEPTMR_CNT, reading the "H" + * register will return the upper 16 bits and simultaneously trigger the + * capture of the lower 16bits in the "L" register. The "L" register may then + * be read. When working with the SLEEPTMR_CMP registers, writing "L" will + * set a shadow register. Writing "H" will cause the value from the "H" write + * and the "L" shadow register to be combined and simultaneously loaded into + * the true 32bit comparator. + * + * + */ +#include PLATFORM_HEADER +#include "error.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" +#include "micro/system-timer.h" + + +//A simple flag used by internalSleepForQs to check that it has exited +//from sleep mode at the request of the expected timer interrupt. +static boolean sleepTimerInterruptOccurred = FALSE; + +// halInternalStartSystemTimer() was moved to micro.c + +/** + * Return a 16 bit real time clock value. With 1024 clock ticks per second, + * a single clock tick occurs every 0.9769625 milliseconds, and a rollover + * of the 16-bit timer occurs every 64 seconds. + */ +int16u halCommonGetInt16uMillisecondTick(void) +{ + return (int16u)halCommonGetInt32uMillisecondTick(); +} + +int16u halCommonGetInt16uQuarterSecondTick(void) +{ + return (int16u)(halCommonGetInt32uMillisecondTick() >> 8); +} + +/** + * Return a 32 bit real time clock value. With 1024 clock ticks per second, + * a single clock tick occurs every 0.9769625 milliseconds, and a rollover + * of the 32-bit timer occurs approximately every 48.5 days. + */ +int32u halCommonGetInt32uMillisecondTick(void) +{ + int32u time; + + time = SLEEPTMR_CNTH<<16; + time |= SLEEPTMR_CNTL; + + return time; +} + + +void halSleepTimerIsr(void) +{ + //clear the second level interrupts + INT_SLEEPTMRFLAG = INT_SLEEPTMRWRAP | INT_SLEEPTMRCMPA | INT_SLEEPTMRCMPB; + + //mark a sleep timer interrupt as having occurred + sleepTimerInterruptOccurred = TRUE; +} + +#define CONVERT_QS_TO_TICKS(x) (x << 8) +#define CONVERT_TICKS_TO_QS(x) (x >> 8) +#define TIMER_MAX_QS 0x1000000 // = 4194304 seconds * 4 = 16777216 +static StStatus internalSleepForQs(boolean useGpioWakeMask, + int32u *duration, + int32u gpioWakeBitMask) +{ + StStatus status = ST_SUCCESS; + int32u sleepOverflowCount; + int32u remainder; + int32u startCount; + + //There is really no reason to bother with a duration of 0qs + if(*duration==0) { + INTERRUPTS_ON(); + return status; + } + + ATOMIC( + //disable top-level interrupt while configuring + INT_CFGCLR = INT_SLEEPTMR; + + //Our tick is calibrated to 1024Hz, giving a tick of 976.6us and an + //overflow of 4194304.0 seconds. Calculate the number of sleep overflows + //in the duration + sleepOverflowCount = (*duration)/TIMER_MAX_QS; + //calculate the remaining ticks + remainder = CONVERT_QS_TO_TICKS((*duration)%TIMER_MAX_QS); + //grab the starting sleep count + startCount = halCommonGetInt32uMillisecondTick(); + + sleepTimerInterruptOccurred = FALSE; + + if(remainder) { + //set CMPA value + SLEEPTMR_CMPAL = (startCount+remainder)&0xFFFF; + SLEEPTMR_CMPAH = ((startCount+remainder)>>16)&0xFFFF; + //clear any stale interrupt flag and set the CMPA interrupt + INT_SLEEPTMRFLAG = INT_SLEEPTMRCMPA; + INT_SLEEPTMRCFG = INT_SLEEPTMRCMPA; + } + if(sleepOverflowCount) { + //set CMPB value + SLEEPTMR_CMPBL = startCount&0xFFFF; + SLEEPTMR_CMPBH = (startCount>>16)&0xFFFF; + //clear any stale interrupt flag and set the CMPB interrupt + //this will also disable the CMPA interrupt, since we only want to wake + //on overflows, not the remainder yet + INT_SLEEPTMRFLAG = INT_SLEEPTMRCMPB; + INT_SLEEPTMRCFG = INT_SLEEPTMRCMPB; + } + + //enable top-level interrupt + INT_CFGSET = INT_SLEEPTMR; + ) + + while(*duration > 0) { + { + halSleepWithOptions(SLEEPMODE_WAKETIMER, gpioWakeBitMask); + } + + INT_SLEEPTMRCFG = INT_SLEEPTMRCFG_RESET; //disable all SleepTMR interrupts + + //If we didn't come out of sleep via a compare or overflow interrupt, + //it was an abnormal sleep interruption; report the event. + if(!sleepTimerInterruptOccurred) { + status = ST_SLEEP_INTERRUPTED; + //Update duration to account for how long last sleep was. Using the + //startCount variable is always valid because full timer wraps always + //return to this value and the remainder is an offset from this value. + //And since the duration is always reduced after each full timer wrap, + //we only need to calculate the final duration here. + *duration -= CONVERT_TICKS_TO_QS(halCommonGetInt32uMillisecondTick() - + startCount); + break; + } else { + if(sleepOverflowCount) { + sleepOverflowCount--; + *duration -= TIMER_MAX_QS; + } else { + *duration -= CONVERT_TICKS_TO_QS(remainder); + } + sleepTimerInterruptOccurred = FALSE; + if(sleepOverflowCount) { + //enable sleeping for a full timer wrap + INT_SLEEPTMRFLAG = INT_SLEEPTMRCMPB; + INT_SLEEPTMRCFG = INT_SLEEPTMRCMPB; + } else if(!sleepOverflowCount && (*duration>0)){ + //enable sleeping for the remainder + INT_SLEEPTMRFLAG = INT_SLEEPTMRCMPA; + INT_SLEEPTMRCFG = INT_SLEEPTMRCMPA; + } + } + } + + return status; +} + +StStatus halSleepForQsWithOptions(int32u *duration, int32u gpioWakeBitMask) +{ + return internalSleepForQs(TRUE, duration, gpioWakeBitMask); +} + diff --git a/cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c b/cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c new file mode 100644 index 000000000..d8958abe8 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c @@ -0,0 +1,54 @@ +/**@file temperature_sensor.c + * @brief MB851 temperature sensor APIS + * + * + * + */ +#include PLATFORM_HEADER +#include BOARD_HEADER +#include "hal/hal.h" +#include "hal/error.h" +#include "hal/micro/temperature_sensor.h" +#include "hal/micro/adc.h" + +void temperatureSensor_Init(void) +{ + /* Configure temperature sensor GPIO */ + halGpioConfig(TEMPERATURE_SENSOR_GPIO,GPIOCFG_ANALOG); + /* Init ADC driver */ + halInternalInitAdc(); + + /* + NOTE: + The ADC extended range is inaccurate due to the high voltage mode bug of the general purpose ADC + (see STM32W108 errata). As consequence, it is not reccomended to use this ADC driver for getting + the temperature values. + */ +#ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN + halAdcSetRange(TRUE); +#endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ +}/* end temperatureSensor_Init() */ + +int32u temperatureSensor_GetValue(int8u type) +{ + static int16u ADCvalue; + static int16s volts; + + /* + NOTE: + The ADC extended range is inaccurate due to the high voltage mode bug of the general purpose ADC + (see STM32W108 errata). As consequence, it is not reccomended to use this ADC driver for getting + the temperature values. + */ +#ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN + halStartAdcConversion(ADC_USER_APP, ADC_REF_INT, ADC_SOURCE_ADC2_VREF2, ADC_CONVERSION_TIME_US_4096); + + halReadAdcBlocking(ADC_USER_APP, &ADCvalue); // This blocks for a while, about 4ms. + + // 100 uVolts + volts = halConvertValueToVolts(ADCvalue); + + return ((18641 - (int32s)volts)*100)/1171; +#endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ +}/* end temperatureSensor_GetValue() */ + diff --git a/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h b/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h new file mode 100644 index 000000000..597b50305 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h @@ -0,0 +1,369 @@ +/** @file hal/micro/cortexm3/token-manufacturing.h + * @brief Definitions for manufacturing tokens. + * + * This file should not be included directly. It is accessed by the other + * token files. + * + * Please see hal/micro/token.h for a full explanation of the tokens. + * + * The tokens listed below are the manufacturing tokens. + * + * Since this file contains both the typedefs and the token defs, there are + * two \#defines used to select which one is needed when this file is included. + * \#define DEFINETYPES is used to select the type definitions and + * \#define DEFINETOKENS is used to select the token definitions. + * Refer to token.h and token.c to see how these are used. + * + * + */ + +/** + * @name Convenience Macros + * @brief The following convenience macros are used to simplify the definition + * process for commonly specified parameters to the basic TOKEN_DEF macro. + * Please see hal/micro/token.h for a more complete explanation. + *@{ + */ +#define DEFINE_MFG_TOKEN(name, type, address, ...) \ + TOKEN_NEXT_ADDRESS(name,(address)) \ + TOKEN_MFG(name, CREATOR_##name, 0, 0, type, 1, __VA_ARGS__) +/** @} END Convenience Macros */ + +////////////////////////////////////////////////////////////////////////////// +// MANUFACTURING DATA +// *the addresses of these tokens must not change* + + +// MANUFACTURING CREATORS +// The creator codes are here in one list instead of next to their token +// definitions so comparision of the codes is easier. The only requirement +// on these creator definitions is that they all must be unique. A favorite +// method for picking creator codes is to use two ASCII characters in order +// to make the codes more memorable. Also, the msb of Stack and Manufacturing +// token creator codes is always 1, while the msb of Application token creator +// codes is always 0. This distinction allows Application tokens +// to freely use the lower 15 bits for creator codes without the risk of +// duplicating a Stack or Manufacturing token creator code. +//--- Fixed Information Block --- +#define CREATOR_MFG_CHIP_DATA 0xC344 // msb+'C'+'D' +#define CREATOR_MFG_PART_DATA 0xF064 // msb+'p'+'d' +#define CREATOR_MFG_TESTER_DATA 0xF464 // msb+'t'+'d' +#define CREATOR_MFG_ST_EUI_64 0xE545 // msb+'e'+'E' +#define CREATOR_MFG_ANALOG_TRIM_NORMAL 0xF46E // msb+'t'+'n' +#define CREATOR_MFG_ANALOG_TRIM_BOOST 0xF442 // msb+'t'+'B' +#define CREATOR_MFG_ANALOG_TRIM_BOTH 0xF462 // msb+'t'+'b' +#define CREATOR_MFG_REG_TRIM 0xF274 // msb+'r'+'t' +#define CREATOR_MFG_1V8_REG_VOLTAGE 0xF276 // msb+'r'+'v' +#define CREATOR_MFG_VREF_VOLTAGE 0xF676 // msb+'v'+'v' +#define CREATOR_MFG_TEMP_CAL 0xF463 // msb+'t'+'c' +#define CREATOR_MFG_FIB_VERSION 0xFF09 +#define CREATOR_MFG_FIB_CHECKSUM 0xE663 // msb+'f'+'c' +#define CREATOR_MFG_FIB_OBS 0xE66F // msb+'f'+'o' +//--- Customer Information Block --- +#define CREATOR_MFG_CIB_OBS 0xE36F // msb+'c'+'o' +#define CREATOR_MFG_CUSTOM_VERSION 0xC356 +#define CREATOR_MFG_CUSTOM_EUI_64 0xE345 +#define CREATOR_MFG_STRING 0xED73 +#define CREATOR_MFG_BOARD_NAME 0xC24E // msb+'B'+'N' (Board Name) +#define CREATOR_MFG_EUI_64 0xB634 +#define CREATOR_MFG_MANUF_ID 0xC944 // msb+'I'+'D' (Id) +#define CREATOR_MFG_PHY_CONFIG 0xD043 // msb+'P'+'C' (Phy Config) +#define CREATOR_MFG_BOOTLOAD_AES_KEY 0xC24B // msb+'B'+'K' (Bootloader Key) +#define CREATOR_MFG_EZSP_STORAGE 0xCD53 +#define CREATOR_MFG_ASH_CONFIG 0xC143 // msb+'A'+'C' (ASH Config) +#define CREATOR_MFG_CBKE_DATA 0xC342 // msb+'C'+'B' (CBke) +#define CREATOR_MFG_INSTALLATION_CODE 0xC943 // msb+'I'+'C' (Installation Code) +#define CREATOR_MFG_OSC24M_BIAS_TRIM 0xB254 // msb+'2'+'T' (2[4mHz] Trim) + +// The master defines indicating the verions number these definitions work with. +#define CURRENT_MFG_TOKEN_VERSION 0x01FE //MSB is version, LSB is complement +#define CURRENT_MFG_CUSTOM_VERSION 0x01FE //MSB is version, LSB is complement + + +#ifndef __MFG_TYPES_DEFINED__ +#define __MFG_TYPES_DEFINED__ +//--- Fixed Information Block --- +typedef int8u tokTypeMfgChipData[24]; +typedef int8u tokTypeMfgPartData[6]; +typedef int8u tokTypeMfgTesterData[6]; +typedef int8u tokTypeMfgStEui64[8]; +typedef struct { + int16u iffilterL; + int16u lna; + int16u ifamp; + int16u rxadcH; + int16u prescalar; + int16u phdet; + int16u vco; + int16u loopfilter; + int16u pa; + int16u iqmixer; +} tokTypeMfgAnalogueTrim; +typedef struct { + int16u iffilterH; + int16u biasmaster; + int16u moddac; + int16u auxadc; + int16u caladc; +} tokTypeMfgAnalogueTrimBoth; +typedef struct { + int8u regTrim1V2; + int8u regTrim1V8; +} tokTypeMfgRegTrim; +typedef int16u tokTypeMfgRegVoltage1V8; +typedef int16u tokTypeMfgAdcVrefVoltage; +typedef int16u tokTypeMfgTempCal; +typedef int16u tokTypeMfgFibVersion; +typedef int16u tokTypeMfgFibChecksum; +typedef struct { + int16u ob2; + int16u ob3; + int16u ob0; + int16u ob1; +} tokTypeMfgFibObs; +//--- Customer Information Block --- +typedef struct { + int16u ob0; + int16u ob1; + int16u ob2; + int16u ob3; + int16u ob4; + int16u ob5; + int16u ob6; + int16u ob7; +} tokTypeMfgCibObs; +typedef int16u tokTypeMfgCustomVersion; +typedef int8u tokTypeMfgCustomEui64[8]; +typedef int8u tokTypeMfgString[16]; +typedef int8u tokTypeMfgBoardName[16]; +typedef int16u tokTypeMfgManufId; +typedef int16u tokTypeMfgPhyConfig; +typedef int8u tokTypeMfgBootloadAesKey[16]; +typedef int8u tokTypeMfgEui64[8]; +typedef int8u tokTypeMfgEzspStorage[8]; +typedef int16u tokTypeMfgAshConfig; +typedef struct { + int8u certificate[48]; + int8u caPublicKey[22]; + int8u privateKey[21]; + // The bottom flag bit is 1 for uninitialized, 0 for initialized. + // The other flag bits should be set to 0 at initialization. + int8u flags; +} tokTypeMfgCbkeData; +typedef struct { + // The bottom flag bit is 1 for uninitialized, 0 for initialized. + // Bits 1 and 2 give the size of the value string: + // 0 = 6 bytes, 1 = 8 bytes, 2 = 12 bytes, 3 = 16 bytes. + // The other flag bits should be set to 0 at initialization. + // Special flags support. Due to a bug in the way some customers + // had programmed the flags field, we will also examine the upper + // bits 9 and 10 for the size field. Those bits are also reserved. + int16u flags; + int8u value[16]; + int16u crc; +} tokTypeMfgInstallationCode; +typedef int16u tokTypeMfgOsc24mBiasTrim; +#endif //__MFG_TYPES_DEFINED__ + + +#ifdef DEFINETOKENS +//The Manufacturing tokens need to be stored at well-defined locations. +//None of these addresses should ever change without extremely great care. +//All locations are OR'ed with DATA_BIG_INFO_BASE to make a full 32bit address. +//--- Fixed Information Block --- +// FIB Bootloader 0x0000 //1918 bytes +#define MFG_CHIP_DATA_LOCATION 0x077E // 24 bytes +#define MFG_PART_DATA_LOCATION 0x0796 // 6 bytes +#define MFG_TESTER_DATA_LOCATION 0x079C // 6 bytes +#define MFG_ST_EUI_64_LOCATION 0x07A2 // 8 bytes +#define MFG_ANALOG_TRIM_NORMAL_LOCATION 0x07AA // 20 bytes +#define MFG_ANALOG_TRIM_BOOST_LOCATION 0x07BE // 20 bytes +#define MFG_ANALOG_TRIM_BOTH_LOCATION 0x07D2 // 10 bytes +#define MFG_REG_TRIM_LOCATION 0x07DC // 2 bytes +#define MFG_1V8_REG_VOLTAGE_LOCATION 0x07DE // 2 bytes +#define MFG_VREF_VOLTAGE_LOCATION 0x07E0 // 2 bytes +#define MFG_TEMP_CAL_LOCATION 0x07E2 // 2 bytes +//reserved 0x07E4 // 16 bytes +#define MFG_FIB_VERSION_LOCATION 0x07F4 // 2 bytes +#define MFG_FIB_CHECKSUM_LOCATION 0x07F6 // 2 bytes +#define MFG_FIB_OBS_LOCATION 0x07F8 // 8 bytes +//--- Customer Information Block --- +#define MFG_CIB_OBS_LOCATION 0x0800 // 16 bytes +#define MFG_CUSTOM_VERSION_LOCATION 0x0810 // 2 bytes +#define MFG_CUSTOM_EUI_64_LOCATION 0x0812 // 8 bytes +#define MFG_STRING_LOCATION 0x081A // 16 bytes +#define MFG_BOARD_NAME_LOCATION 0x082A // 16 bytes +#define MFG_MANUF_ID_LOCATION 0x083A // 2 bytes +#define MFG_PHY_CONFIG_LOCATION 0x083C // 2 bytes +#define MFG_BOOTLOAD_AES_KEY_LOCATION 0x083E // 16 bytes +#define MFG_EZSP_STORAGE_LOCATION 0x084E // 8 bytes +#define MFG_ASH_CONFIG_LOCATION 0x0856 // 40 bytes +#define MFG_CBKE_DATA_LOCATION 0x087E // 92 bytes +#define MFG_INSTALLATION_CODE_LOCATION 0x08DA // 20 bytes +#define MFG_OSC24M_BIAS_TRIM_LOCATION 0x08EE // 2 bytes +// unused 0x08F0 //1808 bytes +//--- Virtual MFG Tokens --- +#define MFG_EUI_64_LOCATION 0x8000 // Special Trigger - see token.c + +// Define the size of indexed token array +#define MFG_ASH_CONFIG_ARRAY_SIZE 20 + +#ifndef TOKEN_NEXT_ADDRESS + #define TOKEN_NEXT_ADDRESS(region, address) +#endif + + +// NOTE: because of their special handling, the manufacturing tokens +// cannot use the convenience macros in their definitions, so the full +// definitions are present here. +//--- Fixed Information Block --- +TOKEN_NEXT_ADDRESS(MFG_CHIP_DATA_ADDR,MFG_CHIP_DATA_LOCATION) +TOKEN_MFG(MFG_CHIP_DATA, CREATOR_MFG_CHIP_DATA, + 0, 0, tokTypeMfgChipData, 1, + {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}) + +TOKEN_NEXT_ADDRESS(MFG_PART_DATA_ADDR,MFG_PART_DATA_LOCATION) +TOKEN_MFG(MFG_PART_DATA, CREATOR_MFG_PART_DATA, + 0, 0, tokTypeMfgPartData, 1, + {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}) + +TOKEN_NEXT_ADDRESS(MFG_TESTER_DATA_ADDR,MFG_TESTER_DATA_LOCATION) +TOKEN_MFG(MFG_TESTER_DATA, CREATOR_MFG_TESTER_DATA, + 0, 0, tokTypeMfgTesterData, 1, + {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}) + +TOKEN_NEXT_ADDRESS(MFG_ST_EUI_64_ADDR,MFG_ST_EUI_64_LOCATION) +TOKEN_MFG(MFG_ST_EUI_64, CREATOR_MFG_ST_EUI_64, + 0, 0, tokTypeMfgStEui64, 1, + {3,0,0,0,0,0,0,3}) + +TOKEN_NEXT_ADDRESS(MFG_ANALOG_TRIM_NORMAL_ADDR,MFG_ANALOG_TRIM_NORMAL_LOCATION) +TOKEN_MFG(MFG_ANALOG_TRIM_NORMAL, CREATOR_MFG_ANALOG_TRIM_NORMAL, + 0, 0, tokTypeMfgAnalogueTrim, 1, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF, + 0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF}) + +TOKEN_NEXT_ADDRESS(MFG_ANALOG_TRIM_BOOST_ADDR,MFG_ANALOG_TRIM_BOOST_LOCATION) +TOKEN_MFG(MFG_ANALOG_TRIM_BOOST, CREATOR_MFG_ANALOG_TRIM_BOOST, + 0, 0, tokTypeMfgAnalogueTrim, 1, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF, + 0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF}) + +TOKEN_NEXT_ADDRESS(MFG_ANALOG_TRIM_BOTH_ADDR,MFG_ANALOG_TRIM_BOTH_LOCATION) +TOKEN_MFG(MFG_ANALOG_TRIM_BOTH, CREATOR_MFG_ANALOG_TRIM_BOTH, + 0, 0, tokTypeMfgAnalogueTrimBoth, 1, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF}) + +TOKEN_NEXT_ADDRESS(MFG_REG_TRIM_ADDR,MFG_REG_TRIM_LOCATION) +TOKEN_MFG(MFG_REG_TRIM, CREATOR_MFG_REG_TRIM, + 0, 0, tokTypeMfgRegTrim, 1, + {0xFF, 0xFF}) + +TOKEN_NEXT_ADDRESS(MFG_1V8_REG_VOLTAGE_ADDR,MFG_1V8_REG_VOLTAGE_LOCATION) +TOKEN_MFG(MFG_1V8_REG_VOLTAGE, CREATOR_MFG_1V8_REG_VOLTAGE, + 0, 0, tokTypeMfgRegVoltage1V8, 1, + 0xFFFF) + +TOKEN_NEXT_ADDRESS(MFG_VREF_VOLTAGE_ADDR,MFG_VREF_VOLTAGE_LOCATION) +TOKEN_MFG(MFG_VREF_VOLTAGE, CREATOR_MFG_VREF_VOLTAGE, + 0, 0, tokTypeMfgAdcVrefVoltage, 1, + 0xFFFF) + +TOKEN_NEXT_ADDRESS(MFG_TEMP_CAL_ADDR,MFG_TEMP_CAL_LOCATION) +TOKEN_MFG(MFG_TEMP_CAL, CREATOR_MFG_TEMP_CAL, + 0, 0, tokTypeMfgTempCal, 1, + 0xFFFF) + +TOKEN_NEXT_ADDRESS(MFG_FIB_VERSION_ADDR,MFG_FIB_VERSION_LOCATION) +TOKEN_MFG(MFG_FIB_VERSION, CREATOR_MFG_FIB_VERSION, + 0, 0, tokTypeMfgFibVersion, 1, + CURRENT_MFG_TOKEN_VERSION) + +TOKEN_NEXT_ADDRESS(MFG_FIB_CHECKSUM_ADDR,MFG_FIB_CHECKSUM_LOCATION) +TOKEN_MFG(MFG_FIB_CHECKSUM, CREATOR_MFG_FIB_CHECKSUM, + 0, 0, tokTypeMfgFibChecksum, 1, + 0xFFFF) + +TOKEN_NEXT_ADDRESS(MFG_FIB_OBS_ADDR,MFG_FIB_OBS_LOCATION) +TOKEN_MFG(MFG_FIB_OBS, CREATOR_MFG_FIB_OBS, + 0, 0, tokTypeMfgFibObs, 1, + {0xFFFF,0x03FC,0xAA55,0xFFFF}) + + +//--- Customer Information Block --- +TOKEN_NEXT_ADDRESS(MFG_CIB_OBS_ADDR,MFG_CIB_OBS_LOCATION) +TOKEN_MFG(MFG_CIB_OBS, CREATOR_MFG_CIB_OBS, + 0, 0, tokTypeMfgCibObs, 1, + {0x5AA5,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF}) + +TOKEN_NEXT_ADDRESS(MFG_CUSTOM_VERSION_ADDR,MFG_CUSTOM_VERSION_LOCATION) +TOKEN_MFG(MFG_CUSTOM_VERSION, CREATOR_MFG_CUSTOM_VERSION, + 0, 0, tokTypeMfgCustomVersion, 1, + CURRENT_MFG_CUSTOM_VERSION) + +TOKEN_NEXT_ADDRESS(MFG_CUSTOM_EUI_64_ADDR,MFG_CUSTOM_EUI_64_LOCATION) +TOKEN_MFG(MFG_CUSTOM_EUI_64, CREATOR_MFG_CUSTOM_EUI_64, + 0, 0, tokTypeMfgCustomEui64, 1, + {0,3,3,3,3,3,3,0}) + +TOKEN_NEXT_ADDRESS(MFG_STRING_ADDR,MFG_STRING_LOCATION) +TOKEN_MFG(MFG_STRING, CREATOR_MFG_STRING, + 0, 0, tokTypeMfgString, 1, + {0,}) + +TOKEN_NEXT_ADDRESS(MFG_BOARD_NAME_ADDR,MFG_BOARD_NAME_LOCATION) +TOKEN_MFG(MFG_BOARD_NAME, CREATOR_MFG_BOARD_NAME, + 0, 0, tokTypeMfgBoardName, 1, + {0,}) + +TOKEN_NEXT_ADDRESS(MFG_MANUF_ID_ADDR,MFG_MANUF_ID_LOCATION) +TOKEN_MFG(MFG_MANUF_ID, CREATOR_MFG_MANUF_ID, + 0, 0, tokTypeMfgManufId, 1, + {0x00,0x00,}) // default to 0 for st + +TOKEN_NEXT_ADDRESS(MFG_PHY_CONFIG_ADDR,MFG_PHY_CONFIG_LOCATION) +TOKEN_MFG(MFG_PHY_CONFIG, CREATOR_MFG_PHY_CONFIG, + 0, 0, tokTypeMfgPhyConfig, 1, + {0x00,0x00,}) // default to non-boost mode, internal pa. + +TOKEN_NEXT_ADDRESS(MFG_BOOTLOAD_AES_KEY_ADDR,MFG_BOOTLOAD_AES_KEY_LOCATION) +TOKEN_MFG(MFG_BOOTLOAD_AES_KEY, CREATOR_MFG_BOOTLOAD_AES_KEY, + 0, 0, tokTypeMfgBootloadAesKey, 1, + {0xFF,}) // default key is all f's + +TOKEN_NEXT_ADDRESS(MFG_EZSP_STORAGE_ADDR,MFG_EZSP_STORAGE_LOCATION) +TOKEN_MFG(MFG_EZSP_STORAGE, CREATOR_MFG_EZSP_STORAGE, + 0, 0, tokTypeMfgEzspStorage, 1, + { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }) + +TOKEN_NEXT_ADDRESS(MFG_ASH_CONFIG_ADDR,MFG_ASH_CONFIG_LOCATION) +TOKEN_MFG(MFG_ASH_CONFIG, CREATOR_MFG_ASH_CONFIG, + 0, 1, tokTypeMfgAshConfig, MFG_ASH_CONFIG_ARRAY_SIZE, + { 0xFFFF, }) + +TOKEN_NEXT_ADDRESS(MFG_CBKE_DATA_ADDR,MFG_CBKE_DATA_LOCATION) +TOKEN_MFG(MFG_CBKE_DATA, CREATOR_MFG_CBKE_DATA, + 0, 0, tokTypeMfgCbkeData, 1, + {0xFF,}) + +TOKEN_NEXT_ADDRESS(MFG_INSTALLATION_CODE_ADDR,MFG_INSTALLATION_CODE_LOCATION) +TOKEN_MFG(MFG_INSTALLATION_CODE, CREATOR_MFG_INSTALLATION_CODE, + 0, 0, tokTypeMfgInstallationCode, 1, + {0xFF,}) + +TOKEN_NEXT_ADDRESS(MFG_OSC24M_BIAS_TRIM_ADDR,MFG_OSC24M_BIAS_TRIM_LOCATION) +TOKEN_MFG(MFG_OSC24M_BIAS_TRIM, CREATOR_MFG_OSC24M_BIAS_TRIM, + 0, 0, tokTypeMfgOsc24mBiasTrim, 1, + {0xFF,}) + +TOKEN_NEXT_ADDRESS(MFG_EUI_64_ADDR,MFG_EUI_64_LOCATION) +TOKEN_MFG(MFG_EUI_64, CREATOR_MFG_EUI_64, + 0, 0, tokTypeMfgEui64, 1, + {3,3,3,3,0,0,0,0}) + +#undef TOKEN_NEXT_ADDRESS + +#endif //DEFINETOKENS + diff --git a/cpu/stm32w108/hal/micro/cortexm3/uart.c b/cpu/stm32w108/hal/micro/cortexm3/uart.c new file mode 100644 index 000000000..831742274 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/uart.c @@ -0,0 +1,259 @@ +/** @file hal/micro/cortexm3/uart.c + * @brief STM32W uart drivers, supporting IAR's standard library + * IO routines. + * + * + */ + +#include PLATFORM_HEADER +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" +#include "uart.h" +#ifdef __GNUC__ +#include +#include +#define _LLIO_STDIN ((int) stdin) +#define _LLIO_STDOUT ((int) stdout) +#define _LLIO_STDERR ((int) stderr) +#define _LLIO_ERROR (-1) +#define __write _write +#define __read _read +#undef putchar +void __io_putchar( char c ); +int putchar (int c) +{ + __io_putchar((char) c); + return c; +} +#endif +#define RECEIVE_QUEUE_SIZE (128) + +int8u rxQ[RECEIVE_QUEUE_SIZE]; +int16u rxHead; +int16u rxTail; +int16u rxUsed; + +////////////////////////////////////////////////////////////////////////////// +// Initialization + +void uartInit(int32u baudrate, int8u databits, SerialParity parity, int8u stopbits) +{ + int32u tempcfg; + int32u tmp; + + assert( (baudrate >= 300) && (baudrate <=921600) ); + + tmp = (2*12000000L + baudrate/2) / baudrate; + SC1_UARTFRAC = tmp & 1; + SC1_UARTPER = tmp / 2; + + if(databits == 7) { + tempcfg = 0; + } else { + tempcfg = SC_UART8BIT; + } + + if (parity == PARITY_ODD) { + tempcfg |= SC_UARTPAR | SC_UARTODD; + } else if( parity == PARITY_EVEN ) { + tempcfg |= SC_UARTPAR; + } + + if ((stopbits & 0x0F) >= 2) { + tempcfg |= SC_UART2STP; + } + SC1_UARTCFG = tempcfg; + + SC1_MODE = SC1_MODE_UART; + + rxHead=0; + rxTail=0; + rxUsed=0; + + halGpioConfig(PORTB_PIN(1),GPIOCFG_OUT_ALT); + halGpioConfig(PORTB_PIN(2),GPIOCFG_IN); + + // Make the RX Valid interrupt level sensitive (instead of edge) + SC1_INTMODE = SC_RXVALLEVEL; + // Enable just RX interrupts; TX interrupts are controlled separately + INT_SC1CFG |= (INT_SCRXVAL | + INT_SCRXOVF | + INT_SC1FRMERR | + INT_SC1PARERR); + INT_SC1FLAG = 0xFFFF; // Clear any stale interrupts + INT_CFGSET = INT_SC1; +} + +////////////////////////////////////////////////////////////////////////////// +// Transmit + +// IAR Standard library hook for serial output +size_t __write(int handle, const unsigned char * buffer, size_t size) +{ + size_t nChars = 0; + + /* This template only writes to "standard out" and "standard err", + * for all other file handles it returns failure. */ + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + if (buffer == 0) { + // This means that we should flush internal buffers. + //spin until TX complete (TX is idle) + while ((SC1_UARTSTAT&SC_UARTTXIDLE)!=SC_UARTTXIDLE) {} + return 0; + } + + // ensure port is configured for UART + if(SC1_MODE != SC1_MODE_UART) { + return _LLIO_ERROR; + } + + while(size--) { + //spin until data register has room for more data + while ((SC1_UARTSTAT&SC_UARTTXFREE)!=SC_UARTTXFREE) {} + SC1_DATA = *buffer; + buffer++; + + ++nChars; + } + + return nChars; +} +#ifdef __GNUC__ +int fflush (FILE *f) +#endif +#ifdef __ICCARM__ +size_t fflush(int handle) +#endif +{ + return __write(_LLIO_STDOUT, NULL, 0); +} + +static void halInternalUart1TxIsr(void) +{ + // Nothing for now, as ouput is blocking from the __write function +} + + +////////////////////////////////////////////////////////////////////////////// +// Receive + +// IAR Standard library hook for serial input +size_t __read(int handle, unsigned char * buffer, size_t size) +{ + int nChars = 0; + + /* This template only reads from "standard in", for all other file + * handles it returns failure. */ + if (handle != _LLIO_STDIN) + { + return _LLIO_ERROR; + } + + for(nChars = 0; (rxUsed>0) && (nChars < size); nChars++) { + ATOMIC( + *buffer++ = rxQ[rxTail]; + rxTail = (rxTail+1) % RECEIVE_QUEUE_SIZE; + rxUsed--; + ) + } + + return nChars; +} + +static void halInternalUart1RxIsr(void) +{ + + // At present we really don't care which interrupt(s) + // occurred, just that one did. Loop reading RXVALID + // data, processing any errors noted + // along the way. + while ( SC1_UARTSTAT & SC_UARTRXVAL ) { + int8u errors = SC1_UARTSTAT & (SC_UARTFRMERR | + SC_UARTRXOVF | + SC_UARTPARERR ); + int8u incoming = (int8u) SC1_DATA; + + if ( (errors == 0) && (rxUsed < (RECEIVE_QUEUE_SIZE-1)) ) { + rxQ[rxHead] = incoming; + rxHead = (rxHead+1) % RECEIVE_QUEUE_SIZE; + rxUsed++; + } else { + // IAR standard library doesn't allow for any error handling in the + // case of rx errors or not having space in the receive queue, so the + // errors are just silently dropped. + } + } // end of while ( SC1_UARTSTAT & SC1_UARTRXVAL ) +} + + +////////////////////////////////////////////////////////////////////////////// +// Interrupts + +void halSc1Isr(void) +{ + int32u interrupt; + + //this read and mask is performed in two steps otherwise the compiler + //will complain about undefined order of volatile access + interrupt = INT_SC1FLAG; + interrupt &= INT_SC1CFG; + + while (interrupt != 0) { + + INT_SC1FLAG = interrupt; // acknowledge the interrupts early + + // RX events + if ( interrupt & (INT_SCRXVAL | // RX has data + INT_SCRXOVF | // RX Overrun error + INT_SC1FRMERR | // RX Frame error + INT_SC1PARERR ) // RX Parity error + ) { + halInternalUart1RxIsr(); + } + + // TX events + if ( interrupt & (INT_SCTXFREE | // TX has room + INT_SCTXIDLE ) // TX idle (more room) + ) { + halInternalUart1TxIsr(); + } + + interrupt = INT_SC1FLAG; + interrupt &= INT_SC1CFG; + } +} + +/******************************************************************************* +* Function Name : __io_getcharNonBlocking +* Description : Non blocking read +* Input : none +* Output : dataByte: buffer containing the read byte if any +* Return : TRUE if there is a data, FALSE otherwise +*******************************************************************************/ +boolean __io_getcharNonBlocking(int8u *data) +{ + if (__read(_LLIO_STDIN,data,1)) + return TRUE; + else + return FALSE; +}/* end serialReadByte() */ + +void __io_putchar( char c ) +{ + __write(_LLIO_STDOUT, (unsigned char *)&c, 1); +} + +int __io_getchar() +{ + unsigned char c; + __read(_LLIO_STDIN, &c, 1); + return (int)(c); +} + +void __io_flush( void ) +{ + __write(_LLIO_STDOUT, NULL, 0); +} diff --git a/cpu/stm32w108/hal/micro/cortexm3/uart.h b/cpu/stm32w108/hal/micro/cortexm3/uart.h new file mode 100644 index 000000000..9d81f6c01 --- /dev/null +++ b/cpu/stm32w108/hal/micro/cortexm3/uart.h @@ -0,0 +1,72 @@ +/** @file hal/micro/cortexm3/uart.h + * @brief Header for STM32W uart drivers, supporting IAR's standard library + * IO routines. + * + * + */ + +#ifndef __UART_MIN_H__ +#define __UART_MIN_H__ +#ifdef __ICCARM__ +#include +#endif + +/** + * @brief A list of the possible values for the parity parameter to uartInit() + */ +typedef enum +{ + PARITY_NONE = 0, + PARITY_ODD = 1, + PARITY_EVEN = 2 +} SerialParity; + +/** + * @brief Initialize the UART + * + * @param baudrate The baudrate which will be used for communication. + * Ex: 115200 + * + * @param databits The number of data bits used for communication. + * Valid values are 7 or 8 + * + * @param parity The type of parity used for communication. + * See the SerialParity enum for possible values + * + * @return stopbits The number of stop bits used for communication. + * Valid values are 1 or 2 + */ +void uartInit(int32u baudrate, int8u databits, SerialParity parity, int8u stopbits); + +#ifdef __ICCARM__ +/** + * @brief Flush the output stream. DLib_Config_Full.h defines fflush(), but + * this library includes too much code so we compile with DLib_Config_Normal.h + * instead which does not define fflush(). Therefore, we manually define + * fflush() in the low level UART driver. This function simply redirects + * to the __write() function with a NULL buffer, triggering a flush. + * + * @param handle The output stream. Should be set to 'stdout' like normal. + * + * @return Zero, indicating success. + */ +size_t fflush(int handle); + +/** + * @brief Define the stdout stream. Since we compile with DLib_Config_Normal.h + * it does not define 'stdout'. There is a low-level IO define '_LLIO_STDOUT' + * which is equivalent to stdout. Therefore, we define 'stdout' to be + * '_LLIO_STDOUT'. + */ +#define stdout _LLIO_STDOUT +#endif +/** + * @brief Read the input byte if any. + */ +boolean __io_getcharNonBlocking(int8u *data); +void __io_putchar( char c ); +int __io_getchar(void); +void __io_flush( void ); + + +#endif //__UART_MIN_H__ diff --git a/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h b/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h new file mode 100644 index 000000000..c823c2d86 --- /dev/null +++ b/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h @@ -0,0 +1,362 @@ +/** @file hal/micro/generic/compiler/platform-common.h + * See @ref platform_common for detailed documentation. + * + * + */ + +/** @addtogroup platform_common + * @brief Compiler and Platform specific definitions and typedefs common to + * all platforms. + * + * platform-common.h provides PLATFORM_HEADER defaults and common definitions. + * This head should never be included directly, it should only be included + * by the specific PLATFORM_HEADER used by your platform. + * + * See platform-common.h for source code. + *@{ + */ + +#ifndef PLATCOMMONOKTOINCLUDE + // This header should only be included by a PLATFORM_HEADER + #error platform-common.h should not be included directly +#endif + +#ifndef __PLATFORMCOMMON_H__ +#define __PLATFORMCOMMON_H__ +//////////////////////////////////////////////////////////////////////////////// +// Many of the common definitions must be explicitly enabled by the +// particular PLATFORM_HEADER being used +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////// +#ifdef _HAL_USE_COMMON_PGM_ + /** \name Master Program Memory Declarations + * These are a set of defines for simple declarations of program memory. + */ + //@{ + /** + * @brief Standard program memory delcaration. + */ + #define PGM const + + /** + * @brief Char pointer to program memory declaration. + */ + #define PGM_P const char * + + /** + * @brief Unsigned char pointer to program memory declaration. + */ + #define PGM_PU const unsigned char * + + + /** + * @brief Sometimes a second PGM is needed in a declaration. Having two + * 'const' declarations generates a warning so we have a second PGM that turns + * into nothing under gcc. + */ + #define PGM_NO_CONST + //@} \\END MASTER PROGRAM MEMORY DECLARATIONS +#endif //_HAL_USE_COMMON_PGM_ + + +//////////////////////////////////////////////////////////////////////////////// +#ifdef _HAL_USE_COMMON_DIVMOD_ + /** \name Divide and Modulus Operations + * Some platforms can perform divide and modulus operations on 32 bit + * quantities more efficiently when the divisor is only a 16 bit quantity. + * C compilers will always promote the divisor to 32 bits before performing the + * operation, so the following utility functions are instead required to take + * advantage of this optimisation. + */ + //@{ + /** + * @brief Provide a portable name for the int32u by int16u division + * library function (which can perform the division with only a single + * assembly instruction on some platforms) + */ + #define halCommonUDiv32By16(x, y) ((int16u) (((int32u) (x)) / ((int16u) (y)))) + + /** + * @brief Provide a portable name for the int32s by int16s division + * library function (which can perform the division with only a single + * assembly instruction on some platforms) + */ + #define halCommonSDiv32By16(x, y) ((int16s) (((int32s) (x)) / ((int16s) (y)))) + + /** + * @brief Provide a portable name for the int32u by int16u modulo + * library function (which can perform the division with only a single + * assembly instruction on some platforms) + */ + #define halCommonUMod32By16(x, y) ((int16u) (((int32u) (x)) % ((int16u) (y)))) + + /** + * @brief Provide a portable name for the int32s by int16s modulo + * library function (which can perform the division with only a single + * assembly instruction on some platforms) + */ + #define halCommonSMod32By16(x, y) ((int16s) (((int32s) (x)) % ((int16s) (y)))) + //@} \\END DIVIDE and MODULUS OPERATIONS +#endif //_HAL_USE_COMMON_DIVMOD_ + + +//////////////////////////////////////////////////////////////////////////////// +#ifdef _HAL_USE_COMMON_MEMUTILS_ + /** \name C Standard Library Memory Utilities + * These should be used in place of the standard library functions. + * + * These functions have the same parameters and expected results as their C + * Standard Library equivalents but may take advantage of certain implementation + * optimizations. + * + * Unless otherwise noted, these functions are utilized by the StStack and are + * therefore required to be implemented in the HAL. Additionally, unless otherwise + * noted, applications that find these functions useful may utilze them. + */ + //@{ + + /** + * @brief Refer to the C stdlib memcpy(). + */ + void halCommonMemCopy(void *dest, const void *src, int8u bytes); + + + /** + * @brief Refer to the C stdlib memset(). + */ + void halCommonMemSet(void *dest, int8u val, int16u bytes); + + + /** + * @brief Refer to the C stdlib memcmp(). + */ + int8s halCommonMemCompare(const void *source0, const void *source1, int8u bytes); + + + /** + * @brief Works like C stdlib memcmp(), but takes a flash space source + * parameter. + */ + int8s halCommonMemPGMCompare(const void *source0, void PGM *source1, int8u bytes); + + /** + * @brief Same as the C stdlib memcpy(), but handles copying from const + * program space. + */ + void halCommonMemPGMCopy(void* dest, void PGM *source, int8u bytes); + + /** + * @brief Friendly convenience macro pointing to the full HAL function. + */ + #define MEMSET(d,v,l) halCommonMemSet(d,v,l) + #define MEMCOPY(d,s,l) halCommonMemCopy(d,s,l) + #define MEMCOMPARE(s0,s1,l) halCommonMemCompare(s0, s1, l) + #define MEMPGMCOMPARE(s0,s1,l) halCommonMemPGMCompare(s0, s1, l) + + //@} // end of C Standard Library Memory Utilities +#endif //_HAL_USE_COMMON_MEMUTILS_ + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +// The following sections are common on all platforms +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/** + * @name Generic Types + *@{ + */ + +/** + * @brief An alias for one, used for clarity. + */ +#define TRUE 1 + +/** + * @brief An alias for zero, used for clarity. + */ +#define FALSE 0 + +#ifndef NULL +/** + * @brief The null pointer. + */ +#define NULL ((void *)0) +#endif + +//@} \\END Generic Types + + +/** + * @name Bit Manipulation Macros + */ +//@{ + +/** + * @brief Useful to reference a single bit of a byte. + */ +#define BIT(x) (1U << (x)) // Unsigned avoids compiler warnings re BIT(15) + +/** + * @brief Useful to reference a single bit of an int32u type. + */ +#define BIT32(x) (((int32u) 1) << (x)) + +/** + * @brief Sets \c bit in the \c reg register or byte. + * @note Assuming \c reg is an IO register, some platforms + * can implement this in a single atomic operation. +*/ +#define SETBIT(reg, bit) reg |= BIT(bit) + +/** + * @brief Sets the bits in the \c reg register or the byte + * as specified in the bitmask \c bits. + * @note This is never a single atomic operation. + */ +#define SETBITS(reg, bits) reg |= (bits) + +/** + * @brief Clears a bit in the \c reg register or byte. + * @note Assuming \c reg is an IO register, some platforms (such as the AVR) + * can implement this in a single atomic operation. + */ +#define CLEARBIT(reg, bit) reg &= ~(BIT(bit)) + +/** + * @brief Clears the bits in the \c reg register or byte + * as specified in the bitmask \c bits. + * @note This is never a single atomic operation. + */ +#define CLEARBITS(reg, bits) reg &= ~(bits) + +/** + * @brief Returns the value of \c bit within the register or byte \c reg. +*/ +#define READBIT(reg, bit) (reg & (BIT(bit))) + +/** + * @brief Returns the value of the bitmask \c bits within + * the register or byte \c reg. + */ +#define READBITS(reg, bits) (reg & (bits)) + +//@} \\END Bit Manipulation Macros + + +//////////////////////////////////////////////////////////////////////////////// +/** + * @name Byte Manipulation Macros + */ +//@{ + +/** + * @brief Returns the low byte of the 16-bit value \c n as an \c int8u. + */ +#define LOW_BYTE(n) ((int8u)((n) & 0xFF)) + +/** + * @brief Returns the high byte of the 16-bit value \c n as an \c int8u. + */ +#define HIGH_BYTE(n) ((int8u)(LOW_BYTE((n) >> 8))) + +/** + * @brief Returns the value built from the two \c int8u + * values \c high and \c low. + */ +#define HIGH_LOW_TO_INT(high, low) ( \ + (( (int16u) (high) ) << 8) + \ + ( (int16u) ( (low) & 0xFF)) \ + ) + +/** + * @brief Returns the low byte of the 32-bit value \c n as an \c int8u. + */ +#define BYTE_0(n) ((int8u)((n) & 0xFF)) + +/** + * @brief Returns the second byte of the 32-bit value \c n as an \c int8u. + */ +#define BYTE_1(n) ((int8u)(BYTE_0((n) >> 8))) + +/** + * @brief Returns the third byte of the 32-bit value \c n as an \c int8u. + */ +#define BYTE_2(n) ((int8u)(BYTE_0((n) >> 16))) + +/** + * @brief Returns the high byte of the 32-bit value \c n as an \c int8u. + */ +#define BYTE_3(n) ((int8u)(BYTE_0((n) >> 24))) + +//@} \\END Byte manipulation macros + + +//////////////////////////////////////////////////////////////////////////////// +/** + * @name Time Manipulation Macros + */ +//@{ + +/** + * @brief Returns the elapsed time between two 8 bit values. + * Result may not be valid if the time samples differ by more than 127 + */ +#define elapsedTimeInt8u(oldTime, newTime) \ + ((int8u) ((int8u)(newTime) - (int8u)(oldTime))) + +/** + * @brief Returns the elapsed time between two 16 bit values. + * Result may not be valid if the time samples differ by more than 32767 + */ +#define elapsedTimeInt16u(oldTime, newTime) \ + ((int16u) ((int16u)(newTime) - (int16u)(oldTime))) + +/** + * @brief Returns the elapsed time between two 32 bit values. + * Result may not be valid if the time samples differ by more than 2147483647 + */ +#define elapsedTimeInt32u(oldTime, newTime) \ + ((int32u) ((int32u)(newTime) - (int32u)(oldTime))) + +/** + * @brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap + * around of the variable before it is wrong. + */ +#define MAX_INT8U_VALUE 0xFF +#define timeGTorEqualInt8u(t1, t2) \ + (elapsedTimeInt8u(t2, t1) <= ((MAX_INT8U_VALUE + 1) / 2)) + +/** + * @brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap + * around of the variable before it is wrong. + */ +#define MAX_INT16U_VALUE 0xFFFF +#define timeGTorEqualInt16u(t1, t2) \ + (elapsedTimeInt16u(t2, t1) <= ((MAX_INT16U_VALUE + 1) / 2)) + +/** + * @brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap + * around of the variable before it is wrong. + */ +#define MAX_INT32U_VALUE 0xFFFFFFFF +#define timeGTorEqualInt32u(t1, t2) \ + (elapsedTimeInt32u(t2, t1) <= ((MAX_INT32U_VALUE + 1) / 2)) + +//@} \\END Time manipulation macros + + + +#endif //__PLATFORMCOMMON_H__ + +/** @} END addtogroup */ + diff --git a/cpu/stm32w108/hal/micro/led.h b/cpu/stm32w108/hal/micro/led.h new file mode 100644 index 000000000..b0bd24a0d --- /dev/null +++ b/cpu/stm32w108/hal/micro/led.h @@ -0,0 +1,65 @@ +/** @file hal/micro/led.h + * @brief Header for led APIs + * + * + */ + +/** @addtogroup led + * @brief Sample API funtions for controlling LEDs. + * + * When specifying an LED to use, always use the BOARDLEDx definitions that + * are defined within the BOARD_HEADER. + * + * See led.h for source code. + *@{ + */ + + +/** @brief Configures GPIOs pertaining to the control of LEDs. + */ +void halInitLed(void); + +/** @brief Ensures that the definitions from the BOARD_HEADER + * are always used as parameters to the LED functions. + */ + typedef int8u HalBoardLed; +// Note: Even though many compilers will use 16 bits for an enum instead of 8, +// we choose to use an enum here. The possible compiler inefficiency does not +// affect stack-based parameters and local variables, which is the +// general case for led paramters. + +/** @brief Atomically wraps an XOR or similar operation for a single GPIO + * pin attached to an LED. + * + * @param led Identifier (from BOARD_HEADER) for the LED to be toggled. + */ +void halToggleLed(HalBoardLed led); + +/** @brief Turns on (sets) a GPIO pin connected to an LED so that the LED + * turns on. + * + * @param led Identifier (from BOARD_HEADER) for the LED to turn on. + */ +void halSetLed(HalBoardLed led); + +/** @brief Turns off (clears) a GPIO pin connected to an LED, which turns + * off the LED. + * + * @param led Identifier (from BOARD_HEADER) for the LED to turn off. + */ +void halClearLed(HalBoardLed led); + +/** @brief Called by the stack to indicate activity over the radio (for + * both transmission and reception). It is called once with \c turnOn TRUE and + * shortly thereafter with \c turnOn FALSE. + * + * Typically does something interesting, such as change the state of + * an LED. + * + * @param turnOn See Usage. + */ +void halStackIndicateActivity(boolean turnOn); + +/** @} // END addtogroup + */ + diff --git a/cpu/stm32w108/hal/micro/mems.h b/cpu/stm32w108/hal/micro/mems.h new file mode 100644 index 000000000..6697924bd --- /dev/null +++ b/cpu/stm32w108/hal/micro/mems.h @@ -0,0 +1,36 @@ +/** @file mems.h + * @brief Header for MB851 mems APIS + * + * + * + */ + +#ifndef _MEMS_H_ +#define _MEMS_H_ + +#include "hal/micro/mems_regs.h" + +/** @brief Mems data type: three acceleration values each related to a specific direction + Watch out: only lower data values (e.g. those terminated by the _l) are + currently used by the device */ + +typedef struct { + int8u outx_l; + int8u outx_h; + int8u outy_l; + int8u outy_h; + int8u outz_l; + int8u outz_h; +} t_mems_data; + + +/** @brief Mems Initialization function + */ +int8u mems_Init(void); + +/** @brief Get mems acceleration values + */ +int8u mems_GetValue(t_mems_data *mems_data); + +#endif /* _MEMS_H_ */ + diff --git a/cpu/stm32w108/hal/micro/mems_regs.h b/cpu/stm32w108/hal/micro/mems_regs.h new file mode 100644 index 000000000..bd06552df --- /dev/null +++ b/cpu/stm32w108/hal/micro/mems_regs.h @@ -0,0 +1,125 @@ +/** @file hal/micro/mems_regs.h + * @brief stm32w108 mems registers + * + * + */ + +#ifndef _MEMS_REGS_H_ +#define _MEMS_REGS_H_ + +//---Size of MEMs data--- +#define MEMS_DATA_SIZE 6 + +//---address of slave I want to communicate with--- +#define kLIS3L02DQ_SLAVE_ADDR 0x38 + +//----------------------------------------------------------------------------- +//---accelerometer register addresses--- +#define OFFSET_X 0x16 +#define OFFSET_Y 0x17 +#define OFFSET_Z 0x18 +#define GAIN_X 0x19 +#define GAIN_Y 0x1A +#define GAIN_Z 0x1B +#define CTRL_REG1 0x20 +#define CTRL_REG2 0x21 +#define STATUS_REG 0x27 +#define OUTX_L 0x28 +#define OUTX_H 0x29 +#define OUTY_L 0x2A +#define OUTY_H 0x2B +#define OUTZ_L 0x2C +#define OUTZ_H 0x2D +#define FF_WU_CFG 0x30 +#define FF_WU_SRC 0x31 +#define FF_WU_ACK 0x32 +#define FF_WU_THS_L 0x34 +#define FF_WU_THS_H 0x35 +#define FF_WU_DURATION 0x36 +#define DD_CFG 0x38 +#define DD_SRC 0x39 +#define DD_ACK 0x3A +#define DD_THSI_L 0x3C +#define DD_THSI_H 0x3D +#define DD_THSE_L 0x3E +#define DD_THSE_H 0x3F + +// Communication control settings +// I2C +#define REPETIR 0x80 +// SPI +#define MEMS_SPI_WRITE 0x00 +#define MEMS_SPI_READ 0x80 +#define MEMS_SPI_MULTIPLE_BYTES 0x40 + +//----------------------------------------------------------------------------- +//---Settings for CTRL_REG1--- + +// Power Down Control (PD) +#define LIS_PD_OFF 0x00 +#define LIS_PD_ON 0x40 + +// Decimation Factor Control (DF) +#define LIS_DF_BY128 0x00 +#define LIS_DF_BY64 0x10 +#define LIS_DF_BY32 0x20 +#define LIS_DF_BY8 0x30 + +// Self Test +#define LIS_ST_NORMAL 0x00 +#define LIS_ST_TEST 0x08 + +// Enable Axis +#define LIS_EA_ALL 0x07 + +//----------------------------------------------------------------------------- +//---Settings for CTRL_REG2--- + +// Full Scale (FS) +#define LIS_FS_2G 0x00 +#define LIS_FS_6G 0x80 + +// Block Data Update (BDU) +#define LIS_BDU_CONTINUOUS 0x00 +#define LIS_BDU_WAIT 0x40 + +// Big/Little Endian Selection (BLE) +#define LIS_BLE_LE 0x00 +#define LIS_BLE_BE 0x20 + +// Data Alignment Selection DAS +#define LIS_DAS_12BIT 0x00 +#define LIS_DAS_16BIT 0x01 + +// Interrupt Enable +#define LIS_INTR_DISABLE 0x00 +#define LIS_INTR_ENABLE 0x08 + +// Data Ready Enable +#define LIS_DRDY_DISABLE 0x00 +#define LIS_DRDY_ENABLE 0x04 + +//----------------------------------------------------------------------------- + +#define LIS_BLE_XX LIS_BLE_BE + + +/* Private Functions Prototypes ----------------------------------------------*/ + +//*********************i2c_read_reg***********************// +//----------Reads a register on the I2C target------------// +//------slave addr is the is the I2C target device--------// +//-reg_addr is the address of the register to be written--// +//-pBuffer is the storage destination for the read data---// +//-NoOfBytes is the amount of data to read----------------// +int8u i2c_read_reg (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOfBytes); + +//*********************i2c_write_reg**********************// +//----------Writes a register on the I2C target-----------// +//------slave addr is the is the I2C target device--------// +//-reg_addr is the address of the register to be written--// +//-reg_value is the value of the register to be written---// +int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); + +#endif /* _MEMS_REGS_H_ */ + diff --git a/cpu/stm32w108/hal/micro/micro-common.h b/cpu/stm32w108/hal/micro/micro-common.h new file mode 100644 index 000000000..d187f4fd1 --- /dev/null +++ b/cpu/stm32w108/hal/micro/micro-common.h @@ -0,0 +1,116 @@ +/** @file micro-common.h + * @brief Minimal Hal functions common across all microcontroller-specific files. + * See @ref micro for documentation. + * + * + */ + +/** @addtogroup micro + * Many of the supplied example applications use these microcontroller functions. + * See hal/micro/micro-common.h for source code. + * + *@{ + */ + +#ifndef __MICRO_COMMON_H__ +#define __MICRO_COMMON_H__ + + +/** @brief Initializes microcontroller-specific peripherals. +*/ +void halInit(void); + +/** @brief Restarts the microcontroller and therefore everything else. +*/ +void halReboot(void); + +/** @brief Powers up microcontroller peripherals and board peripherals. +*/ +void halPowerUp(void); + +/** @brief Powers down microcontroller peripherals and board peripherals. +*/ +void halPowerDown(void); + +/** @brief The value that must be passed as the single parameter to + * ::halInternalDisableWatchDog() in order to sucessfully disable the watchdog + * timer. + */ +#define MICRO_DISABLE_WATCH_DOG_KEY 0xA5 + +/** @brief Enables the watchdog timer. + */ +void halInternalEnableWatchDog(void); + +/** @brief Disables the watchdog timer. + * + * @note To prevent the watchdog from being disabled accidentally, + * a magic key must be provided. + * + * @param magicKey A value (::MICRO_DISABLE_WATCH_DOG_KEY) that enables the function. + */ +void halInternalDisableWatchDog(int8u magicKey); + +/** @brief Determines whether the watchdog has been enabled or disabled. + * + * @return A boolean value indicating if the watchdog is current enabled. + */ +boolean halInternalWatchDogEnabled( void ); + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/** @brief Enumerations for the possible microcontroller sleep modes. + * - SLEEPMODE_RUNNING + * Everything is active and running. In practice this mode is not + * used, but it is defined for completeness of information. + * - SLEEPMODE_IDLE + * Only the CPU is idled. The rest of the chip continues runing + * normally. The chip will wake from any interrupt. + * - SLEEPMODE_WAKETIMER + * The sleep timer clock sources remain running. The RC is always + * running and the 32kHz XTAL depends on the board header. Wakeup + * is possible from both GPIO and the sleep timer. System time + * is maintained. The sleep timer is assumed to be configured + * properly for wake events. + * - SLEEPMODE_MAINTAINTIMER + * The sleep timer clock sources remain running. The RC is always + * running and the 32kHz XTAL depends on the board header. Wakeup + * is possible from only GPIO. System time is maintained. + * - SLEEPMODE_NOTIMER + * The sleep timer clock sources (both RC and XTAL) are turned off. + * Wakeup is possible from only GPIO. System time is lost. + */ +enum SleepModes +#else +typedef int8u SleepModes; +enum +#endif +{ + SLEEPMODE_RUNNING = 0, + SLEEPMODE_IDLE = 1, + SLEEPMODE_WAKETIMER = 2, + SLEEPMODE_MAINTAINTIMER = 3, + SLEEPMODE_NOTIMER = 4, +}; + +/** @brief Blocks the current thread of execution for the specified + * amount of time, in microseconds. + * + * The function is implemented with cycle-counted busy loops + * and is intended to create the short delays required when interfacing with + * hardware peripherals. + * + * The accuracy of the timing provided by this function is not specified, + * but a general rule is that when running off of a crystal oscillator it will + * be within 10us. If the micro is running off of another type of oscillator + * (e.g. RC) the timing accuracy will potentially be much worse. + * + * @param us The specified time, in microseconds. + Values should be between 1 and 65535 microseconds. + */ +void halCommonDelayMicroseconds(int16u us); + + +#endif //__MICRO_COMMON_H__ + +/** @} END micro group */ + diff --git a/cpu/stm32w108/hal/micro/system-timer.h b/cpu/stm32w108/hal/micro/system-timer.h new file mode 100644 index 000000000..0d4ba9591 --- /dev/null +++ b/cpu/stm32w108/hal/micro/system-timer.h @@ -0,0 +1,84 @@ +/** @file hal/micro/system-timer.h + * @brief Header file for system_timer APIs + * + * + * + + */ + +/** @addtogroup system_timer + * @brief Functions that provide access to the system clock. + * + * A single system tick (as returned by ::halCommonGetInt16uMillisecondTick() and + * ::halCommonGetInt32uMillisecondTick() ) is approximately 1 millisecond. + * + * - When used with a 32.768kHz crystal, the system tick is 0.976 milliseconds. + * + * - When used with a 3.6864MHz crystal, the system tick is 1.111 milliseconds. + * + * A single quarter-second tick (as returned by + * ::halCommonGetInt16uQuarterSecondTick() ) is approximately 0.25 seconds. + * + * The values used by the time support functions will wrap after an interval. + * The length of the interval depends on the length of the tick and the number + * of bits in the value. However, there is no issue when comparing time deltas + * of less than half this interval with a subtraction, if all data types are the + * same. + * + * See system-timer.h for source code. + *@{ + */ + +#ifndef __SYSTEM_TIMER_H__ +#define __SYSTEM_TIMER_H__ + +/** + * @brief Initializes the system tick. + * + * @return Time to update the async registers after RTC is started (units of 100 + * microseconds). + */ +int16u halInternalStartSystemTimer(void); + + +/** + * @brief Returns the current system time in system ticks, as a 16-bit + * value. + * + * @return The least significant 16 bits of the current system time, in system + * ticks. + */ +//#pragma pagezero_on // place this function in zero-page memory for xap +int16u halCommonGetInt16uMillisecondTick(void); +//#pragma pagezero_off + +/** + * @brief Returns the current system time in system ticks, as a 32-bit + * value. + * + * @nostackusage + * + * @return The least significant 32 bits of the current system time, in + * system ticks. + */ +int32u halCommonGetInt32uMillisecondTick(void); + +/** + * @brief Returns the current system time in quarter second ticks, as a + * 16-bit value. + * + * @nostackusage + * + * @return The least significant 16 bits of the current system time, in system + * ticks multiplied by 256. + */ +int16u halCommonGetInt16uQuarterSecondTick(void); + +#endif //__SYSTEM_TIMER_H__ + +/**@} //END addtogroup + */ + + + + diff --git a/cpu/stm32w108/hal/micro/temperature_sensor.h b/cpu/stm32w108/hal/micro/temperature_sensor.h new file mode 100644 index 000000000..073bfc0ce --- /dev/null +++ b/cpu/stm32w108/hal/micro/temperature_sensor.h @@ -0,0 +1,27 @@ +/** @file temperature_sensor.h + * @brief Header for temperature sensor driver + * + * + * + */ +#ifndef _TEMP_SENSOR_H_ +#define _TEMP_SENSOR_H_ + +/* Include --------------------------------------------------------------------*/ +#include "hal/micro/adc.h" +/* Define --------------------------------------------------------------------*/ + +/* Typedef -------------------------------------------------------------------*/ + +/* Functions -----------------------------------------------------------------*/ + +/** @brief Temperature Sensor Initialization function +*/ +void temperatureSensor_Init(void); + +/** @brief Get temperature sensor value +*/ +int32u temperatureSensor_GetValue(int8u type); + +#endif /* _TEMP_SENSOR_H_ */ + diff --git a/cpu/stm32w108/hal/token-phy.h b/cpu/stm32w108/hal/token-phy.h new file mode 100644 index 000000000..91a1042b8 --- /dev/null +++ b/cpu/stm32w108/hal/token-phy.h @@ -0,0 +1,51 @@ +/** + * @file token-phy.h + * @brief Definitions for phy tokens. + * + * The file token-phy.h should not be included directly. + * It is accessed by the other token files. + * + * + */ + +#ifndef DEFINE_INDEXED_TOKEN + #define DEFINE_INDEXED_TOKEN(name, type, arraysize, ...) \ + TOKEN_DEF(name, CREATOR_##name, 0, 1, type, (arraysize), __VA_ARGS__) +#endif + + +#if defined PHY_STM32W108XX + +#ifdef DEFINETYPES +typedef struct { + int8u vcoAtLna; // the VCO tune value at the time LNA value was calculated. + int8u modDac; // msb : cal needed , bit 0-5 : value + int8u filter; // msb : cal needed , bit 0-4 : value + int8u lna; // msb : cal needed , bit 0-5 : value +} tokTypeStackCalData; +#endif + + +#ifdef DEFINETOKENS + +#define CREATOR_STACK_CAL_DATA 0xD243 // msb+'R'+'C' (Radio Calibration) +#define STACK_CAL_DATA_ARRAY_SIZE 16 + + +// This breaks the simulated eeprom unit test, so we ifdef it out +// of existence. +#ifndef ST_TEST +DEFINE_INDEXED_TOKEN(STACK_CAL_DATA, + tokTypeStackCalData, STACK_CAL_DATA_ARRAY_SIZE, + { + 0xff, // vcoAtLna default: invalid VCO value. + 0x80, // modDac default: cal needed. + 0x80, // filter default: cal needed. + 0x80 // lna default: cal needed. + }) +#endif //ST_TEST + +#endif //DEFINETOKENS + +#endif // defined PHY_STM32W108XX + diff --git a/cpu/stm32w108/leds-arch.c b/cpu/stm32w108/leds-arch.c new file mode 100644 index 000000000..b3e65220d --- /dev/null +++ b/cpu/stm32w108/leds-arch.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: leds-arch.c,v 1.1 2010/10/25 09:03:38 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Leds. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include "contiki-conf.h" +#include "dev/leds.h" + + +/*---------------------------------------------------------------------------*/ +void +leds_arch_init(void) +{ + LED_CONFIG(); + + LEDS_PORT |= (LEDS_CONF_RED | LEDS_CONF_GREEN); +} +/*---------------------------------------------------------------------------*/ +unsigned char +leds_arch_get(void) +{ + return ((LEDS_PORT & LEDS_CONF_RED) ? 0 : LEDS_RED) + | ((LEDS_PORT & LEDS_CONF_GREEN) ? 0 : LEDS_GREEN); +} +/*---------------------------------------------------------------------------*/ +void +leds_arch_set(unsigned char leds) +{ + + LEDS_PORT = (LEDS_PORT & ~(LEDS_CONF_RED|LEDS_CONF_GREEN)) + | ((leds & LEDS_RED) ? 0 : LEDS_CONF_RED) + | ((leds & LEDS_GREEN) ? 0 : LEDS_CONF_GREEN); + +} +/*---------------------------------------------------------------------------*/ \ No newline at end of file diff --git a/cpu/stm32w108/mtarch.h b/cpu/stm32w108/mtarch.h new file mode 100644 index 000000000..a61c7be97 --- /dev/null +++ b/cpu/stm32w108/mtarch.h @@ -0,0 +1,13 @@ +/* + * Implementation of multithreading in ARM Cortex-M3. To be done. + */ + + +#ifndef __MTARCH_H__ +#define __MTARCH_H__ + +struct mtarch_thread { + short mt_thread; +}; + +#endif /* __MTARCH_H__ */ \ No newline at end of file diff --git a/cpu/stm32w108/rand.c b/cpu/stm32w108/rand.c new file mode 100644 index 000000000..1e9ab12de --- /dev/null +++ b/cpu/stm32w108/rand.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: rand.c,v 1.1 2010/10/25 09:03:38 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Clock. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include "lib/rand.h" +#include "dev/stm32w-radio.h" + +int rand(void) +{ + u16_t rand_num; + + ST_RadioGetRandomNumbers(&rand_num, 1); + + rand_num &= RAND_MAX; + + return (int)rand_num; +} + +/* + * It does nothing, since the rand already generates true random numbers. + */ +void srand(unsigned int seed) +{ +} diff --git a/cpu/stm32w108/rtimer-arch.c b/cpu/stm32w108/rtimer-arch.c new file mode 100644 index 000000000..2c3b08f89 --- /dev/null +++ b/cpu/stm32w108/rtimer-arch.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: rtimer-arch.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Real-timer specific implementation for STM32W. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + + +#include "sys/energest.h" +#include "sys/rtimer.h" + + +#define DEBUG 0 +#if DEBUG +#include +#define PRINTF(...) printf(__VA_ARGS__) +#else +#define PRINTF(...) +#endif + + + +static u32_t time_msb = 0; // Most significant bits of the current time. + +// time of the next rtimer event. Initially is set to the max value. +static rtimer_clock_t next_rtimer_time = 0; + +static u16_t saved_TIM1CFG; + + +/*---------------------------------------------------------------------------*/ +void halTimer1Isr(void){ + + + if(INT_TIM1FLAG & INT_TIMUIF){ // Overflow event. + + //PRINTF("O %4x.\r\n", TIM1_CNT); + //printf("OV "); + + time_msb++; + rtimer_clock_t now = ((rtimer_clock_t)time_msb << 16)|TIM1_CNT; + + rtimer_clock_t clock_to_wait = next_rtimer_time - now; + + if(clock_to_wait <= 0x10000 && clock_to_wait > 0){ // We must set now the Timer Compare Register. + + TIM1_CCR1 = (int16u)clock_to_wait; + INT_TIM1FLAG = INT_TIMCC1IF; + INT_TIM1CFG |= INT_TIMCC1IF; // Compare 1 interrupt enable. + } + + INT_TIM1FLAG = INT_TIMUIF; + + } + + else if(INT_TIM1FLAG & INT_TIMCC1IF){ // Compare event. + + INT_TIM1CFG &= ~INT_TIMCC1IF; // Disable the next compare interrupt + + PRINTF("\nCompare event %4x\r\n", TIM1_CNT); + PRINTF("INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG); + ENERGEST_ON(ENERGEST_TYPE_IRQ); + rtimer_run_next(); + ENERGEST_OFF(ENERGEST_TYPE_IRQ); + INT_TIM1FLAG = INT_TIMCC1IF; + + } + +} +/*---------------------------------------------------------------------------*/ +void +rtimer_arch_init(void) +{ + TIM1_CR1 = 0; + + TIM1_PSC = RT_PRESCALER; + + TIM1_ARR = 0xffff; // Counting from 0 to the maximum value. + + // Bits of TIMx_CCMR1 as default. + + TIM1_EGR = TIM_UG; // Update Generation. + + INT_TIM1FLAG = 0xffff; + + INT_TIM1CFG = INT_TIMUIF; // Update interrupt enable (interrupt on overflow). + + TIM1_CR1 = TIM_CEN; // Counter enable. + + INT_CFGSET = INT_TIM1; // Enable top level interrupt. + +} +/*---------------------------------------------------------------------------*/ +void rtimer_arch_disable_irq(void) +{ + ATOMIC( + saved_TIM1CFG = INT_TIM1CFG; + INT_TIM1CFG = 0; + ) +} +/*---------------------------------------------------------------------------*/ +void rtimer_arch_enable_irq(void) +{ + INT_TIM1CFG = saved_TIM1CFG; +} +/*---------------------------------------------------------------------------*/ +rtimer_clock_t rtimer_arch_now(void) +{ + return ((rtimer_clock_t)time_msb << 16)|TIM1_CNT; +} + +/*---------------------------------------------------------------------------*/ + +void +rtimer_arch_schedule(rtimer_clock_t t) +{ + + PRINTF("rtimer_arch_schedule time %4x\r\n", /*((u32_t*)&t)+1,*/(u32_t)t); + + next_rtimer_time = t; + + rtimer_clock_t now = rtimer_arch_now(); + + rtimer_clock_t clock_to_wait = t - now; + + PRINTF("now %2x\r\n", TIM1_CNT); + PRINTF("clock_to_wait %4x\r\n", clock_to_wait); + + if(clock_to_wait <= 0x10000){ // We must set now the Timer Compare Register. + + TIM1_CCR1 = (int16u)now + (int16u)clock_to_wait; + INT_TIM1FLAG = INT_TIMCC1IF; + INT_TIM1CFG |= INT_TIMCC1IF; // Compare 1 interrupt enable. + + PRINTF("2-INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG); + + } + // else compare register will be set at overflow interrupt closer to the rtimer event. + +} diff --git a/cpu/stm32w108/rtimer-arch.h b/cpu/stm32w108/rtimer-arch.h new file mode 100644 index 000000000..586e37c16 --- /dev/null +++ b/cpu/stm32w108/rtimer-arch.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: rtimer-arch.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ + +/** + * \file + * Real-timer header file for STM32W. + * \author + * Salvatore Pitrulli + */ + +#ifndef __RTIMER_ARCH_H__ +#define __RTIMER_ARCH_H__ + +#include "contiki-conf.h" +#include "sys/clock.h" + + +#define RT_RESOLUTION RES_171US + + +#define RES_341US 0 +#define RES_171US 1 +#define RES_85US 2 + +// If it was possible to define a custom size for the rtimer_clock_t type: +//typedef unsigned long long rtimer_clock_t; // Only 48 bit are used. It's enough for hundreds of years. + +#if RT_RESOLUTION == RES_341US +#define RT_PRESCALER 12 // CK_CNT = PCLK/4096 = 12 MHz/4096 = 2929.6875 Hz +#define RTIMER_ARCH_SECOND 2930 // One tick: 341.33 us. Using this value we will delay about 9.22 sec after a day. +#endif /* RT_RESOLUTION == RES_341US */ + +#if RT_RESOLUTION == RES_171US +#define RT_PRESCALER 11 // CK_CNT = PCLK/2048 = 12 MHz/2048 = 5859.375 Hz +#define RTIMER_ARCH_SECOND 5859 // One tick: 170.66 us. Using this value we will advance about 5.53 sec after a day. +#endif /* RT_RESOLUTION == RES_171US */ + +#if RT_RESOLUTION == RES_85US +#define RT_PRESCALER 10 // CK_CNT = PCLK/2048 = 12 MHz/2048 = 5859.375 Hz +#define RTIMER_ARCH_SECOND 11719 // One tick: 85.33 us. Using this value we will delay about 1.84 sec after a day. +#endif /* RT_RESOLUTION == RES_85US */ + +rtimer_clock_t rtimer_arch_now(void); +//#define rtimer_arch_now() clock_time() + +void rtimer_arch_disable_irq(void); +void rtimer_arch_enable_irq(void); + +#endif /* __RTIMER_ARCH_H__ */ diff --git a/cpu/stm32w108/simplemac/include/phy-library.h b/cpu/stm32w108/simplemac/include/phy-library.h new file mode 100644 index 000000000..7739811b7 --- /dev/null +++ b/cpu/stm32w108/simplemac/include/phy-library.h @@ -0,0 +1,831 @@ +/* + * File: stack/phy/phy-library.h + * Description: Interface definition for library functionality. + * + * + */ + +#include "stm32w108_type.h" + +//--------------------------------------------------------------------------- +// Definitions +//------------ + +/** + * @name SIMPLEMAC version defines + *@{ + */ + + +/** + * @brief Version major number + */ +#define SIMPLEMAC_VERSION_MAJOR 1 + +/** + * @brief Version minor number + */ +#define SIMPLEMAC_VERSION_MINOR 0 + +/** + * @brief Version patch number + */ +#define SIMPLEMAC_VERSION_PATCH 0 + +/** + * @brief Version qualifier + */ +#define SIMPLEMAC_VERSION_QUAL "" + +#define _SQUOTEME(a) #a +#define SQUOTEME(a) _SQUOTEME(a) + +/** + * @brief Version string + */ +#define SIMPLEMAC_VERSION_STRING SQUOTEME(SIMPLEMAC_VERSION_MAJOR) "." SQUOTEME(SIMPLEMAC_VERSION_MINOR) "." SQUOTEME(SIMPLEMAC_VERSION_PATCH) SIMPLEMAC_VERSION_QUAL + +//@} \\END SIMPLEMAC version defines + + +#define SECURITY_BLOCK_SIZE 16 // bytes +#define MIN_RADIO_POWER -43 // dBm +#define MAX_RADIO_POWER 3 // dBm + +#ifndef __PHY_H__ +enum { + ST_RADIO_POWER_MODE_RX_ON, + ST_RADIO_POWER_MODE_OFF +}; +typedef u8 RadioPowerMode; + +//--------------------------------------------------------------------------- +// Transmit Configuration +//----------------------- +// The application must declare this structure and initialize each member +// variable. radioTransmitConfig must be initialized prior to calling +// ST_RadioTransmit() and may be modified only while no transmit operation is +// in progress. + +#define RADIO_CCA_ATTEMPT_MAX_DEFAULT 4 +#define RADIO_BACKOFF_EXPONENT_MIN_DEFAULT 3 +#define RADIO_BACKOFF_EXPONENT_MAX_DEFAULT 5 + +typedef struct { + boolean waitForAck; // Wait for ACK if ACK request set in FCF. + boolean checkCca; // backoff and check CCA before transmit. + u8 ccaAttemptMax; // The number of CCA attempts before failure; + u8 backoffExponentMin; // Backoff exponent for the initial CCA attempt. + u8 backoffExponentMax; // Backoff exponent for the final CCA attempt(s). + boolean appendCrc; // Append CRC to transmitted packets. +} RadioTransmitConfig; +#endif// __PHY_H__ + +#ifndef ST_TYPES_H +/** + * @name txPowerModes for stSetTxPowerMode and mfglibSetPower + */ +//@{ + +/** @brief The application should call ::stSetTxPowerMode() with the + * txPowerMode parameter set to this value to disable all power mode options, + * resulting in normal power mode and bi-directional RF transmitter output. + */ +#define ST_TX_POWER_MODE_DEFAULT 0x0000 +/** @brief The application should call ::stSetTxPowerMode() with the + * txPowerMode parameter set to this value to enable boost power mode. + */ +#define ST_TX_POWER_MODE_BOOST 0x0001 +/** @brief The application should call ::stSetTxPowerMode() with the + * txPowerMode parameter set to this value to enable the alternate transmitter + * output. + */ +#define ST_TX_POWER_MODE_ALTERNATE 0x0002 +/** @brief The application should call ::stSetTxPowerMode() with the + * txPowerMode parameter set to this value to enable both boost mode and the + * alternate transmitter output. + */ +#define ST_TX_POWER_MODE_BOOST_AND_ALTERNATE (ST_TX_POWER_MODE_BOOST \ + |ST_TX_POWER_MODE_ALTERNATE) +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// The application does not ever need to call stSetTxPowerMode() with the +// txPowerMode parameter set to this value. This value is used internally by +// the stack to indicate that the default token configuration has not been +// overidden by a prior call to stSetTxPowerMode(). +#define ST_TX_POWER_MODE_USE_TOKEN 0x8000 +#endif//DOXYGEN_SHOULD_SKIP_THIS +//@} \\END Definitions + +/** + * @brief The maximum 802.15.4 channel number is 26. + */ +#define ST_MAX_802_15_4_CHANNEL_NUMBER 26 + +/** + * @brief The minimum 802.15.4 channel number is 11. + */ +#define ST_MIN_802_15_4_CHANNEL_NUMBER 11 + +/** + * @brief There are sixteen 802.15.4 channels. + */ +#define ST_NUM_802_15_4_CHANNELS \ + (ST_MAX_802_15_4_CHANNEL_NUMBER - ST_MIN_802_15_4_CHANNEL_NUMBER + 1) + +#endif //ST_TYPES_H + + + + +//--------------------------------------------------------------------------- +/** @name + * Radio power state control APIs + * + * @brief + * These APIs control the overall radio initialization and power state. + */ +//@{ + +/** @brief + * This function performs one-time radio initialization and calibration. + * This function must be called once after chip reset or wake from deep sleep. + * This function will power up the radio while it configures the radio channel. + * After the radio is configured and the channel is set the radio will be left + * in the state specified by the \c initialRadioPowerMode parameter. + * This function calls ST_RadioSetPowerMode(), + * ST_RadioEnableAddressFiltering(), ST_RadioEnableAutoAck(), + * ST_RadioSetCoordinator(), ST_RadioSetPower(), ST_RadioSetChannel(), + * ST_RadioEnablePacketTrace(), and ST_RadioEnableReceiveCrc() + * providing the last used argument for each function. If these functions have + * not been called before ST_RadioInit() then the default for each is used. + * Only the functions listed above can be called before ST_RadioInit(). + * All other library functions must not be called until after + * ST_RadioInit() has been called once after each chip reset or wake from deep + * sleep. + * + * @param + * initialRadioPowerMode specifies the state that the function will leave the + * radio in after it is configured. This parameter can be either: + * ST_RADIO_POWER_MODE_OFF - radio will be powered down. + * ST_RADIO_POWER_MODE_RX_ON - radio will be left in the on (receive) state. + * + * @return ::ST_SUCCESS or a status code indicating the reason for failure. + */ +StStatus ST_RadioInit(RadioPowerMode initialRadioPowerMode); + +/** @brief + * Turns on the radio. The last radio configuration is used. + */ +void ST_RadioWake(void); + +/** @brief + * This function turns off the radio. + * Any transmit or receive packets in progress are aborted. + * The library may or may not call ST_RadioTransmitCompleteIsrCallback() for an + * aborted transmit packet. + * ST_RadioWake() must not be called within 250us of having called + * ST_RadioSleep(). + */ +void ST_RadioSleep(void); + +//@}//END Radio power state control APIs + + +//--------------------------------------------------------------------------- +/** @name + * Channel APIs + * + * @brief + * These APIs control channel selection and calibration. + */ +//@{ + +/** @brief + * Configures the radio to communicate on a 802.15.4 channel. + * If ST_RadioInit() has not been called yet, the channel number is recorded + * but no calibration takes place. The specified channel will be configured + * when ST_RadioInit() is eventually called. + * If the radio is asleep this function will wake it to perform channel + * calibration and then return it to sleep before exiting. + * The first time a channel is selected all radio parameters will be calibrated + * for that channel. This full calibration process can take up to 200ms to + * complete. The results of some of these calibrations are stored in flash + * tokens for use the next time the same channel is selected. Subsequent calls + * to ST_RadioSetChannel() requesting the same channel will take less time + * because the stored values will be retrieved from the flash tokens and reused. + * + * @param channel the 802.15.4 channel that the radio will communicate on. + * + * @return ::ST_SUCCESS or a status code indicating the reason for failure. + */ +StStatus ST_RadioSetChannel(u8 channel); + +/** @brief + * This function gets the 802.15.4 channel that the radio is configured to use. + * + * @return the 802.15.4 channel that the radio is configured to use. + */ +u8 ST_RadioGetChannel(void); + +/** @brief + * This function is identical to ST_RadioSetChannel() except that it + * calibrates all radio parameters regardless of whether calibration is + * required. + * + * NOTE: This function does not need to be called under normal operating + * conditions. The library will reuse available stored calibration values + * and will perform necessary re-calibration automatically. Calling this + * function will cause the library to calibrate all radio parameters and + * store the results in flash, overwriting previous stored values. Use of + * this function will cause unnecessary flash wear and will take longer to + * complete than a call to ST_RadioSetChannel(). This function should only + * be called to recover from hardware-related calibration problems, which + * should only occur during hardware development. + * + * @param channel the 802.15.4 channel that the radio will communicate on. + * + * @return ::ST_SUCCESS or a status code indicating the reason for failure. + */ +StStatus ST_RadioSetChannelAndForceCalibration(u8 channel); + +/** @brief + * This function checks to see if the radio needs calibrating to maintain + * expected performance as environmental conditions change. + * If this function indicates that the calibration is needed, the application + * should call ST_RadioCalibrateCurrentChannel(). + * + * NOTE: This function must not be called while a transmit is in progress. + * + * @return TRUE if calibration is needed to compensate for temperature changes, + * FALSE otherwise. + */ +boolean ST_RadioCheckRadio(void); + +/** @brief + * This function performs necessary recalibration to counteract the effects of + * temperature changes since the last calibration. It should be called by the + * application when ST_RadioCheckRadio() indicates that calibration is needed. + */ +void ST_RadioCalibrateCurrentChannel(void); + +//@}//END Channel APIs + + +//--------------------------------------------------------------------------- +/** @name + * Transmit APIs + * + * @brief + * These APIs control the transmission of packets. + */ +//@{ + +/** @brief + * This function transmits a packet using the configuration specified in + * \c radioTransmitConfig. + * + * @param *packet A pointer to the packet to be transmitted. The first byte of + * \c packet must be set to the number of payload bytes to be transmitted. + * If \c radioTransmitConfig.appendCrc is TRUE the length byte must accommodate + * the hardware-appended two-byte CRC. + * e.g. A packet with a two-byte payload would be represented in memory as: + * {0x04, 0x00, 0x01, 0xc0, 0xc1} where 0xc0 and 0xc1 are the CRC bytes. + * If \c radioTransmitConfig.checkCca is TRUE this function performs CSMA-CA + * backoff(s) and CCA check(s) before transmitting, else it starts the + * transmit process immediately. + * + * @return ::ST_SUCCESS if the transmission process is successfully started. + * In this case ST_RadioTransmitCompleteIsrCallback() will eventually be + * called to indicate the completion status. If the radio is busy transmitting, + * this function returns an error code and + * ST_RadioTransmitCompleteIsrCallback() will not be called. + */ +StStatus ST_RadioTransmit(u8* packet); + +/** @brief + * This function is called by the library once after each ST_RadioTransmit() + * call that returned successfully. If the ST_RadioTransmit() call returned + * an error ST_RadioTransmitCompleteIsrCallback() will not be called. + * + * NOTE: ST_RadioTransmit() can be called again within the context of this + * callback. + * + * @param status parameter indicates one of the following conditions: + * ::ST_SUCCESS - the last byte of the non-ACK-request packet has been + * transmitted. + * ::ST_PHY_ACK_RECEIVED - the requested ACK was received. + * ::ST_MAC_NO_ACK_RECEIVED - the requested ACK was not received in time. + * ::ST_PHY_TX_CCA_FAIL - unable to transmit due to lack of clear channel on + * all attempts. + * ::ST_PHY_TX_UNDERFLOW - DMA underflow occurred while transmitting. Should + * never happen. + * ::ST_PHY_TX_INCOMPLETE - The PLL synthesizer failed to lock while + * transmitting. Should never happen. + * + * @param sfdSentTime the value of the MAC timer captured when the SFD was sent. + * + * @param framePending TRUE if the received ACK indicates that data is + * pending for this node, FALSE otherwise. + */ +extern void ST_RadioTransmitCompleteIsrCallback(StStatus status, + u32 sfdSentTime, + boolean framePending); + +/** @brief + * This function sets the Energy Detection Clear Channel Assessment threshold. + * + * @param threshold the energy level in dBm below which the channel will be + * considered clear. + */ +void ST_RadioSetEdCcaThreshold(s8 threshold); + +/** @brief + * This function get the Energy Detection Clear Channel Assessment threshold. + * + * @return the Energy Detection Clear Channel Assessment threshold in units of + * dBm. + */ +s8 ST_RadioGetEdCcaThreshold(void); + +/** @brief This function enables or disables notification of the SFD sent event + * via the ST_RadioSfdSentIsrCallback(). + * + * @param enable TRUE if the notification is to be enabled, FALSE if the + * notification is to be disabled. + */ +void ST_RadioEnableSfdSentNotification(boolean enable); + +/** @brief + * This function indicates whether the SFD sent notification via + * \c ST_RadioSfdSentIsrCallback() is enabled or disabled. + * + * @return TRUE if the SFD sent notification is enabled, FALSE otherwise. + */ +boolean ST_RadioSfdSentNotificationEnabled(void); + +/** @brief + * This function is called by the library in response to an SFD sent event if + * this notification has been enabled by a call to + * \c ST_RadioEnableSfdSentNotification(). + * + * NOTE: This callback is called for ACKs as well as normal packets. + * + * NOTE: In cases of extreme interrupt latency it is possible that + * \c sfdSentTime may contain the SFD time of the last received packet instead + * of the time of the last transmitted packet. + * + * @param sfdSentTime the value of the MAC timer when the SFD was sent in the + * last transmitted packet. + */ +void ST_RadioSfdSentIsrCallback(u32 sfdSentTime); + +/** @brief + * This function sets the radio transmit power to a new level within the minimum + * and maximum values specified in the datasheet for the specific device. + * + * NOTE: It is possible for this function to succeed and set the power level to + * a value other than that specified in the \c power parameter. The reason for + * for this behavior is that not all integer power levels are available at lower + * power levels. When a specific power level is not available the next higher + * power level is used. + * + * @return ::ST_SUCCESS if the power level has been changed, or an error + * status code if not (e.g. if the requested value is out of range). + * + * @param power the desired power level in units of dBm. + */ +StStatus ST_RadioSetPower(s8 power); + +/** @brief + * This function gets the radio transmit power level. + * + * @return the radio transmit power level in units of dBm. + */ +s8 ST_RadioGetPower(void); + +//@}//END Transmit APIs + + +//--------------------------------------------------------------------------- +/** @name + * Receive APIs + * + * @brief + * These APIs control the reception of packets. + */ +//@{ + +/** @brief + * This function is called by the library when a packet has been received. + * + * @param *packet points to the packet data beginning with the length byte. + * The CRC bytes will have been removed from the packet. + * + * @param ackFramePendingSet TRUE if the library set the Frame Pending bit in + * the hardware-generated MAC ACK to this packet, FALSE otherwise. + * + * @param time The value of the MAC timer when the SFD was received for this + * packet. + * + * @param errors The number of correlator errors in the packet. + * + * @param rssi The energy detected over the last 8 symbols of the packet in + * units of dBm. + */ +extern void ST_RadioReceiveIsrCallback(u8 *packet, + boolean ackFramePendingSet, + u32 time, + u16 errors, + s8 rssi); + +/** @brief + * This function enables or disables address filtering on PAN ID, node ID, and + * EUI 64. + * + * NOTE: Address filtering is enabled by default. + * + * @param enable TRUE to enable address filtering, FALSE otherwise. + */ +void ST_RadioEnableAddressFiltering(boolean enable); + +/** @brief + * This function gets the address filtering status of the device. + * + * @return TRUE if address filtering is enabled, FALSE otherwise. + */ +boolean ST_RadioAddressFilteringEnabled(void); + +/** @brief + * This function enables or disables automatic transmission of ACKs in response + * to received packets which request ACKs. + * + * NOTE: Address filtering must be enabled for automatic transmission of ACKs to + * occur. + * + * NOTE: Automatic acknowledgement is enabled by default. + * + * @param enable TRUE to enable automatic acknowledgement transmission, FALSE + * otherwise. + */ +void ST_RadioEnableAutoAck(boolean enable); + +/** @brief + * This function gets the automatic acknowledgement status of the device. + * + * @return TRUE if automatic acknowledgement is enabled, FALSE otherwise. + */ +boolean ST_RadioAutoAckEnabled(void); + +/** @brief + * This function sets the short address of the node. + * + * @param nodeId the 16-bit address to use for filtering short-addressed + * packets when address filtering is enabled. + * + */ +void ST_RadioSetNodeId(u16 nodeId); + +/** @brief + * This function gets the short address of the node. + * + * @return nodeId the 16-bit address to use for filtering short-addressed + * packets. + */ +u16 ST_RadioGetNodeId(void); + +/** @brief + * This function sets the PAN id of the node. + * + * @param panId the 16-bit PAN id to use for filtering packets when address + * filtering is enabled. + */ +void ST_RadioSetPanId(u16 panId); + +/** @brief + * This function gets the PAN id of the node. + * + * @return 16-bit PAN id to use for filtering packets when address + * filtering is enabled. + */ +u16 ST_RadioGetPanId(void); + +/** @brief + * This function get the EUI 64 of the node. + * + * NOTE: The EUI 64 is set via manufacturing tokens (See the Programming and + * Serialization Specification for details). + * + * @return the memory address of the 64-bit EUI address to use for filtering + * long-addressed packets when address filtering is enabled. + */ +u8* ST_RadioGetEui64(void); + +/** @brief + * This function is called by the library after the long address fields of a + * packet have been received. The library will set the frame pending bit in the + * outgoing ACK only if the return value is TRUE. The application must lookup + * the \c eui64 in its own data structures and return TRUE if there is data + * pending, FALSE otherwise. It is critical that this function complete as + * quickly as possible to ensure the frame pending bit can be set before the ACK + * is transmitted. + * + * @return TRUE if the frame pending bit should be set in the outgoing ACK. + */ +boolean ST_RadioDataPendingLongIdIsrCallback(u8* longId); + +/** @brief + * This function is called by the library after the short address fields of a + * packet have been received. The library will set the frame pending bit in the + * outgoing ACK only if the return value is TRUE. The application must lookup + * \c shortId in its own data structures and return TRUE if there is data + * pending, FALSE otherwise. It is critical that this function complete as + * quickly as possible to ensure the frame pending bit can be set before the ACK + * is transmitted. + * + * @return TRUE if the frame pending bit should be set in the outgoing ACK. + */ +boolean ST_RadioDataPendingShortIdIsrCallback(u16 shortId); + +/** @brief + * This function sets or clears coordinator mode for this node. A + * coordinator is able to receive 802.15.4. DATA frames that have no destination + * address. A node that is not a coordinator will not receive these packets. + * + * NOTE: The source PAN id of the DATA frame with no destination address must + * still match the node PAN id in order for it to be received by the + * coordinator node. + * + * NOTE: A node is not a coordinator by default. + * + * @param coordinator TRUE to enable coordinator mode, FALSE to disable + * coordinator mode. + */ +void ST_RadioSetCoordinator(boolean coordinator); + +/** @brief + * This function gets the coordinator status of the node. + * + * @return TRUE if the node is configured as a coordinator, FALSE otherwise. + */ +boolean ST_RadioDeviceIsCoordinator(void); + +/** @brief + * This function enables or disables notification of DMA receive buffer overflow + * events via ST_RadioOverflowIsrCallback(). + * + * @param enable TRUE to enable overflow notification, FALSE otherwise. + */ +void ST_RadioEnableOverflowNotification(boolean enable); + +/** @brief + * This function indicates whether the overflow notification via + * ST_RadioOverflowIsrCallback() is enabled or disabled. + * + * @return TRUE if overflow notification is enabled, FALSE otherwise. + */ +boolean ST_RadioOverflowNotificationEnabled(void); + +/** @brief + * This function is called by the library in response to a receive overflow + * event if this notification is enabled by a call to + * ST_RadioEnableOverflowNotification(). + */ +void ST_RadioOverflowIsrCallback(void); + +/** @brief + * This function enables or disables discarding received packets that fail the + * Cyclic Redundancy Check. + * + * NOTE: When this option is enabled the library automatically strips the CRC + * bytes off of packets that pass CRC check. + * + * NOTE: Discarding packets that fail CRC is enabled by default. + * + * @param enable TRUE to enable discarding packets that fail CRC, FALSE + * otherwise. + */ +void ST_RadioEnableReceiveCrc(boolean enable); + +/** @brief + * This function gets the receive CRC configuration of the node. + * + * @return TRUE if received packets that fail CRC will be discarded, FALSE + * otherwise. + */ +boolean ST_RadioReceiveCrcEnabled(void); + +//@}//END Receive APIs + + +//--------------------------------------------------------------------------- +/** @name + * MAC Timer APIs + * + * @brief + * These APIs expose an interface to the MAC Timer. + * The MAC timer is 20-bits long with each LSB tick representing 1us. + * The MAC timer rolls over to zero approximately once every second. + * The MAC timer is free-running from the time that ST_RadioInit() is called. + */ +//@{ + +/** @brief + * This function gets an instantaneous reading of the MAC timer. + * + * @return the current value of the MAC timer. + */ +u32 ST_RadioGetMacTimer(void); + +/** @brief + * This function enables or disables comparison of the MAC timer against an + * application-supplied value and notification via + * ST_RadioMacTimerCompareIsrCallback(). + * + * @param enable TRUE to enable MAC timer comparison and notification via a + * callback. + */ +void ST_RadioEnableMacTimerCompare(boolean enable); + +/** @brief + * This function indicates whether MAC timer comparison and callback + * notification are enabled or disabled. + * + * @return TRUE if MAC timer comparison and notification are enabled, FALSE + * otherwise. + */ +boolean ST_RadioMacTimerCompareEnabled(void); + +/** @brief + * This function sets the value to compare against the MAC timer. + * + * @param value the value to compare against the MAC timer. + */ +void ST_RadioSetMacTimerCompare(u32 value); + +/** @brief + * This function gets the value to compare against the MAC timer. + * + * @return the value to compare against the MAC timer. + */ +u32 ST_RadioGetMacTimerCompare(void); + +/** @brief + * This function is called by the library in response to MAC timer comparison + * event. + */ +extern void ST_RadioMacTimerCompareIsrCallback(void); +//@}//END MAC Timer APIs + + +//--------------------------------------------------------------------------- +/** @name + * Cryptography APIs + * + * @brief + * These APIs provide an interface to the hardware AES coprocessor. + */ +//@{ + +/** @brief + * This function sets the key to use during AES encryption. + * + * @param *key pointer to 128 bits of key data. + */ +void ST_AesSetKey(u8* key); + +/** + * This function gets the key that is used during AES encryption. + * + * @param *key pointer to memory where 128 bits of key data will be written. + */ +void ST_AesGetKey(u8* key); + +/** @brief + * This function encrypts the 128 bits of plaintext data located at \c block + * using the AES coprocessor previously configured by ST_AesSetKey(). + * The resulting 128 bits of cyphertext are stored at \c block, overwriting + * the supplied plaintext. + * + * @param block pointer to memory containing the plaintext when this function is + * called and containing the cyphertext after this function has returned. + */ +void ST_AesEncrypt(u8* block); + +//@}//END Cryptography APIs + + +//--------------------------------------------------------------------------- +/** @name + * Miscellaneous APIs + * + * @brief + * These APIs control diagnostic and configuration functionality. + */ +//@{ + +/** @brief + * This function starts transmission of a carrier wave at the current channel + * center frequency. The carrier wave will be transmitted until + * ST_RadioStopTransmitTone() is called. + * + * NOTE: The radio must be idle (not transmitting) before entering this mode. + * + * NOTE: Other radio APIs must not be called while in this mode. + */ +void ST_RadioStartTransmitTone(void); + +/** @brief + * This function stops transmission of carrier wave started by + * ST_RadioStartTransmitTone(). + */ +void ST_RadioStopTransmitTone(void); + +/** @brief + * this function starts transmission of a continuous stream of modulated data. + * No packet framing is present in this transmission. Random symbols will be + * transmitted until ST_RadioStopTransmitStream() is called. + * + * NOTE: The radio must be idle (not transmitting) before entering this mode. + * + * NOTE: Other radio APIs must not be called while in this mode. + */ +void ST_RadioStartTransmitStream(void); + +/** @brief + * This function stops transmission of continuous stream of modulated data + * started by ST_RadioStartTransmitStream(). + */ +void ST_RadioStopTransmitStream(void); + +/** @brief + * This function gets a reading of the average energy detected over the previous + * eight symbol periods (128us total). + * + * @return the energy level detected in units of dBm. + */ +s8 ST_RadioEnergyDetection(void); + +/** @brief + * This function accesses radio hardware to obtain true random numbers. + * + * @param *rn pointer to memory to hold \c count random numbers. + * + * @param count the number of 16-bit random numbers to get. + */ +void ST_RadioGetRandomNumbers(u16 *rn, u8 count); + +/** @brief + * This function gets the clear or busy status of the channel. + * + * @return TRUE if channel is clear, FALSE if channel is busy. + */ +boolean ST_RadioChannelIsClear(void); + +/** @brief + * This function enables or disables Packet Trace output. + * Before being enabled, the associated IO pins must be separately + * configured to allow for the packet trace peripheral to control the pins. + * + * NOTE: Packet Trace is on by default. + * + * @param enable TRUE to enable Packet Trace, FALSE otherwise. + */ +void ST_RadioEnablePacketTrace(boolean enable); + +/** @brief + * This function indicates whether Packet Trace is enabled or not. + * + * @return TRUE if Packet Trace is enabled, FALSE otherwise. + */ +boolean ST_RadioPacketTraceEnabled(void); + +/** @brief + * This function sets the radio power mode according to the bits + * encoded in \c powerMode. + * + * NOTE: The default power mode is whatever is configured in the PHY_CONFIG + * token (normal, bi-directional mode if not explicitly set otherwise. + * + * NOTE: It is preferable to set this configuration via the PHY_CONFIG token + * rather than using this API. + * + * @param txPowerMode encodes the power mode as follows: + * bit 0 set to 0: Normal mode. + * bit 0 set to 1: Boost mode. + * bit 1 set to 0: Use bi-directional transmit path. + * bit 1 set to 1: Use alternate transmit path. + * + * @return ::ST_SUCCESS always. + */ +StStatus ST_RadioSetPowerMode(u16 txPowerMode); + +/** @brief + * This function gets the radio power mode. + * + * @return the radio power mode (boost/normal, bi-directional/alternate transmit + * path) encoded as bits in a 16-bit word (see ST_RadioSetPowerMode() + * documentation for details). + */ +u16 ST_RadioGetPowerMode(void); + +//@}//END Miscellaneous APIs diff --git a/cpu/stm32w108/slip_uart1.c b/cpu/stm32w108/slip_uart1.c new file mode 100644 index 000000000..d8ba0894a --- /dev/null +++ b/cpu/stm32w108/slip_uart1.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: slip_uart1.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Machine dependent STM32W SLIP routines for UART1. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include + + +#include "contiki.h" + +#include "dev/slip.h" +#include "dev/uart1.h" + +void +slip_arch_init(unsigned long ubr) +{ + uart1_set_input(slip_input_byte); +} + +void +slip_arch_writeb(unsigned char c) +{ + uart1_writeb(c); +} + diff --git a/cpu/stm32w108/uip_arch.c b/cpu/stm32w108/uip_arch.c new file mode 100644 index 000000000..d02c7881a --- /dev/null +++ b/cpu/stm32w108/uip_arch.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* uip_arch.c +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + + + + +#include "net/uip.h" +#include "net/uip_arch.h" + +/*-----------------------------------------------------------------------------------*/ +#if UIP_TCP +void +uip_add32(u8_t *op32, u16_t op16) +{ + uint32_t op32_align, uip_acc32_align; + + op32_align = ((uint32_t)op32[0])<<24 | ((uint32_t)op32[1])<<16 | ((uint16_t)op32[2])<<8 | op32[3]; + + uip_acc32_align = op32_align + op16; + + uip_acc32[3] = uip_acc32_align; + uip_acc32[2] = uip_acc32_align>>8; + uip_acc32[1] = uip_acc32_align>>16; + uip_acc32[0] = uip_acc32_align>>24; + +} +#endif +/*-----------------------------------------------------------------------------------*/ diff --git a/cpu/stm32w108/watchdog.c b/cpu/stm32w108/watchdog.c new file mode 100644 index 000000000..43770adc6 --- /dev/null +++ b/cpu/stm32w108/watchdog.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: watchdog.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Watchdog +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include + +#include "dev/watchdog.h" + +#include PLATFORM_HEADER +#include "hal/error.h" +#include "hal/hal.h" + + +/*---------------------------------------------------------------------------*/ +void +watchdog_init(void) +{ + +} +/*---------------------------------------------------------------------------*/ +void +watchdog_start(void) +{ + /* We setup the watchdog to reset the device after 2.048 seconds, + unless watchdog_periodic() is called. */ + halInternalEnableWatchDog(); +} +/*---------------------------------------------------------------------------*/ +void +watchdog_periodic(void) +{ + /* This function is called periodically to restart the watchdog + timer. */ + halResetWatchdog(); +} +/*---------------------------------------------------------------------------*/ +void +watchdog_stop(void) +{ + halInternalDisableWatchDog(MICRO_DISABLE_WATCH_DOG_KEY); +} +/*---------------------------------------------------------------------------*/ +void +watchdog_reboot(void) +{ + halReboot(); +} +/*---------------------------------------------------------------------------*/ diff --git a/platform/mb851/Makefile.mb851 b/platform/mb851/Makefile.mb851 new file mode 100644 index 000000000..afca59dfd --- /dev/null +++ b/platform/mb851/Makefile.mb851 @@ -0,0 +1,18 @@ +# $Id: Makefile.mb851,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + + +ARCH= irq.c sensors.c acc-sensor.c button-sensor.c temperature-sensor.c mems.c + +CONTIKI_TARGET_DIRS = . dev +ifndef CONTIKI_TARGET_MAIN +CONTIKI_TARGET_MAIN = contiki-main.c #contiki-init-net.c +endif + +ifdef UIP_CONF_IPV6 +CFLAGS += -DWITH_UIP6=1 +endif + +CONTIKI_TARGET_SOURCEFILES += $(ARCH) $(CONTIKI_TARGET_MAIN) + +MCU=STM32W108 +include $(CONTIKI)/cpu/stm32w108/Makefile.stm32w108 diff --git a/platform/mb851/apps/shell-sensors.c b/platform/mb851/apps/shell-sensors.c new file mode 100644 index 000000000..9ff6b917f --- /dev/null +++ b/platform/mb851/apps/shell-sensors.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * $Id: shell-sensors.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ + + /** + * \file + * Shell function for temp and acc sensors. + * \author + * Salvatore Pitrulli + */ + +#include +#include + +#include "contiki.h" +#include "shell.h" +#include "contiki-net.h" +#include "dev/temperature-sensor.h" +#include "dev/acc-sensor.h" + +/*---------------------------------------------------------------------------*/ +PROCESS(shell_sensors_process, "sensors"); +SHELL_COMMAND(sensors_command, + "sensors", + "sensors {temp|acc}: get sensor value", + &shell_sensors_process); +/*---------------------------------------------------------------------------*/ +PROCESS_THREAD(shell_sensors_process, ev, data) +{ + + char str_buf[22]; + + PROCESS_BEGIN(); + + if(data == NULL) { + shell_output_str(&sensors_command, + "sensors {temp|acc}: a sensor must be specified", ""); + PROCESS_EXIT(); + } + + if(strcmp(data,"temp")==0) { + + unsigned int temp = temperature_sensor.value(0); + + snprintf(str_buf,sizeof(str_buf),"%d.%d degC",temp/10,temp-(temp/10)*10); + + shell_output_str(&sensors_command, "Temp: ", str_buf); + + } + else if (strcmp(data,"acc")==0) { + + snprintf(str_buf,sizeof(str_buf),"%d,%d,%d) mg",acc_sensor.value(ACC_X_AXIS),acc_sensor.value(ACC_Y_AXIS),acc_sensor.value(ACC_Z_AXIS)); + + shell_output_str(&sensors_command, "(X,Y,Z): (", str_buf); + + } + + PROCESS_END(); +} +/*---------------------------------------------------------------------------*/ +void +shell_sensors_init(void) +{ + SENSORS_ACTIVATE(acc_sensor); + + shell_register_command(&sensors_command); +} +/*---------------------------------------------------------------------------*/ diff --git a/platform/mb851/apps/shell-sensors.h b/platform/mb851/apps/shell-sensors.h new file mode 100644 index 000000000..a61562ffa --- /dev/null +++ b/platform/mb851/apps/shell-sensors.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + * $Id: shell-sensors.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ + +/** + * \file + * Header file for Contik shell sensors command. + * \author + * Salvatore Pitrulli + */ + +#ifndef __SHELL_SENSORS_H__ +#define __SHELL_SENSORS_H__ + +#include "shell.h" + +void shell_sensors_init(void); + +#endif /* __SHELL_SENSORS_H__ */ diff --git a/platform/mb851/contiki-conf.h b/platform/mb851/contiki-conf.h new file mode 100644 index 000000000..2e12288ed --- /dev/null +++ b/platform/mb851/contiki-conf.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: contiki-conf.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* contiki-conf.h for MB851. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + + +#ifndef __CONTIKI_CONF_H__ +#define __CONTIKI_CONF_H__ + +#include PLATFORM_HEADER + +#include +#include // For memcpm(). + +#define CC_CONF_REGISTER_ARGS 0 +#define CC_CONF_FUNCTION_POINTER_ARGS 1 +#define CC_CONF_FASTCALL +#define CC_CONF_VA_ARGS 1 +#define CC_CONF_INLINE inline + +#define CCIF +#define CLIF + +typedef uint8_t u8_t; +typedef uint16_t u16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef unsigned short uip_stats_t; + + +//#define FIXED_NET_ADDRESS 1 +//#define NET_ADDR_A 0x2001 +//#define NET_ADDR_B 0xdb8 +//#define NET_ADDR_C 0xbbbb +//#define NET_ADDR_D 0xabcd + +#define UART1_CONF_TX_WITH_INTERRUPT 0 +#define WITH_SERIAL_LINE_INPUT 1 +#define ENERGEST_CONF_ON 0 +#define TELNETD_CONF_NUMLINES 6 + +#define QUEUEBUF_CONF_NUM 2 + + +#if WITH_UIP6 + +/* No radio cycling */ +#define NETSTACK_CONF_NETWORK sicslowpan_driver +#define NETSTACK_CONF_MAC nullmac_driver +#define NETSTACK_CONF_RDC sicslowmac_driver +#define NETSTACK_CONF_FRAMER framer_802154 +#define NETSTACK_CONF_RADIO stm32w_radio_driver + + +#define UIP_CONF_ROUTER 1 +#define UIP_CONF_IPV6_RPL 1 +#define UIP_CONF_ND6_SEND_RA 0 +//#define RPL_BORDER_ROUTER 0 + +/* A trick to resolve a compilation error with IAR. */ +#ifdef __ICCARM__ +#define UIP_CONF_DS6_AADDR_NBU 1 +#endif + +#define UIP_CONF_IPV6 1 +#define UIP_CONF_IPV6_QUEUE_PKT 0 // This is a very costly feature as it increases the RAM usage by approximately UIP_ND6_MAX_NEIGHBORS * UIP_LINK_MTU bytes. +#define UIP_CONF_IPV6_CHECKS 1 +#define UIP_CONF_IPV6_REASSEMBLY 0 +#define UIP_CONF_NETIF_MAX_ADDRESSES 3 +#define UIP_CONF_ND6_MAX_PREFIXES 2 +#define UIP_CONF_ND6_MAX_NEIGHBORS 2 +#define UIP_CONF_ND6_MAX_DEFROUTERS 1 +#define UIP_CONF_IP_FORWARD 0 +#define UIP_CONF_BUFFER_SIZE 200 +#define UIP_CONF_MAX_CONNECTIONS 6 +#define UIP_CONF_MAX_LISTENPORTS 6 +#define UIP_CONF_UDP_CONNS 3 + +#define SICSLOWPAN_CONF_COMPRESSION_IPV6 0 +#define SICSLOWPAN_CONF_COMPRESSION_HC1 1 +#define SICSLOWPAN_CONF_COMPRESSION_HC06 2 +#define SICSLOWPAN_CONF_COMPRESSION SICSLOWPAN_CONF_COMPRESSION_HC06 +#define SICSLOWPAN_CONF_FRAG 1 +#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS 2 +#define SICSLOWPAN_CONF_MAXAGE 2 + +#define UIP_CONF_ICMP6 0 +#endif /* WITH_UIP6 */ + +#define UIP_CONF_UDP 1 +#define UIP_CONF_TCP 1 + +#define IEEE802154_CONF_PANID 0x1234 +#define STM32W_NODE_ID 0x5678 // to be deleted +#define RF_CHANNEL 16 +#define RADIO_RXBUFS 2 // Set to a number greater than 1 to decrease packet loss probability at high rates (e.g, with fragmented packets) +#define RIMEADDR_CONF_SIZE 8 +#define UIP_CONF_LL_802154 1 +#define UIP_CONF_LLH_LEN 0 + +typedef unsigned long clock_time_t; + +#define CLOCK_CONF_SECOND 1000 + +typedef unsigned long long rtimer_clock_t; +#define RTIMER_CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0) + +/* LEDs ports MB851 */ +#define LEDS_CONF_RED 0x20 +#define LEDS_CONF_GREEN 0x40 +#define LEDS_PORT GPIO_PBOUT +// Open drain +#define LED_CONFIG() GPIO_PBCFGH |= 0x0550; \ + GPIO_PBCFGH &= 0xf55f + + +#define UIP_ARCH_ADD32 1 +#define UIP_ARCH_CHKSUM 0 + +#define UIP_CONF_BYTE_ORDER UIP_LITTLE_ENDIAN + + +#ifdef PROJECT_CONF_H +#include PROJECT_CONF_H +#endif /* PROJECT_CONF_H */ + + +#endif /* __CONTIKI_CONF_H__ */ diff --git a/platform/mb851/contiki-init-net.c b/platform/mb851/contiki-init-net.c new file mode 100644 index 000000000..f40513c88 --- /dev/null +++ b/platform/mb851/contiki-init-net.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: contiki-init-net.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Functions for net initialization. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include "contiki-net.h" + +#if UIP_CONF_IPV6 + +#define DEBUG 1 +#if DEBUG +#include +#define PRINTF(...) printf(__VA_ARGS__) +#define PRINT6ADDR(addr) PRINTF(" %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x ", ((u8_t *)addr)[0], ((u8_t *)addr)[1], ((u8_t *)addr)[2], ((u8_t *)addr)[3], ((u8_t *)addr)[4], ((u8_t *)addr)[5], ((u8_t *)addr)[6], ((u8_t *)addr)[7], ((u8_t *)addr)[8], ((u8_t *)addr)[9], ((u8_t *)addr)[10], ((u8_t *)addr)[11], ((u8_t *)addr)[12], ((u8_t *)addr)[13], ((u8_t *)addr)[14], ((u8_t *)addr)[15]) +#define PRINTLLADDR(lladdr) PRINTF(" %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x ",lladdr.u8[0], lladdr.u8[1], lladdr.u8[2], lladdr.u8[3],lladdr.u8[4], lladdr.u8[5], lladdr.u8[6], lladdr.u8[7]) +#else +#define PRINTF(...) +#define PRINT6ADDR(addr) +#define PRINTLLADDR(addr) +#endif + +void print_address(uip_ds6_addr_t *lladdr) +{ + int i; + + for(i = 0; i < 7; ++i) { + printf("%02x%02x:", lladdr->ipaddr.u8[i * 2], lladdr->ipaddr.u8[i * 2 + 1]); + } + printf("%02x%02x", lladdr->ipaddr.u8[14], lladdr->ipaddr.u8[15]); +} + +/*---------------------------------------------------------------------------*/ +void print_addresses(void) +{ + uip_ds6_addr_t *lladdr; + + + printf("link-local IPv6 address: "); + + lladdr = uip_ds6_get_link_local(-1); + if(lladdr != NULL){ + print_address(lladdr); + printf("\r\n"); + } + else + printf("None\r\n"); + + printf("global IPv6 address: "); + + lladdr = uip_ds6_get_global(-1); + if(lladdr != NULL){ + print_address(lladdr); + printf("\r\n"); + } + else + printf("None\r\n"); + +} + +#if FIXED_NET_ADDRESS + +#include "net/rpl/rpl.h" + + +void set_net_address(void) +{ + uip_ipaddr_t ipaddr; +#if RPL_BORDER_ROUTER + rpl_dag_t *dag; +#endif + + uip_ip6addr(&ipaddr, NET_ADDR_A, NET_ADDR_B, NET_ADDR_C, NET_ADDR_D, 0, 0, 0, 0); + uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr); + uip_ds6_addr_add(&ipaddr, 0, ADDR_TENTATIVE); + + +//#if !UIP_CONF_ROUTER +// uip_ds6_prefix_add(&ipaddr, 64, 0); // For on-link determination. +//#else +// uip_ds6_prefix_add(&ipaddr, 64, 0, 0, 600, 600); +//#endif + + print_addresses(); + +#if RPL_BORDER_ROUTER + dag = rpl_set_root(&ipaddr); + if(dag != NULL) { + PRINTF("This node is setted as root of a DAG.\r\n"); + } + else { + PRINTF("Error while setting this node as root of a DAG.\r\n"); + } +#endif + +} +#endif /* FIXED_GLOBAL_ADDRESS */ + + +#endif /* UIP_CONF_IPV6 */ \ No newline at end of file diff --git a/platform/mb851/contiki-init-net.h b/platform/mb851/contiki-init-net.h new file mode 100644 index 000000000..10abd828e --- /dev/null +++ b/platform/mb851/contiki-init-net.h @@ -0,0 +1,6 @@ +#ifndef __CONTIKI_INIT_NET_H__ +#define __CONTIKI_INIT_NET_H__ + +void print_address(uip_ds6_addr_t *lladdr); + +#endif /* __CONTIKI_INIT_NET_H__ */ \ No newline at end of file diff --git a/platform/mb851/contiki-main.c b/platform/mb851/contiki-main.c new file mode 100644 index 000000000..99e98a68a --- /dev/null +++ b/platform/mb851/contiki-main.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: contiki-main.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Contiki main file. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + + +#include PLATFORM_HEADER +#include "hal/error.h" +#include "hal/hal.h" +#include BOARD_HEADER +#include "micro/adc.h" + +#include + + +#include "contiki.h" + +#include "dev/watchdog.h" +#include "dev/leds.h" +#include "dev/button-sensor.h" +#include "dev/temperature-sensor.h" +#include "dev/acc-sensor.h" +#include "dev/uart1.h" +#include "dev/serial-line.h" + +#include "dev/stm32w-radio.h" +#include "net/netstack.h" +#include "net/rime/rimeaddr.h" +#include "net/rime.h" +#include "net/rime/rime-udp.h" +#include "net/uip.h" + + +#define DEBUG 1 +#if DEBUG +#include +#define PRINTF(...) printf(__VA_ARGS__) +#define PRINT6ADDR(addr) PRINTF(" %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x ", ((u8_t *)addr)[0], ((u8_t *)addr)[1], ((u8_t *)addr)[2], ((u8_t *)addr)[3], ((u8_t *)addr)[4], ((u8_t *)addr)[5], ((u8_t *)addr)[6], ((u8_t *)addr)[7], ((u8_t *)addr)[8], ((u8_t *)addr)[9], ((u8_t *)addr)[10], ((u8_t *)addr)[11], ((u8_t *)addr)[12], ((u8_t *)addr)[13], ((u8_t *)addr)[14], ((u8_t *)addr)[15]) +#define PRINTLLADDR(lladdr) PRINTF(" %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x ",lladdr.u8[0], lladdr.u8[1], lladdr.u8[2], lladdr.u8[3],lladdr.u8[4], lladdr.u8[5], lladdr.u8[6], lladdr.u8[7]) +#else +#define PRINTF(...) +#define PRINT6ADDR(addr) +#define PRINTLLADDR(addr) +#endif + + +#ifdef WITH_UIP6 +PROCINIT(&etimer_process, &tcpip_process, &sensors_process); +#else +PROCINIT(&etimer_process, &sensors_process); +#warning "No TCP/IP process!" +#endif + +SENSORS(&button_sensor,&temperature_sensor,&acc_sensor); + +/*---------------------------------------------------------------------------*/ + +int +main(void) +{ + + /* + * Initalize hardware. + */ + halInit(); + clock_init(); + + uart1_init(115200); + + // Led initialization + leds_init(); + + INTERRUPTS_ON(); + + PRINTF("\r\nStarting "); + PRINTF(CONTIKI_VERSION_STRING); + PRINTF(" on MB851\r\n"); + + /* + * Initialize Contiki and our processes. + */ + + process_init(); + + #if WITH_SERIAL_LINE_INPUT + uart1_set_input(serial_line_input_byte); + serial_line_init(); + #endif + +#ifdef WITH_UIP6 + + netstack_init(); + + { + rimeaddr_t lladdr; + + int8u *stm32w_eui64 = ST_RadioGetEui64(); + { + int8u c; + for(c = 0; c < 8; c++) { // Copy the EUI-64 to lladdr converting from Little-Endian to Big-Endian. + lladdr.u8[c] = stm32w_eui64[7 - c]; + } + } + PRINTF("\n\rRadio EUI-64:"); + PRINTLLADDR(lladdr); + PRINTF("\n\r"); + + rimeaddr_set_node_addr(&lladdr); + + memcpy(&uip_lladdr.addr, &lladdr, sizeof(uip_lladdr.addr)); + } + +#endif + + ctimer_init(); + rtimer_init(); + + procinit_init(); + + energest_init(); + ENERGEST_ON(ENERGEST_TYPE_CPU); + + autostart_start(autostart_processes); + + + watchdog_start(); + + while(1){ + + int r; + + do { + /* Reset watchdog. */ + watchdog_periodic(); + r = process_run(); + } while(r > 0); + + + + ENERGEST_OFF(ENERGEST_TYPE_CPU); + //watchdog_stop(); + ENERGEST_ON(ENERGEST_TYPE_LPM); + /* Go to idle mode. */ + halSleepWithOptions(SLEEPMODE_IDLE,0); + /* We are awake. */ + //watchdog_start(); + ENERGEST_OFF(ENERGEST_TYPE_LPM); + ENERGEST_ON(ENERGEST_TYPE_CPU); + + } + +} + + + +/*int8u errcode __attribute__(( section(".noinit") )); + +void halBaseBandIsr(){ + + errcode = 1; + leds_on(LEDS_RED); +} + +void BusFault_Handler(){ + + errcode = 2; + leds_on(LEDS_RED); +} + +void halDebugIsr(){ + + errcode = 3; + leds_on(LEDS_RED); +} + +void DebugMon_Handler(){ + + errcode = 4; + //leds_on(LEDS_RED); +} + +void HardFault_Handler(){ + + errcode = 5; + //leds_on(LEDS_RED); + //halReboot(); +} + +void MemManage_Handler(){ + + errcode = 6; + //leds_on(LEDS_RED); + //halReboot(); +} + +void UsageFault_Handler(){ + + errcode = 7; + //leds_on(LEDS_RED); + //halReboot(); +}*/ + +void Default_Handler() +{ + //errcode = 8; + leds_on(LEDS_RED); + halReboot(); +} diff --git a/platform/mb851/dev/acc-sensor.c b/platform/mb851/dev/acc-sensor.c new file mode 100644 index 000000000..e3e6221c9 --- /dev/null +++ b/platform/mb851/dev/acc-sensor.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: acc-sensor.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Accelerometer. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + + +#include "dev/acc-sensor.h" +#include "mems.h" + +void clock_wait(int i); + +#define FALSE 0 +#define TRUE 1 + +/*---------------------------------------------------------------------------*/ +static int +active(void) +{ + int8u reg; + if(!i2c_read_reg (kLIS3L02DQ_SLAVE_ADDR,CTRL_REG1, ®, 1)) + return FALSE; + + return (reg & 0x40) ? TRUE : FALSE ; +} +/*---------------------------------------------------------------------------*/ +static int +value(int type) +{ + + int8s i2c_data = 0; + int8u reg_addr; + + switch(type) { + case ACC_X_AXIS: + reg_addr = OUTX_H; + break; + + case ACC_Y_AXIS: + reg_addr = OUTY_H; + break; + + case ACC_Z_AXIS: + reg_addr = OUTZ_H; + break; + + default: + return 0; + } + + i2c_read_reg(kLIS3L02DQ_SLAVE_ADDR, reg_addr, (int8u *)&i2c_data, 1); + + if(MEMS_GetFullScale()==ACC_HIGH_RANGE){ + return ((int16s)i2c_data)*HIGH_RANGE_SENSITIVITY; + } + else { + return ((int16s)i2c_data)*LOW_RANGE_SENSITIVITY; + } + +} +/*---------------------------------------------------------------------------*/ +static int +configure(int type, int value) +{ + switch(type) { + + case SENSORS_HW_INIT: + return Mems_Init(); + + case SENSORS_ACTIVE: + if(value){ + if(MEMS_On()){ + clock_wait(8); + return 1; + } + return 0; + } + else + return MEMS_Off(); + + case ACC_RANGE: + return MEMS_SetFullScale((boolean)value); + + case ACC_HPF: + if(value < ACC_HPF_DISABLE){ + return i2c_write_reg(kLIS3L02DQ_SLAVE_ADDR, CTRL_REG2, (1<<4) | (int8u)value); + } + else { + return i2c_write_reg(kLIS3L02DQ_SLAVE_ADDR, CTRL_REG2, 0x00); + } + } + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +status(int type) +{ + switch(type) { + + case SENSORS_READY: + return active(); + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(acc_sensor, ACC_SENSOR, + value, configure, status); + + + + diff --git a/platform/mb851/dev/acc-sensor.h b/platform/mb851/dev/acc-sensor.h new file mode 100644 index 000000000..9092db742 --- /dev/null +++ b/platform/mb851/dev/acc-sensor.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: acc-sensor.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Accelerometer header file. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#ifndef __ACC_SENSOR_H__ +#define __ACC_SENSOR_H__ + +#include "lib/sensors.h" +#include "mems.h" + +extern const struct sensors_sensor acc_sensor; + +#define ACC_SENSOR "Acc" + +/* The type values used in the configure() function. +*/ + +/* Full-scale*/ +#define ACC_RANGE 1 // type + +#define ACC_LOW_RANGE MEMS_LOW_RANGE // Values +#define ACC_HIGH_RANGE MEMS_HIGH_RANGE + +/* High pass filter and cut-off frequencies*/ +#define ACC_HPF 2 // type + +#define ACC_HPF_DISABLE 4 // Values +#define ACC_1HZ 3 +#define ACC_2HZ 2 +#define ACC_4HZ 1 +#define ACC_8HZ 0 + +/* The type values used in the value() function. + * The returned value is expressed in mg units and can be negative. +*/ +#define ACC_X_AXIS 1 +#define ACC_Y_AXIS 2 +#define ACC_Z_AXIS 3 + +#endif /* __ACC_SENSOR_H__ */ diff --git a/platform/mb851/dev/button-sensor.c b/platform/mb851/dev/button-sensor.c new file mode 100644 index 000000000..cd4d8d05a --- /dev/null +++ b/platform/mb851/dev/button-sensor.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: button-sensor.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Button sensor. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include "dev/button-sensor.h" +#include "hal/micro/micro-common.h" +#include "hal/micro/cortexm3/micro-common.h" + +#include BOARD_HEADER + +#define DEBOUNCE 1 + +/** + * @brief Point the proper IRQ at the desired pin for BUTTON0. + */ +#define BUTTON_S1_SEL() do { GPIO_IRQCSEL = BUTTON_S1; } while(0) +/** + * @brief The interrupt service routine for BUTTON_S1. + */ +#define BUTTON_S1_ISR halIrqCIsr +/** + * @brief The interrupt configuration register for BUTTON_S1. + */ +#define BUTTON_S1_INTCFG GPIO_INTCFGC +/** + * @brief The interrupt bit for BUTTON_S1. + */ +#define BUTTON_S1_INT_EN_BIT INT_IRQC +/** + * @brief The interrupt bit for BUTTON_S1. + */ +#define BUTTON_S1_FLAG_BIT INT_IRQCFLAG +/** + * @brief The missed interrupt bit for BUTTON_S1. + */ +#define BUTTON_S1_MISS_BIT INT_MISSIRQC + +#if DEBOUNCE +static struct timer debouncetimer; +#endif + +#define FALSE 0 +#define TRUE 1 + +/*---------------------------------------------------------------------------*/ +static void +init(void) +{ + #if DEBOUNCE + timer_set(&debouncetimer, 0); + #endif + + //Input, pulled up or down (selected by GPIO_PxOUT: 0 = pull-down, 1 = pull-up). + halGpioConfig(BUTTON_S1,GPIOCFG_IN_PUD); + BUTTON_S1_OUTPUT_GPIO |= GPIOOUT_PULLUP << BUTTON_S1_GPIO_PIN; + + + BUTTON_S1_SEL(); + BUTTON_S1_INTCFG = 0x40; // Falling edge triggered. +} +/*---------------------------------------------------------------------------*/ +static void +activate(void) +{ + INT_CFGSET = BUTTON_S1_INT_EN_BIT; +} +/*---------------------------------------------------------------------------*/ +static void +deactivate(void) +{ + INT_CFGCLR = BUTTON_S1_INT_EN_BIT; +} +/*---------------------------------------------------------------------------*/ +static int +active(void) +{ + return (INT_CFGSET & BUTTON_S1_INT_EN_BIT) ? TRUE : FALSE ; +} +/*---------------------------------------------------------------------------*/ +static int +value(int type) +{ +#if DEBOUNCE + return (BUTTON_S1_INPUT_GPIO & (1< 1) + addr += REPETIR; + + SC2_TWICTRL1 |= SC_TWISTART; // send start + WAIT_CMD_FIN(); + + SEND_BYTE(slave_addr | 0x00); // send the address low byte + WAIT_TX_FIN(); + + SEND_BYTE(addr); + WAIT_TX_FIN(); + + SC2_TWICTRL1 |= SC_TWISTART; // send start + WAIT_CMD_FIN(); + + SEND_BYTE(slave_addr | 0x01); // send the address low byte + WAIT_TX_FIN(); + + // loop receiving the data + for (i=0;ioutx_h = i2c_buffer[0]; +// mems_data->outx_l = i2c_buffer[1]; +// mems_data->outy_h = i2c_buffer[2]; +// mems_data->outy_l = i2c_buffer[3]; +// mems_data->outz_h = i2c_buffer[4]; +// mems_data->outz_l = i2c_buffer[5]; +// +// return i; +//}/* end I2C_MEMS_Read() */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/platform/mb851/dev/mems.h b/platform/mb851/dev/mems.h new file mode 100644 index 000000000..45fa920fc --- /dev/null +++ b/platform/mb851/dev/mems.h @@ -0,0 +1,59 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : mems.h +* Author : MCD Application Team +* Version : V1.0 +* Date : January 2010 +* Description : header file for mems driver +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef _MEMS_H_ +#define _MEMS_H_ + +/* Define --------------------------------------------------------------------*/ +#include "mems_regs.h" + +/* Define --------------------------------------------------------------------*/ +// Sensitivity values in mg/digit +#define HIGH_RANGE_SENSITIVITY 72 +#define LOW_RANGE_SENSITIVITY 18 + +#define MEMS_LOW_RANGE 0 +#define MEMS_HIGH_RANGE 1 + +/* Typedef -------------------------------------------------------------------*/ +/* Mems data type: three acceleration values each related to a specific direction + Watch out: only lower data values (e.g. those terminated by the _l) are + currently used by the device */ + +typedef struct { + int8s outx_l; + int8s outx_h; + int8s outy_l; + int8s outy_h; + int8s outz_l; + int8s outz_h; +} t_mems_data; + +/* Functions -----------------------------------------------------------------*/ + +/* Mems Initialization function */ +int8u Mems_Init(void); + +int8u MEMS_On(void); +int8u MEMS_Off(void); +int8u MEMS_SetFullScale(boolean range); +boolean MEMS_GetFullScale(void); + +/* Get mems acceleration values */ +int8u Mems_GetValue(t_mems_data *mems_data); + +#endif /* _MEMS_H_ */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/platform/mb851/dev/mems_regs.h b/platform/mb851/dev/mems_regs.h new file mode 100644 index 000000000..9796339a4 --- /dev/null +++ b/platform/mb851/dev/mems_regs.h @@ -0,0 +1,139 @@ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : mems_regs.h +* Author : MCD Application Team +* Version : V1.0 +* Date : January 2010 +* Description : stm32w108 mems registers +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef _MEMS_REGS_H_ +#define _MEMS_REGS_H_ + +/* Private include ------------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ + +//---Size of MEMs data--- +#define MEMS_DATA_SIZE 6 + +//---address of slave I want to communicate with--- +#define kLIS3L02DQ_SLAVE_ADDR 0x38 + +//----------------------------------------------------------------------------- +//---accelerometer register addresses--- +#define OFFSET_X 0x16 +#define OFFSET_Y 0x17 +#define OFFSET_Z 0x18 +#define GAIN_X 0x19 +#define GAIN_Y 0x1A +#define GAIN_Z 0x1B +#define CTRL_REG1 0x20 +#define CTRL_REG2 0x21 +#define STATUS_REG 0x27 +#define OUTX_L 0x28 +#define OUTX_H 0x29 +#define OUTY_L 0x2A +#define OUTY_H 0x2B +#define OUTZ_L 0x2C +#define OUTZ_H 0x2D +#define FF_WU_CFG 0x30 +#define FF_WU_SRC 0x31 +#define FF_WU_ACK 0x32 +#define FF_WU_THS_L 0x34 +#define FF_WU_THS_H 0x35 +#define FF_WU_DURATION 0x36 +#define DD_CFG 0x38 +#define DD_SRC 0x39 +#define DD_ACK 0x3A +#define DD_THSI_L 0x3C +#define DD_THSI_H 0x3D +#define DD_THSE_L 0x3E +#define DD_THSE_H 0x3F + +// Communication control settings +// I2C +#define REPETIR 0x80 +// SPI +#define MEMS_SPI_WRITE 0x00 +#define MEMS_SPI_READ 0x80 +#define MEMS_SPI_MULTIPLE_BYTES 0x40 + +//----------------------------------------------------------------------------- +//---Settings for CTRL_REG1--- + +// Power Down Control (PD) +#define LIS_PD_OFF 0x00 +#define LIS_PD_ON 0x40 + +// Decimation Factor Control (DF) +#define LIS_DF_BY128 0x00 +#define LIS_DF_BY64 0x10 +#define LIS_DF_BY32 0x20 +#define LIS_DF_BY8 0x30 + +// Self Test +#define LIS_ST_NORMAL 0x00 +#define LIS_ST_TEST 0x08 + +// Enable Axis +#define LIS_EA_ALL 0x07 + +//----------------------------------------------------------------------------- +//---Settings for CTRL_REG2--- + +// Full Scale (FS) +#define LIS_FS_2G 0x00 +#define LIS_FS_6G 0x80 + +// Block Data Update (BDU) +#define LIS_BDU_CONTINUOUS 0x00 +#define LIS_BDU_WAIT 0x40 + +// Big/Little Endian Selection (BLE) +#define LIS_BLE_LE 0x00 +#define LIS_BLE_BE 0x20 + +// Data Alignment Selection DAS +#define LIS_DAS_12BIT 0x00 +#define LIS_DAS_16BIT 0x01 + +// Interrupt Enable +#define LIS_INTR_DISABLE 0x00 +#define LIS_INTR_ENABLE 0x08 + +// Data Ready Enable +#define LIS_DRDY_DISABLE 0x00 +#define LIS_DRDY_ENABLE 0x04 + +//----------------------------------------------------------------------------- + +#define LIS_BLE_XX LIS_BLE_BE + + +/* Private Functions Prototypes ----------------------------------------------*/ + +//*********************i2c_read_reg***********************// +//----------Reads a register on the I2C target------------// +//------slave addr is the is the I2C target device--------// +//-reg_addr is the address of the register to be written--// +//-pBuffer is the storage destination for the read data---// +//-NoOfBytes is the amount of data to read----------------// +int8u i2c_read_reg (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOfBytes); + +//*********************i2c_write_reg**********************// +//----------Writes a register on the I2C target-----------// +//------slave addr is the is the I2C target device--------// +//-reg_addr is the address of the register to be written--// +//-reg_value is the value of the register to be written---// +int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); + +#endif /* _MEMS_REGS_H_ */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/platform/mb851/dev/temperature-sensor.c b/platform/mb851/dev/temperature-sensor.c new file mode 100644 index 000000000..f0ebc57e1 --- /dev/null +++ b/platform/mb851/dev/temperature-sensor.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: temperature-sensor.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Temperature sensor. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +/** + * NOTE: + * For the temperature measurement, the ADC extended range mode is needed; + * but this is inaccurate due to the high voltage mode bug of the general purpose ADC + * (see STM32W108 errata). + */ + + +#include PLATFORM_HEADER +#include BOARD_HEADER +#include "hal/error.h" +#include "hal/hal.h" +#include "micro/adc.h" + +#include "dev/temperature-sensor.h" + + +/*---------------------------------------------------------------------------*/ +static void +init(void) +{ + halGpioConfig(TEMPERATURE_SENSOR_GPIO,GPIOCFG_ANALOG); + halInternalInitAdc(); + halAdcSetRange(TRUE); +} +/*---------------------------------------------------------------------------*/ +static int +value(int type) +{ + static int16u ADCvalue; + static int16s volts; + + halStartAdcConversion(ADC_USER_APP, ADC_REF_INT, ADC_SOURCE_ADC2_VREF2, ADC_CONVERSION_TIME_US_4096); + + halReadAdcBlocking(ADC_USER_APP, &ADCvalue); // This blocks for a while, about 4ms. + + // 100 uVolts + volts = halConvertValueToVolts(ADCvalue); + + //return ((18641 - (int32s)volts)*100)/1171; // +- 0.23 degC in the range (-10;65) degC + return ((18663 - (int32s)volts)*100)/1169; // +- 0.004 degC in the range (20;30) degC + +} +/*---------------------------------------------------------------------------*/ +static int +configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + return 1; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +status(int type) +{ + switch(type) { + + case SENSORS_READY: + return 1; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, + value, configure, status); diff --git a/platform/mb851/dev/temperature-sensor.h b/platform/mb851/dev/temperature-sensor.h new file mode 100644 index 000000000..ba0402b9a --- /dev/null +++ b/platform/mb851/dev/temperature-sensor.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: temperature-sensor.h,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Temperature sensor. +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +/* + * Value returned by temperature_sensor.value() is expressed in units of 0.1 °C. + */ +/** + * NOTE: + * For the temperature measurement, the ADC extended range mode is needed; + * but this is inaccurate due to the high voltage mode bug of the general purpose ADC + * (see STM32W108 errata). + */ + +#ifndef __TEMPERATURE_SENSOR_H__ +#define __TEMPERATURE_SENSOR_H__ + +#include "lib/sensors.h" + +extern const struct sensors_sensor temperature_sensor; + +#define TEMPERATURE_SENSOR "Temperature" + +#endif /* __TEMPERATURE_SENSOR_H__ */