adapted to the new spi and cc2420 naming - and split config file
This commit is contained in:
joxe
parent
705f8cc451
commit
857883558b
5 changed files with 215 additions and 126 deletions
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@ -14,6 +14,10 @@ CONTIKI_TARGET_SOURCEFILES += $(SENSOR_BOARD_SOURCEFILES)
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CONTIKIAVR=$(CONTIKI)/cpu/avr
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CONTIKIBOARD=.
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ifdef UIP_CONF_IPV6
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CFLAGS += -DWITH_UIP6=1
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endif
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# MicaZ runs on Clock rate 7.3728 MHz
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CONTIKI_PLAT_DEFS = -DF_CPU=7372800UL -DAUTO_CRC_PADDING=2
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@ -45,37 +45,15 @@
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#define NETSTACK_CONF_NETWORK rime_driver
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#define NETSTACK_CONF_MAC csma_driver
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#define NETSTACK_CONF_RDC cxmac_driver
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#define NETSTACK_CONF_RADIO cc2420_driver
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#define MAC_CONF_CHANNEL_CHECK_RATE 8
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#define RF_CHANNEL 26
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#define HAVE_STDINT_H
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#include "avrdef.h"
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/*
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* MCU and clock rate.
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* MICAZ runs on 7.3728 MHz clock.
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*/
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#define MCU_MHZ 7
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#define PLATFORM PLATFORM_AVR
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/* Clock ticks per second */
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#define CLOCK_CONF_SECOND 128
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/* COM port to be used for SLIP connection */
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#define SLIP_PORT RS232_PORT_0
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/* Pre-allocated memory for loadable modules heap space (in bytes)*/
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#define MMEM_CONF_SIZE 256
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/* Use the following address for code received via the codeprop
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* facility
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*/
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#define EEPROMFS_ADDR_CODEPROP 0x8000
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#define EEPROM_NODE_ID_START 0x00
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#include "platform-conf.h"
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#define TIMESYNCH_CONF_ENABLED 1
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#define CC2420_CONF_TIMESTAMPS 1
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@ -133,90 +111,6 @@
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#define UIP_CONF_TCP_SPLIT 0
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/* LEDs ports. */
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#define LEDS_PxDIR DDRA // port direction register
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#define LEDS_PxOUT PORTA // port register
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#define LEDS_CONF_RED 0x04 //red led
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#define LEDS_CONF_GREEN 0x02 // green led
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#define LEDS_CONF_YELLOW 0x01 // yellow led
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/*
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* SPI bus configuration for the MicaZ.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF SPDR
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#define SPI_RXBUF SPDR
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#define BV(bitno) _BV(bitno)
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#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
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#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
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#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define FIFO_P 6 /* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */
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#define FIFO 7 /* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */
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#define CCA 6 /* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */
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#define SFD 4 /* - Input: SFD from CC2420 - ATMEGA128 PORTD, PIN4 */
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#define CSN 0 /* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */
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#define VREG_EN 5 /* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */
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#define RESET_N 6 /* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */
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/* Pin status. */
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#define FIFO_IS_1 (!!(PINB & BV(FIFO)))
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#define CCA_IS_1 (!!(PIND & BV(CCA) ))
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#define RESET_IS_1 (!!(PINA & BV(RESET_N)))
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#define VREG_IS_1 (!!(PINA & BV(VREG_EN)))
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#define FIFOP_IS_1 (!!(PINE & BV(FIFO_P)))
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#define SFD_IS_1 (!!(PIND & BV(SFD)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() ( PORTA |= BV(RESET_N) )
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#define SET_RESET_ACTIVE() ( PORTA &= ~BV(RESET_N) )
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() ( PORTA |= BV(VREG_EN) )
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#define SET_VREG_INACTIVE() ( PORTA &= ~BV(VREG_EN) )
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/* CC2420 rising edge trigger for external interrupt 6 (FIFOP).
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* Enable the external interrupt request for INT6.
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* See Atmega128 datasheet about EICRB Register
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*/
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#define FIFOP_INT_INIT() do {\
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EICRB |= 0x30; \
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CLEAR_FIFOP_INT(); \
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} while (0)
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/* FIFOP on external interrupt 6. */
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#define ENABLE_FIFOP_INT() do { EIMSK |= 0x40; } while (0)
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#define DISABLE_FIFOP_INT() do { EIMSK &= ~0x40; } while (0)
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#define CLEAR_FIFOP_INT() do { EIFR = 0x40; } while (0)
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/* Enables/disables CC2420 access to the SPI bus (not the bus).
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*
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* These guys should really be renamed but are compatible with the
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* original Chipcon naming.
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*
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* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
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* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
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*/
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#define SPI_ENABLE() ( PORTB &= ~BV(CSN) ) /* ENABLE CSn (active low) */
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#define SPI_DISABLE() ( PORTB |= BV(CSN) ) /* DISABLE CSn (active low) */
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typedef unsigned short clock_time_t;
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typedef unsigned short uip_stats_t;
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typedef unsigned long off_t;
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@ -44,24 +44,24 @@
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void
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cc2420_arch_init(void)
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{
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SFIOR |= BV(PUD); /* Beware, disable all pull-ups. */
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SFIOR |= BV(PUD); /* Beware, disable all pull-ups. */
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spi_init();
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DDRA |= BV(RESET_N);
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DDRA |= BV(VREG_EN);
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DDRB &= ~BV(FIFO);
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DDRD &= ~BV(CCA);
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DDRD &= ~BV(SFD);
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DDRE &= ~BV(FIFO_P);
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DDRA |= BV(CC2420_RESET_PIN);
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DDRA |= BV(CC2420_VREG_PIN);
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DDRB &= ~BV(CC2420_FIFO_PIN);
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DDRD &= ~BV(CC2420_CCA_PIN);
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DDRD &= ~BV(CC2420_SFD_PIN);
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DDRE &= ~BV(CC2420_FIFOP_PIN);
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PORTA |= BV(RESET_N);
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PORTB |= BV(CSN);
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PORTA |= BV(CC2420_RESET_PIN);
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PORTB |= BV(CC2420_CSN_PIN);
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SPI_DISABLE(); /* Unselect radio. */
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CC2420_SPI_DISABLE(); /* Unselect radio. */
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}
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ISR(INT6_vect)
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ISR(CC2420_IRQ_VECTOR)
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{
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/* TODO : wakeup from sleep mode */
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cc2420_interrupt();
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@ -48,10 +48,6 @@
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#include "net/rime.h"
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#include "net/netstack.h"
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#ifndef RF_CHANNEL
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#define RF_CHANNEL 26
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#endif
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void
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init_net(void)
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{
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195
platform/micaz/platform-conf.h
Normal file
195
platform/micaz/platform-conf.h
Normal file
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@ -0,0 +1,195 @@
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/*
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* Copyright (c) 2010, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: platform-conf.h,v 1.1 2010/06/23 10:25:54 joxe Exp $
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*/
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/**
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* \file
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* A brief description of what this file is
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* \author
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* Niclas Finne <nfi@sics.se>
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* Joakim Eriksson <joakime@sics.se>
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*/
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#ifndef __PLATFORM_CONF_H__
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#define __PLATFORM_CONF_H__
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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#define PLATFORM PLATFORM_AVR
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/*
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* MCU and clock rate.
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* MICAZ runs on 7.3728 MHz clock.
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*/
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#define MCU_MHZ 7
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/* Clock ticks per second */
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#define CLOCK_CONF_SECOND 128
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/* LED ports */
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#define LEDS_PxDIR DDRA // port direction register
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#define LEDS_PxOUT PORTA // port register
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#define LEDS_CONF_RED 0x04 //red led
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#define LEDS_CONF_GREEN 0x02 // green led
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#define LEDS_CONF_YELLOW 0x01 // yellow led
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/* COM port to be used for SLIP connection */
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#define SLIP_PORT RS232_PORT_0
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/* Pre-allocated memory for loadable modules heap space (in bytes)*/
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#define MMEM_CONF_SIZE 256
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/* Use the following address for code received via the codeprop
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* facility
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*/
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#define EEPROMFS_ADDR_CODEPROP 0x8000
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#define EEPROM_NODE_ID_START 0x00
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#define NETSTACK_CONF_RADIO cc2420_driver
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/*
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* SPI bus configuration for the TMote Sky.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF SPDR
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#define SPI_RXBUF SPDR
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#define BV(bitno) _BV(bitno)
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#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
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#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
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#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
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/*
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* SPI bus - M25P80 external flash configuration.
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*/
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#define FLASH_PWR 3 /* P4.3 Output */
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#define FLASH_CS 4 /* P4.4 Output */
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#define FLASH_HOLD 7 /* P4.7 Output */
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/* Enable/disable flash access to the SPI bus (active low). */
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#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
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#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
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#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
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#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define CC2420_CONF_SYMBOL_LOOP_COUNT 500
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define FIFO_P 6
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#define FIFO 7
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#define CCA 6
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#define SFD 4
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#define CSN 0
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#define VREG_EN 5
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#define RESET_N 6
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/* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */
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#define CC2420_FIFOP_PORT(type) P##type##E
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#define CC2420_FIFOP_PIN 6
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/* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */
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#define CC2420_FIFO_PORT(type) P##type##B
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#define CC2420_FIFO_PIN 7
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/* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */
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#define CC2420_CCA_PORT(type) P##type##D
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#define CC2420_CCA_PIN 6
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/* - Input: SFD from CC2420 - ATMEGA128 PORTD, PIN4 */
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#define CC2420_SFD_PORT(type) P##type##D
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#define CC2420_SFD_PIN 4
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/* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */
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#define CC2420_CSN_PORT(type) P##type##B
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#define CC2420_CSN_PIN 0
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/* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */
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#define CC2420_VREG_PORT(type) P##type##A
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#define CC2420_VREG_PIN 5
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/* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */
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#define CC2420_RESET_PORT(type) P##type##A
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#define CC2420_RESET_PIN 6
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#define CC2420_IRQ_VECTOR INT6_vect
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/* Pin status. */
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#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
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#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
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#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
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#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(ORT) |= BV(CC2420_RESET_PIN))
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#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(ORT) &= ~BV(CC2420_RESET_PIN))
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(ORT) |= BV(CC2420_VREG_PIN))
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#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(ORT) &= ~BV(CC2420_VREG_PIN))
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/* CC2420 rising edge trigger for external interrupt 6 (FIFOP).
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* Enable the external interrupt request for INT6.
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* See Atmega128 datasheet about EICRB Register
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*/
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#define CC2420_FIFOP_INT_INIT() do {\
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EICRB |= 0x30; \
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CC2420_CLEAR_FIFOP_INT(); \
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} while (0)
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/* FIFOP on external interrupt 6. */
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#define CC2420_ENABLE_FIFOP_INT() do { EIMSK |= 0x40; } while (0)
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#define CC2420_DISABLE_FIFOP_INT() do { EIMSK &= ~0x40; } while (0)
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#define CC2420_CLEAR_FIFOP_INT() do { EIFR = 0x40; } while (0)
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/*
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* Enables/disables CC2420 access to the SPI bus (not the bus).
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* (Chip Select)
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*/
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#define CC2420_SPI_ENABLE() (PORTB &= ~BV(CSN)) /* ENABLE CSn (active low) */
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#define CC2420_SPI_DISABLE() (PORTB |= BV(CSN)) /* DISABLE CSn (active low) */
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#endif /* __PLATFORM_CONF_H__ */
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