diff --git a/platform/micaz/Makefile.micaz b/platform/micaz/Makefile.micaz index 093ba3ce9..8c83f528e 100755 --- a/platform/micaz/Makefile.micaz +++ b/platform/micaz/Makefile.micaz @@ -6,7 +6,7 @@ SENSOR_BOARD_SOURCEFILES = mts300.c CONTIKI_TARGET_SOURCEFILES += adc.c rs232.c cfs-eeprom.c contiki-micaz-main.c \ leds-arch.c cc2420.c init-net-rime.c node-id.c \ - clock.c spi.c cc2420-arch.c rtimer-arch.c ds2401.c \ + clock.c spi.c cc2420-arch.c rtimer-arch.c ds2401.c \ battery-sensor.c CONTIKI_TARGET_SOURCEFILES += $(SENSOR_BOARD_SOURCEFILES) @@ -14,6 +14,10 @@ CONTIKI_TARGET_SOURCEFILES += $(SENSOR_BOARD_SOURCEFILES) CONTIKIAVR=$(CONTIKI)/cpu/avr CONTIKIBOARD=. +ifdef UIP_CONF_IPV6 +CFLAGS += -DWITH_UIP6=1 +endif + # MicaZ runs on Clock rate 7.3728 MHz CONTIKI_PLAT_DEFS = -DF_CPU=7372800UL -DAUTO_CRC_PADDING=2 diff --git a/platform/micaz/contiki-conf.h b/platform/micaz/contiki-conf.h index 74c2b4b4d..9226c3ad9 100644 --- a/platform/micaz/contiki-conf.h +++ b/platform/micaz/contiki-conf.h @@ -45,37 +45,15 @@ #define NETSTACK_CONF_NETWORK rime_driver #define NETSTACK_CONF_MAC csma_driver #define NETSTACK_CONF_RDC cxmac_driver -#define NETSTACK_CONF_RADIO cc2420_driver #define MAC_CONF_CHANNEL_CHECK_RATE 8 +#define RF_CHANNEL 26 + #define HAVE_STDINT_H #include "avrdef.h" - -/* - * MCU and clock rate. - * MICAZ runs on 7.3728 MHz clock. - */ -#define MCU_MHZ 7 - -#define PLATFORM PLATFORM_AVR - -/* Clock ticks per second */ -#define CLOCK_CONF_SECOND 128 - -/* COM port to be used for SLIP connection */ -#define SLIP_PORT RS232_PORT_0 - -/* Pre-allocated memory for loadable modules heap space (in bytes)*/ -#define MMEM_CONF_SIZE 256 - -/* Use the following address for code received via the codeprop - * facility - */ -#define EEPROMFS_ADDR_CODEPROP 0x8000 - -#define EEPROM_NODE_ID_START 0x00 +#include "platform-conf.h" #define TIMESYNCH_CONF_ENABLED 1 #define CC2420_CONF_TIMESTAMPS 1 @@ -133,90 +111,6 @@ #define UIP_CONF_TCP_SPLIT 0 - - - -/* LEDs ports. */ -#define LEDS_PxDIR DDRA // port direction register -#define LEDS_PxOUT PORTA // port register -#define LEDS_CONF_RED 0x04 //red led -#define LEDS_CONF_GREEN 0x02 // green led -#define LEDS_CONF_YELLOW 0x01 // yellow led - - -/* - * SPI bus configuration for the MicaZ. - */ - -/* SPI input/output registers. */ -#define SPI_TXBUF SPDR -#define SPI_RXBUF SPDR - -#define BV(bitno) _BV(bitno) - -#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0) -#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0) - -#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */ -#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */ -#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */ - -/* - * SPI bus - CC2420 pin configuration. - */ - -#define FIFO_P 6 /* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */ -#define FIFO 7 /* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */ -#define CCA 6 /* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */ - -#define SFD 4 /* - Input: SFD from CC2420 - ATMEGA128 PORTD, PIN4 */ -#define CSN 0 /* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */ -#define VREG_EN 5 /* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */ -#define RESET_N 6 /* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */ - -/* Pin status. */ - -#define FIFO_IS_1 (!!(PINB & BV(FIFO))) -#define CCA_IS_1 (!!(PIND & BV(CCA) )) -#define RESET_IS_1 (!!(PINA & BV(RESET_N))) -#define VREG_IS_1 (!!(PINA & BV(VREG_EN))) -#define FIFOP_IS_1 (!!(PINE & BV(FIFO_P))) -#define SFD_IS_1 (!!(PIND & BV(SFD))) - -/* The CC2420 reset pin. */ -#define SET_RESET_INACTIVE() ( PORTA |= BV(RESET_N) ) -#define SET_RESET_ACTIVE() ( PORTA &= ~BV(RESET_N) ) - -/* CC2420 voltage regulator enable pin. */ -#define SET_VREG_ACTIVE() ( PORTA |= BV(VREG_EN) ) -#define SET_VREG_INACTIVE() ( PORTA &= ~BV(VREG_EN) ) - -/* CC2420 rising edge trigger for external interrupt 6 (FIFOP). - * Enable the external interrupt request for INT6. - * See Atmega128 datasheet about EICRB Register - */ -#define FIFOP_INT_INIT() do {\ - EICRB |= 0x30; \ - CLEAR_FIFOP_INT(); \ -} while (0) - -/* FIFOP on external interrupt 6. */ -#define ENABLE_FIFOP_INT() do { EIMSK |= 0x40; } while (0) -#define DISABLE_FIFOP_INT() do { EIMSK &= ~0x40; } while (0) -#define CLEAR_FIFOP_INT() do { EIFR = 0x40; } while (0) - -/* Enables/disables CC2420 access to the SPI bus (not the bus). - * - * These guys should really be renamed but are compatible with the - * original Chipcon naming. - * - * SPI_CC2420_ENABLE/SPI_CC2420_DISABLE??? - * CC2420_ENABLE_SPI/CC2420_DISABLE_SPI??? - */ - -#define SPI_ENABLE() ( PORTB &= ~BV(CSN) ) /* ENABLE CSn (active low) */ -#define SPI_DISABLE() ( PORTB |= BV(CSN) ) /* DISABLE CSn (active low) */ - typedef unsigned short clock_time_t; typedef unsigned short uip_stats_t; typedef unsigned long off_t; diff --git a/platform/micaz/dev/cc2420-arch.c b/platform/micaz/dev/cc2420-arch.c index 285fe08ed..7b8ae9be5 100644 --- a/platform/micaz/dev/cc2420-arch.c +++ b/platform/micaz/dev/cc2420-arch.c @@ -44,24 +44,24 @@ void cc2420_arch_init(void) { - SFIOR |= BV(PUD); /* Beware, disable all pull-ups. */ + SFIOR |= BV(PUD); /* Beware, disable all pull-ups. */ spi_init(); - DDRA |= BV(RESET_N); - DDRA |= BV(VREG_EN); - DDRB &= ~BV(FIFO); - DDRD &= ~BV(CCA); - DDRD &= ~BV(SFD); - DDRE &= ~BV(FIFO_P); + DDRA |= BV(CC2420_RESET_PIN); + DDRA |= BV(CC2420_VREG_PIN); + DDRB &= ~BV(CC2420_FIFO_PIN); + DDRD &= ~BV(CC2420_CCA_PIN); + DDRD &= ~BV(CC2420_SFD_PIN); + DDRE &= ~BV(CC2420_FIFOP_PIN); - PORTA |= BV(RESET_N); - PORTB |= BV(CSN); - - SPI_DISABLE(); /* Unselect radio. */ + PORTA |= BV(CC2420_RESET_PIN); + PORTB |= BV(CC2420_CSN_PIN); + + CC2420_SPI_DISABLE(); /* Unselect radio. */ } -ISR(INT6_vect) +ISR(CC2420_IRQ_VECTOR) { /* TODO : wakeup from sleep mode */ cc2420_interrupt(); diff --git a/platform/micaz/init-net-rime.c b/platform/micaz/init-net-rime.c index 567cb8d41..c020820a2 100644 --- a/platform/micaz/init-net-rime.c +++ b/platform/micaz/init-net-rime.c @@ -48,10 +48,6 @@ #include "net/rime.h" #include "net/netstack.h" -#ifndef RF_CHANNEL -#define RF_CHANNEL 26 -#endif - void init_net(void) { diff --git a/platform/micaz/platform-conf.h b/platform/micaz/platform-conf.h new file mode 100644 index 000000000..a2521131d --- /dev/null +++ b/platform/micaz/platform-conf.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2010, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: platform-conf.h,v 1.1 2010/06/23 10:25:54 joxe Exp $ + */ + +/** + * \file + * A brief description of what this file is + * \author + * Niclas Finne + * Joakim Eriksson + */ + +#ifndef __PLATFORM_CONF_H__ +#define __PLATFORM_CONF_H__ + +/* + * Definitions below are dictated by the hardware and not really + * changeable! + */ +#define PLATFORM PLATFORM_AVR + +/* + * MCU and clock rate. + * MICAZ runs on 7.3728 MHz clock. + */ +#define MCU_MHZ 7 + +/* Clock ticks per second */ +#define CLOCK_CONF_SECOND 128 + + +/* LED ports */ +#define LEDS_PxDIR DDRA // port direction register +#define LEDS_PxOUT PORTA // port register +#define LEDS_CONF_RED 0x04 //red led +#define LEDS_CONF_GREEN 0x02 // green led +#define LEDS_CONF_YELLOW 0x01 // yellow led + +/* COM port to be used for SLIP connection */ +#define SLIP_PORT RS232_PORT_0 + +/* Pre-allocated memory for loadable modules heap space (in bytes)*/ +#define MMEM_CONF_SIZE 256 + +/* Use the following address for code received via the codeprop + * facility + */ +#define EEPROMFS_ADDR_CODEPROP 0x8000 + +#define EEPROM_NODE_ID_START 0x00 + + +#define NETSTACK_CONF_RADIO cc2420_driver + + +/* + * SPI bus configuration for the TMote Sky. + */ + +/* SPI input/output registers. */ +#define SPI_TXBUF SPDR +#define SPI_RXBUF SPDR + +#define BV(bitno) _BV(bitno) + +#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0) +#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0) + +#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */ +#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */ +#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */ + +/* + * SPI bus - M25P80 external flash configuration. + */ + +#define FLASH_PWR 3 /* P4.3 Output */ +#define FLASH_CS 4 /* P4.4 Output */ +#define FLASH_HOLD 7 /* P4.7 Output */ + +/* Enable/disable flash access to the SPI bus (active low). */ + +#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) ) +#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) ) + +#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) ) +#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) ) + +/* + * SPI bus - CC2420 pin configuration. + */ + +#define CC2420_CONF_SYMBOL_LOOP_COUNT 500 + +/* + * SPI bus - CC2420 pin configuration. + */ + +#define FIFO_P 6 +#define FIFO 7 +#define CCA 6 + +#define SFD 4 +#define CSN 0 +#define VREG_EN 5 +#define RESET_N 6 + + +/* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */ +#define CC2420_FIFOP_PORT(type) P##type##E +#define CC2420_FIFOP_PIN 6 +/* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */ +#define CC2420_FIFO_PORT(type) P##type##B +#define CC2420_FIFO_PIN 7 +/* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */ +#define CC2420_CCA_PORT(type) P##type##D +#define CC2420_CCA_PIN 6 +/* - Input: SFD from CC2420 - ATMEGA128 PORTD, PIN4 */ +#define CC2420_SFD_PORT(type) P##type##D +#define CC2420_SFD_PIN 4 +/* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */ +#define CC2420_CSN_PORT(type) P##type##B +#define CC2420_CSN_PIN 0 +/* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */ +#define CC2420_VREG_PORT(type) P##type##A +#define CC2420_VREG_PIN 5 +/* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */ +#define CC2420_RESET_PORT(type) P##type##A +#define CC2420_RESET_PIN 6 + +#define CC2420_IRQ_VECTOR INT6_vect + +/* Pin status. */ +#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN))) +#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN))) +#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN))) +#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN))) + +/* The CC2420 reset pin. */ +#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(ORT) |= BV(CC2420_RESET_PIN)) +#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(ORT) &= ~BV(CC2420_RESET_PIN)) + +/* CC2420 voltage regulator enable pin. */ +#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(ORT) |= BV(CC2420_VREG_PIN)) +#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(ORT) &= ~BV(CC2420_VREG_PIN)) + +/* CC2420 rising edge trigger for external interrupt 6 (FIFOP). + * Enable the external interrupt request for INT6. + * See Atmega128 datasheet about EICRB Register + */ +#define CC2420_FIFOP_INT_INIT() do {\ + EICRB |= 0x30; \ + CC2420_CLEAR_FIFOP_INT(); \ +} while (0) + +/* FIFOP on external interrupt 6. */ +#define CC2420_ENABLE_FIFOP_INT() do { EIMSK |= 0x40; } while (0) +#define CC2420_DISABLE_FIFOP_INT() do { EIMSK &= ~0x40; } while (0) +#define CC2420_CLEAR_FIFOP_INT() do { EIFR = 0x40; } while (0) + +/* + * Enables/disables CC2420 access to the SPI bus (not the bus). + * (Chip Select) + */ +#define CC2420_SPI_ENABLE() (PORTB &= ~BV(CSN)) /* ENABLE CSn (active low) */ +#define CC2420_SPI_DISABLE() (PORTB |= BV(CSN)) /* DISABLE CSn (active low) */ + +#endif /* __PLATFORM_CONF_H__ */