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x86: Add support for PCI BAR1

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This patch adds support for PCI BAR1 and also changes
the pci_init(), instead of having one function for each `bar`
we now set the `bar` to pci_config_addr_t parameter before calling
the pci_init() function..
This commit is contained in:
Ricardo de Almeida Gonzaga 2015-09-10 11:26:00 -03:00 committed by Jesus Sanchez-Palencia
parent 6dc27579bc
commit 60f6edef80
4 changed files with 7 additions and 10 deletions
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7
cpu/x86/drivers/legacy_pc/pci.c
View file

@ -234,12 +234,9 @@ pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy)
* \param meta Base address of optional driver-defined metadata. * \param meta Base address of optional driver-defined metadata.
*/ */
void void
pci_init_bar0(pci_driver_t *c_this, pci_init(pci_driver_t *c_this, pci_config_addr_t pci_addr, uintptr_t meta)
pci_config_addr_t pci_addr,
uintptr_t meta)
{ {
pci_addr.reg_off = PCI_CONFIG_REG_BAR0; /* The reg_off (BAR) value is masked to clear non-address bits. */
/* The BAR0 value is masked to clear non-address bits. */
c_this->mmio = pci_config_read(pci_addr) & ~0xFFF; c_this->mmio = pci_config_read(pci_addr) & ~0xFFF;
c_this->meta = meta; c_this->meta = meta;
} }

7
cpu/x86/drivers/legacy_pc/pci.h
View file

@ -34,8 +34,9 @@
#include <stdint.h> #include <stdint.h>
#include "helpers.h" #include "helpers.h"
/** PCI configuration register identifier for Base Address Register 0 (BAR0) */ /** PCI configuration register identifier for Base Address Registers */
#define PCI_CONFIG_REG_BAR0 0x10 #define PCI_CONFIG_REG_BAR0 0x10
#define PCI_CONFIG_REG_BAR1 0x14
/** PCI Interrupt Routing is mapped using Interrupt Queue Agents */ /** PCI Interrupt Routing is mapped using Interrupt Queue Agents */
typedef enum { typedef enum {
@ -106,9 +107,7 @@ typedef struct pci_driver {
uintptr_t meta; /**< Driver-defined metadata base address */ uintptr_t meta; /**< Driver-defined metadata base address */
} pci_driver_t; } pci_driver_t;
void pci_init_bar0(pci_driver_t *c_this, void pci_init(pci_driver_t *c_this, pci_config_addr_t pci_addr, uintptr_t meta);
pci_config_addr_t pci_addr,
uintptr_t meta);
int pci_irq_agent_set_pirq(IRQAGENT agent, INTR_PIN pin, PIRQ pirq); int pci_irq_agent_set_pirq(IRQAGENT agent, INTR_PIN pin, PIRQ pirq);
void pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy); void pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy);

2
cpu/x86/drivers/legacy_pc/uart-16x50.c
View file

@ -79,7 +79,7 @@ uart_16x50_init(uart_16x50_driver_t *c_this,
/* This assumes that the UART had an MMIO range assigned to it by the /* This assumes that the UART had an MMIO range assigned to it by the
* firmware during boot. * firmware during boot.
*/ */
pci_init_bar0(c_this, pci_addr, 0); pci_init(c_this, pci_addr, 0);
uart_16x50_regs_t *regs = (uart_16x50_regs_t *)c_this->mmio; uart_16x50_regs_t *regs = (uart_16x50_regs_t *)c_this->mmio;

1
cpu/x86/drivers/quarkX1000/uart.c
View file

@ -57,6 +57,7 @@ quarkX1000_uart_init(quarkX1000_uart_dev_t dev)
/* PCI addresses from section 18.4 of Intel Quark SoC X1000 Datasheet. */ /* PCI addresses from section 18.4 of Intel Quark SoC X1000 Datasheet. */
pci_addr.dev = 20; pci_addr.dev = 20;
pci_addr.func = (dev == QUARK_X1000_UART_0) ? 1 : 5; pci_addr.func = (dev == QUARK_X1000_UART_0) ? 1 : 5;
pci_addr.reg_off = PCI_CONFIG_REG_BAR0;
uart_16x50_init((dev == QUARK_X1000_UART_0) ? &quarkX1000_uart0 : &quarkX1000_uart1, pci_addr, QUARK_X1000_UART_DL_115200); uart_16x50_init((dev == QUARK_X1000_UART_0) ? &quarkX1000_uart0 : &quarkX1000_uart1, pci_addr, QUARK_X1000_UART_DL_115200);
} }