From 60f6edef804f22fa79724dcc2bcc2f3431a56395 Mon Sep 17 00:00:00 2001
From: Ricardo de Almeida Gonzaga <ricardo.gonzaga@intel.com>
Date: Thu, 10 Sep 2015 11:26:00 -0300
Subject: [PATCH] x86: Add support for PCI BAR1

This patch adds support for PCI BAR1 and also changes
the pci_init(), instead of having one function for each `bar`
we now set the `bar` to pci_config_addr_t parameter before calling
the pci_init() function..
---
 cpu/x86/drivers/legacy_pc/pci.c        | 7 ++-----
 cpu/x86/drivers/legacy_pc/pci.h        | 7 +++----
 cpu/x86/drivers/legacy_pc/uart-16x50.c | 2 +-
 cpu/x86/drivers/quarkX1000/uart.c      | 1 +
 4 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/cpu/x86/drivers/legacy_pc/pci.c b/cpu/x86/drivers/legacy_pc/pci.c
index 922a3db4b..2af9f4883 100644
--- a/cpu/x86/drivers/legacy_pc/pci.c
+++ b/cpu/x86/drivers/legacy_pc/pci.c
@@ -234,12 +234,9 @@ pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy)
  * \param meta     Base address of optional driver-defined metadata.
  */
 void
-pci_init_bar0(pci_driver_t *c_this,
-              pci_config_addr_t pci_addr,
-              uintptr_t meta)
+pci_init(pci_driver_t *c_this, pci_config_addr_t pci_addr, uintptr_t meta)
 {
-  pci_addr.reg_off = PCI_CONFIG_REG_BAR0;
-  /* The BAR0 value is masked to clear non-address bits. */
+  /* The reg_off (BAR) value is masked to clear non-address bits. */
   c_this->mmio = pci_config_read(pci_addr) & ~0xFFF;
   c_this->meta = meta;
 }
diff --git a/cpu/x86/drivers/legacy_pc/pci.h b/cpu/x86/drivers/legacy_pc/pci.h
index 180d0a074..c938f9c6c 100644
--- a/cpu/x86/drivers/legacy_pc/pci.h
+++ b/cpu/x86/drivers/legacy_pc/pci.h
@@ -34,8 +34,9 @@
 #include <stdint.h>
 #include "helpers.h"
 
-/** PCI configuration register identifier for Base Address Register 0 (BAR0) */
+/** PCI configuration register identifier for Base Address Registers */
 #define PCI_CONFIG_REG_BAR0 0x10
+#define PCI_CONFIG_REG_BAR1 0x14
 
 /** PCI Interrupt Routing is mapped using Interrupt Queue Agents */
 typedef enum {
@@ -106,9 +107,7 @@ typedef struct pci_driver {
   uintptr_t meta; /**< Driver-defined metadata base address */
 } pci_driver_t;
 
-void pci_init_bar0(pci_driver_t *c_this,
-                   pci_config_addr_t pci_addr,
-                   uintptr_t meta);
+void pci_init(pci_driver_t *c_this, pci_config_addr_t pci_addr, uintptr_t meta);
 int pci_irq_agent_set_pirq(IRQAGENT agent, INTR_PIN pin, PIRQ pirq);
 void pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy);
 
diff --git a/cpu/x86/drivers/legacy_pc/uart-16x50.c b/cpu/x86/drivers/legacy_pc/uart-16x50.c
index 1b9bab10b..296719faa 100644
--- a/cpu/x86/drivers/legacy_pc/uart-16x50.c
+++ b/cpu/x86/drivers/legacy_pc/uart-16x50.c
@@ -79,7 +79,7 @@ uart_16x50_init(uart_16x50_driver_t *c_this,
   /* This assumes that the UART had an MMIO range assigned to it by the
    * firmware during boot.
    */
-  pci_init_bar0(c_this, pci_addr, 0);
+  pci_init(c_this, pci_addr, 0);
 
   uart_16x50_regs_t *regs = (uart_16x50_regs_t *)c_this->mmio;
 
diff --git a/cpu/x86/drivers/quarkX1000/uart.c b/cpu/x86/drivers/quarkX1000/uart.c
index ba56992c9..23731ba93 100644
--- a/cpu/x86/drivers/quarkX1000/uart.c
+++ b/cpu/x86/drivers/quarkX1000/uart.c
@@ -57,6 +57,7 @@ quarkX1000_uart_init(quarkX1000_uart_dev_t dev)
   /* PCI addresses from section 18.4 of Intel Quark SoC X1000 Datasheet. */
   pci_addr.dev = 20;
   pci_addr.func = (dev == QUARK_X1000_UART_0) ? 1 : 5;
+  pci_addr.reg_off = PCI_CONFIG_REG_BAR0;
 
   uart_16x50_init((dev == QUARK_X1000_UART_0) ? &quarkX1000_uart0 : &quarkX1000_uart1, pci_addr, QUARK_X1000_UART_DL_115200);
 }