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Merge pull request #1816 from bthebaudeau/cm-cc2538-mt

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Cortex-M and CC2538 multi-threading
This commit is contained in:
Benoît Thébaudeau 2016-11-24 23:28:05 +01:00 committed by GitHub
parent 86dbd590db 9c47f874c4
commit 52a8dcc65b
67 changed files with 11378 additions and 5968 deletions
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10
core/sys/mt.c
View file

@ -68,14 +68,13 @@ mt_start(struct mt_thread *thread, void (* function)(void *), void *data)
stack with the correct parameters. */ stack with the correct parameters. */
mtarch_start(&thread->thread, function, data); mtarch_start(&thread->thread, function, data);
thread->state = MT_STATE_READY; thread->state = MT_STATE_STARTED;
} }
/*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/
void void
mt_exec(struct mt_thread *thread) mt_exec(struct mt_thread *thread)
{ {
if(thread->state == MT_STATE_READY) { if(thread->state == MT_STATE_STARTED) {
thread->state = MT_STATE_RUNNING;
current = thread; current = thread;
/* Switch context to the thread. The function call will not return /* Switch context to the thread. The function call will not return
until the the thread has yielded, or is preempted. */ until the the thread has yielded, or is preempted. */
@ -87,21 +86,18 @@ void
mt_yield(void) mt_yield(void)
{ {
mtarch_pstop(); mtarch_pstop();
current->state = MT_STATE_READY;
current = NULL;
/* This function is called from the running thread, and we call the /* This function is called from the running thread, and we call the
switch function in order to switch the thread to the main Contiki switch function in order to switch the thread to the main Contiki
program instead. For us, the switch function will not return program instead. For us, the switch function will not return
until the next time we are scheduled to run. */ until the next time we are scheduled to run. */
mtarch_yield(); mtarch_yield();
} }
/*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/
void void
mt_exit(void) mt_exit(void)
{ {
mtarch_pstop();
current->state = MT_STATE_EXITED; current->state = MT_STATE_EXITED;
current = NULL;
mtarch_yield(); mtarch_yield();
} }
/*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/

14
core/sys/mt.h
View file

@ -84,9 +84,8 @@
#include "contiki.h" #include "contiki.h"
#define MT_STATE_READY 1 #define MT_STATE_STARTED 1
#define MT_STATE_RUNNING 2 #define MT_STATE_EXITED 2
#define MT_STATE_EXITED 5
/** /**
* An opaque structure that is used for holding the state of a thread. * An opaque structure that is used for holding the state of a thread.
@ -183,18 +182,9 @@ void mtarch_pstop(void);
struct mt_thread { struct mt_thread {
int state; int state;
process_event_t *evptr;
process_data_t *dataptr;
struct mtarch_thread thread; struct mtarch_thread thread;
}; };
/**
* No error.
*
* \hideinitializer
*/
#define MT_OK 1
/** /**
* Initializes the multithreading library. * Initializes the multithreading library.
* *

16
cpu/arm/arm.txt
View file

@ -1,19 +1,19 @@
/** /**
* @defgroup cmsis CMSIS (Cortex Microcontroller Software Interface Standard) * \defgroup cmsis CMSIS (Cortex Microcontroller Software Interface Standard)
* @ingroup arm * \ingroup arm
*/ */
/** /**
* @defgroup aducrf101 ADUCRF101 * \defgroup aducrf101 ADUCRF101
* @ingroup arm * \ingroup arm
*/ */
/** /**
* @defgroup at91sam7s AT91SAM7S * \defgroup at91sam7s AT91SAM7S
* @ingroup arm * \ingroup arm
*/ */
/** /**
* @defgroup stm32f103 STM32F103 * \defgroup stm32f103 STM32F103
* @ingroup arm * \ingroup arm
*/ */

734
cpu/arm/common/CMSIS/cmsis_armcc.h Normal file
View file

@ -0,0 +1,734 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

1800
cpu/arm/common/CMSIS/cmsis_armcc_V6.h Normal file
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cpu/arm/common/CMSIS/cmsis_gcc.h Normal file
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49
cpu/arm/common/CMSIS/core.txt
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@ -1,50 +1,59 @@
/** /**
* @addtogroup CMSIS_Core_FunctionInterface * \addtogroup CMSIS_Core_FunctionInterface
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @addtogroup CMSIS_core_register * \addtogroup CMSIS_core_register
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @addtogroup CMSIS_glob_defs * \addtogroup CMSIS_glob_defs
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @addtogroup CMSIS_MISRA_Exceptions * \addtogroup CMSIS_MISRA_Exceptions
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @addtogroup CMSIS_core_definitions * \addtogroup CMSIS_core_definitions
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @addtogroup CMSIS_SIMD_intrinsics * \addtogroup CMSIS_SIMD_intrinsics
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @addtogroup CMSIS_Core_InstructionInterface * \addtogroup CMSIS_Core_InstructionInterface
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @defgroup Cortex_M0 Cortex-M0 * \defgroup Cortex_M0 Cortex-M0
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @defgroup Cortex_M3 Cortex-M3 * \defgroup Cortex-M0+ Cortex-M0+
* @ingroup cmsis * \ingroup cmsis
*/ */
/** /**
* @defgroup Cortex_M4 Cortex-M4 * \defgroup Cortex_M3 Cortex-M3
* @ingroup cmsis * \ingroup cmsis
*/ */
/**
* \defgroup Cortex_M4 Cortex-M4
* \ingroup cmsis
*/
/**
* \defgroup Cortex_M7 Cortex-M7
* \ingroup cmsis
*/

511
cpu/arm/common/CMSIS/core_cm0.h
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@ -1,13 +1,10 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm0.h * @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.30 * @version V4.30
* @date 06. May 2014 * @date 20. October 2015
*
* @note
*
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
@ -37,16 +34,21 @@
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CM0_H_GENERIC #ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions /**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules: CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br> \li Required Rule 8.5, object/function definition in header file.<br>
@ -63,17 +65,18 @@
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
/** \ingroup Cortex_M0 /**
\ingroup Cortex_M0
@{ @{
*/ */
/* CMSIS CM0 definitions */ /* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
@ -81,6 +84,11 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
@ -100,36 +108,44 @@
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) /* Cosmic */ #elif defined ( __CSMC__ )
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/ */
#define __FPU_USED 0 #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
#if defined __ARMVFP__ #if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____ #if defined __TI_VFP_SUPPORT__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined ( __TASKING__ )
@ -137,15 +153,19 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) /* Cosmic */ #elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400) // FPU present for parser #if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include <stdint.h> /* standard types definitions */ #include "core_cmInstr.h" /* Core Instruction Access */
#include <core_cmInstr.h> /* Core Instruction Access */ #include "core_cmFunc.h" /* Core Function Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */ #endif /* __CORE_CM0_H_GENERIC */
@ -154,20 +174,24 @@
#ifndef __CORE_CM0_H_DEPENDANT #ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV #ifndef __CM0_REV
#define __CM0_REV 0x0000 #define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!" #warning "__CM0_REV not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2 #define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0 #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
@ -188,6 +212,11 @@
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */ /*@} end of group Cortex_M0 */
@ -200,30 +229,26 @@
- Core SCB Register - Core SCB Register
- Core SysTick Register - Core SysTick Register
******************************************************************************/ ******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions /**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices. \brief Type definitions and defines for Cortex-M processor based devices.
*/ */
/** \ingroup CMSIS_core_register /**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers \defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions. \brief Core Register type definitions.
@{ @{
*/ */
/** \brief Union type to access the Application Program Status Register (APSR). /**
\brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union
{ {
struct struct
{ {
#if (__CORTEX_M != 0x04) uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@ -232,8 +257,22 @@ typedef union
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
/** \brief Union type to access the Interrupt Program Status Register (IPSR). #define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union
{ {
@ -245,24 +284,22 @@ typedef union
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union
{ {
struct struct
{ {
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@ -271,215 +308,271 @@ typedef union
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
/** \brief Union type to access the Control Registers (CONTROL). #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union
{ {
struct struct
{ {
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register /**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers \brief Type definitions for the NVIC Registers
@{ @{
*/ */
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct
{ {
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31]; uint32_t RESERVED0[31U];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31]; uint32_t RSERVED1[31U];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31]; uint32_t RESERVED2[31U];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31]; uint32_t RESERVED3[31U];
uint32_t RESERVED4[64]; uint32_t RESERVED4[64U];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type; } NVIC_Type;
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register /**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers \brief Type definitions for the System Control Block Registers
@{ @{
*/ */
/** \brief Structure type to access the System Control Block (SCB). /**
\brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct
{ {
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0; uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1; uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type; } SCB_Type;
/* SCB CPUID Register Definitions */ /* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */ /* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */ /* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */ /* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */ /* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */ /* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register /**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers. \brief Type definitions for the System Timer Registers.
@{ @{
*/ */
/** \brief Structure type to access the System Timer (SysTick). /**
\brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct
{ {
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type; } SysTick_Type;
/* SysTick Control / Status Register Definitions */ /* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */ /* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */ /* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */ /* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register /**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
are only accessible over DAP and not via processor. Therefore Therefore they are not covered by the Cortex-M0 header file.
they are not covered by the Cortex-M0 header file.
@{ @{
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register /**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures. \brief Definitions for base addresses, unions, and structures.
@{ @{
@ -507,13 +600,15 @@ typedef struct
- Core SysTick Functions - Core SysTick Functions
- Core Register Access Functions - Core Register Access Functions
******************************************************************************/ ******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference /**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface /**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC. \brief Functions that manage interrupts and exceptions via the NVIC.
@{ @{
@ -521,128 +616,142 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */ /* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt /**
\brief Get External Interrupt Enable State
\details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
\return 0 Interrupt is disabled.
\return 1 Interrupt is enabled.
*/
__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
The function enables a device-specific interrupt in the NVIC interrupt controller.
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
} }
/** \brief Disable External Interrupt /**
\brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
} }
/** \brief Get Pending Interrupt /**
\brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
for the specified interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** \brief Set Pending Interrupt /**
\brief Set Pending Interrupt
The function sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
} }
/** \brief Clear Pending Interrupt /**
\brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
} }
/** \brief Set Interrupt Priority /**
\brief Set Interrupt Priority
The function sets the priority of an interrupt. \details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt. \note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if(IRQn < 0) { if ((int32_t)(IRQn) < 0)
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | {
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
else { (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | }
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
} }
/** \brief Get Interrupt Priority /**
\brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt \details Reads the priority of an interrupt.
number can be positive to specify an external (device specific) The interrupt number can be positive to specify an external (device specific) interrupt,
interrupt, or negative to specify an internal (core) interrupt. or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented \return Interrupt Priority.
priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{ {
if(IRQn < 0) { if ((int32_t)(IRQn) < 0)
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ {
else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ }
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
} }
/** \brief System Reset /**
\brief System Reset
The function initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk); SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
for(;;) /* wait until reset */
{
__NOP();
}
} }
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
@ -650,40 +759,40 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface /**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System. \brief Functions that configure the System.
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0) #if (__Vendor_SysTickConfig == 0U)
/** \brief System Tick Configuration /**
\brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer. \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts. Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts. \param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded. \return 0 Function succeeded.
\return 1 Function failed. \return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{ {
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = ticks - 1; /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */ return (0UL); /* Function successful */
} }
#endif #endif
@ -693,10 +802,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
#endif /* __CORE_CM0_H_DEPENDANT */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */ #endif /* __CMSIS_GENERIC */

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cpu/arm/common/CMSIS/core_cm0plus.h
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cpu/arm/common/CMSIS/core_cm4.h
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cpu/arm/common/CMSIS/core_cm4_simd.h
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@ -1,697 +0,0 @@
/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.30
* @date 17. February 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/* not yet supported */
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM4_SIMD_H */

2525
cpu/arm/common/CMSIS/core_cm7.h Normal file
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602
cpu/arm/common/CMSIS/core_cmFunc.h
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@ -1,13 +1,10 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cmFunc.h * @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File * @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.30 * @version V4.30
* @date 17. February 2014 * @date 20. October 2015
*
* @note
*
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
@ -35,6 +32,12 @@
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H #ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H #define __CORE_CMFUNC_H
@ -45,589 +48,36 @@
@{ @{
*/ */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
/* ARM armcc specific functions */ #if defined ( __CC_ARM )
#include "cmsis_armcc.h"
#if (__ARMCC_VERSION < 400677) /*------------------ ARM Compiler V6 -------------------*/
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#endif #include "cmsis_armcc_V6.h"
/* intrinsic void __enable_irq(); */ /*------------------ GNU Compiler ----------------------*/
/* intrinsic void __disable_irq(); */ #elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/** \brief Get Control Register /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ #elif defined ( __TMS470__ )
/* TI CCS specific functions */
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ #elif defined ( __TASKING__ )
/* TASKING carm specific functions */
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ #elif defined ( __CSMC__ )
/* Cosmic specific functions */
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif

652
cpu/arm/common/CMSIS/core_cmInstr.h
View file

@ -1,13 +1,10 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cmInstr.h * @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File * @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.30 * @version V4.30
* @date 17. February 2014 * @date 20. October 2015
*
* @note
*
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
@ -35,6 +32,12 @@
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H #ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H #define __CORE_CMINSTR_H
@ -45,639 +48,36 @@
@{ @{
*/ */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
/* ARM armcc specific functions */ #if defined ( __CC_ARM )
#include "cmsis_armcc.h"
#if (__ARMCC_VERSION < 400677) /*------------------ ARM Compiler V6 -------------------*/
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#endif #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/** \brief No Operation /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return ((uint8_t) result); /* Add explicit type cast here */
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ #elif defined ( __TMS470__ )
/* TI CCS specific functions */
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ #elif defined ( __TASKING__ )
/* TASKING carm specific functions */
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ #elif defined ( __CSMC__ )
/* Cosmic specific functions */
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/*
* Copyright (c) 2016, Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup arm-cm-mtarch
* @{
*
* \file
* Implmentation of the ARM Cortex-M support for Contiki multi-threading.
*/
#include CMSIS_DEV_HDR
#include "sys/mt.h"
#include <stdint.h>
#define EXC_RETURN_PROCESS_THREAD_BASIC_FRAME 0xfffffffd
/* Check whether EXC_RETURN[3:0] in LR indicates a preempted process thread. */
#if __ARM_ARCH == 7
#define PREEMPTED_PROCESS_THREAD() \
"and r0, lr, #0xf\n\t" \
"cmp r0, #0xd\n\t"
#elif __ARM_ARCH == 6
#define PREEMPTED_PROCESS_THREAD() \
"mov r0, lr\n\t" \
"movs r1, #0xf\n\t" \
"and r0, r1\n\t" \
"cmp r0, #0xd\n\t"
#else
#error Unsupported ARM architecture
#endif
/*----------------------------------------------------------------------------*/
/**
* \brief SVCall system handler
*
* This exception handler executes the action requested by the corresponding
* \c svc instruction, which is a task switch from the main Contiki thread to an
* mt thread or the other way around.
*/
__attribute__ ((__naked__))
void
svcall_handler(void)
{
/* This is a controlled system handler, so do not use ENERGEST_TYPE_IRQ. */
/*
* Decide whether to switch to the main thread or to a process thread,
* depending on the type of the thread preempted by SVCall.
*/
__asm__ (PREEMPTED_PROCESS_THREAD()
#if __ARM_ARCH == 7
"it eq\n\t"
#endif
"beq switch_to_main_thread\n\t"
/*
* - Retrieve from the main stack the PSP passed to SVCall through R0. Note
* that it cannot be retrieved directly from R0 on exception entry because
* this register may have been overwritten by other exceptions on SVCall
* entry.
* - Save the main thread context to the main stack.
* - Restore the process thread context from the process stack.
* - Return to Thread mode, resuming the process thread.
*/
#if __ARM_ARCH == 7
"ldr r0, [sp]\n\t"
"push {r4-r11, lr}\n\t"
"add r1, r0, #9 * 4\n\t"
"msr psp, r1\n\t"
"ldmia r0, {r4-r11, pc}");
#elif __ARM_ARCH == 6
"mov r0, r8\n\t"
"mov r1, r9\n\t"
"mov r2, r10\n\t"
"mov r3, r11\n\t"
"push {r0-r7, lr}\n\t"
"ldr r0, [sp, #9 * 4]\n\t"
"ldmia r0!, {r4-r7}\n\t"
"mov r8, r4\n\t"
"mov r9, r5\n\t"
"mov r10, r6\n\t"
"mov r11, r7\n\t"
"ldmia r0!, {r3-r7}\n\t"
"msr psp, r0\n\t"
"bx r3");
#endif
}
/*----------------------------------------------------------------------------*/
/**
* \brief PendSV system handler
*
* This exception handler executes following a call to mtarch_pstart() from
* another exception handler. It performs a task switch to the main Contiki
* thread if it is not already running.
*/
__attribute__ ((__naked__))
void
pendsv_handler(void)
{
/* This is a controlled system handler, so do not use ENERGEST_TYPE_IRQ. */
/*
* Return without doing anything if PendSV has not preempted a process thread.
* This can occur either because PendSV has preempted the main thread, in
* which case there is nothing to do, or because mtarch_pstart() has been
* called from an exception handler without having called mt_init() first, in
* which case PendSV may have preempted an exception handler and nothing must
* be done because mt is not active.
*/
__asm__ ( PREEMPTED_PROCESS_THREAD()
#if __ARM_ARCH == 7
"it ne\n\t"
"bxne lr\n"
#elif __ARM_ARCH == 6
"beq switch_to_main_thread\n\t"
"bx lr\n"
#endif
/*
* - Save the process thread context to the process stack.
* - Place into the main stack the updated PSP that SVCall must return through
* R0.
* - Restore the main thread context from the main stack.
* - Return to Thread mode, resuming the main thread.
*/
"switch_to_main_thread:\n\t"
"mrs r0, psp\n\t"
#if __ARM_ARCH == 7
"stmdb r0!, {r4-r11, lr}\n\t"
"str r0, [sp, #9 * 4]\n\t"
"pop {r4-r11, pc}");
#elif __ARM_ARCH == 6
"mov r3, lr\n\t"
"sub r0, #5 * 4\n\t"
"stmia r0!, {r3-r7}\n\t"
"mov r4, r8\n\t"
"mov r5, r9\n\t"
"sub r0, #9 * 4\n\t"
"mov r6, r10\n\t"
"mov r7, r11\n\t"
"stmia r0!, {r4-r7}\n\t"
"pop {r4-r7}\n\t"
"sub r0, #4 * 4\n\t"
"mov r8, r4\n\t"
"mov r9, r5\n\t"
"str r0, [sp, #5 * 4]\n\t"
"mov r10, r6\n\t"
"mov r11, r7\n\t"
"pop {r4-r7, pc}");
#endif
}
/*----------------------------------------------------------------------------*/
void
mtarch_init(void)
{
SCB->CCR = (SCB->CCR
#ifdef SCB_CCR_NONBASETHRDENA_Msk
/*
* Make sure that any attempt to enter Thread mode with exceptions
* active faults.
*
* Only SVCall and PendSV are allowed to forcibly enter Thread
* mode, and they are configured with the same, lowest exception
* priority, so no other exceptions may be active.
*/
& ~SCB_CCR_NONBASETHRDENA_Msk
#endif
/*
* Force 8-byte stack pointer alignment on exception entry in order
* to be able to use AAPCS-conforming functions as exception
* handlers.
*/
) | SCB_CCR_STKALIGN_Msk;
/*
* Configure SVCall and PendSV with the same, lowest exception priority.
*
* This makes sure that they cannot preempt each other, and that the processor
* executes them after having handled all other exceptions. If both are
* pending at the same time, then SVCall takes precedence because of its lower
* exception number. In addition, the associated exception handlers do not
* have to check whether they are returning to Thread mode, because they
* cannot preempt any other exception.
*/
NVIC_SetPriority(SVCall_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
/*
* Force the preceding configurations to take effect before further
* operations.
*/
__DSB();
__ISB();
}
/*----------------------------------------------------------------------------*/
void
mtarch_start(struct mtarch_thread *thread,
void (*function)(void *data), void *data)
{
struct mtarch_thread_context *context = &thread->start_stack.context;
/*
* Initialize the thread context with the appropriate values to call
* function() with data and to make function() return to mt_exit() without
* having to call it explicitly.
*/
context->exc_return = EXC_RETURN_PROCESS_THREAD_BASIC_FRAME;
context->r0 = (uint32_t)data;
context->lr = (uint32_t)mt_exit;
context->pc = (uint32_t)function;
context->xpsr = xPSR_T_Msk;
thread->psp = (uint32_t)context;
}
/*----------------------------------------------------------------------------*/
void
mtarch_exec(struct mtarch_thread *thread)
{
/* Pass the PSP to SVCall, and get the updated PSP as its return value. */
register uint32_t psp __asm__ ("r0") = thread->psp;
__asm__ volatile ("svc #0"
: "+r" (psp)
:: "memory");
thread->psp = psp;
}
/*----------------------------------------------------------------------------*/
__attribute__ ((__naked__))
void
mtarch_yield(void)
{
/* Invoke SVCall. */
__asm__ ("svc #0\n\t"
"bx lr");
}
/*----------------------------------------------------------------------------*/
void
mtarch_stop(struct mtarch_thread *thread)
{
}
/*----------------------------------------------------------------------------*/
void
mtarch_pstart(void)
{
/* Trigger PendSV. */
SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
}
/*----------------------------------------------------------------------------*/
void
mtarch_pstop(void)
{
}
/*----------------------------------------------------------------------------*/
void
mtarch_remove(void)
{
}
/*----------------------------------------------------------------------------*/
/** @} */

119
cpu/arm/common/sys/mtarch.h Normal file
View file

@ -0,0 +1,119 @@
/*
* Copyright (c) 2016, Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup arm
* @{
*
* \defgroup arm-cm-mtarch ARM Cortex-M support for Contiki multi-threading
*
* All the Cortex-M devices supported by CMSIS-CORE are supported.
*
* An exception handler can decide to make the main Contiki thread preempt any
* running mt thread by calling mtarch_pstart() (e.g. to perform urgent
* operations that have been triggered by some event or that had been
* scheduled). If the running thread is already the main Contiki thread, then
* nothing happens. The corresponding task switch takes place when leaving
* Handler mode. The main Contiki thread then resumes after the call to
* mt_exec() that yielded to the preempted mt thread.
* @{
*
* \file
* Header file for the ARM Cortex-M support for Contiki multi-threading.
*/
#ifndef MTARCH_H_
#define MTARCH_H_
#include "contiki-conf.h"
#include "sys/cc.h"
#include <stdint.h>
#ifndef MTARCH_CONF_STACKSIZE
/** Thread stack size configuration, expressed as a number of 32-bit words. */
#define MTARCH_CONF_STACKSIZE 256
#endif
/** Actual stack size, with minimum size and alignment requirements enforced. */
#define MTARCH_STACKSIZE ((MAX(MTARCH_CONF_STACKSIZE, \
sizeof(struct mtarch_thread_context) / \
sizeof(uint32_t)) + 1) & ~1)
/**
* Structure of a saved thread context.
*
* <tt>xpsr..r0</tt> are managed by the processor (except in mtarch_start()),
* while the other register values are handled by the software.
*/
struct mtarch_thread_context {
#if __ARM_ARCH == 7
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
#endif
uint32_t r8;
uint32_t r9;
uint32_t r10;
uint32_t r11;
uint32_t exc_return;
#if __ARM_ARCH == 6
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
#endif
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r12;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
};
struct mtarch_thread {
uint32_t psp;
union {
struct {
uint32_t free[MTARCH_STACKSIZE -
sizeof(struct mtarch_thread_context) / sizeof(uint32_t)];
struct mtarch_thread_context context;
} start_stack;
uint32_t stack[MTARCH_STACKSIZE];
} CC_ALIGN(8);
};
#endif /* MTARCH_H_ */
/**
* @}
* @}
*/

10
cpu/cc2538/Makefile.cc2538
View file

@ -14,7 +14,7 @@ LDSCRIPT = $(OBJECTDIR)/cc2538.ld
CFLAGS += -mcpu=cortex-m3 -mthumb -mlittle-endian CFLAGS += -mcpu=cortex-m3 -mthumb -mlittle-endian
CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -ffunction-sections -fdata-sections
CFLAGS += -fshort-enums -fomit-frame-pointer -fno-strict-aliasing CFLAGS += -fshort-enums -fomit-frame-pointer -fno-strict-aliasing
CFLAGS += -Wall CFLAGS += -Wall -DCMSIS_DEV_HDR=\"cc2538_cm3.h\"
LDFLAGS += -mcpu=cortex-m3 -mthumb -nostartfiles LDFLAGS += -mcpu=cortex-m3 -mthumb -nostartfiles
LDFLAGS += -T $(LDSCRIPT) LDFLAGS += -T $(LDSCRIPT)
LDFLAGS += -Wl,--gc-sections,--sort-section=alignment LDFLAGS += -Wl,--gc-sections,--sort-section=alignment
@ -42,7 +42,7 @@ endif
CLEAN += symbols.c symbols.h *.d *.elf *.hex CLEAN += symbols.c symbols.h *.d *.elf *.hex
### CPU-dependent directories ### CPU-dependent directories
CONTIKI_CPU_DIRS = . dev usb CONTIKI_CPU_DIRS = ../arm/common/CMSIS . dev usb
### Use the existing debug I/O in cpu/arm/common ### Use the existing debug I/O in cpu/arm/common
CONTIKI_CPU_DIRS += ../arm/common/dbg-io CONTIKI_CPU_DIRS += ../arm/common/dbg-io
@ -52,7 +52,7 @@ CONTIKI_CPU_DIRS += ../cc253x/usb/common ../cc253x/usb/common/cdc-acm
### CPU-dependent source files ### CPU-dependent source files
CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c
CONTIKI_CPU_SOURCEFILES += nvic.c cpu.c sys-ctrl.c gpio.c ioc.c spi.c adc.c CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi.c adc.c
CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c
CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c
CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c
@ -79,7 +79,7 @@ CPU_STARTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(CPU_START_SOURCEFILES
CONTIKI_SOURCEFILES += $(CONTIKI_CPU_SOURCEFILES) $(DEBUG_IO_SOURCEFILES) CONTIKI_SOURCEFILES += $(CONTIKI_CPU_SOURCEFILES) $(DEBUG_IO_SOURCEFILES)
CONTIKI_SOURCEFILES += $(USB_CORE_SOURCEFILES) $(USB_ARCH_SOURCEFILES) CONTIKI_SOURCEFILES += $(USB_CORE_SOURCEFILES) $(USB_ARCH_SOURCEFILES)
MODULES += lib/newlib MODULES += lib/newlib cpu/arm/common/sys
.SECONDEXPANSION: .SECONDEXPANSION:
@ -123,4 +123,4 @@ LDGENFLAGS += -x c -P -E
# NB: Assumes LDSCRIPT was not overridden and is in $(OBJECTDIR) # NB: Assumes LDSCRIPT was not overridden and is in $(OBJECTDIR)
$(LDSCRIPT): $(SOURCE_LDSCRIPT) FORCE | $(OBJECTDIR) $(LDSCRIPT): $(SOURCE_LDSCRIPT) FORCE | $(OBJECTDIR)
$(TRACE_CC) $(TRACE_CC)
$(Q)$(CC) $(LDGENFLAGS) $< -o $@ $(Q)$(CC) $(LDGENFLAGS) $< | grep -v '^\s*#\s*pragma\>' > $@

144
cpu/cc2538/cc2538_cm3.h Normal file
View file

@ -0,0 +1,144 @@
/*
* Template:
* Copyright (c) 2012 ARM LIMITED
* All rights reserved.
*
* CC2538:
* Copyright (c) 2016, Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup cc2538
* @{
*
* \defgroup cc2538-cm3 CC2538 Cortex-M3
*
* CC2538 Cortex-M3 CMSIS definitions
* @{
*
* \file
* CMSIS Cortex-M3 core peripheral access layer header file for CC2538
*/
#ifndef CC2538_CM3_H
#define CC2538_CM3_H
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup CC2538_CMSIS CC2538 CMSIS Definitions
* Configuration of the Cortex-M3 Processor and Core Peripherals
* @{
*/
/** \name Interrupt Number Definition
* @{
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ****************************/
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /**< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** CC2538-Specific Interrupt Numbers *********************************/
GPIO_A_IRQn = 0, /**< GPIO port A Interrupt */
GPIO_B_IRQn = 1, /**< GPIO port B Interrupt */
GPIO_C_IRQn = 2, /**< GPIO port C Interrupt */
GPIO_D_IRQn = 3, /**< GPIO port D Interrupt */
UART0_IRQn = 5, /**< UART0 Interrupt */
UART1_IRQn = 6, /**< UART1 Interrupt */
SSI0_IRQn = 7, /**< SSI0 Interrupt */
I2C_IRQn = 8, /**< I²C Interrupt */
ADC_IRQn = 14, /**< ADC Interrupt */
WDT_IRQn = 18, /**< Watchdog Timer Interrupt */
GPT0A_IRQn = 19, /**< GPTimer 0A Interrupt */
GPT0B_IRQn = 20, /**< GPTimer 0B Interrupt */
GPT1A_IRQn = 21, /**< GPTimer 1A Interrupt */
GPT1B_IRQn = 22, /**< GPTimer 1B Interrupt */
GPT2A_IRQn = 23, /**< GPTimer 2A Interrupt */
GPT2B_IRQn = 24, /**< GPTimer 2B Interrupt */
ADC_CMP_IRQn = 25, /**< Analog Comparator Interrupt */
RF_TX_RX_ALT_IRQn = 26, /**< RF Tx/Rx (Alternate) Interrupt */
RF_ERR_ALT_IRQn = 27, /**< RF Error (Alternate) Interrupt */
SYS_CTRL_IRQn = 28, /**< System Control Interrupt */
FLASH_CTRL_IRQn = 29, /**< Flash memory Control Interrupt */
AES_ALT_IRQn = 30, /**< AES (Alternate) Interrupt */
PKA_ALT_IRQn = 31, /**< PKA (Alternate) Interrupt */
SMT_ALT_IRQn = 32, /**< SM Timer (Alternate) Interrupt */
MACT_ALT_IRQn = 33, /**< MAC Timer (Alternate) Interrupt */
SSI1_IRQn = 34, /**< SSI1 Interrupt */
GPT3A_IRQn = 35, /**< GPTimer 3A Interrupt */
GPT3B_IRQn = 36, /**< GPTimer 3B Interrupt */
UDMA_SW_IRQn = 46, /**< µDMA Software Interrupt */
UDMA_ERR_IRQn = 47, /**< µDMA Error Interrupt */
USB_IRQn = 140, /**< USB Interrupt */
RF_TX_RX_IRQn = 141, /**< RF Tx/Rx Interrupt */
RF_ERR_IRQn = 142, /**< RF Error Interrupt */
AES_IRQn = 143, /**< AES Interrupt */
PKA_IRQn = 144, /**< PKA Interrupt */
SMT_IRQn = 145, /**< SM Timer Interrupt */
MACT_IRQn = 146 /**< MAC Timer Interrupt */
} IRQn_Type;
/** @} */
/** \name Processor and Core Peripheral Section
* @{
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV 0x0200 /**< Core Revision r2p0 */
#define __MPU_PRESENT 1 /**< MPU present or not */
#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
/** @} */
/** @} */ /* CC2538_CMSIS */
#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
#ifdef __cplusplus
}
#endif
#endif /* CC2538_CM3_H */
/**
* @}
* @}
*/

18
cpu/cc2538/clock.c
View file

@ -49,7 +49,7 @@
* Clock driver implementation for the TI cc2538 * Clock driver implementation for the TI cc2538
*/ */
#include "contiki.h" #include "contiki.h"
#include "systick.h" #include "cc2538_cm3.h"
#include "reg.h" #include "reg.h"
#include "cpu.h" #include "cpu.h"
#include "dev/gptimer.h" #include "dev/gptimer.h"
@ -69,12 +69,12 @@
#endif #endif
#define PRESCALER_VALUE (SYS_CTRL_SYS_CLOCK / SYS_CTRL_1MHZ - 1) #define PRESCALER_VALUE (SYS_CTRL_SYS_CLOCK / SYS_CTRL_1MHZ - 1)
/* Reload value for SysTick counter */ /* Period of the SysTick counter expressed as a number of ticks */
#if SYS_CTRL_SYS_CLOCK % CLOCK_SECOND #if SYS_CTRL_SYS_CLOCK % CLOCK_SECOND
/* Too low clock speeds will lead to reduced accurracy */ /* Too low clock speeds will lead to reduced accurracy */
#error System clock speed too slow for CLOCK_SECOND, accuracy reduced #error System clock speed too slow for CLOCK_SECOND, accuracy reduced
#endif #endif
#define RELOAD_VALUE (SYS_CTRL_SYS_CLOCK / CLOCK_SECOND - 1) #define SYSTICK_PERIOD (SYS_CTRL_SYS_CLOCK / CLOCK_SECOND)
static volatile uint64_t rt_ticks_startup = 0, rt_ticks_epoch = 0; static volatile uint64_t rt_ticks_startup = 0, rt_ticks_epoch = 0;
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
@ -92,13 +92,7 @@ static volatile uint64_t rt_ticks_startup = 0, rt_ticks_epoch = 0;
void void
clock_init(void) clock_init(void)
{ {
REG(SYSTICK_STRELOAD) = RELOAD_VALUE; SysTick_Config(SYSTICK_PERIOD);
/* System clock source, Enable */
REG(SYSTICK_STCTRL) |= SYSTICK_STCTRL_CLK_SRC | SYSTICK_STCTRL_ENABLE;
/* Enable the SysTick Interrupt */
REG(SYSTICK_STCTRL) |= SYSTICK_STCTRL_INTEN;
/* /*
* Remove the clock gate to enable GPT0 and then initialise it * Remove the clock gate to enable GPT0 and then initialise it
@ -230,12 +224,12 @@ void
clock_adjust(void) clock_adjust(void)
{ {
/* Halt the SysTick while adjusting */ /* Halt the SysTick while adjusting */
REG(SYSTICK_STCTRL) &= ~SYSTICK_STCTRL_ENABLE; SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
update_ticks(); update_ticks();
/* Re-Start the SysTick */ /* Re-Start the SysTick */
REG(SYSTICK_STCTRL) |= SYSTICK_STCTRL_ENABLE; SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**

72
cpu/cc2538/cpu.c
View file

@ -1,72 +0,0 @@
/*
* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup cc2538-cpu
* @{
*
* \file
* Implementations of interrupt control on the cc2538 Cortex-M3 micro
*/
/*---------------------------------------------------------------------------*/
unsigned long __attribute__((naked))
cpu_cpsie(void)
{
unsigned long ret;
/* Read PRIMASK and enable interrupts */
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" bx lr\n"
: "=r" (ret));
/* The inline asm returns, we never reach here.
* We add a return statement to keep the compiler happy */
return ret;
}
/*---------------------------------------------------------------------------*/
unsigned long __attribute__((naked))
cpu_cpsid(void)
{
unsigned long ret;
/* Read PRIMASK and disable interrupts */
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n"
: "=r" (ret));
/* The inline asm returns, we never reach here.
* We add a return statement to keep the compiler happy */
return ret;
}
/*---------------------------------------------------------------------------*/
/** @} */

10
cpu/cc2538/cpu.h
View file

@ -54,17 +54,13 @@
#ifndef CPU_H_ #ifndef CPU_H_
#define CPU_H_ #define CPU_H_
/** \brief Disables all CPU interrupts */ #include "cc2538_cm3.h"
unsigned long cpu_cpsid(void);
/** \brief Enables all CPU interrupts */ /** \brief Enables all CPU interrupts */
unsigned long cpu_cpsie(void); #define INTERRUPTS_ENABLE() __enable_irq()
/** \brief Enables all CPU interrupts */
#define INTERRUPTS_ENABLE() cpu_cpsie()
/** \brief Disables all CPU interrupts. */ /** \brief Disables all CPU interrupts. */
#define INTERRUPTS_DISABLE() cpu_cpsid() #define INTERRUPTS_DISABLE() __disable_irq()
#endif /* CPU_H_ */ #endif /* CPU_H_ */

6
cpu/cc2538/dev/aes.c
View file

@ -237,8 +237,8 @@ aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv,
if(process != NULL) { if(process != NULL) {
crypto_register_process_notification(process); crypto_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_AES); NVIC_ClearPendingIRQ(AES_IRQn);
nvic_interrupt_enable(NVIC_INT_AES); NVIC_EnableIRQ(AES_IRQn);
} }
if(data_len != 0) { if(data_len != 0) {
@ -282,7 +282,7 @@ aes_auth_crypt_get_result(void *iv, void *tag)
AES_CTRL_INT_CLR_KEY_ST_WR_ERR | AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
AES_CTRL_INT_CLR_KEY_ST_RD_ERR; AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
nvic_interrupt_disable(NVIC_INT_AES); NVIC_DisableIRQ(AES_IRQn);
crypto_register_process_notification(NULL); crypto_register_process_notification(NULL);
/* Disable the master control / DMA clock */ /* Disable the master control / DMA clock */

48
cpu/cc2538/dev/bignum-driver.c
View file

@ -130,8 +130,8 @@ bignum_mod_start(const uint32_t *number,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -158,7 +158,7 @@ bignum_mod_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */
@ -238,8 +238,8 @@ bignum_cmp_start(const uint32_t *number1,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -257,7 +257,7 @@ bignum_cmp_get_result(void)
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Check the compare register. */ /* Check the compare register. */
@ -346,8 +346,8 @@ bignum_inv_mod_start(const uint32_t *number,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -374,7 +374,7 @@ bignum_inv_mod_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */
@ -469,8 +469,8 @@ bignum_mul_start(const uint32_t *multiplicand,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -498,7 +498,7 @@ bignum_mul_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */
@ -594,8 +594,8 @@ bignum_add_start(const uint32_t *number1,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -623,7 +623,7 @@ bignum_add_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */
@ -720,8 +720,8 @@ bignum_subtract_start(const uint32_t *number1,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -749,7 +749,7 @@ bignum_subtract_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */
@ -864,8 +864,8 @@ bignum_exp_mod_start(const uint32_t *number,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -892,7 +892,7 @@ bignum_exp_mod_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */
@ -1000,8 +1000,8 @@ bignum_divide_start(const uint32_t *dividend,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -1029,7 +1029,7 @@ bignum_divide_get_result(uint32_t *buffer,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
/* Get the MSW register value. */ /* Get the MSW register value. */

6
cpu/cc2538/dev/cc2538-rf.c
View file

@ -345,10 +345,10 @@ set_poll_mode(uint8_t enable)
mac_timer_init(); mac_timer_init();
REG(RFCORE_XREG_RFIRQM0) &= ~RFCORE_XREG_RFIRQM0_FIFOP; /* mask out FIFOP interrupt source */ REG(RFCORE_XREG_RFIRQM0) &= ~RFCORE_XREG_RFIRQM0_FIFOP; /* mask out FIFOP interrupt source */
REG(RFCORE_SFR_RFIRQF0) &= ~RFCORE_SFR_RFIRQF0_FIFOP; /* clear pending FIFOP interrupt */ REG(RFCORE_SFR_RFIRQF0) &= ~RFCORE_SFR_RFIRQF0_FIFOP; /* clear pending FIFOP interrupt */
nvic_interrupt_disable(NVIC_INT_RF_RXTX); /* disable RF interrupts */ NVIC_DisableIRQ(RF_TX_RX_IRQn); /* disable RF interrupts */
} else { } else {
REG(RFCORE_XREG_RFIRQM0) |= RFCORE_XREG_RFIRQM0_FIFOP; /* enable FIFOP interrupt source */ REG(RFCORE_XREG_RFIRQM0) |= RFCORE_XREG_RFIRQM0_FIFOP; /* enable FIFOP interrupt source */
nvic_interrupt_enable(NVIC_INT_RF_RXTX); /* enable RF interrupts */ NVIC_EnableIRQ(RF_TX_RX_IRQn); /* enable RF interrupts */
} }
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
@ -516,7 +516,7 @@ init(void)
/* Acknowledge all RF Error interrupts */ /* Acknowledge all RF Error interrupts */
REG(RFCORE_XREG_RFERRM) = RFCORE_XREG_RFERRM_RFERRM; REG(RFCORE_XREG_RFERRM) = RFCORE_XREG_RFERRM_RFERRM;
nvic_interrupt_enable(NVIC_INT_RF_ERR); NVIC_EnableIRQ(RF_ERR_IRQn);
if(CC2538_RF_CONF_TX_USE_DMA) { if(CC2538_RF_CONF_TX_USE_DMA) {
/* Disable peripheral triggers for the channel */ /* Disable peripheral triggers for the channel */

4
cpu/cc2538/dev/crypto.c
View file

@ -61,8 +61,8 @@ crypto_isr(void)
{ {
ENERGEST_ON(ENERGEST_TYPE_IRQ); ENERGEST_ON(ENERGEST_TYPE_IRQ);
nvic_interrupt_unpend(NVIC_INT_AES); NVIC_ClearPendingIRQ(AES_IRQn);
nvic_interrupt_disable(NVIC_INT_AES); NVIC_DisableIRQ(AES_IRQn);
if(notification_process != NULL) { if(notification_process != NULL) {
process_poll((struct process *)notification_process); process_poll((struct process *)notification_process);

18
cpu/cc2538/dev/ecc-driver.c
View file

@ -152,8 +152,8 @@ ecc_mul_start(uint32_t *scalar, ec_point_t *ec_point,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -181,7 +181,7 @@ ecc_mul_get_result(ec_point_t *ec_point,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
if(REG(PKA_SHIFT) == 0x00000000) { if(REG(PKA_SHIFT) == 0x00000000) {
@ -319,8 +319,8 @@ ecc_mul_gen_pt_start(uint32_t *scalar, ecc_curve_info_t *curve,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -349,7 +349,7 @@ ecc_mul_gen_pt_get_result(ec_point_t *ec_point,
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
if(REG(PKA_SHIFT) == 0x00000000) { if(REG(PKA_SHIFT) == 0x00000000) {
@ -492,8 +492,8 @@ ecc_add_start(ec_point_t *ec_point1, ec_point_t *ec_point2,
/* Enable Interrupt */ /* Enable Interrupt */
if(process != NULL) { if(process != NULL) {
pka_register_process_notification(process); pka_register_process_notification(process);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_enable(NVIC_INT_PKA); NVIC_EnableIRQ(PKA_IRQn);
} }
return PKA_STATUS_SUCCESS; return PKA_STATUS_SUCCESS;
@ -519,7 +519,7 @@ ecc_add_get_result(ec_point_t *ec_point, uint32_t result_vector)
} }
/* Disable Interrupt */ /* Disable Interrupt */
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
pka_register_process_notification(NULL); pka_register_process_notification(NULL);
if(REG(PKA_SHIFT) == 0x00000000) { if(REG(PKA_SHIFT) == 0x00000000) {

68
cpu/cc2538/dev/mpu.h
View file

@ -1,68 +0,0 @@
/*
* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup cc2538
* @{
*
* \defgroup cc2538-mpu cc2538 Memory Protection Unit
*
* Driver for the cc2538 Memory Protection Unit
* @{
*
* \file
* Header file for the ARM Memory Protection Unit
*/
#ifndef MPU_H_
#define MPU_H_
#define MPU_MPU_TYPE 0xE000ED90 /**< MPU Type */
#define MPU_MPU_CTRL 0xE000ED94 /**< MPU Control */
#define MPU_MPU_NUMBER 0xE000ED98 /**< MPU Region Number */
#define MPU_MPU_BASE 0xE000ED9C /**< MPU Region Base Address */
#define MPU_MPU_ATTR 0xE000EDA0 /**< MPU Region Attribute and Size */
#define MPU_MPU_BASE1 0xE000EDA4 /**< MPU Region Base Address Alias 1 */
#define MPU_MPU_ATTR1 0xE000EDA8 /**< MPU Region Attribute and Size Alias 1 */
#define MPU_MPU_BASE2 0xE000EDAC /**< MPU Region Base Address Alias 2 */
#define MPU_MPU_ATTR2 0xE000EDB0 /**< MPU Region Attribute and Size Alias 2*/
#define MPU_MPU_BASE3 0xE000EDB4 /**< MPU Region Base Address Alias 3 */
#define MPU_MPU_ATTR3 0xE000EDB8 /**< MPU Region Attribute and Size Alias 3*/
#define MPU_DBG_CTRL 0xE000EDF0 /**< Debug Control and Status Reg */
#define MPU_DBG_XFER 0xE000EDF4 /**< Debug Core Reg. Transfer Select */
#define MPU_DBG_DATA 0xE000EDF8 /**< Debug Core Register Data */
#define MPU_DBG_INT 0xE000EDFC /**< Debug Reset Interrupt Control */
#define MPU_SW_TRIG 0xE000EF00 /**< Software Trigger Interrupt */
#endif /* MPU_H_ */
/**
* @}
* @}
*/

66
cpu/cc2538/dev/nvic.c
View file

@ -38,74 +38,12 @@
*/ */
#include "contiki.h" #include "contiki.h"
#include "dev/nvic.h" #include "dev/nvic.h"
#include "dev/scb.h" #include "cc2538_cm3.h"
#include "reg.h"
#include <stdint.h>
static uint32_t *interrupt_enable;
static uint32_t *interrupt_disable;
static uint32_t *interrupt_pend;
static uint32_t *interrupt_unpend;
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
nvic_init() nvic_init()
{ {
interrupt_enable = (uint32_t *)NVIC_EN0;
interrupt_disable = (uint32_t *)NVIC_DIS0;
interrupt_pend = (uint32_t *)NVIC_PEND0;
interrupt_unpend = (uint32_t *)NVIC_UNPEND0;
/* Provide our interrupt table to the NVIC */ /* Provide our interrupt table to the NVIC */
REG(SCB_VTABLE) = NVIC_VTABLE_ADDRESS; SCB->VTOR = NVIC_VTABLE_ADDRESS;
}
/*---------------------------------------------------------------------------*/
void
nvic_interrupt_enable(uint32_t intr)
{
/* Writes of 0 are ignored, which is why we can simply use = */
interrupt_enable[intr >> 5] = 1 << (intr & 0x1F);
}
/*---------------------------------------------------------------------------*/
void
nvic_interrupt_disable(uint32_t intr)
{
/* Writes of 0 are ignored, which is why we can simply use = */
interrupt_disable[intr >> 5] = 1 << (intr & 0x1F);
}
/*---------------------------------------------------------------------------*/
void
nvic_interrupt_en_restore(uint32_t intr, uint8_t v)
{
if(v != 1) {
return;
}
interrupt_enable[intr >> 5] = 1 << (intr & 0x1F);
}
/*---------------------------------------------------------------------------*/
uint8_t
nvic_interrupt_en_save(uint32_t intr)
{
uint8_t rv = ((interrupt_enable[intr >> 5] & (1 << (intr & 0x1F)))
> NVIC_INTERRUPT_DISABLED);
nvic_interrupt_disable(intr);
return rv;
}
/*---------------------------------------------------------------------------*/
void
nvic_interrupt_pend(uint32_t intr)
{
/* Writes of 0 are ignored, which is why we can simply use = */
interrupt_pend[intr >> 5] = 1 << (intr & 0x1F);
}
/*---------------------------------------------------------------------------*/
void
nvic_interrupt_unpend(uint32_t intr)
{
/* Writes of 0 are ignored, which is why we can simply use = */
interrupt_unpend[intr >> 5] = 1 << (intr & 0x1F);
} }
/** @} */ /** @} */

179
cpu/cc2538/dev/nvic.h
View file

@ -43,14 +43,13 @@
#ifndef NVIC_H_ #ifndef NVIC_H_
#define NVIC_H_ #define NVIC_H_
#include "cc2538_cm3.h"
#include <stdint.h> #include <stdint.h>
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** \name NVIC Constants and Configuration /** \name NVIC Constants and Configuration
* @{ * @{
*/ */
#define NVIC_INTERRUPT_ENABLED 0x00000001
#define NVIC_INTERRUPT_DISABLED 0x00000000
#ifdef NVIC_CONF_VTABLE_ADDRESS #ifdef NVIC_CONF_VTABLE_ADDRESS
#define NVIC_VTABLE_ADDRESS NVIC_CONF_VTABLE_ADDRESS #define NVIC_VTABLE_ADDRESS NVIC_CONF_VTABLE_ADDRESS
#else #else
@ -59,183 +58,9 @@ extern void(*const vectors[])(void);
#endif #endif
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** \name NVIC Interrupt assignments
* @{
*/
#define NVIC_INT_GPIO_PORT_A 0 /**< GPIO port A */
#define NVIC_INT_GPIO_PORT_B 1 /**< GPIO port B */
#define NVIC_INT_GPIO_PORT_C 2 /**< GPIO port C */
#define NVIC_INT_GPIO_PORT_D 3 /**< GPIO port D */
#define NVIC_INT_UART0 5 /**< UART0 */
#define NVIC_INT_UART1 6 /**< UART1 */
#define NVIC_INT_SSI0 7 /**< SSI0 */
#define NVIC_INT_I2C 8 /**< I2C */
#define NVIC_INT_ADC 14 /**< ADC */
#define NVIC_INT_WDT 18 /**< Watchdog Timer */
#define NVIC_INT_GPTIMER_0A 19 /**< GPTimer 0A */
#define NVIC_INT_GPTIMER_0B 20 /**< GPTimer 0B */
#define NVIC_INT_GPTIMER_1A 21 /**< GPTimer 1A */
#define NVIC_INT_GPTIMER_1B 22 /**< GPTimer 1B */
#define NVIC_INT_GPTIMER_2A 23 /**< GPTimer 2A */
#define NVIC_INT_GPTIMER_2B 24 /**< GPTimer 2B */
#define NVIC_INT_ADC_CMP 25 /**< Analog Comparator */
#define NVIC_INT_RF_RXTX_ALT 26 /**< RF TX/RX (Alternate) */
#define NVIC_INT_RF_ERR_ALT 27 /**< RF Error (Alternate) */
#define NVIC_INT_SYS_CTRL 28 /**< System Control */
#define NVIC_INT_FLASH_CTRL 29 /**< Flash memory control */
#define NVIC_INT_AES_ALT 30 /**< AES (Alternate) */
#define NVIC_INT_PKA_ALT 31 /**< PKA (Alternate) */
#define NVIC_INT_SM_TIMER_ALT 32 /**< SM Timer (Alternate) */
#define NVIC_INT_MAC_TIMER_ALT 33 /**< MAC Timer (Alternate) */
#define NVIC_INT_SSI1 34 /**< SSI1 */
#define NVIC_INT_GPTIMER_3A 35 /**< GPTimer 3A */
#define NVIC_INT_GPTIMER_3B 36 /**< GPTimer 3B */
#define NVIC_INT_UDMA 46 /**< uDMA software */
#define NVIC_INT_UDMA_ERR 47 /**< uDMA error */
#define NVIC_INT_USB 140 /**< USB */
#define NVIC_INT_RF_RXTX 141 /**< RF Core Rx/Tx */
#define NVIC_INT_RF_ERR 142 /**< RF Core Error */
#define NVIC_INT_AES 143 /**< AES */
#define NVIC_INT_PKA 144 /**< PKA */
#define NVIC_INT_SM_TIMER 145 /**< SM Timer */
#define NVIC_INT_MACTIMER 146 /**< MAC Timer */
/** @} */
/*---------------------------------------------------------------------------*/
/** \name NVIC Register Declarations
* @{
*/
#define NVIC_EN0 0xE000E100 /**< Interrupt 0-31 Set Enable */
#define NVIC_EN1 0xE000E104 /**< Interrupt 32-54 Set Enable */
#define NVIC_EN2 0xE000E108 /**< Interrupt 64-95 Set Enable */
#define NVIC_EN3 0xE000E10C /**< Interrupt 96-127 Set Enable */
#define NVIC_EN4 0xE000E110 /**< Interrupt 128-131 Set Enable */
#define NVIC_DIS0 0xE000E180 /**< Interrupt 0-31 Clear Enable */
#define NVIC_DIS1 0xE000E184 /**< Interrupt 32-54 Clear Enable */
#define NVIC_DIS2 0xE000E188 /**< Interrupt 64-95 Clear Enable */
#define NVIC_DIS3 0xE000E18C /**< Interrupt 96-127 Clear Enable */
#define NVIC_DIS4 0xE000E190 /**< Interrupt 128-131 Clear Enable */
#define NVIC_PEND0 0xE000E200 /**< Interrupt 0-31 Set Pending */
#define NVIC_PEND1 0xE000E204 /**< Interrupt 32-54 Set Pending */
#define NVIC_PEND2 0xE000E208 /**< Interrupt 64-95 Set Pending */
#define NVIC_PEND3 0xE000E20C /**< Interrupt 96-127 Set Pending */
#define NVIC_PEND4 0xE000E210 /**< Interrupt 128-131 Set Pending */
#define NVIC_UNPEND0 0xE000E280 /**< Interrupt 0-31 Clear Pending */
#define NVIC_UNPEND1 0xE000E284 /**< Interrupt 32-54 Clear Pending */
#define NVIC_UNPEND2 0xE000E288 /**< Interrupt 64-95 Clear Pending */
#define NVIC_UNPEND3 0xE000E28C /**< Interrupt 96-127 Clear Pending */
#define NVIC_UNPEND4 0xE000E290 /**< Interrupt 128-131 Clear Pending */
#define NVIC_ACTIVE0 0xE000E300 /**< Interrupt 0-31 Active Bit */
#define NVIC_ACTIVE1 0xE000E304 /**< Interrupt 32-54 Active Bit */
#define NVIC_ACTIVE2 0xE000E308 /**< Interrupt 64-95 Active Bit */
#define NVIC_ACTIVE3 0xE000E30C /**< Interrupt 96-127 Active Bit */
#define NVIC_ACTIVE4 0xE000E310 /**< Interrupt 128-131 Active Bit */
#define NVIC_PRI0 0xE000E400 /**< Interrupt 0-3 Priority */
#define NVIC_PRI1 0xE000E404 /**< Interrupt 4-7 Priority */
#define NVIC_PRI2 0xE000E408 /**< Interrupt 8-11 Priority */
#define NVIC_PRI3 0xE000E40C /**< Interrupt 12-15 Priority */
#define NVIC_PRI4 0xE000E410 /**< Interrupt 16-19 Priority */
#define NVIC_PRI5 0xE000E414 /**< Interrupt 20-23 Priority */
#define NVIC_PRI6 0xE000E418 /**< Interrupt 24-27 Priority */
#define NVIC_PRI7 0xE000E41C /**< Interrupt 28-31 Priority */
#define NVIC_PRI8 0xE000E420 /**< Interrupt 32-35 Priority */
#define NVIC_PRI9 0xE000E424 /**< Interrupt 36-39 Priority */
#define NVIC_PRI10 0xE000E428 /**< Interrupt 40-43 Priority */
#define NVIC_PRI11 0xE000E42C /**< Interrupt 44-47 Priority */
#define NVIC_PRI12 0xE000E430 /**< Interrupt 48-51 Priority */
#define NVIC_PRI13 0xE000E434 /**< Interrupt 52-53 Priority */
#define NVIC_PRI14 0xE000E438 /**< Interrupt 56-59 Priority */
#define NVIC_PRI15 0xE000E43C /**< Interrupt 60-63 Priority */
#define NVIC_PRI16 0xE000E440 /**< Interrupt 64-67 Priority */
#define NVIC_PRI17 0xE000E444 /**< Interrupt 68-71 Priority */
#define NVIC_PRI18 0xE000E448 /**< Interrupt 72-75 Priority */
#define NVIC_PRI19 0xE000E44C /**< Interrupt 76-79 Priority */
#define NVIC_PRI20 0xE000E450 /**< Interrupt 80-83 Priority */
#define NVIC_PRI21 0xE000E454 /**< Interrupt 84-87 Priority */
#define NVIC_PRI22 0xE000E458 /**< Interrupt 88-91 Priority */
#define NVIC_PRI23 0xE000E45C /**< Interrupt 92-95 Priority */
#define NVIC_PRI24 0xE000E460 /**< Interrupt 96-99 Priority */
#define NVIC_PRI25 0xE000E464 /**< Interrupt 100-103 Priority */
#define NVIC_PRI26 0xE000E468 /**< Interrupt 104-107 Priority */
#define NVIC_PRI27 0xE000E46C /**< Interrupt 108-111 Priority */
#define NVIC_PRI28 0xE000E470 /**< Interrupt 112-115 Priority */
#define NVIC_PRI29 0xE000E474 /**< Interrupt 116-119 Priority */
#define NVIC_PRI30 0xE000E478 /**< Interrupt 120-123 Priority */
#define NVIC_PRI31 0xE000E47C /**< Interrupt 124-127 Priority */
#define NVIC_PRI32 0xE000E480 /**< Interrupt 128-131 Priority */
#define NVIC_PRI33 0xE000E480 /**< Interrupt 132-135 Priority */
#define NVIC_PRI34 0xE000E484 /**< Interrupt 136-139 Priority */
#define NVIC_PRI35 0xE000E488 /**< Interrupt 140-143 Priority */
#define NVIC_PRI36 0xE000E48c /**< Interrupt 144-147 Priority */
/** @} */
/*---------------------------------------------------------------------------*/
/** \brief Initialises the NVIC driver */ /** \brief Initialises the NVIC driver */
void nvic_init(); void nvic_init();
/**
* \brief Enables interrupt intr
* \param intr The interrupt number (NOT the vector number). For example,
* GPIO Port A interrupt is 0, not 16.
*
* Possible values for the \e intr param are defined as NVIC_INT_xyz. For
* instance, to enable the GPIO Port A interrupt, pass NVIC_INT_GPIO_PORT_A
*/
void nvic_interrupt_enable(uint32_t intr);
/**
* \brief Disables interrupt intr
* \param intr The interrupt number (NOT the vector number). For example,
* GPIO Port A interrupt is 0, not 16.
*
* Possible values for the \e intr param are defined as NVIC_INT_xyz. For
* instance, to disable the GPIO Port A interrupt, pass NVIC_INT_GPIO_PORT_A
*/
void nvic_interrupt_disable(uint32_t intr);
/**
* \brief Enables interrupt intr if v > 0
* \param intr The interrupt number (NOT the vector number). For example,
* GPIO Port A interrupt is 0, not 16.
* \param v 0: No effect, 1: Enables the interrupt
*
* This function is useful to restore an interrupt to a state previously
* saved by nvic_interrupt_en_save. Thus, if when nvic_interrupt_en_save was
* called the interrupt was enabled, this function will re-enabled it.
* Possible values for the \e intr param are defined as NVIC_INT_xyz. For
* instance, to disable the GPIO Port A interrupt, pass NVIC_INT_GPIO_PORT_A
*/
void nvic_interrupt_en_restore(uint32_t intr, uint8_t v);
/**
* \brief Checks the interrupt enabled status for intr
* \param intr The interrupt number (NOT the vector number). For example,
* GPIO Port A interrupt is 0, not 16.
* \return 1: Enabled, 0: Disabled
*
* Possible values for the \e intr param are defined as NVIC_INT_xyz. For
* instance, to disable the GPIO Port A interrupt, pass NVIC_INT_GPIO_PORT_A
*/
uint8_t nvic_interrupt_en_save(uint32_t intr);
/**
* \brief Sets intr to pending
* \param intr The interrupt number (NOT the vector number). For example,
* GPIO Port A interrupt is 0, not 16.
*
* Possible values for the \e intr param are defined as NVIC_INT_xyz. For
* instance, to enable the GPIO Port A interrupt, pass NVIC_INT_GPIO_PORT_A
*/
void nvic_interrupt_pend(uint32_t intr);
/**
* \brief Sets intr to no longer pending
* \param intr The interrupt number (NOT the vector number). For example,
* GPIO Port A interrupt is 0, not 16.
*
* Possible values for the \e intr param are defined as NVIC_INT_xyz. For
* instance, to disable the GPIO Port A interrupt, pass NVIC_INT_GPIO_PORT_A
*/
void nvic_interrupt_unpend(uint32_t intr);
#endif /* NVIC_H_ */ #endif /* NVIC_H_ */
/** /**

4
cpu/cc2538/dev/pka.c
View file

@ -64,8 +64,8 @@ pka_isr(void)
{ {
ENERGEST_ON(ENERGEST_TYPE_IRQ); ENERGEST_ON(ENERGEST_TYPE_IRQ);
nvic_interrupt_unpend(NVIC_INT_PKA); NVIC_ClearPendingIRQ(PKA_IRQn);
nvic_interrupt_disable(NVIC_INT_PKA); NVIC_DisableIRQ(PKA_IRQn);
if(notification_process != NULL) { if(notification_process != NULL) {
process_poll((struct process *)notification_process); process_poll((struct process *)notification_process);

83
cpu/cc2538/dev/scb.h
View file

@ -1,83 +0,0 @@
/*
* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup cc2538
* @{
*
* \defgroup cc2538-scb cc2538 System Control Block (SCB)
*
* Offsets and bit definitions for SCB registers
* @{
*
* \file
* Header file for the System Control Block (SCB)
*/
#ifndef SCB_H_
#define SCB_H_
#define SCB_CPUID 0xE000ED00 /**< CPU ID Base */
#define SCB_INTCTRL 0xE000ED04 /**< Interrupt Control and State */
#define SCB_VTABLE 0xE000ED08 /**< Vector Table Offset */
#define SCB_APINT 0xE000ED0C /**< Application Interrupt and Reset Control */
#define SCB_SYSCTRL 0xE000ED10 /**< System Control */
#define SCB_CFGCTRL 0xE000ED14 /**< Configuration and Control */
#define SCB_SYSPRI1 0xE000ED18 /**< System Handler Priority 1 */
#define SCB_SYSPRI2 0xE000ED1C /**< System Handler Priority 2 */
#define SCB_SYSPRI3 0xE000ED20 /**< System Handler Priority 3 */
#define SCB_SYSHNDCTRL 0xE000ED24 /**< System Handler Control and State */
#define SCB_FAULTSTAT 0xE000ED28 /**< Configurable Fault Status */
#define SCB_HFAULTSTAT 0xE000ED2C /**< Hard Fault Status */
#define SCB_DEBUG_STAT 0xE000ED30 /**< Debug Status Register */
#define SCB_MMADDR 0xE000ED34 /**< Memory Management Fault Address */
#define SCB_FAULT_ADDR 0xE000ED38 /**< Bus Fault Address */
/*---------------------------------------------------------------------------*/
/** \name VTABLE register bits
* @{
*/
#define SCB_VTABLE_BASE 0x20000000 /**< Vector Table Base */
#define SCB_VTABLE_OFFSET_M 0x1FFFFE00 /**< Vector Table Offset */
/** @} */
/*---------------------------------------------------------------------------*/
/** \name SCB_SYSCTRL register bits
* @{
*/
#define SCB_SYSCTRL_SEVONPEND 0x00000010 /**< Wake up on pending */
#define SCB_SYSCTRL_SLEEPDEEP 0x00000004 /**< Deep sleep enable */
#define SCB_SYSCTRL_SLEEPEXIT 0x00000002 /**< Sleep on ISR exit */
/** @} */
/*---------------------------------------------------------------------------*/
#endif /* SCB_H_ */
/**
* @}
* @}
*/

53
cpu/cc2538/dev/systick.h
View file

@ -1,53 +0,0 @@
/*
* Copyright (c) 2012, Texas Instruments Incorporated - http:/www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \file
* Header for with definitions related to the cc2538 SysTick
*/
/*---------------------------------------------------------------------------*/
#ifndef SYSTICK_H_
#define SYSTICK_H_
/*---------------------------------------------------------------------------*/
/* SysTick Register Definitions */
#define SYSTICK_STCTRL 0xE000E010 /* Control and Status */
#define SYSTICK_STRELOAD 0xE000E014 /* Reload Value */
#define SYSTICK_STCURRENT 0xE000E018 /* Current Value */
#define SYSTICK_STCAL 0xE000E01C /* SysTick Calibration */
/*---------------------------------------------------------------------------*/
/* Bit Definitions for the STCTRL Register */
#define SYSTICK_STCTRL_COUNT 0x00010000 /* Count Flag */
#define SYSTICK_STCTRL_CLK_SRC 0x00000004 /* Clock Source */
#define SYSTICK_STCTRL_INTEN 0x00000002 /* Interrupt Enable */
#define SYSTICK_STCTRL_ENABLE 0x00000001 /* Enable */
#endif /* SYSTICK_H_ */
/** @} */

6
cpu/cc2538/dev/uart.c
View file

@ -181,7 +181,7 @@ static const uart_regs_t uart_regs[UART_INSTANCE_COUNT] = {
.tx = {UART0_TX_PORT, UART0_TX_PIN}, .tx = {UART0_TX_PORT, UART0_TX_PIN},
.cts = {-1, -1}, .cts = {-1, -1},
.rts = {-1, -1}, .rts = {-1, -1},
.nvic_int = NVIC_INT_UART0 .nvic_int = UART0_IRQn
}, { }, {
.sys_ctrl_rcgcuart_uart = SYS_CTRL_RCGCUART_UART1, .sys_ctrl_rcgcuart_uart = SYS_CTRL_RCGCUART_UART1,
.sys_ctrl_scgcuart_uart = SYS_CTRL_SCGCUART_UART1, .sys_ctrl_scgcuart_uart = SYS_CTRL_SCGCUART_UART1,
@ -195,7 +195,7 @@ static const uart_regs_t uart_regs[UART_INSTANCE_COUNT] = {
.tx = {UART1_TX_PORT, UART1_TX_PIN}, .tx = {UART1_TX_PORT, UART1_TX_PIN},
.cts = {UART1_CTS_PORT, UART1_CTS_PIN}, .cts = {UART1_CTS_PORT, UART1_CTS_PIN},
.rts = {UART1_RTS_PORT, UART1_RTS_PIN}, .rts = {UART1_RTS_PORT, UART1_RTS_PIN},
.nvic_int = NVIC_INT_UART1 .nvic_int = UART1_IRQn
} }
}; };
static int (* input_handler[UART_INSTANCE_COUNT])(unsigned char c); static int (* input_handler[UART_INSTANCE_COUNT])(unsigned char c);
@ -328,7 +328,7 @@ uart_init(uint8_t uart)
REG(regs->base + UART_CTL) |= UART_CTL_UARTEN; REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
/* Enable UART0 Interrupts */ /* Enable UART0 Interrupts */
nvic_interrupt_enable(regs->nvic_int); NVIC_EnableIRQ(regs->nvic_int);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void

4
cpu/cc2538/dev/udma.c
View file

@ -62,8 +62,8 @@ udma_init()
REG(UDMA_CTLBASE) = (uint32_t)(&channel_config); REG(UDMA_CTLBASE) = (uint32_t)(&channel_config);
nvic_interrupt_enable(NVIC_INT_UDMA); NVIC_EnableIRQ(UDMA_SW_IRQn);
nvic_interrupt_enable(NVIC_INT_UDMA_ERR); NVIC_EnableIRQ(UDMA_ERR_IRQn);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void

4
cpu/cc2538/lpm.c
View file

@ -39,10 +39,10 @@
#include "sys/energest.h" #include "sys/energest.h"
#include "sys/process.h" #include "sys/process.h"
#include "dev/sys-ctrl.h" #include "dev/sys-ctrl.h"
#include "dev/scb.h"
#include "dev/rfcore-xreg.h" #include "dev/rfcore-xreg.h"
#include "rtimer-arch.h" #include "rtimer-arch.h"
#include "lpm.h" #include "lpm.h"
#include "cc2538_cm3.h"
#include "reg.h" #include "reg.h"
#include <stdbool.h> #include <stdbool.h>
@ -379,7 +379,7 @@ lpm_init()
* By default, we will enter PM0 unless lpm_enter() decides otherwise * By default, we will enter PM0 unless lpm_enter() decides otherwise
*/ */
REG(SYS_CTRL_PMCTL) = SYS_CTRL_PMCTL_PM0; REG(SYS_CTRL_PMCTL) = SYS_CTRL_PMCTL_PM0;
REG(SCB_SYSCTRL) |= SCB_SYSCTRL_SLEEPDEEP; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
max_pm = LPM_CONF_MAX_PM; max_pm = LPM_CONF_MAX_PM;

48
cpu/cc2538/mtarch.h
View file

@ -1,48 +0,0 @@
/*
* Copyright (c) 2010, Loughborough University - Computer Science
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* \file
* Stub header file for multi-threading. It doesn't do anything, it
* just exists so that mt.c can compile cleanly.
*
* This is based on the original mtarch.h for z80 by Takahide Matsutsuka
*
* \author
* George Oikonomou - <oikonomou@users.sourceforge.net>
*/
#ifndef MTARCH_H_
#define MTARCH_H_
struct mtarch_thread {
unsigned char *sp;
};
#endif /* MTARCH_H_ */

6
cpu/cc2538/rtimer-arch.c
View file

@ -99,7 +99,7 @@ rtimer_arch_schedule(rtimer_clock_t t)
/* Store the value. The LPM module will query us for it */ /* Store the value. The LPM module will query us for it */
next_trigger = t; next_trigger = t;
nvic_interrupt_enable(NVIC_INT_SM_TIMER); NVIC_EnableIRQ(SMT_IRQn);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
rtimer_clock_t rtimer_clock_t
@ -147,8 +147,8 @@ rtimer_isr()
next_trigger = 0; next_trigger = 0;
nvic_interrupt_unpend(NVIC_INT_SM_TIMER); NVIC_ClearPendingIRQ(SMT_IRQn);
nvic_interrupt_disable(NVIC_INT_SM_TIMER); NVIC_DisableIRQ(SMT_IRQn);
rtimer_run_next(); rtimer_run_next();

6
cpu/cc2538/startup-gcc.c
View file

@ -52,6 +52,8 @@ void nmi_handler(void);
void default_handler(void); void default_handler(void);
/* System Handler and ISR prototypes implemented elsewhere */ /* System Handler and ISR prototypes implemented elsewhere */
void svcall_handler(void); /* See mtarch.c */
void pendsv_handler(void); /* See mtarch.c */
void clock_isr(void); /* SysTick Handler */ void clock_isr(void); /* SysTick Handler */
void gpio_port_a_isr(void); void gpio_port_a_isr(void);
void gpio_port_b_isr(void); void gpio_port_b_isr(void);
@ -119,10 +121,10 @@ void(*const vectors[])(void) =
0, /* 8 Reserved */ 0, /* 8 Reserved */
0, /* 9 Reserved */ 0, /* 9 Reserved */
0, /* 10 Reserved */ 0, /* 10 Reserved */
default_handler, /* 11 SVCall handler */ svcall_handler, /* 11 SVCall handler */
default_handler, /* 12 Debug monitor handler */ default_handler, /* 12 Debug monitor handler */
0, /* 13 Reserved */ 0, /* 13 Reserved */
default_handler, /* 14 The PendSV handler */ pendsv_handler, /* 14 The PendSV handler */
clock_isr, /* 15 The SysTick handler */ clock_isr, /* 15 The SysTick handler */
gpio_port_a_isr, /* 16 GPIO Port A */ gpio_port_a_isr, /* 16 GPIO Port A */
gpio_port_b_isr, /* 17 GPIO Port B */ gpio_port_b_isr, /* 17 GPIO Port B */

62
cpu/cc2538/usb/usb-arch.c
View file

@ -167,6 +167,24 @@ static void in_ep_interrupt_handler(uint8_t ep_hw);
static void out_ep_interrupt_handler(uint8_t ep_hw); static void out_ep_interrupt_handler(uint8_t ep_hw);
static void ep0_interrupt_handler(void); static void ep0_interrupt_handler(void);
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
static uint8_t
disable_irq(void)
{
uint8_t enabled = NVIC_IsIRQEnabled(USB_IRQn);
if(enabled) {
NVIC_DisableIRQ(USB_IRQn);
}
return enabled;
}
/*---------------------------------------------------------------------------*/
static void
restore_irq(uint8_t enabled)
{
if(enabled) {
NVIC_EnableIRQ(USB_IRQn);
}
}
/*---------------------------------------------------------------------------*/
static void static void
notify_process(unsigned int e) notify_process(unsigned int e)
{ {
@ -205,12 +223,12 @@ usb_arch_get_global_events(void)
uint8_t flag; uint8_t flag;
volatile unsigned int e; volatile unsigned int e;
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
e = events; e = events;
events = 0; events = 0;
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
return e; return e;
} }
@ -222,12 +240,12 @@ usb_get_ep_events(uint8_t addr)
uint8_t flag; uint8_t flag;
usb_endpoint_t *ep = EP_STRUCT(addr); usb_endpoint_t *ep = EP_STRUCT(addr);
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
e = ep->events; e = ep->events;
ep->events = 0; ep->events = 0;
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
return e; return e;
} }
@ -360,7 +378,7 @@ usb_arch_setup(void)
udma_channel_mask_set(USB_ARCH_CONF_TX_DMA_CHAN); udma_channel_mask_set(USB_ARCH_CONF_TX_DMA_CHAN);
} }
nvic_interrupt_enable(NVIC_INT_USB); NVIC_EnableIRQ(USB_IRQn);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -381,7 +399,7 @@ usb_submit_recv_buffer(uint8_t addr, usb_buffer *buffer)
return; return;
} }
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
tailp = &ep->buffer; tailp = &ep->buffer;
while(*tailp) { while(*tailp) {
@ -404,7 +422,7 @@ usb_submit_recv_buffer(uint8_t addr, usb_buffer *buffer)
} }
} }
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -419,7 +437,7 @@ usb_submit_xmit_buffer(uint8_t addr, usb_buffer *buffer)
return; return;
} }
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
if(EP_HW_NUM(addr) == 0) { if(EP_HW_NUM(addr) == 0) {
if(buffer->data == NULL) { if(buffer->data == NULL) {
@ -429,7 +447,7 @@ usb_submit_xmit_buffer(uint8_t addr, usb_buffer *buffer)
REG(USB_INDEX) = 0; REG(USB_INDEX) = 0;
REG(USB_CS0) = USB_CS0_CLR_OUTPKT_RDY | USB_CS0_DATA_END; REG(USB_CS0) = USB_CS0_CLR_OUTPKT_RDY | USB_CS0_DATA_END;
notify_ep_process(ep, USB_EP_EVENT_NOTIFICATION); notify_ep_process(ep, USB_EP_EVENT_NOTIFICATION);
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
return; return;
} else { } else {
/* Release the HW FIFO */ /* Release the HW FIFO */
@ -455,7 +473,7 @@ usb_submit_xmit_buffer(uint8_t addr, usb_buffer *buffer)
res = ep0_tx(); res = ep0_tx();
} }
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
if(res & USB_WRITE_NOTIFY) { if(res & USB_WRITE_NOTIFY) {
notify_ep_process(ep, USB_EP_EVENT_NOTIFICATION); notify_ep_process(ep, USB_EP_EVENT_NOTIFICATION);
@ -520,7 +538,7 @@ ep_setup(uint8_t addr)
ep->events = 0; ep->events = 0;
ep->xfer_size = ep_xfer_size[ei]; ep->xfer_size = ep_xfer_size[ei];
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
/* Select endpoint register */ /* Select endpoint register */
REG(USB_INDEX) = ei; REG(USB_INDEX) = ei;
@ -536,7 +554,7 @@ ep_setup(uint8_t addr)
} }
} }
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -616,7 +634,7 @@ usb_arch_disable_endpoint(uint8_t addr)
ep->flags &= ~USB_EP_FLAGS_ENABLED; ep->flags &= ~USB_EP_FLAGS_ENABLED;
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
REG(USB_INDEX) = ei; REG(USB_INDEX) = ei;
if(ei == 0) { if(ei == 0) {
@ -628,7 +646,7 @@ usb_arch_disable_endpoint(uint8_t addr)
out_ep_dis(addr); out_ep_dis(addr);
} }
} }
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -638,11 +656,11 @@ usb_arch_discard_all_buffers(uint8_t addr)
uint8_t flag; uint8_t flag;
volatile usb_endpoint_t *ep = EP_STRUCT(addr); volatile usb_endpoint_t *ep = EP_STRUCT(addr);
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
buffer = ep->buffer; buffer = ep->buffer;
ep->buffer = NULL; ep->buffer = NULL;
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
while(buffer) { while(buffer) {
buffer->flags &= ~USB_BUFFER_SUBMITTED; buffer->flags &= ~USB_BUFFER_SUBMITTED;
@ -689,11 +707,11 @@ usb_arch_control_stall(uint8_t addr)
return; return;
} }
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
set_stall(addr, 1); set_stall(addr, 1);
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -711,7 +729,7 @@ usb_arch_halt_endpoint(uint8_t addr, int halt)
return; return;
} }
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
if(halt) { if(halt) {
ep->halted = 0x1; ep->halted = 0x1;
@ -732,7 +750,7 @@ usb_arch_halt_endpoint(uint8_t addr, int halt)
} }
} }
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -767,7 +785,7 @@ usb_arch_send_pending(uint8_t addr)
uint8_t ret; uint8_t ret;
uint8_t ei = EP_INDEX(addr); uint8_t ei = EP_INDEX(addr);
flag = nvic_interrupt_en_save(NVIC_INT_USB); flag = disable_irq();
REG(USB_INDEX) = ei; REG(USB_INDEX) = ei;
if(ei == 0) { if(ei == 0) {
@ -776,7 +794,7 @@ usb_arch_send_pending(uint8_t addr)
ret = REG(USB_CSIL) & USB_CSIL_INPKT_RDY; ret = REG(USB_CSIL) & USB_CSIL_INPKT_RDY;
} }
nvic_interrupt_en_restore(NVIC_INT_USB, flag); restore_irq(flag);
return ret; return ret;
} }

1
examples/cc2538-common/test-pwm.c
View file

@ -50,7 +50,6 @@
#include "dev/watchdog.h" #include "dev/watchdog.h"
#include "dev/sys-ctrl.h" #include "dev/sys-ctrl.h"
#include "pwm.h" #include "pwm.h"
#include "systick.h"
#include "lpm.h" #include "lpm.h"
#include "dev/ioc.h" #include "dev/ioc.h"
#include <stdio.h> #include <stdio.h>

2
examples/cc2538dk/cc2538-demo.c
View file

@ -152,7 +152,7 @@ PROCESS_THREAD(cc2538_demo_process, ev, data)
} else if(data == &button_left_sensor || data == &button_right_sensor) { } else if(data == &button_left_sensor || data == &button_right_sensor) {
leds_toggle(LEDS_BUTTON); leds_toggle(LEDS_BUTTON);
} else if(data == &button_down_sensor) { } else if(data == &button_down_sensor) {
cpu_cpsid(); INTERRUPTS_DISABLE();
leds_on(LEDS_REBOOT); leds_on(LEDS_REBOOT);
watchdog_reboot(); watchdog_reboot();
} else if(data == &button_up_sensor) { } else if(data == &button_up_sensor) {

2
examples/zolertia/zoul/project-conf.h
View file

@ -48,7 +48,7 @@
*/ */
#define MOTION_SENSOR_PORT GPIO_A_NUM #define MOTION_SENSOR_PORT GPIO_A_NUM
#define MOTION_SENSOR_PIN 5 #define MOTION_SENSOR_PIN 5
#define MOTION_SENSOR_VECTOR NVIC_INT_GPIO_PORT_A #define MOTION_SENSOR_VECTOR GPIO_A_IRQn
#endif /* PROJECT_CONF_H_ */ #endif /* PROJECT_CONF_H_ */

1
platform/cc2538dk/contiki-main.c
View file

@ -46,7 +46,6 @@
#include "dev/adc.h" #include "dev/adc.h"
#include "dev/leds.h" #include "dev/leds.h"
#include "dev/sys-ctrl.h" #include "dev/sys-ctrl.h"
#include "dev/scb.h"
#include "dev/nvic.h" #include "dev/nvic.h"
#include "dev/uart.h" #include "dev/uart.h"
#include "dev/watchdog.h" #include "dev/watchdog.h"

10
platform/cc2538dk/dev/board.h
View file

@ -141,27 +141,27 @@
/** BUTTON_SELECT -> PA3 */ /** BUTTON_SELECT -> PA3 */
#define BUTTON_SELECT_PORT GPIO_A_NUM #define BUTTON_SELECT_PORT GPIO_A_NUM
#define BUTTON_SELECT_PIN 3 #define BUTTON_SELECT_PIN 3
#define BUTTON_SELECT_VECTOR NVIC_INT_GPIO_PORT_A #define BUTTON_SELECT_VECTOR GPIO_A_IRQn
/** BUTTON_LEFT -> PC4 */ /** BUTTON_LEFT -> PC4 */
#define BUTTON_LEFT_PORT GPIO_C_NUM #define BUTTON_LEFT_PORT GPIO_C_NUM
#define BUTTON_LEFT_PIN 4 #define BUTTON_LEFT_PIN 4
#define BUTTON_LEFT_VECTOR NVIC_INT_GPIO_PORT_C #define BUTTON_LEFT_VECTOR GPIO_C_IRQn
/** BUTTON_RIGHT -> PC5 */ /** BUTTON_RIGHT -> PC5 */
#define BUTTON_RIGHT_PORT GPIO_C_NUM #define BUTTON_RIGHT_PORT GPIO_C_NUM
#define BUTTON_RIGHT_PIN 5 #define BUTTON_RIGHT_PIN 5
#define BUTTON_RIGHT_VECTOR NVIC_INT_GPIO_PORT_C #define BUTTON_RIGHT_VECTOR GPIO_C_IRQn
/** BUTTON_UP -> PC6 */ /** BUTTON_UP -> PC6 */
#define BUTTON_UP_PORT GPIO_C_NUM #define BUTTON_UP_PORT GPIO_C_NUM
#define BUTTON_UP_PIN 6 #define BUTTON_UP_PIN 6
#define BUTTON_UP_VECTOR NVIC_INT_GPIO_PORT_C #define BUTTON_UP_VECTOR GPIO_C_IRQn
/** BUTTON_DOWN -> PC7 */ /** BUTTON_DOWN -> PC7 */
#define BUTTON_DOWN_PORT GPIO_C_NUM #define BUTTON_DOWN_PORT GPIO_C_NUM
#define BUTTON_DOWN_PIN 7 #define BUTTON_DOWN_PIN 7
#define BUTTON_DOWN_VECTOR NVIC_INT_GPIO_PORT_C #define BUTTON_DOWN_VECTOR GPIO_C_IRQn
/* Notify various examples that we have Buttons */ /* Notify various examples that we have Buttons */
#define PLATFORM_HAS_BUTTON 1 #define PLATFORM_HAS_BUTTON 1

10
platform/cc2538dk/dev/button-sensor.c
View file

@ -135,7 +135,7 @@ config_select(int type, int value)
ioc_set_over(BUTTON_SELECT_PORT, BUTTON_SELECT_PIN, IOC_OVERRIDE_PUE); ioc_set_over(BUTTON_SELECT_PORT, BUTTON_SELECT_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(BUTTON_SELECT_VECTOR); NVIC_EnableIRQ(BUTTON_SELECT_VECTOR);
gpio_register_callback(btn_callback, BUTTON_SELECT_PORT, BUTTON_SELECT_PIN); gpio_register_callback(btn_callback, BUTTON_SELECT_PORT, BUTTON_SELECT_PIN);
return 1; return 1;
@ -159,7 +159,7 @@ config_left(int type, int value)
ioc_set_over(BUTTON_LEFT_PORT, BUTTON_LEFT_PIN, IOC_OVERRIDE_PUE); ioc_set_over(BUTTON_LEFT_PORT, BUTTON_LEFT_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(BUTTON_LEFT_VECTOR); NVIC_EnableIRQ(BUTTON_LEFT_VECTOR);
gpio_register_callback(btn_callback, BUTTON_LEFT_PORT, BUTTON_LEFT_PIN); gpio_register_callback(btn_callback, BUTTON_LEFT_PORT, BUTTON_LEFT_PIN);
return 1; return 1;
@ -183,7 +183,7 @@ config_right(int type, int value)
ioc_set_over(BUTTON_RIGHT_PORT, BUTTON_RIGHT_PIN, IOC_OVERRIDE_PUE); ioc_set_over(BUTTON_RIGHT_PORT, BUTTON_RIGHT_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(BUTTON_RIGHT_VECTOR); NVIC_EnableIRQ(BUTTON_RIGHT_VECTOR);
gpio_register_callback(btn_callback, BUTTON_RIGHT_PORT, BUTTON_RIGHT_PIN); gpio_register_callback(btn_callback, BUTTON_RIGHT_PORT, BUTTON_RIGHT_PIN);
return 1; return 1;
@ -207,7 +207,7 @@ config_up(int type, int value)
ioc_set_over(BUTTON_UP_PORT, BUTTON_UP_PIN, IOC_OVERRIDE_PUE); ioc_set_over(BUTTON_UP_PORT, BUTTON_UP_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(BUTTON_UP_VECTOR); NVIC_EnableIRQ(BUTTON_UP_VECTOR);
gpio_register_callback(btn_callback, BUTTON_UP_PORT, BUTTON_UP_PIN); gpio_register_callback(btn_callback, BUTTON_UP_PORT, BUTTON_UP_PIN);
return 1; return 1;
@ -231,7 +231,7 @@ config_down(int type, int value)
ioc_set_over(BUTTON_DOWN_PORT, BUTTON_DOWN_PIN, IOC_OVERRIDE_PUE); ioc_set_over(BUTTON_DOWN_PORT, BUTTON_DOWN_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(BUTTON_DOWN_VECTOR); NVIC_EnableIRQ(BUTTON_DOWN_VECTOR);
gpio_register_callback(btn_callback, BUTTON_DOWN_PORT, BUTTON_DOWN_PIN); gpio_register_callback(btn_callback, BUTTON_DOWN_PORT, BUTTON_DOWN_PIN);
return 1; return 1;

2
platform/openmote-cc2538/board.h
View file

@ -125,7 +125,7 @@
/** BUTTON_USER -> PC3 */ /** BUTTON_USER -> PC3 */
#define BUTTON_USER_PORT GPIO_C_NUM #define BUTTON_USER_PORT GPIO_C_NUM
#define BUTTON_USER_PIN 3 #define BUTTON_USER_PIN 3
#define BUTTON_USER_VECTOR NVIC_INT_GPIO_PORT_C #define BUTTON_USER_VECTOR GPIO_C_IRQn
/* Notify various examples that we have Buttons */ /* Notify various examples that we have Buttons */
#define PLATFORM_HAS_BUTTON 1 #define PLATFORM_HAS_BUTTON 1
/** @} */ /** @} */

1
platform/openmote-cc2538/contiki-main.c
View file

@ -48,7 +48,6 @@
#include "contiki.h" #include "contiki.h"
#include "dev/leds.h" #include "dev/leds.h"
#include "dev/sys-ctrl.h" #include "dev/sys-ctrl.h"
#include "dev/scb.h"
#include "dev/nvic.h" #include "dev/nvic.h"
#include "dev/uart.h" #include "dev/uart.h"
#include "dev/i2c.h" #include "dev/i2c.h"

4
platform/openmote-cc2538/dev/button-sensor.c
View file

@ -158,10 +158,10 @@ config_user(int type, int value)
case SENSORS_ACTIVE: case SENSORS_ACTIVE:
if(value) { if(value) {
GPIO_ENABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK); GPIO_ENABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK);
nvic_interrupt_enable(BUTTON_USER_VECTOR); NVIC_EnableIRQ(BUTTON_USER_VECTOR);
} else { } else {
GPIO_DISABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK); GPIO_DISABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK);
nvic_interrupt_disable(BUTTON_USER_VECTOR); NVIC_DisableIRQ(BUTTON_USER_VECTOR);
} }
return value; return value;
case BUTTON_SENSOR_CONFIG_TYPE_INTERVAL: case BUTTON_SENSOR_CONFIG_TYPE_INTERVAL:

1
platform/zoul/contiki-main.c
View file

@ -47,7 +47,6 @@
#include "contiki.h" #include "contiki.h"
#include "dev/leds.h" #include "dev/leds.h"
#include "dev/sys-ctrl.h" #include "dev/sys-ctrl.h"
#include "dev/scb.h"
#include "dev/nvic.h" #include "dev/nvic.h"
#include "dev/uart.h" #include "dev/uart.h"
#include "dev/watchdog.h" #include "dev/watchdog.h"

2
platform/zoul/dev/ac-dimmer.c
View file

@ -137,7 +137,7 @@ configure(int type, int value)
/* Enable interrupts */ /* Enable interrupts */
GPIO_ENABLE_INTERRUPT(DIMMER_SYNC_PORT_BASE, DIMMER_SYNC_PIN_MASK); GPIO_ENABLE_INTERRUPT(DIMMER_SYNC_PORT_BASE, DIMMER_SYNC_PIN_MASK);
// ioc_set_over(DIMMER_SYNC_PORT, DIMMER_SYNC_PIN, IOC_OVERRIDE_PUE); // ioc_set_over(DIMMER_SYNC_PORT, DIMMER_SYNC_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(DIMMER_INT_VECTOR); NVIC_EnableIRQ(DIMMER_INT_VECTOR);
enabled = 1; enabled = 1;
dimming = DIMMER_DEFAULT_START_VALUE; dimming = DIMMER_DEFAULT_START_VALUE;

2
platform/zoul/dev/ac-dimmer.h
View file

@ -73,7 +73,7 @@
#ifdef DIMMER_CONF_INT_VECTOR #ifdef DIMMER_CONF_INT_VECTOR
#define DIMMER_INT_VECTOR DIMMER_CONF_INT_VECTOR #define DIMMER_INT_VECTOR DIMMER_CONF_INT_VECTOR
#else #else
#define DIMMER_INT_VECTOR NVIC_INT_GPIO_PORT_A #define DIMMER_INT_VECTOR GPIO_A_IRQn
#endif #endif
/** @} */ /** @} */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */

4
platform/zoul/dev/button-sensor.c
View file

@ -157,10 +157,10 @@ config_user(int type, int value)
case SENSORS_ACTIVE: case SENSORS_ACTIVE:
if(value) { if(value) {
GPIO_ENABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK); GPIO_ENABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK);
nvic_interrupt_enable(BUTTON_USER_VECTOR); NVIC_EnableIRQ(BUTTON_USER_VECTOR);
} else { } else {
GPIO_DISABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK); GPIO_DISABLE_INTERRUPT(BUTTON_USER_PORT_BASE, BUTTON_USER_PIN_MASK);
nvic_interrupt_disable(BUTTON_USER_VECTOR); NVIC_DisableIRQ(BUTTON_USER_VECTOR);
} }
return value; return value;
case BUTTON_SENSOR_CONFIG_TYPE_INTERVAL: case BUTTON_SENSOR_CONFIG_TYPE_INTERVAL:

8
platform/zoul/dev/cc1200-zoul-arch.c
View file

@ -183,7 +183,7 @@ cc1200_arch_gpio0_setup_irq(int rising)
GPIO_ENABLE_INTERRUPT(CC1200_GDO0_PORT_BASE, CC1200_GDO0_PIN_MASK); GPIO_ENABLE_INTERRUPT(CC1200_GDO0_PORT_BASE, CC1200_GDO0_PIN_MASK);
ioc_set_over(CC1200_GDO0_PORT, CC1200_GDO0_PIN, IOC_OVERRIDE_PUE); ioc_set_over(CC1200_GDO0_PORT, CC1200_GDO0_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(CC1200_GPIOx_VECTOR); NVIC_EnableIRQ(CC1200_GPIOx_VECTOR);
gpio_register_callback(cc1200_int_handler, CC1200_GDO0_PORT, gpio_register_callback(cc1200_int_handler, CC1200_GDO0_PORT,
CC1200_GDO0_PIN); CC1200_GDO0_PIN);
} }
@ -205,7 +205,7 @@ cc1200_arch_gpio2_setup_irq(int rising)
GPIO_ENABLE_INTERRUPT(CC1200_GDO2_PORT_BASE, CC1200_GDO2_PIN_MASK); GPIO_ENABLE_INTERRUPT(CC1200_GDO2_PORT_BASE, CC1200_GDO2_PIN_MASK);
ioc_set_over(CC1200_GDO2_PORT, CC1200_GDO2_PIN, IOC_OVERRIDE_PUE); ioc_set_over(CC1200_GDO2_PORT, CC1200_GDO2_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(CC1200_GPIOx_VECTOR); NVIC_EnableIRQ(CC1200_GPIOx_VECTOR);
gpio_register_callback(cc1200_int_handler, CC1200_GDO2_PORT, gpio_register_callback(cc1200_int_handler, CC1200_GDO2_PORT,
CC1200_GDO2_PIN); CC1200_GDO2_PIN);
} }
@ -215,7 +215,7 @@ cc1200_arch_gpio0_enable_irq(void)
{ {
GPIO_ENABLE_INTERRUPT(CC1200_GDO0_PORT_BASE, CC1200_GDO0_PIN_MASK); GPIO_ENABLE_INTERRUPT(CC1200_GDO0_PORT_BASE, CC1200_GDO0_PIN_MASK);
ioc_set_over(CC1200_GDO0_PORT, CC1200_GDO0_PIN, IOC_OVERRIDE_PUE); ioc_set_over(CC1200_GDO0_PORT, CC1200_GDO0_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(CC1200_GPIOx_VECTOR); NVIC_EnableIRQ(CC1200_GPIOx_VECTOR);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -229,7 +229,7 @@ cc1200_arch_gpio2_enable_irq(void)
{ {
GPIO_ENABLE_INTERRUPT(CC1200_GDO2_PORT_BASE, CC1200_GDO2_PIN_MASK); GPIO_ENABLE_INTERRUPT(CC1200_GDO2_PORT_BASE, CC1200_GDO2_PIN_MASK);
ioc_set_over(CC1200_GDO2_PORT, CC1200_GDO2_PIN, IOC_OVERRIDE_PUE); ioc_set_over(CC1200_GDO2_PORT, CC1200_GDO2_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(CC1200_GPIOx_VECTOR); NVIC_EnableIRQ(CC1200_GPIOx_VECTOR);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void

2
platform/zoul/dev/grove-gyro.c
View file

@ -603,7 +603,7 @@ configure(int type, int value)
int_en = 1; int_en = 1;
GPIO_ENABLE_INTERRUPT(GROVE_GYRO_INT_PORT_BASE, GROVE_GYRO_INT_PIN_MASK); GPIO_ENABLE_INTERRUPT(GROVE_GYRO_INT_PORT_BASE, GROVE_GYRO_INT_PIN_MASK);
ioc_set_over(I2C_INT_PORT, I2C_INT_PIN, IOC_OVERRIDE_PUE); ioc_set_over(I2C_INT_PORT, I2C_INT_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(I2C_INT_VECTOR); NVIC_EnableIRQ(I2C_INT_VECTOR);
PRINTF("Gyro: Data interrupt configured\n"); PRINTF("Gyro: Data interrupt configured\n");
return GROVE_GYRO_SUCCESS; return GROVE_GYRO_SUCCESS;

2
platform/zoul/dev/motion-sensor.c
View file

@ -119,7 +119,7 @@ configure(int type, int value)
process_start(&motion_int_process, NULL); process_start(&motion_int_process, NULL);
GPIO_ENABLE_INTERRUPT(MOTION_SENSOR_PORT_BASE, MOTION_SENSOR_PIN_MASK); GPIO_ENABLE_INTERRUPT(MOTION_SENSOR_PORT_BASE, MOTION_SENSOR_PIN_MASK);
nvic_interrupt_enable(MOTION_SENSOR_VECTOR); NVIC_EnableIRQ(MOTION_SENSOR_VECTOR);
return MOTION_SUCCESS; return MOTION_SUCCESS;
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/

2
platform/zoul/dev/rtcc.c
View file

@ -523,7 +523,7 @@ rtcc_set_alarm_time_date(simple_td_map *data, uint8_t state, uint8_t repeat,
} else { } else {
GPIO_ENABLE_INTERRUPT(RTC_INT1_PORT_BASE, RTC_INT1_PIN_MASK); GPIO_ENABLE_INTERRUPT(RTC_INT1_PORT_BASE, RTC_INT1_PIN_MASK);
ioc_set_over(RTC_INT1_PORT, RTC_INT1_PIN, IOC_OVERRIDE_PUE); ioc_set_over(RTC_INT1_PORT, RTC_INT1_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(RTC_INT1_VECTOR); NVIC_EnableIRQ(RTC_INT1_VECTOR);
} }
if (trigger == RTCC_TRIGGER_INT1) { if (trigger == RTCC_TRIGGER_INT1) {

2
platform/zoul/dev/tsl256x.c
View file

@ -453,7 +453,7 @@ configure(int type, int value)
* resistor instead if no external pull-up is present. * resistor instead if no external pull-up is present.
*/ */
ioc_set_over(I2C_INT_PORT, I2C_INT_PIN, IOC_OVERRIDE_PUE); ioc_set_over(I2C_INT_PORT, I2C_INT_PIN, IOC_OVERRIDE_PUE);
nvic_interrupt_enable(I2C_INT_VECTOR); NVIC_EnableIRQ(I2C_INT_VECTOR);
PRINTF("TSL256X: Interrupt configured\n"); PRINTF("TSL256X: Interrupt configured\n");
return TSL256X_SUCCESS; return TSL256X_SUCCESS;

4
platform/zoul/dev/weather-meter.c
View file

@ -449,8 +449,8 @@ configure(int type, int value)
GPIO_ENABLE_INTERRUPT(ANEMOMETER_SENSOR_PORT_BASE, ANEMOMETER_SENSOR_PIN_MASK); GPIO_ENABLE_INTERRUPT(ANEMOMETER_SENSOR_PORT_BASE, ANEMOMETER_SENSOR_PIN_MASK);
GPIO_ENABLE_INTERRUPT(RAIN_GAUGE_SENSOR_PORT_BASE, RAIN_GAUGE_SENSOR_PIN_MASK); GPIO_ENABLE_INTERRUPT(RAIN_GAUGE_SENSOR_PORT_BASE, RAIN_GAUGE_SENSOR_PIN_MASK);
nvic_interrupt_enable(ANEMOMETER_SENSOR_VECTOR); NVIC_EnableIRQ(ANEMOMETER_SENSOR_VECTOR);
nvic_interrupt_enable(RAIN_GAUGE_SENSOR_VECTOR); NVIC_EnableIRQ(RAIN_GAUGE_SENSOR_VECTOR);
enabled = 1; enabled = 1;
PRINTF("Weather: started\n"); PRINTF("Weather: started\n");

4
platform/zoul/dev/weather-meter.h
View file

@ -118,7 +118,7 @@ extern void (*rain_gauge_int_callback)(uint16_t value);
#ifdef WEATHER_METER_CONF_ANEMOMETER_VECTOR #ifdef WEATHER_METER_CONF_ANEMOMETER_VECTOR
#define ANEMOMETER_SENSOR_VECTOR WEATHER_METER_CONF_ANEMOMETER_VECTOR #define ANEMOMETER_SENSOR_VECTOR WEATHER_METER_CONF_ANEMOMETER_VECTOR
#else #else
#define ANEMOMETER_SENSOR_VECTOR NVIC_INT_GPIO_PORT_D #define ANEMOMETER_SENSOR_VECTOR GPIO_D_IRQn
#endif #endif
/** @} */ /** @} */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
@ -139,7 +139,7 @@ extern void (*rain_gauge_int_callback)(uint16_t value);
#ifdef WEATHER_METER_CONF_RAIN_GAUGE_VECTOR #ifdef WEATHER_METER_CONF_RAIN_GAUGE_VECTOR
#define RAIN_GAUGE_SENSOR_VECTOR WEATHER_METER_CONF_RAIN_GAUGE_VECTOR #define RAIN_GAUGE_SENSOR_VECTOR WEATHER_METER_CONF_RAIN_GAUGE_VECTOR
#else #else
#define RAIN_GAUGE_SENSOR_VECTOR NVIC_INT_GPIO_PORT_D #define RAIN_GAUGE_SENSOR_VECTOR GPIO_D_IRQn
#endif #endif
/** @} */ /** @} */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */

6
platform/zoul/firefly-reva/board.h
View file

@ -265,7 +265,7 @@
/** BUTTON_USER -> PA3 */ /** BUTTON_USER -> PA3 */
#define BUTTON_USER_PORT GPIO_A_NUM #define BUTTON_USER_PORT GPIO_A_NUM
#define BUTTON_USER_PIN 3 #define BUTTON_USER_PIN 3
#define BUTTON_USER_VECTOR NVIC_INT_GPIO_PORT_A #define BUTTON_USER_VECTOR GPIO_A_IRQn
/* Notify various examples that we have an user button. /* Notify various examples that we have an user button.
* If ADC6 channel is used, then disable the user button * If ADC6 channel is used, then disable the user button
@ -330,7 +330,7 @@
#define I2C_SDA_PIN 2 #define I2C_SDA_PIN 2
#define I2C_INT_PORT GPIO_D_NUM #define I2C_INT_PORT GPIO_D_NUM
#define I2C_INT_PIN 1 #define I2C_INT_PIN 1
#define I2C_INT_VECTOR NVIC_INT_GPIO_PORT_D #define I2C_INT_VECTOR GPIO_D_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
@ -368,7 +368,7 @@
#define CC1200_GDO2_PIN 0 #define CC1200_GDO2_PIN 0
#define CC1200_RESET_PORT GPIO_C_NUM #define CC1200_RESET_PORT GPIO_C_NUM
#define CC1200_RESET_PIN 7 #define CC1200_RESET_PIN 7
#define CC1200_GPIOx_VECTOR NVIC_INT_GPIO_PORT_B #define CC1200_GPIOx_VECTOR GPIO_B_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**

6
platform/zoul/firefly/board.h
View file

@ -264,7 +264,7 @@
/** BUTTON_USER -> PA3 */ /** BUTTON_USER -> PA3 */
#define BUTTON_USER_PORT GPIO_A_NUM #define BUTTON_USER_PORT GPIO_A_NUM
#define BUTTON_USER_PIN 3 #define BUTTON_USER_PIN 3
#define BUTTON_USER_VECTOR NVIC_INT_GPIO_PORT_A #define BUTTON_USER_VECTOR GPIO_A_IRQn
/* Notify various examples that we have an user button. /* Notify various examples that we have an user button.
* If ADC6 channel is used, then disable the user button * If ADC6 channel is used, then disable the user button
@ -329,7 +329,7 @@
#define I2C_SDA_PIN 2 #define I2C_SDA_PIN 2
#define I2C_INT_PORT GPIO_D_NUM #define I2C_INT_PORT GPIO_D_NUM
#define I2C_INT_PIN 1 #define I2C_INT_PIN 1
#define I2C_INT_VECTOR NVIC_INT_GPIO_PORT_D #define I2C_INT_VECTOR GPIO_D_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
@ -367,7 +367,7 @@
#define CC1200_GDO2_PIN 0 #define CC1200_GDO2_PIN 0
#define CC1200_RESET_PORT GPIO_C_NUM #define CC1200_RESET_PORT GPIO_C_NUM
#define CC1200_RESET_PIN 7 #define CC1200_RESET_PIN 7
#define CC1200_GPIOx_VECTOR NVIC_INT_GPIO_PORT_B #define CC1200_GPIOx_VECTOR GPIO_B_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**

8
platform/zoul/remote-reva/board.h
View file

@ -268,7 +268,7 @@
/** BUTTON_USER -> PA3 */ /** BUTTON_USER -> PA3 */
#define BUTTON_USER_PORT GPIO_A_NUM #define BUTTON_USER_PORT GPIO_A_NUM
#define BUTTON_USER_PIN 3 #define BUTTON_USER_PIN 3
#define BUTTON_USER_VECTOR NVIC_INT_GPIO_PORT_A #define BUTTON_USER_VECTOR GPIO_A_IRQn
/* Notify various examples that we have an user button. /* Notify various examples that we have an user button.
* If ADC6 channel is used, then disable the user button * If ADC6 channel is used, then disable the user button
@ -336,7 +336,7 @@
#define I2C_SDA_PIN 2 #define I2C_SDA_PIN 2
#define I2C_INT_PORT GPIO_D_NUM #define I2C_INT_PORT GPIO_D_NUM
#define I2C_INT_PIN 1 #define I2C_INT_PIN 1
#define I2C_INT_VECTOR NVIC_INT_GPIO_PORT_D #define I2C_INT_VECTOR GPIO_D_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
@ -395,7 +395,7 @@
#define CC1200_GDO2_PIN 0 #define CC1200_GDO2_PIN 0
#define CC1200_RESET_PORT GPIO_C_NUM #define CC1200_RESET_PORT GPIO_C_NUM
#define CC1200_RESET_PIN 7 #define CC1200_RESET_PIN 7
#define CC1200_GPIOx_VECTOR NVIC_INT_GPIO_PORT_B #define CC1200_GPIOx_VECTOR GPIO_B_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
@ -460,7 +460,7 @@
#define RTC_SCL_PIN I2C_SCL_PIN #define RTC_SCL_PIN I2C_SCL_PIN
#define RTC_INT1_PORT GPIO_A_NUM #define RTC_INT1_PORT GPIO_A_NUM
#define RTC_INT1_PIN 4 #define RTC_INT1_PIN 4
#define RTC_INT1_VECTOR NVIC_INT_GPIO_PORT_A #define RTC_INT1_VECTOR GPIO_A_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**

8
platform/zoul/remote-revb/board.h
View file

@ -293,7 +293,7 @@
*/ */
#define BUTTON_USER_PORT GPIO_A_NUM #define BUTTON_USER_PORT GPIO_A_NUM
#define BUTTON_USER_PIN 3 #define BUTTON_USER_PIN 3
#define BUTTON_USER_VECTOR NVIC_INT_GPIO_PORT_A #define BUTTON_USER_VECTOR GPIO_A_IRQn
/* Notify various examples that we have an user button. /* Notify various examples that we have an user button.
* If ADC6 channel is used, then disable the user button * If ADC6 channel is used, then disable the user button
@ -360,7 +360,7 @@
#define I2C_SDA_PIN 2 #define I2C_SDA_PIN 2
#define I2C_INT_PORT GPIO_D_NUM #define I2C_INT_PORT GPIO_D_NUM
#define I2C_INT_PIN 0 #define I2C_INT_PIN 0
#define I2C_INT_VECTOR NVIC_INT_GPIO_PORT_D #define I2C_INT_VECTOR GPIO_D_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
@ -419,7 +419,7 @@
#define CC1200_GDO2_PIN 0 #define CC1200_GDO2_PIN 0
#define CC1200_RESET_PORT GPIO_C_NUM #define CC1200_RESET_PORT GPIO_C_NUM
#define CC1200_RESET_PIN 7 #define CC1200_RESET_PIN 7
#define CC1200_GPIOx_VECTOR NVIC_INT_GPIO_PORT_B #define CC1200_GPIOx_VECTOR GPIO_B_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
@ -487,7 +487,7 @@
#define RTC_SCL_PIN I2C_SCL_PIN #define RTC_SCL_PIN I2C_SCL_PIN
#define RTC_INT1_PORT GPIO_D_NUM #define RTC_INT1_PORT GPIO_D_NUM
#define RTC_INT1_PIN 3 #define RTC_INT1_PIN 3
#define RTC_INT1_VECTOR NVIC_INT_GPIO_PORT_D #define RTC_INT1_VECTOR GPIO_D_IRQn
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**