x86: Add support for (paging-based) protection domains
This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
This commit is contained in:
Michael LeMay
parent
b0de416682
commit
3908253038
48 changed files with 3558 additions and 295 deletions
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@ -28,11 +28,13 @@
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu.h"
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#include "gdt.h"
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#include "helpers.h"
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#include "idt.h"
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#include "interrupt.h"
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#include "irq.h"
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#include "stacks.h"
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static void
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double_fault_handler(struct interrupt_context context)
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@ -40,16 +42,79 @@ double_fault_handler(struct interrupt_context context)
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halt();
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}
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/*---------------------------------------------------------------------------*/
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void
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cpu_init(void)
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/* The OS has switched to its own segment descriptors. However, the protection
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* domain support, if enabled, has not yet been fully activated.
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*/
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static void
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boot_stage1(void)
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{
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gdt_init();
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idt_init();
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/* Set an interrupt handler for Double Fault exception. This way, we avoid
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* the system to triple fault, leaving no trace about what happened.
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*/
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SET_INTERRUPT_HANDLER(8, 1, double_fault_handler);
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SET_EXCEPTION_HANDLER(8, 1, double_fault_handler);
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irq_init();
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/* Initialize protection domain support, if enabled */
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prot_domains_init();
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prot_domains_leave_boot_stage1();
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}
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/*---------------------------------------------------------------------------*/
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int main(void);
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/* This routine runs with the initial, flat address space, even if protection
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* domain support is enabled. The goal behind the design of this routine is to
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* keep it as short as possible, since it is unable to directly reference data
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* and invoke functions that are intended to be accessible later after the
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* system has booted when a multi-segment protection domain model is in use.
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*/
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void
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cpu_boot_stage0(void)
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{
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/* Reserve three stack slots for return addresses */
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uintptr_t top_of_stack = STACKS_INIT_TOP;
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#if X86_CONF_PROT_DOMAINS != X86_CONF_PROT_DOMAINS__NONE
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uintptr_t *top_of_stack_ptr = (uintptr_t *)top_of_stack;
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top_of_stack_ptr[0] = (uintptr_t)prot_domains_launch_kernel;
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top_of_stack_ptr[1] = (uintptr_t)prot_domains_launch_app;
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#endif
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/* Perform common GDT initialization */
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gdt_init();
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/* Switch all data segment registers to the newly-initialized flat data
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* descriptor.
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*/
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__asm__(
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"mov %0, %%ds\n\t"
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"mov %0, %%es\n\t"
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"mov %0, %%fs\n\t"
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"mov %0, %%gs\n\t"
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:
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: "r" (GDT_SEL_DATA_FLAT)
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);
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/**
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* Perform specific GDT initialization tasks for the protection domain
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* implementation that is enabled, if any.
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*/
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prot_domains_gdt_init();
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/* Do not pass memory operands to the asm block below, since it is
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* switching from the flat address space to a multi-segment address space
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* model if such a model is used by the enabled protection domain
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* implementation, if any.
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*/
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__asm__(
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"mov %[_ss_], %%ss\n\t"
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"mov %[_esp_], %%esp\n\t"
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"ljmp %[_cs_], %[_stage1_]\n\t"
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:
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: [_ss_] "r" (GDT_SEL_STK_EXC),
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[_esp_] "r" (top_of_stack),
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[_cs_] "i" ((uint16_t)GDT_SEL_CODE_EXC),
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[_stage1_] "i" (boot_stage1)
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);
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}
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@ -31,6 +31,8 @@
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#ifndef CPU_H
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#define CPU_H
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void cpu_init(void);
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#include "prot-domains.h"
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void cpu_boot_stage0(void) ATTR_CODE_BOOT;
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#endif /* CPU_H */
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@ -29,45 +29,15 @@
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*/
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#include <stdint.h>
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#include "gdt.h"
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#include "gdt-layout.h"
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#include "helpers.h"
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#include "prot-domains.h"
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#include "segmentation.h"
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#define NUM_DESC 3
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#define GDT_IDX_NULL 0
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#define GDT_IDX_CODE 1
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#define GDT_IDX_DATA 2
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/* All code in the x86 port of Contiki runs at ring (privilege) level 0 */
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#define PRIV_LVL 0
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/* Compute GDT selector from descriptor index and requested privilege level */
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#define GDT_SEL(IDX, RPL) (((IDX) << 3) | (RPL))
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#define GDT_SEL_NULL GDT_SEL(GDT_IDX_NULL, 0)
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#define GDT_SEL_CODE GDT_SEL(GDT_IDX_CODE, PRIV_LVL)
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#define GDT_SEL_DATA GDT_SEL(GDT_IDX_DATA, PRIV_LVL)
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/* Each define here is for a specific flag in the descriptor. Refer to Intel
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* Combined Manual (Intel 64 and IA-32 Architectures Software Developer's
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* Manual), Vol. 3, Section 3.4.5 for a description of each flag.
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*/
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#define SEG_DESCTYPE(x) ((x) << 0x04) /* Descriptor type (0 for system, 1 for code/data) */
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#define SEG_PRES(x) ((x) << 0x07) /* Present */
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#define SEG_SAVL(x) ((x) << 0x0C) /* Available for system use */
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#define SEG_LONG(x) ((x) << 0x0D) /* Long mode */
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#define SEG_SIZE(x) ((x) << 0x0E) /* Size (0 for 16-bit, 1 for 32) */
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#define SEG_GRAN(x) ((x) << 0x0F) /* Granularity (0 for 1B - 1MB, 1 for 4KB - 4GB) */
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#define SEG_PRIV(x) (((x) & 0x03) << 0x05) /* Set privilege level (0 - 3) */
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#define SEG_DATA_RDWR 0x02 /* Read/Write */
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#define SEG_CODE_EXRD 0x0A /* Execute/Read */
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#define GDT_CODE_PL0 SEG_DESCTYPE(1) | SEG_PRES(1) | SEG_SAVL(0) | \
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SEG_LONG(0) | SEG_SIZE(1) | SEG_GRAN(1) | \
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SEG_PRIV(0) | SEG_CODE_EXRD
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#define GDT_DATA_PL0 SEG_DESCTYPE(1) | SEG_PRES(1) | SEG_SAVL(0) | \
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SEG_LONG(0) | SEG_SIZE(1) | SEG_GRAN(1) | \
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SEG_PRIV(0) | SEG_DATA_RDWR
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#define GDT_MEM_PL0 (SEG_DESCTYPE_NSYS | SEG_GRAN_PAGE)
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#define GDT_CODE_PL0 (GDT_MEM_PL0 | SEG_TYPE_CODE_EXRD)
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#define GDT_DATA_PL0 (GDT_MEM_PL0 | SEG_TYPE_DATA_RDWR)
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typedef struct gdtr
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{
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@ -75,41 +45,53 @@ typedef struct gdtr
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uint32_t base;
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} __attribute__((packed)) gdtr_t;
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typedef uint64_t segment_desc_t;
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/* From Intel Combined Manual, Vol. 3 , Section 3.5.1: The base addresses of
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* the GDT should be aligned on an eight-byte boundary to yield the best
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* processor performance.
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*/
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static segment_desc_t gdt[NUM_DESC] __attribute__ ((aligned (8)));
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segment_desc_t __attribute__ ((aligned(8))) ATTR_BSS_GDT_START
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gdt[GDT_NUM_FIXED_DESC];
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static void
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set_descriptor(unsigned int index, uint32_t base, uint32_t limit, uint16_t flag)
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#define GDT_LEN \
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((((uintptr_t)&_ebss_gdt_addr) - \
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(uintptr_t)gdt)/sizeof(segment_desc_t))
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/*---------------------------------------------------------------------------*/
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static void ATTR_CODE_BOOT
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set_descriptor(unsigned int index,
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uint32_t base,
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uint32_t len,
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uint16_t flag)
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{
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segment_desc_t descriptor;
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if (index >= NUM_DESC)
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return;
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if(GDT_LEN <= index) {
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halt();
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}
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/* Create the high 32 bit segment */
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descriptor = limit & 0x000F0000; /* set limit bits 19:16 */
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descriptor |= (flag << 8) & 0x00F0FF00; /* set type, p, dpl, s, g, d/b, l and avl fields */
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descriptor |= (base >> 16) & 0x000000FF; /* set base bits 23:16 */
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descriptor |= base & 0xFF000000; /* set base bits 31:24 */
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/* Shift by 32 to allow for low part of segment */
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descriptor <<= 32;
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/* Create the low 32 bit segment */
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descriptor |= base << 16; /* set base bits 15:0 */
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descriptor |= limit & 0x0000FFFF; /* set limit bits 15:0 */
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segment_desc_init(&descriptor, base, len, flag);
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/* Save descriptor into gdt */
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gdt[index] = descriptor;
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}
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/*---------------------------------------------------------------------------*/
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void
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gdt_copy_desc_change_dpl(unsigned int dest_idx,
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unsigned int src_idx,
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unsigned dpl)
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{
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segment_desc_t desc;
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if((GDT_LEN <= dest_idx) || (GDT_LEN <= src_idx)) {
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halt();
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}
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/* This function initializes the Global Offset Table. For simplicity, the
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desc = gdt[src_idx];
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SEG_SET_FLAG(desc, DPL, dpl);
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gdt[dest_idx] = desc;
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}
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/*---------------------------------------------------------------------------*/
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/* This function initializes the Global Descriptor Table. For simplicity, the
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* memory is organized following the flat model. Thus, memory appears to
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* Contiki as a single continuous address space. Code, data, and stack
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* are all contained in this address space (so called linear address space).
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gdtr_t gdtr;
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/* Initialize gdtr structure */
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gdtr.limit = sizeof(segment_desc_t) * NUM_DESC - 1;
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gdtr.limit = sizeof(segment_desc_t) * GDT_LEN - 1;
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gdtr.base = (uint32_t) &gdt;
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/* Initialize descriptors */
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set_descriptor(GDT_IDX_NULL, 0, 0, 0);
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set_descriptor(GDT_IDX_CODE, 0, 0x0FFFFF, GDT_CODE_PL0);
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set_descriptor(GDT_IDX_DATA, 0, 0x0FFFFF, GDT_DATA_PL0);
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set_descriptor(GDT_IDX_CODE_FLAT, 0, 0x100000, GDT_CODE_PL0);
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set_descriptor(GDT_IDX_DATA_FLAT, 0, 0x100000, GDT_DATA_PL0);
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/* Load GDTR register and update segment registers.
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*
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* CS register cannot be changed directly. For that reason, we do a far jump.
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*/
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__asm__ ("lgdt %[_gdtr_]\n\t"
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"jmp %[_cs_], $1f\n\t"
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"1:\n\t"
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"mov %[_ds_], %%ds\n\t"
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"mov %[_ds_], %%ss\n\t"
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"mov %[_ds_], %%es\n\t"
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"mov %[_ds_], %%fs\n\t"
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"mov %[_ds_], %%gs\n\t"
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:
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: [_gdtr_] "m" (gdtr),
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[_cs_] "i" (GDT_SEL_CODE),
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[_ds_] "r" (GDT_SEL_DATA)
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);
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/* Load GDTR */
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__asm__ __volatile__ ("lgdt %0" :: "m" (gdtr));
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}
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/*---------------------------------------------------------------------------*/
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void
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gdt_insert(unsigned int idx, segment_desc_t desc)
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{
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if(GDT_LEN <= idx) {
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halt();
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}
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gdt[idx] = desc;
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}
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/*---------------------------------------------------------------------------*/
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void
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gdt_lookup(unsigned int idx, segment_desc_t *desc)
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{
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if((GDT_LEN <= idx) || (desc == NULL)) {
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halt();
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}
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*desc = gdt[idx];
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}
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/*---------------------------------------------------------------------------*/
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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* Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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#ifndef GDT_H
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#define GDT_H
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void gdt_init(void);
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#include "gdt-layout.h"
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#include "prot-domains.h"
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#include "segmentation.h"
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extern segment_desc_t gdt[];
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extern int _ebss_gdt_addr;
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#define GDT_IDX_OF_DESC(ptr) \
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((((uintptr_t)(ptr)) - ((uintptr_t)&gdt))/ \
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sizeof(segment_desc_t))
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/**
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* \brief Compute the selector for a GDT entry allocated somewhere besides gdt.c.
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* \param ptr Pointer to GDT descriptor.
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* \param rpl Requested Privilege Level.
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*/
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#define GDT_SEL_OF_DESC(ptr, rpl) GDT_SEL(GDT_IDX_OF_DESC(ptr), rpl)
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#define ATTR_BSS_GDT __attribute__((section(".gdt_bss")))
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#define ATTR_BSS_GDT_START __attribute__((section(".gdt_bss_start")))
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void gdt_copy_desc_change_dpl(unsigned int dest_idx,
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unsigned int src_idx,
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unsigned dpl);
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void gdt_init(void) ATTR_CODE_BOOT;
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void gdt_insert(unsigned int idx, segment_desc_t desc);
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void gdt_lookup(unsigned int idx, segment_desc_t *desc);
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#endif /* GDT_H */
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gdt-layout.h"
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#include "prot-domains.h"
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#include <stdint.h>
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#include "helpers.h"
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#include "segmentation.h"
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#include "idt.h"
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#define NUM_DESC 256
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* of the IDT should be aligned on an 8-byte boundary to maximize performance
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* of cache line fills.
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*/
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static intr_gate_desc_t idt[NUM_DESC] __attribute__ ((aligned(8)));
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static intr_gate_desc_t __attribute__((aligned(8))) ATTR_BSS_KERN
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idt[NUM_DESC];
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/*---------------------------------------------------------------------------*/
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/* XXX: If you change this function prototype, make sure you fix the assembly
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* code in SET_INTERRUPT_HANDLER macro in interrupt.h. Otherwise, you might
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* code in SET_INT_EXC_HANDLER macro in interrupt.h. Otherwise, you might
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* face a very-hard-to-find bug in the interrupt handling system.
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*/
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void
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idt_set_intr_gate_desc(int intr_num, uint32_t offset)
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idt_set_intr_gate_desc(int intr_num,
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uint32_t offset,
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uint16_t cs,
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uint16_t dpl)
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{
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intr_gate_desc_t *desc = &idt[intr_num];
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desc->offset_low = offset & 0xFFFF;
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desc->selector = 0x08; /* Offset in GDT for code segment */
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desc->selector = cs;
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desc->fixed = BIT(9) | BIT(10);
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desc->d = 1;
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desc->dpl = 0;
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desc->dpl = dpl;
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desc->p = 1;
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desc->offset_high = (offset >> 16) & 0xFFFF;
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}
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@ -32,8 +32,12 @@
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#define IDT_H
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#include <stdint.h>
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#include "prot-domains.h"
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void idt_init(void);
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void idt_set_intr_gate_desc(int intr_num, uint32_t offset);
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void idt_init(void) ATTR_CODE_BOOT;
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void idt_set_intr_gate_desc(int intr_num,
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uint32_t offset,
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uint16_t cs,
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uint16_t dpl);
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#endif /* IDT_H */
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@ -32,10 +32,17 @@
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#define INTERRUPT_H
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#include <stdint.h>
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#include "gdt-layout.h"
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#include "idt.h"
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struct interrupt_context {
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/* The general-purpose register values are saved by the pushal instruction in
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* the interrupt dispatcher. Having access to these saved values may be
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* useful in some future interrupt or exception handler, and saving and later
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* restoring them also enables the ISR to freely overwrite the EAX, ECX, and
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* EDX registers as is permitted by the cdecl calling convention.
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*/
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uint32_t edi;
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uint32_t esi;
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uint32_t ebp;
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@ -44,16 +51,28 @@ struct interrupt_context {
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uint32_t edx;
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uint32_t ecx;
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uint32_t eax;
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/* These two values are pushed on the stack by the CPU when it delivers an
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* exception with an associated error code. Currently, only the double fault
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* handler accepts this structure as a parameter, and that type of exception
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* does have an associated error code.
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*/
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uint32_t error_code;
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uint32_t eip;
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/* The CPU pushes additional values beyond these on the stack, specifically
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* the code segment descriptor and flags. If a privilege-level change occurs
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* during delivery, the CPU additionally pushes the stack pointer and stack
|
||||
* segment descriptor.
|
||||
*/
|
||||
};
|
||||
|
||||
#define ISR_STUB(label_str, has_error_code, handler_str) \
|
||||
#define ISR_STUB(label_str, has_error_code, handler_str, exc) \
|
||||
"jmp 2f\n\t" \
|
||||
".align 4\n\t" \
|
||||
label_str ":\n\t" \
|
||||
" pushal\n\t" \
|
||||
PROT_DOMAINS_ENTER_ISR(exc) \
|
||||
" call " handler_str "\n\t" \
|
||||
PROT_DOMAINS_LEAVE_ISR(exc) \
|
||||
" popal\n\t" \
|
||||
" .if " #has_error_code "\n\t" \
|
||||
" add $4, %%esp\n\t" \
|
||||
|
|
@ -72,6 +91,14 @@ struct interrupt_context {
|
|||
* void handler(void)
|
||||
* Otherwise, it should be:
|
||||
* void handler(struct interrupt_context context)
|
||||
* exc: 0 if this is an interrupt, which should be handled
|
||||
* at the interrupt privilege level. 1 if this is an
|
||||
* exception, which should be handled at the
|
||||
* exception privilege level.
|
||||
* dpl: Privilege level for IDT descriptor, which is the
|
||||
* numerically-highest privilege level that can
|
||||
* generate this interrupt with a software interrupt
|
||||
* instruction.
|
||||
*
|
||||
* Since there is no easy way to write an Interrupt Service Routines
|
||||
* (ISR) in C (for further information on this, see [1]), we provide
|
||||
|
|
@ -81,18 +108,30 @@ struct interrupt_context {
|
|||
*
|
||||
* [1] http://wiki.osdev.org/Interrupt_Service_Routines
|
||||
*/
|
||||
#define SET_INTERRUPT_HANDLER(num, has_error_code, handler) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"push $1f\n\t" \
|
||||
"push %0\n\t" \
|
||||
"call %P1\n\t" \
|
||||
"add $8, %%esp\n\t" \
|
||||
ISR_STUB("1", has_error_code, "%P2") \
|
||||
:: "g" (num), "i" (idt_set_intr_gate_desc), "i" (handler) \
|
||||
: "eax", "ecx", "edx" \
|
||||
); \
|
||||
#define SET_INT_EXC_HANDLER(num, has_error_code, handler, exc, dpl) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"pushl %[_dpl_]\n\t" \
|
||||
"pushl %[_cs_]\n\t" \
|
||||
"pushl $1f\n\t" \
|
||||
"pushl %[_isr_num_]\n\t" \
|
||||
"call idt_set_intr_gate_desc\n\t" \
|
||||
"add $16, %%esp\n\t" \
|
||||
ISR_STUB("1", has_error_code, "%P[_handler_]", exc) \
|
||||
: \
|
||||
: [_isr_num_] "g" (num), \
|
||||
[_handler_] "i" (handler), \
|
||||
[_cs_] "i" (exc ? GDT_SEL_CODE_EXC : GDT_SEL_CODE_INT), \
|
||||
[_dpl_] "i" (dpl) \
|
||||
/* the invocation of idt_set_intr_gate_desc may clobber */ \
|
||||
/* the caller-saved registers: */ \
|
||||
: "eax", "ecx", "edx" \
|
||||
); \
|
||||
} while (0)
|
||||
#define SET_INTERRUPT_HANDLER(num, has_error_code, handler) \
|
||||
SET_INT_EXC_HANDLER(num, has_error_code, handler, 0, PRIV_LVL_INT)
|
||||
#define SET_EXCEPTION_HANDLER(num, has_error_code, handler) \
|
||||
SET_INT_EXC_HANDLER(num, has_error_code, handler, 1, PRIV_LVL_EXC)
|
||||
|
||||
/* Disable maskable hardware interrupts */
|
||||
#define DISABLE_IRQ() \
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue