3908253038
This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gdt-layout.h"
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#include "prot-domains.h"
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#include <stdint.h>
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#include "helpers.h"
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#include "segmentation.h"
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#include "idt.h"
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#define NUM_DESC 256
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typedef struct idtr {
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uint16_t limit;
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uint32_t base;
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} __attribute__((packed)) idtr_t;
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typedef struct intr_gate_desc {
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uint16_t offset_low;
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uint16_t selector; /* Segment Selector for destination code segment */
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uint16_t fixed:11;
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uint16_t d:1; /* Size of gate: 1 = 32 bits; 0 = 16 bits */
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uint16_t pad:1;
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uint16_t dpl:2; /* Descriptor Privilege Level */
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uint16_t p:1; /* Segment Present flag */
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uint16_t offset_high;
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} __attribute__((packed)) intr_gate_desc_t;
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/* According to Intel Combined Manual, Vol. 3, Section 6.10, the base addresses
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* of the IDT should be aligned on an 8-byte boundary to maximize performance
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* of cache line fills.
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*/
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static intr_gate_desc_t __attribute__((aligned(8))) ATTR_BSS_KERN
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idt[NUM_DESC];
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/*---------------------------------------------------------------------------*/
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/* XXX: If you change this function prototype, make sure you fix the assembly
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* code in SET_INT_EXC_HANDLER macro in interrupt.h. Otherwise, you might
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* face a very-hard-to-find bug in the interrupt handling system.
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*/
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void
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idt_set_intr_gate_desc(int intr_num,
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uint32_t offset,
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uint16_t cs,
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uint16_t dpl)
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{
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intr_gate_desc_t *desc = &idt[intr_num];
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desc->offset_low = offset & 0xFFFF;
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desc->selector = cs;
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desc->fixed = BIT(9) | BIT(10);
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desc->d = 1;
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desc->dpl = dpl;
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desc->p = 1;
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desc->offset_high = (offset >> 16) & 0xFFFF;
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}
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/*---------------------------------------------------------------------------*/
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/* Initialize Interrupt Descriptor Table. The IDT is initialized with
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* null descriptors. Therefore, any interrupt at this point will cause
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* a triple fault.
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*/
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void
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idt_init(void)
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{
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idtr_t idtr;
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/* Initialize idtr structure */
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idtr.limit = (sizeof(intr_gate_desc_t) * NUM_DESC) - 1;
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idtr.base = (uint32_t)&idt;
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/* Load IDTR register */
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__asm__("lidt %0\n\t" :: "m" (idtr));
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}
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