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x86: Add support for (paging-based) protection domains

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This patch implements a simple, lightweight form of protection domains
using a pluggable framework.  Currently, the following plugin is
available:

 - Flat memory model with paging.

The overall goal of a protection domain implementation within this
framework is to define a set of resources that should be accessible to
each protection domain and to prevent that protection domain from
accessing other resources.  The details of each implementation of
protection domains may differ substantially, but they should all be
guided by the principle of least privilege.  However, that idealized
principle is balanced against the practical objectives of limiting the
number of relatively time-consuming context switches and minimizing
changes to existing code.

For additional information, please refer to cpu/x86/mm/README.md.

This patch also causes the C compiler to be used as the default linker
and assembler.
This commit is contained in:
Michael LeMay 2015-08-10 08:34:02 -07:00
parent b0de416682
commit 3908253038
48 changed files with 3558 additions and 295 deletions
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63
cpu/x86/drivers/legacy_pc/uart-16x50.c
View file

@ -28,9 +28,12 @@
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "uart-16x50.h"
#include <stdlib.h>
#include "helpers.h"
#include "paging.h"
#include "prot-domains.h"
#include "syscalls.h"
#include "uart-16x50.h"
/* Refer to Intel Quark SoC X1000 Datasheet, Chapter 18 for more details on
* UART operation.
@ -64,24 +67,22 @@ typedef struct uart_16x50_regs {
volatile uint32_t mcr, lsr, msr, scr, usr, htx, dmasa;
} uart_16x50_regs_t;
/*---------------------------------------------------------------------------*/
/**
* \brief Initialize an MMIO-programmable 16X50 UART.
* \param c_this Structure that will be initialized to represent the device.
* \param pci_addr PCI address of device.
* \param dl Divisor setting to configure the baud rate.
#if X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__PAGING
/* When paging-based protection domains are in use, at least one page of memory
* must be reserved to facilitate access to the MMIO region, since that is the
* smallest unit of memory that can be managed with paging:
*/
void
uart_16x50_init(uart_16x50_driver_t *c_this,
pci_config_addr_t pci_addr,
uint16_t dl)
{
/* This assumes that the UART had an MMIO range assigned to it by the
* firmware during boot.
*/
pci_init(c_this, pci_addr, 0);
#define UART_MMIO_SZ MIN_PAGE_SIZE
#else
#define UART_MMIO_SZ sizeof(uart_16x50_regs_t)
#endif
uart_16x50_regs_t *regs = (uart_16x50_regs_t *)c_this->mmio;
void uart_16x50_setup(uart_16x50_driver_t c_this, uint16_t dl);
/*---------------------------------------------------------------------------*/
SYSCALLS_DEFINE(uart_16x50_setup, uart_16x50_driver_t c_this, uint16_t dl)
{
uart_16x50_regs_t *regs = (uart_16x50_regs_t *)PROT_DOMAINS_MMIO(c_this);
/* Set the DLAB bit to enable access to divisor settings. */
regs->lcr = UART_LCR_7_DLAB;
@ -109,10 +110,9 @@ uart_16x50_init(uart_16x50_driver_t *c_this,
* This procedure will block indefinitely until the UART is ready
* to accept the character to be transmitted.
*/
void
uart_16x50_tx(uart_16x50_driver_t c_this, uint8_t c)
SYSCALLS_DEFINE(uart_16x50_tx, uart_16x50_driver_t c_this, uint8_t c)
{
struct uart_16x50_regs *regs = (uart_16x50_regs_t *)c_this.mmio;
uart_16x50_regs_t *regs = (uart_16x50_regs_t *)PROT_DOMAINS_MMIO(c_this);
/* Wait for space in TX FIFO. */
while((regs->lsr & UART_LSR_5_THRE) == 0);
@ -121,3 +121,26 @@ uart_16x50_tx(uart_16x50_driver_t c_this, uint8_t c)
regs->rbr_thr_dll = c;
}
/*---------------------------------------------------------------------------*/
/**
* \brief Initialize an MMIO-programmable 16X50 UART.
* \param c_this Structure that will be initialized to represent the device.
* \param pci_addr PCI address of device.
* \param dl Divisor setting to configure the baud rate.
*/
void
uart_16x50_init(uart_16x50_driver_t *c_this,
pci_config_addr_t pci_addr,
uint16_t dl)
{
/* This assumes that the UART had an MMIO range assigned to it by the
* firmware during boot.
*/
pci_init(c_this, pci_addr, UART_MMIO_SZ, 0, 0);
SYSCALLS_INIT(uart_16x50_setup);
SYSCALLS_AUTHZ(uart_16x50_setup, *c_this);
SYSCALLS_INIT(uart_16x50_tx);
SYSCALLS_AUTHZ(uart_16x50_tx, *c_this);
uart_16x50_setup(*c_this, dl);
}
/*---------------------------------------------------------------------------*/