2010-08-24 18:23:20 +02:00
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/*
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* Copyright (c) 2006, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)$Id: spix.c,v 1.1 2010/08/24 16:23:20 joxe Exp $
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*/
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2011-05-25 17:21:51 +02:00
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#include "contiki.h"
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2010-08-24 18:23:20 +02:00
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/*
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* This is SPI initialization code for the MSP430X architecture.
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*
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*/
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unsigned char spi_busy = 0;
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/*
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* Initialize SPI bus.
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*/
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void
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spi_init(void)
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{
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//static unsigned char spi_inited = 0;
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//if (spi_inited)
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//return;
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// Initalize ports for communication with SPI units.
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UCB0CTL1 |= UCSWRST; //reset usci
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UCB0CTL1 |= UCSSEL_2; //smclk while usci is reset
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UCB0CTL0 = ( UCMSB | UCMST | UCSYNC | UCCKPL); // MSB-first 8-bit, Master, Synchronous, 3 pin SPI master, no ste, watch-out for clock-phase UCCKPH
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UCB0BR1 = 0x00;
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UCB0BR0 = 0x02;
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// UCB0MCTL = 0; // Dont need modulation control.
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P3SEL |= BV(SCK) | BV(MOSI) | BV(MISO); // Select Peripheral functionality
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P3DIR |= BV(SCK) | BV(MISO); // Configure as outputs(SIMO,CLK).
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//ME1 |= USPIE0; // Module enable ME1 --> U0ME? xxx/bg
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// Clear pending interrupts before enable!!!
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IFG2 &= ~UCB0RXIFG;
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IFG2 &= ~UCB0TXIFG;
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UCB0CTL1 &= ~UCSWRST; // Remove RESET before enabling interrupts
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//Enable UCB0 Interrupts
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//IE2 |= UCB0TXIE; // Enable USCI_B0 TX Interrupts
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//IE2 |= UCB0RXIE; // Enable USCI_B0 RX Interrupts
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}
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