61 lines
2.5 KiB
C
61 lines
2.5 KiB
C
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/*
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* Copyright (c) 2011, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "contiki.h"
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/*
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* This is SPI initialization code for the MSP430X architecture.
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*
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*/
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unsigned char spi_busy = 0;
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/*
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* Initialize SPI bus.
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*/
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void
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spi_init(void)
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{
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UCB0CTL1 |= UCSWRST; // Put state machine in reset
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UCB0CTL1 = UCSSEL0 | UCSSEL1; // Select ACLK
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UCB0CTL0 |= UCCKPH | UCSYNC | UCMSB | UCMST; // 3-pin, 8-bit SPI master, rising edge capture
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// 16 bit baud rate register
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UCB0BR0 = 0x00; // MSB => 0
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UCB0BR1 = 0x08; // LSB => SMCLK / (UCxxBR0 + UCxxBR1 <20> 256)
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// Set MOSI and SCLK as OUT and MISO as IN ports
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P3SEL |= ( BIT1 + BIT2 + BIT3 ); // Port3 = SPI peripheral
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P3DIR |= ( BIT1 + BIT3 ); // MOSI and SCLK as Output
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P3DIR &= ~BIT2; // Don't forget to configure MISO as Input
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P3DIR |= BIT0;
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UCB0CTL1 &= ~UCSWRST; // Initialize USCI state machine
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}
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