4cdb7ba9b6
This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
131 lines
6.7 KiB
C
131 lines
6.7 KiB
C
/*
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* Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_MM_TSS_PROT_DOMAINS_H_
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#define CPU_X86_MM_TSS_PROT_DOMAINS_H_
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "ldt-layout.h"
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#include "segmentation.h"
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#include "tss.h"
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struct dom_kern_data {
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/** Task State Segment */
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tss_t tss;
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/** Local Descriptor Table with per-domain descriptors */
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segment_desc_t ldt[LDT_NUM_DESC];
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} __attribute__((packed));
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/* relies on dom_kern_data: */
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#include "multi-segment.h"
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/* relies on ATTR_KERN_ADDR_SPACE: */
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#include "syscalls.h"
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/**
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* Data associated with each protection domain that is owned by clients of that
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* domain and used to identify the domain.
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*/
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struct dom_client_data {
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dom_id_t dom_id;
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/** The selector is only 16 bits, but it is padded to 32 bits. */
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uint32_t tss_sel;
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};
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extern uint32_t prot_domains_main_esp;
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#define SYSCALLS_STUB_MIDDLE(nm) \
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/* If already in the callee protection domain, skip the protection */ \
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/* domain switch and directly invoke the system call body */ \
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" je _syscall_" #nm "\n\t" \
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" movl $" EXP_STRINGIFY(_syscall_ent_##nm) ", prot_domains_syscall\n\t" \
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" mov %esp, prot_domains_main_esp\n\t"
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#define SYSCALLS_STUB(nm) \
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SYSCALLS_ALLOC_ENTRYPOINT(nm); \
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asm ( \
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".text\n\t" \
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".global " #nm "\n\t" \
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#nm ":\n\t" \
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" str %ax\n\t" \
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/* Compare current Task Register selector to selector for callee */ \
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/* protection domain, in tss_sel field of dom_client_data */ \
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" cmpw %ax, 8(%esp)\n\t" \
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SYSCALLS_STUB_MIDDLE(nm) \
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/* This will treat the dom_id field as the offset for the call, but */ \
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/* that is ignored when performing a far call to a task */ \
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" lcall *4(%esp)\n\t" \
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" ret\n\t")
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#define SYSCALLS_STUB_SINGLETON(nm, dcd) \
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SYSCALLS_ALLOC_ENTRYPOINT(nm); \
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asm ( \
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".text\n\t" \
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".global " #nm "\n\t" \
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#nm ":\n\t" \
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" str %ax\n\t" \
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/* Compare current Task Register selector to selector for callee */ \
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/* protection domain, in tss_sel field of dom_client_data */ \
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" cmpw %ax, %" SEG_KERN "s:(4 + " #dcd ")\n\t" \
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SYSCALLS_STUB_MIDDLE(nm) \
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/* This will treat the dom_id field as the offset for the call, but */ \
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/* that is ignored when performing a far call to a task */ \
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" lcall *%" SEG_KERN "s:" #dcd "\n\t" \
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" ret\n\t")
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#define PROT_DOMAINS_ENTER_ISR(exc) \
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MULTI_SEGMENT_ENTER_ISR(exc) \
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/* It is possible that the system call dispatcher is being interrupted, */ \
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/* and some interrupt handlers perform system calls. Thus, it is */ \
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/* necessary to save and restore the system call dispatcher parameters */ \
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/* (in callee-saved registers). */ \
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"mov prot_domains_main_esp, %%esi\n\t" \
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"mov prot_domains_syscall, %%edi\n\t" \
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PROT_DOMAINS_ENTER_ISR_COMMON(exc)
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#define PROT_DOMAINS_LEAVE_ISR(exc) \
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PROT_DOMAINS_LEAVE_ISR_COMMON(exc) \
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"mov %%edi, prot_domains_syscall\n\t" \
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"mov %%esi, prot_domains_main_esp\n\t" \
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MULTI_SEGMENT_LEAVE_ISR(exc)
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/* Allocate two additional GDT entries for each protection domain. Note that
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* the particular storage allocated by this statement may actually be used for
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* some other protection domain, depending on how the linker happens to arrange
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* all of the GDT storage. The GDT_IDX_TSS and GDT_IDX_LDT macros in
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* gdt-layout.h determine which storage is used for each protection domain.
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* Thus, this storage should not be referenced directly by its variable name.
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*/
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#define PROT_DOMAINS_ALLOC_IMPL(nm) \
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static segment_desc_t ATTR_BSS_GDT_MID _gdt_storage_##nm[2]
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#endif /* CPU_X86_MM_TSS_PROT_DOMAINS_H_ */
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