206 lines
6.8 KiB
C
206 lines
6.8 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-uart
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* @{
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*
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* \file
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* Implementation of the cc2538 UART driver
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*/
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#include "contiki.h"
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#include "sys/energest.h"
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#include "dev/sys-ctrl.h"
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#include "dev/ioc.h"
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#include "dev/gpio.h"
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#include "dev/uart.h"
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#include "reg.h"
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#include <stdint.h>
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#include <string.h>
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static int (* input_handler)(unsigned char c);
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/*---------------------------------------------------------------------------*/
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/*
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* Once we know what UART we're on, configure correct values to be written to
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* the correct registers
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*/
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#if UART_BASE==UART_1_BASE
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/* Running, in sleep, in deep sleep, enable the clock for the correct UART */
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#define SYS_CTRL_RCGCUART_UART SYS_CTRL_RCGCUART_UART1
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#define SYS_CTRL_SCGCUART_UART SYS_CTRL_SCGCUART_UART1
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#define SYS_CTRL_DCGCUART_UART SYS_CTRL_DCGCUART_UART1
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#define NVIC_INT_UART NVIC_INT_UART1
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#define IOC_PXX_SEL_UART_TXD IOC_PXX_SEL_UART1_TXD
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#define IOC_UARTRXD_UART IOC_UARTRXD_UART1
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#else /* Defaults for UART0 */
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#define SYS_CTRL_RCGCUART_UART SYS_CTRL_RCGCUART_UART0
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#define SYS_CTRL_SCGCUART_UART SYS_CTRL_SCGCUART_UART0
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#define SYS_CTRL_DCGCUART_UART SYS_CTRL_DCGCUART_UART0
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#define NVIC_INT_UART NVIC_INT_UART0
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#define IOC_PXX_SEL_UART_TXD IOC_PXX_SEL_UART0_TXD
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#define IOC_UARTRXD_UART IOC_UARTRXD_UART0
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#endif
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/*---------------------------------------------------------------------------*/
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static void
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reset(void)
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{
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uint32_t lchr;
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/* Make sure the UART is disabled before trying to configure it */
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REG(UART_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
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/* Clear error status */
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REG(UART_BASE | UART_ECR) = 0xFF;
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/* Store LCHR configuration */
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lchr = REG(UART_BASE | UART_LCRH);
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/* Flush FIFOs by clearing LCHR.FEN */
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REG(UART_BASE | UART_LCRH) = 0;
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/* Restore LCHR configuration */
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REG(UART_BASE | UART_LCRH) = lchr;
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/* UART Enable */
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REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_init(void)
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{
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/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
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REG(SYS_CTRL_RCGCUART) |= SYS_CTRL_RCGCUART_UART;
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REG(SYS_CTRL_SCGCUART) |= SYS_CTRL_SCGCUART_UART;
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REG(SYS_CTRL_DCGCUART) |= SYS_CTRL_DCGCUART_UART;
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/* Run on SYS_DIV */
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REG(UART_BASE | UART_CC) = 0;
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/*
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* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
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*
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* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
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* ioc.h. The value can also be calculated as:
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*
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* (port << 3) + pin
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*/
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REG(IOC_UARTRXD_UART) = (UART_RX_PORT << 3) + UART_RX_PIN;
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/*
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* Pad Control for the TX pin:
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* - Set function to UART0 TX
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* - Output Enable
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*/
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ioc_set_sel(UART_TX_PORT, UART_TX_PIN, IOC_PXX_SEL_UART_TXD);
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ioc_set_over(UART_TX_PORT, UART_TX_PIN, IOC_OVERRIDE_OE);
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/* Set RX and TX pins to peripheral mode */
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(UART_TX_PORT), GPIO_PIN_MASK(UART_TX_PIN));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(UART_RX_PORT), GPIO_PIN_MASK(UART_RX_PIN));
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/*
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* UART Interrupt Masks:
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* Acknowledge RX and RX Timeout
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* Acknowledge Framing, Overrun and Break Errors
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*/
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REG(UART_BASE | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(UART_BASE | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(UART_BASE | UART_IFLS) =
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UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
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/* Make sure the UART is disabled before trying to configure it */
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REG(UART_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
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/* Baud Rate Generation */
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REG(UART_BASE | UART_IBRD) = UART_CONF_IBRD;
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REG(UART_BASE | UART_FBRD) = UART_CONF_FBRD;
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/* UART Control: 8N1 with FIFOs */
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REG(UART_BASE | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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/* UART Enable */
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REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
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/* Enable UART0 Interrupts */
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nvic_interrupt_enable(NVIC_INT_UART);
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_set_input(int (* input)(unsigned char c))
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{
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input_handler = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_write_byte(uint8_t b)
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{
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/* Block if the TX FIFO is full */
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while(REG(UART_BASE | UART_FR) & UART_FR_TXFF);
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REG(UART_BASE | UART_DR) = b;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_isr(void)
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{
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uint16_t mis;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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/* Store the current MIS and clear all flags early, except the RTM flag.
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* This will clear itself when we read out the entire FIFO contents */
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mis = REG(UART_BASE | UART_MIS) & 0x0000FFFF;
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REG(UART_BASE | UART_ICR) = 0x0000FFBF;
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if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
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while(!(REG(UART_BASE | UART_FR) & UART_FR_RXFE)) {
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if(input_handler != NULL) {
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input_handler((unsigned char)(REG(UART_BASE | UART_DR) & 0xFF));
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} else {
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/* To prevent an Overrun Error, we need to flush the FIFO even if we
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* don't have an input_handler. Use mis as a data trash can */
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mis = REG(UART_BASE | UART_DR);
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}
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}
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} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {
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/* ISR triggered due to some error condition */
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reset();
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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/** @} */
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