96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
/* Timer registers are all 16-bit wide with 16-bit access only */
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#define TMR_OFFSET (0x20)
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#define TMR_BASE (0x80007000)
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#define TMR0_BASE (TMR_BASE)
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#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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/* Timer 0 registers */
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#define TMR0_COMP1 (TMR0_BASE + TMR_REGOFF_COMP1)
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT (TMR0_BASE + TMR_REGOFF_CAPT)
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#define TMR0_LOAD (TMR0_BASE + TMR_REGOFF_LOAD)
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#define TMR0_HOLD (TMR0_BASE + TMR_REGOFF_HOLD)
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#define TMR0_CNTR (TMR0_BASE + TMR_REGOFF_CTRL)
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#define TMR0_CTRL (TMR0_BASE + TMR_REGOFF_CTRL)
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#define TMR0_SCTRL (TMR0_BASE + TMR_REGOFF_SCTRL)
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#define TMR0_CMPLD1 (TMR0_BASE + TMR_REGOFF_CMPLD1)
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#define TMR0_CMPLD2 (TMR0_BASE + TMR_REGOFF_CMPLD2)
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#define TMR0_CSCTRL (TMR0_BASE + TMR_REGOFF_CSCTRL)
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/* one enable register to rule them all */
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#define TMR_ENBL TMR0_BASE + TMR_REGOFF_ENBL
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#define MBAR_GPIO 0x80000000
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#define GPIO_PAD_DIR0 0x80000000
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#define GPIO_DATA0 0x80000008
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#define UART1_DATA 0x80005008
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#define DELAY 400000
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#define reg32(x) (*(volatile uint32_t *)(x))
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#define reg16(x) (*(volatile uint16_t *)(x))
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#include "embedded_types.h"
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#include "isr.h"
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no_isrs();
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__attribute__ ((section ("startup")))
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void main(void) {
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/* pin direction */
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reg32(GPIO_PAD_DIR0) = 0x00000500;
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/* timer setup */
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/* CTRL */
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#define COUNT_MODE 1 /* use rising edge of primary source */
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#define PRIME_SRC 0xf /* Perip. clock with 128 prescale (for 24Mhz = 187500Hz)*/
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#define SEC_SRC 0 /* don't need this */
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#define ONCE 0 /* keep counting */
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#define LEN 1 /* count until compare then reload with value in LOAD */
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#define DIR 0 /* count up */
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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reg16(TMR_ENBL) = 0; /* tmrs reset to enabled */
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reg16(TMR0_SCTRL) = 0;
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reg16(TMR0_LOAD) = 0; /* reload to zero */
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reg16(TMR0_COMP_UP) = 18750; /* trigger a reload at the end */
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reg16(TMR0_CMPLD1) = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
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reg16(TMR0_CNTR) = 0; /* reset count register */
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reg16(TMR0_CTRL) = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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reg16(TMR_ENBL) = 0xf; /* enable all the timers --- why not? */
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while(1) {
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/* blink on */
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reg32(GPIO_DATA0) = 0x00000500;
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while((reg16(TMR0_SCTRL)>>15) == 0) { continue; }
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reg16(TMR0_SCTRL) = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
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/* blink off */
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reg32(GPIO_DATA0) = 0x00000000;
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while((reg16(TMR0_SCTRL)>>15) == 0) { continue; }
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reg16(TMR0_SCTRL) = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
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};
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}
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