f1ca1b742c
spi-arch.h configures dev/spi.h, so it must be #included first. Luckily, this mistake did not have any consequence here, but fix it in order to avoid possible future issues. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
96 lines
4 KiB
C
96 lines
4 KiB
C
/*
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* Copyright (c) 2013, University of Michigan.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-spi
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* @{
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*
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* \file
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* Implementation of the cc2538 SPI peripheral
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*/
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#include "contiki.h"
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#include "reg.h"
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#include "spi-arch.h"
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#include "dev/ioc.h"
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#include "dev/sys-ctrl.h"
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#include "dev/spi.h"
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#include "dev/ssi.h"
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#include "dev/gpio.h"
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/**
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* \brief Initialize the SPI bus.
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*
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* This SPI init() function uses the following #defines to set the pins:
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* CC2538_SPI_CLK_PORT_NUM CC2538_SPI_CLK_PIN_NUM
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* CC2538_SPI_MOSI_PORT_NUM CC2538_SPI_MOSI_PIN_NUM
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* CC2538_SPI_MISO_PORT_NUM CC2538_SPI_MISO_PIN_NUM
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* CC2538_SPI_SEL_PORT_NUM CC2538_SPI_SEL_PIN_NUM
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*
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* This sets the SPI data width to 8 bits and the mode to Freescale mode 3.
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*/
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void
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spi_init(void)
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{
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/* Enable the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) |= 1;
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/* Start by disabling the peripheral before configuring it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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/* Set the IO clock as the SSI clock */
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REG(SSI0_BASE + SSI_CC) = 1;
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/* Set the mux correctly to connect the SSI pins to the correct GPIO pins */
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ioc_set_sel(CC2538_SPI_CLK_PORT_NUM, CC2538_SPI_CLK_PIN_NUM, IOC_PXX_SEL_SSI0_CLKOUT);
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ioc_set_sel(CC2538_SPI_MOSI_PORT_NUM, CC2538_SPI_MOSI_PIN_NUM, IOC_PXX_SEL_SSI0_TXD);
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REG(IOC_SSIRXD_SSI0) = (CC2538_SPI_MISO_PORT_NUM * 8) + CC2538_SPI_MISO_PIN_NUM;
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ioc_set_sel(CC2538_SPI_SEL_PORT_NUM, CC2538_SPI_SEL_PIN_NUM, IOC_PXX_SEL_SSI0_FSSOUT);
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/* Put all the SSI gpios into peripheral mode */
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_CLK_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_CLK_PIN_NUM));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_MOSI_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_MOSI_PIN_NUM));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_MISO_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_MISO_PIN_NUM));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_SEL_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_SEL_PIN_NUM));
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/* Disable any pull ups or the like */
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ioc_set_over(CC2538_SPI_CLK_PORT_NUM, CC2538_SPI_CLK_PIN_NUM, IOC_OVERRIDE_DIS);
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ioc_set_over(CC2538_SPI_MOSI_PORT_NUM, CC2538_SPI_MOSI_PIN_NUM, IOC_OVERRIDE_DIS);
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ioc_set_over(CC2538_SPI_MISO_PORT_NUM, CC2538_SPI_MISO_PIN_NUM, IOC_OVERRIDE_DIS);
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ioc_set_over(CC2538_SPI_SEL_PORT_NUM, CC2538_SPI_SEL_PIN_NUM, IOC_OVERRIDE_DIS);
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/* Configure the clock */
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REG(SSI0_BASE + SSI_CPSR) = 2;
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/* Put the ssi in motorola SPI mode with 8 bit data */
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REG(SSI0_BASE + SSI_CR0) = SSI_CR0_SPH_M | SSI_CR0_SPO_M | (7);
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/* Enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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}
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/** @} */
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