3908253038
This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
159 lines
6.5 KiB
C
159 lines
6.5 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_DRIVERS_QUARKX1000_I2C_REGISTERS_H_
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#define CPU_X86_DRIVERS_QUARKX1000_I2C_REGISTERS_H_
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#define QUARKX1000_IC_CON 0x00
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#define QUARKX1000_IC_TAR 0x04
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#define QUARKX1000_IC_DATA_CMD 0x10
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#define QUARKX1000_IC_SS_SCL_HCNT 0x14
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#define QUARKX1000_IC_SS_SCL_LCNT 0x18
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#define QUARKX1000_IC_FS_SCL_HCNT 0x1C
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#define QUARKX1000_IC_FS_SCL_LCNT 0x20
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#define QUARKX1000_IC_INTR_STAT 0x2C
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#define QUARKX1000_IC_INTR_MASK 0x30
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#define QUARKX1000_IC_RAW_INTR_STAT 0x34
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#define QUARKX1000_IC_RX_TL 0x38
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#define QUARKX1000_IC_TX_TL 0x3C
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#define QUARKX1000_IC_CLR_INTR 0x40
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#define QUARKX1000_IC_CLR_RX_UNDER 0x44
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#define QUARKX1000_IC_CLR_RX_OVER 0x48
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#define QUARKX1000_IC_CLR_TX_OVER 0x4C
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#define QUARKX1000_IC_CLR_RD_REQ 0x50
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#define QUARKX1000_IC_CLR_TX_ABRT 0x54
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#define QUARKX1000_IC_CLR_ACTIVITY 0x5C
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#define QUARKX1000_IC_CLR_STOP_DET 0x60
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#define QUARKX1000_IC_CLR_START_DET 0x64
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#define QUARKX1000_IC_ENABLE 0x6C
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#define QUARKX1000_IC_STATUS 0x70
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#define QUARKX1000_IC_TXFLR 0x74
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#define QUARKX1000_IC_RXFLR 0x78
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#define QUARKX1000_IC_SDA_HOLD 0x7C
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#define QUARKX1000_IC_TX_ABRT_SOURCE 0x80
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#define QUARKX1000_IC_ENABLE_STATUS 0x9C
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#define QUARKX1000_IC_FS_SPKLEN 0xA0
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#define QUARKX1000_IC_HIGHEST QUARKX1000_IC_FS_SPKLEN
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/* IC_CON */
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#define QUARKX1000_IC_CON_MASTER_MODE_SHIFT 0
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#define QUARKX1000_IC_CON_MASTER_MODE_MASK 0x01
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#define QUARKX1000_IC_CON_SPEED_SHIFT 1
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#define QUARKX1000_IC_CON_SPEED_MASK 0x06
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#define QUARKX1000_IC_CON_10BITADDR_MASTER_SHIFT 4
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#define QUARKX1000_IC_CON_10BITADDR_MASTER_MASK 0x10
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#define QUARKX1000_IC_CON_RESTART_EN_SHIFT 5
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#define QUARKX1000_IC_CON_RESTART_EN_MASK 0x20
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/* IC_TAR */
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#define QUARKX1000_IC_TAR_SHIFT 0
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#define QUARKX1000_IC_TAR_MASK 0x3FF
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/* IC_DATA_CMD */
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#define QUARKX1000_IC_DATA_CMD_DAT_SHIFT 0
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#define QUARKX1000_IC_DATA_CMD_DAT_MASK 0x0FF
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#define QUARKX1000_IC_DATA_CMD_CMD_SHIFT 8
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#define QUARKX1000_IC_DATA_CMD_CMD_MASK 0x100
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#define QUARKX1000_IC_DATA_CMD_STOP_SHIFT 9
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#define QUARKX1000_IC_DATA_CMD_STOP_MASK 0x200
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#define QUARKX1000_IC_DATA_CMD_RESTART_SHIFT 10
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#define QUARKX1000_IC_DATA_CMD_RESTART_MASK 0x400
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/* IC_SS_SCL_HCNT */
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#define QUARKX1000_IC_SS_SCL_HCNT_SHIFT 0
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#define QUARKX1000_IC_SS_SCL_HCNT_MASK 0xFFFF
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/* IC_SS_SCL_LCNT */
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#define QUARKX1000_IC_SS_SCL_LCNT_SHIFT 0
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#define QUARKX1000_IC_SS_SCL_LCNT_MASK 0xFFFF
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/* IC_FS_SCL_HCNT */
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#define QUARKX1000_IC_FS_SCL_HCNT_SHIFT 0
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#define QUARKX1000_IC_FS_SCL_HCNT_MASK 0xFFFF
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/* IC_FS_SCL_LCNT */
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#define QUARKX1000_IC_FS_SCL_LCNT_SHIFT 0
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#define QUARKX1000_IC_FS_SCL_LCNT_MASK 0xFFFF
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/* IC_INTR_STAT */
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#define QUARKX1000_IC_INTR_STAT_RX_UNDER_SHIFT 0
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#define QUARKX1000_IC_INTR_STAT_RX_UNDER_MASK 0x001
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#define QUARKX1000_IC_INTR_STAT_RX_OVER_SHIFT 1
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#define QUARKX1000_IC_INTR_STAT_RX_OVER_MASK 0x002
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#define QUARKX1000_IC_INTR_STAT_RX_FULL_SHIFT 2
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#define QUARKX1000_IC_INTR_STAT_RX_FULL_MASK 0x004
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#define QUARKX1000_IC_INTR_STAT_TX_OVER_SHIFT 3
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#define QUARKX1000_IC_INTR_STAT_TX_OVER_MASK 0x008
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#define QUARKX1000_IC_INTR_STAT_TX_EMPTY_SHIFT 4
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#define QUARKX1000_IC_INTR_STAT_TX_EMPTY_MASK 0x010
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#define QUARKX1000_IC_INTR_STAT_RD_REQ_SHIFT 5
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#define QUARKX1000_IC_INTR_STAT_RD_REQ_MASK 0x020
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#define QUARKX1000_IC_INTR_STAT_TX_ABRT_SHIFT 6
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#define QUARKX1000_IC_INTR_STAT_TX_ABRT_MASK 0x040
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#define QUARKX1000_IC_INTR_STAT_ACTIVITY_SHIFT 8
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#define QUARKX1000_IC_INTR_STAT_ACTIVITY_MASK 0x100
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#define QUARKX1000_IC_INTR_STAT_STOP_DET_SHIFT 9
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#define QUARKX1000_IC_INTR_STAT_STOP_DET_MASK 0x200
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#define QUARKX1000_IC_INTR_STAT_START_DET_SHIFT 10
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#define QUARKX1000_IC_INTR_STAT_START_DET_MASK 0x400
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/* IC_ENABLE */
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#define QUARKX1000_IC_ENABLE_SHIFT 0
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#define QUARKX1000_IC_ENABLE_MASK 0x01
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/* IC_STATUS */
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#define QUARKX1000_IC_STATUS_ACTIVITY_SHIFT 0
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#define QUARKX1000_IC_STATUS_ACTIVITY_MASK 0x01
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#define QUARKX1000_IC_STATUS_TFNF_SHIFT 1
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#define QUARKX1000_IC_STATUS_TFNF_MASK 0x02
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#define QUARKX1000_IC_STATUS_TFE_SHIFT 2
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#define QUARKX1000_IC_STATUS_TFE_MASK 0x04
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#define QUARKX1000_IC_STATUS_RFNE_SHIFT 3
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#define QUARKX1000_IC_STATUS_RFNE_MASK 0x08
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#define QUARKX1000_IC_STATUS_RFF_SHIFT 4
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#define QUARKX1000_IC_STATUS_RFF_MASK 0x10
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#define QUARKX1000_IC_STATUS_MST_ACTIVITY_SHIFT 5
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#define QUARKX1000_IC_STATUS_MST_ACTIVITY_MASK 0x20
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/* IC_TXFLR */
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#define QUARKX1000_IC_TXFLR_SHIFT 0
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#define QUARKX1000_IC_TXFLR_MASK 0x1F
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/* IC_RXFLR */
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#define QUARKX1000_IC_RXFLR_SHIFT 0
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#define QUARKX1000_IC_RXFLR_MASK 0x1F
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/* IC_FS_SPKLEN */
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#define QUARKX1000_IC_FS_SPKLEN_SHIFT 0
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#define QUARKX1000_IC_FS_SPKLEN_MASK 0xFF
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#endif /* CPU_X86_DRIVERS_QUARKX1000_I2C_REGISTERS_H_ */
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