257 lines
9.3 KiB
C
257 lines
9.3 KiB
C
/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of libmc1322x: see http://mc1322x.devl.org
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* for details.
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*
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*
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*/
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#ifndef TMR_H
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#define TMR_H
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#include "utils.h"
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/* Timer registers are all 16-bit wide with 16-bit access only */
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#define TMR_OFFSET (0x20)
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#define TMR_BASE (0x80007000)
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#define TMR0_BASE (TMR_BASE)
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#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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/* Structure-based register definitions */
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/* Example use:
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TMR2->CTRL = 0x1234;
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TMR2->CTRLbits = (struct TMR_CTRL) {
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.DIR = 1,
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.OUTPUT_MODE = 2,
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};
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TMR2->CTRLbits.PRIMARY_CNT_SOURCE = 3;
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*/
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struct TMR_struct {
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uint16_t COMP1;
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uint16_t COMP2;
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uint16_t CAPT;
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uint16_t LOAD;
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uint16_t HOLD;
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uint16_t CNTR;
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union {
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uint16_t CTRL;
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struct TMR_CTRL {
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uint16_t OUTPUT_MODE:3;
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uint16_t CO_INIT:1;
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uint16_t DIR:1;
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uint16_t LENGTH:1;
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uint16_t ONCE:1;
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uint16_t SECONDARY_CNT_SOURCE:2;
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uint16_t PRIMARY_CNT_SOURCE:4;
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uint16_t COUNT_MODE:3;
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} CTRLbits;
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};
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union {
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uint16_t SCTRL;
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struct TMR_SCTRL {
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uint16_t OEN:1;
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uint16_t OPS:1;
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uint16_t FORCE:1;
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uint16_t VAL:1;
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uint16_t EEOF:1;
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uint16_t MSTR:1;
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uint16_t CAPTURE_MODE:2;
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uint16_t INPUT:1;
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uint16_t IPS:1;
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uint16_t IEFIE:1;
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uint16_t IEF:1;
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uint16_t TOFIE:1;
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uint16_t TOF:1;
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uint16_t TCFIE:1;
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uint16_t TCF:1;
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} SCTRLbits;
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};
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uint16_t CMPLD1;
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uint16_t CMPLD2;
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union {
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uint16_t CSCTRL;
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struct TMR_CSCTRL {
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uint16_t CL1:2;
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uint16_t CL2:2;
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uint16_t TCF1:1;
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uint16_t TCF2:1;
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uint16_t TCF1EN:1;
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uint16_t TCF2EN:1;
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uint16_t :5;
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uint16_t FILT_EN:1;
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uint16_t DBG_EN:2;
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} CSCTRLbits;
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};
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uint16_t reserved[4];
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union {
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uint16_t ENBL;
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struct TMR_ENBL {
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union {
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struct {
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uint16_t ENBL:4;
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};
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struct {
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uint16_t ENBL3:1;
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uint16_t ENBL2:1;
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uint16_t ENBL1:1;
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uint16_t ENBL0:1;
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};
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};
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uint16_t :12;
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} ENBLbits;
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};
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};
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static volatile struct TMR_struct * const TMR0 = (void *) (TMR0_BASE);
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static volatile struct TMR_struct * const TMR1 = (void *) (TMR1_BASE);
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static volatile struct TMR_struct * const TMR2 = (void *) (TMR2_BASE);
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static volatile struct TMR_struct * const TMR3 = (void *) (TMR3_BASE);
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/* Get timer pointer from timer number */
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#define TMR_ADDR(x) ((volatile struct TMR_struct *)(((uint32_t)(x) * TMR_OFFSET) + TMR_BASE))
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/* Get timer number from the timer pointer. */
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#define TMR_NUM(x) (((uint32_t)(x) - TMR_BASE) / TMR_OFFSET)
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/* Used to compute which enable bit to set for a particular timer, e.g.
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TMR0.ENBL |= TMR_ENABLE_BIT(TMR2);
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Helpful when you're using macros to define timers
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*/
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#define TMR_ENABLE_BIT(x) (1 << TMR_NUM(x))
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#define TMR0_PIN GPIO_08
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#define TMR1_PIN GPIO_09
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#define TMR2_PIN GPIO_10
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#define TMR3_PIN GPIO_11
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/* Old timer definitions, for compatibility */
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#ifndef REG_NO_COMPAT
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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/* one enable register to rule them all */
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#define TMR_ENBL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_ENBL))
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/* Timer 0 registers */
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#define TMR0_COMP1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP1))
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP2))
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CAPT))
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#define TMR0_LOAD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_LOAD))
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#define TMR0_HOLD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_HOLD))
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#define TMR0_CNTR ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CNTR))
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#define TMR0_CTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
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#define TMR0_SCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_SCTRL))
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#define TMR0_CMPLD1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD1))
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#define TMR0_CMPLD2 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD2))
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#define TMR0_CSCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 1 registers */
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#define TMR1_COMP1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP1))
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#define TMR1_COMP_UP TMR1_COMP1
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#define TMR1_COMP2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP2))
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#define TMR1_COMP_DOWN TMR1_COMP2
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#define TMR1_CAPT ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CAPT))
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#define TMR1_LOAD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_LOAD))
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#define TMR1_HOLD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_HOLD))
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#define TMR1_CNTR ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CNTR))
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#define TMR1_CTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
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#define TMR1_SCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_SCTRL))
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#define TMR1_CMPLD1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD1))
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#define TMR1_CMPLD2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD2))
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#define TMR1_CSCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 2 registers */
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#define TMR2_COMP1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP1))
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#define TMR2_COMP_UP TMR2_COMP1
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#define TMR2_COMP2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP2))
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#define TMR2_COMP_DOWN TMR2_COMP2
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#define TMR2_CAPT ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CAPT))
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#define TMR2_LOAD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_LOAD))
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#define TMR2_HOLD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_HOLD))
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#define TMR2_CNTR ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CNTR))
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#define TMR2_CTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
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#define TMR2_SCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_SCTRL))
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#define TMR2_CMPLD1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD1))
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#define TMR2_CMPLD2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD2))
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#define TMR2_CSCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 3 registers */
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#define TMR3_COMP1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP1))
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#define TMR3_COMP_UP TMR3_COMP1
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#define TMR3_COMP2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP2))
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#define TMR3_COMP_DOWN TMR3_COMP2
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#define TMR3_CAPT ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CAPT))
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#define TMR3_LOAD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_LOAD))
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#define TMR3_HOLD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_HOLD))
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#define TMR3_CNTR ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CNTR))
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#define TMR3_CTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
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#define TMR3_SCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_SCTRL))
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#define TMR3_CMPLD1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD1))
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#define TMR3_CMPLD2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD2))
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#define TMR3_CSCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CSCTRL))
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#define TMR(num, reg) CAT2(TMR,num,_##reg)
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#endif /* REG_NO_COMPAT */
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/* Initialize timer. This just counts and interrupts, doesn't drive an output.
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timer_num = 0, 1, 2, 3
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rate = desired rate in Hz,
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enable_int = whether to enable an interrupt on every cycle
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Returns actual timer rate. */
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uint32_t timer_setup_ex(int timer_num, uint32_t rate, int enable_int);
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/* Initialize timer. This just counts and interrupts, doesn't drive an output.
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timer = TMR0, TMR1, TMR2, TMR3
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rate = desired rate in Hz,
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enable_int = whether to enable an interrupt on every cycle
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Returns actual timer rate. */
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#define timer_setup(timer,rate,enable_int) timer_setup_ex(TMR_NUM(timer), rate, enable_int)
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#endif
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