3908253038
This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
148 lines
7.1 KiB
C
148 lines
7.1 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef INTERRUPT_H
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#define INTERRUPT_H
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#include <stdint.h>
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#include "gdt-layout.h"
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#include "idt.h"
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struct interrupt_context {
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/* The general-purpose register values are saved by the pushal instruction in
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* the interrupt dispatcher. Having access to these saved values may be
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* useful in some future interrupt or exception handler, and saving and later
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* restoring them also enables the ISR to freely overwrite the EAX, ECX, and
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* EDX registers as is permitted by the cdecl calling convention.
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*/
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uint32_t edi;
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uint32_t esi;
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uint32_t ebp;
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uint32_t esp;
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uint32_t ebx;
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uint32_t edx;
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uint32_t ecx;
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uint32_t eax;
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/* These two values are pushed on the stack by the CPU when it delivers an
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* exception with an associated error code. Currently, only the double fault
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* handler accepts this structure as a parameter, and that type of exception
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* does have an associated error code.
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*/
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uint32_t error_code;
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uint32_t eip;
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/* The CPU pushes additional values beyond these on the stack, specifically
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* the code segment descriptor and flags. If a privilege-level change occurs
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* during delivery, the CPU additionally pushes the stack pointer and stack
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* segment descriptor.
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*/
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};
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#define ISR_STUB(label_str, has_error_code, handler_str, exc) \
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"jmp 2f\n\t" \
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".align 4\n\t" \
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label_str ":\n\t" \
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" pushal\n\t" \
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PROT_DOMAINS_ENTER_ISR(exc) \
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" call " handler_str "\n\t" \
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PROT_DOMAINS_LEAVE_ISR(exc) \
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" popal\n\t" \
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" .if " #has_error_code "\n\t" \
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" add $4, %%esp\n\t" \
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" .endif\n\t" \
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" iret\n\t" \
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"2:\n\t"
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/* Helper macro to register interrupt handler function.
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*
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* num: Interrupt number (0-255)
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* has_error_code: 0 if interrupt doesn't push error code onto the
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* stack. Otherwise, set this argument to 1.
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* handler: Pointer to function that should be called once the
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* interrupt is raised. In case has_error_code == 0
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* the function prototype should be the following:
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* void handler(void)
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* Otherwise, it should be:
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* void handler(struct interrupt_context context)
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* exc: 0 if this is an interrupt, which should be handled
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* at the interrupt privilege level. 1 if this is an
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* exception, which should be handled at the
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* exception privilege level.
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* dpl: Privilege level for IDT descriptor, which is the
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* numerically-highest privilege level that can
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* generate this interrupt with a software interrupt
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* instruction.
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*
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* Since there is no easy way to write an Interrupt Service Routines
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* (ISR) in C (for further information on this, see [1]), we provide
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* this helper macro. It basically provides an assembly trampoline
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* to a C function (handler parameter) which, indeed, handles the
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* interrupt.
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*
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* [1] http://wiki.osdev.org/Interrupt_Service_Routines
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*/
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#define SET_INT_EXC_HANDLER(num, has_error_code, handler, exc, dpl) \
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do { \
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__asm__ __volatile__ ( \
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"pushl %[_dpl_]\n\t" \
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"pushl %[_cs_]\n\t" \
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"pushl $1f\n\t" \
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"pushl %[_isr_num_]\n\t" \
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"call idt_set_intr_gate_desc\n\t" \
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"add $16, %%esp\n\t" \
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ISR_STUB("1", has_error_code, "%P[_handler_]", exc) \
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: \
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: [_isr_num_] "g" (num), \
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[_handler_] "i" (handler), \
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[_cs_] "i" (exc ? GDT_SEL_CODE_EXC : GDT_SEL_CODE_INT), \
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[_dpl_] "i" (dpl) \
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/* the invocation of idt_set_intr_gate_desc may clobber */ \
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/* the caller-saved registers: */ \
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: "eax", "ecx", "edx" \
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); \
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} while (0)
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#define SET_INTERRUPT_HANDLER(num, has_error_code, handler) \
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SET_INT_EXC_HANDLER(num, has_error_code, handler, 0, PRIV_LVL_INT)
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#define SET_EXCEPTION_HANDLER(num, has_error_code, handler) \
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SET_INT_EXC_HANDLER(num, has_error_code, handler, 1, PRIV_LVL_EXC)
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/* Disable maskable hardware interrupts */
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#define DISABLE_IRQ() \
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do { \
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__asm__ ("cli"); \
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} while (0)
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/* Enable maskable hardware interrupts */
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#define ENABLE_IRQ() \
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do { \
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__asm__ ("sti"); \
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} while (0)
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#endif /* INTERRUPT_H */
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