357 lines
9.2 KiB
C
357 lines
9.2 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "contiki.h"
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#include "gpio.h"
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#include "gpio-pcal9535a.h"
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#include "i2c.h"
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#include "stdio.h"
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#define REG_INPUT_PORT0 0x00
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#define REG_INPUT_PORT1 0x01
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#define REG_OUTPUT_PORT0 0x02
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#define REG_OUTPUT_PORT1 0x03
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#define REG_POL_INV_PORT0 0x04
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#define REG_POL_INV_PORT1 0x05
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#define REG_CONF_PORT0 0x06
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#define REG_CONG_PORT1 0x07
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#define REG_OUT_DRV_STRENGTH_PORT0_L 0x40
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#define REG_OUT_DRV_STRENGTH_PORT0_H 0x41
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#define REG_OUT_DRV_STRENGTH_PORT1_L 0x42
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#define REG_OUT_DRV_STRENGTH_PORT1_H 0x43
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#define REG_INPUT_LATCH_PORT0 0x44
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#define REG_INPUT_LATCH_PORT1 0x45
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#define REG_PUD_EN_PORT0 0x46
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#define REG_PUD_EN_PORT1 0x47
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#define REG_PUD_SEL_PORT0 0x48
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#define REG_PUD_SEL_PORT1 0x49
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#define REG_INT_MASK_PORT0 0x4A
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#define REG_INT_MASK_PORT1 0x4B
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#define REG_INT_STATUS_PORT0 0x4C
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#define REG_INT_STATUS_PORT1 0x4D
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#define REG_OUTPUT_PORT_CONF 0x4F
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#define READ_PORT_TIMEOUT (CLOCK_SECOND / 100)
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#define READ_PORT_TRIES 5
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static int
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read_port_regs(struct gpio_pcal9535a_data *data, uint8_t reg, union gpio_pcal9535a_port_data *buf)
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{
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int r;
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uint8_t tries = READ_PORT_TRIES;
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buf->byte[0] = reg;
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buf->byte[1] = 0;
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if(quarkX1000_i2c_write(buf->byte, 1, data->i2c_slave_addr) < 0) {
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return -1;
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}
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do {
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clock_wait(READ_PORT_TIMEOUT);
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r = quarkX1000_i2c_read(buf->byte, 2, data->i2c_slave_addr);
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if(r == 0) {
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break;
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}
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} while(tries--);
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if(r < 0) {
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return -1;
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}
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return 0;
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}
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static int
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write_port_regs(struct gpio_pcal9535a_data *data, uint8_t reg, union gpio_pcal9535a_port_data *buf)
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{
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uint8_t cmd[] = { reg, buf->byte[0], buf->byte[1] };
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if(quarkX1000_i2c_polling_write(cmd, sizeof(cmd), data->i2c_slave_addr) < 0) {
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return -1;
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}
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return 0;
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}
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static int
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setup_pin_dir(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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union gpio_pcal9535a_port_data *port = &data->reg_cache.dir;
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uint16_t bit_mask, new_value = 0;
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bit_mask = 1 << pin;
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if((flags & QUARKX1000_GPIO_DIR_MASK) == QUARKX1000_GPIO_IN) {
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new_value = 1 << pin;
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}
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port->all &= ~bit_mask;
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port->all |= new_value;
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return write_port_regs(data, REG_CONF_PORT0, port);
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}
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static int
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setup_pin_pullupdown(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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union gpio_pcal9535a_port_data *port;
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uint16_t bit_mask, new_value = 0;
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if((flags & QUARKX1000_GPIO_PUD_MASK) != QUARKX1000_GPIO_PUD_NORMAL) {
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port = &data->reg_cache.pud_sel;
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bit_mask = 1 << pin;
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if((flags & QUARKX1000_GPIO_PUD_MASK) == QUARKX1000_GPIO_PUD_PULL_UP) {
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new_value = 1 << pin;
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}
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port->all &= ~bit_mask;
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port->all |= new_value;
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if(write_port_regs(data, REG_PUD_SEL_PORT0, port) < 0) {
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return -1;
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}
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}
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port = &data->reg_cache.pud_en;
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bit_mask = 1 << pin;
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if((flags & QUARKX1000_GPIO_PUD_MASK) != QUARKX1000_GPIO_PUD_NORMAL) {
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new_value = 1 << pin;
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}
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port->all &= ~bit_mask;
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port->all |= new_value;
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return write_port_regs(data, REG_PUD_EN_PORT0, port);
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}
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static int
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setup_pin_polarity(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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union gpio_pcal9535a_port_data *port = &data->reg_cache.pol_inv;
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uint16_t bit_mask, new_value = 0;
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bit_mask = 1 << pin;
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if((flags & QUARKX1000_GPIO_POL_MASK) == QUARKX1000_GPIO_POL_INV) {
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new_value = 1 << pin;
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}
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port->all &= ~bit_mask;
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port->all |= new_value;
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if(write_port_regs(data, REG_POL_INV_PORT0, port) < 0) {
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return -1;
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}
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data->out_pol_inv = port->all;
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return 0;
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}
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int
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gpio_pcal9535a_write(struct gpio_pcal9535a_data *data, uint32_t pin, uint32_t value)
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{
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union gpio_pcal9535a_port_data *port = &data->reg_cache.output;
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uint16_t bit_mask, new_value;
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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bit_mask = 1 << pin;
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new_value = (value << pin) & bit_mask;
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new_value ^= (data->out_pol_inv & bit_mask);
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new_value &= bit_mask;
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port->all &= ~bit_mask;
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port->all |= new_value;
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return write_port_regs(data, REG_OUTPUT_PORT0, port);
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}
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int
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gpio_pcal9535a_read(struct gpio_pcal9535a_data *data, uint32_t pin, uint32_t *value)
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{
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union gpio_pcal9535a_port_data buf;
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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if(read_port_regs(data, REG_INPUT_PORT0, &buf) < 0) {
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return -1;
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}
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*value = (buf.all >> pin) & 0x01;
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return 0;
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}
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int
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gpio_pcal9535a_config(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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if(setup_pin_dir(data, pin, flags) < 0) {
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return -1;
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}
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if(setup_pin_polarity(data, pin, flags) < 0) {
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return -1;
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}
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if(setup_pin_pullupdown(data, pin, flags) < 0) {
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return -1;
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}
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return 0;
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}
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static int
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setup_port_dir(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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union gpio_pcal9535a_port_data *port = &data->reg_cache.dir;
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port->all = ((flags & QUARKX1000_GPIO_DIR_MASK) == QUARKX1000_GPIO_IN) ? 0xFFFF : 0x0;
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return write_port_regs(data, REG_CONF_PORT0, port);
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}
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static int
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setup_port_pullupdown(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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union gpio_pcal9535a_port_data *port;
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if((flags & QUARKX1000_GPIO_PUD_MASK) != QUARKX1000_GPIO_PUD_NORMAL) {
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port = &data->reg_cache.pud_sel;
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port->all = ((flags & QUARKX1000_GPIO_PUD_MASK) == QUARKX1000_GPIO_PUD_PULL_UP) ? 0xFFFF : 0x0;
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if(write_port_regs(data, REG_PUD_SEL_PORT0, port) < 0) {
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return -1;
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}
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}
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port = &data->reg_cache.pud_en;
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port->all = ((flags & QUARKX1000_GPIO_PUD_MASK) != QUARKX1000_GPIO_PUD_NORMAL) ? 0xFFFF : 0x0;
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return write_port_regs(data, REG_PUD_EN_PORT0, port);
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}
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static int
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setup_port_polarity(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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union gpio_pcal9535a_port_data *port = &data->reg_cache.pol_inv;
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port->all = ((flags & QUARKX1000_GPIO_POL_MASK) == QUARKX1000_GPIO_POL_INV) ? 0xFFFF : 0x0;
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if(write_port_regs(data, REG_POL_INV_PORT0, port) < 0) {
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return -1;
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}
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data->out_pol_inv = port->all;
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return 0;
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}
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int
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gpio_pcal9535a_write_port(struct gpio_pcal9535a_data *data, uint32_t pin, uint32_t value)
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{
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union gpio_pcal9535a_port_data *port = &data->reg_cache.output;
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uint16_t bit_mask, new_value;
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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port->all = value;
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bit_mask = data->out_pol_inv;
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new_value = value & bit_mask;
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new_value ^= data->out_pol_inv;
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new_value &= bit_mask;
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port->all &= ~bit_mask;
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port->all |= new_value;
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return write_port_regs(data, REG_OUTPUT_PORT0, port);
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}
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int
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gpio_pcal9535a_read_port(struct gpio_pcal9535a_data *data, uint32_t pin, uint32_t *value)
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{
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union gpio_pcal9535a_port_data buf;
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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if(read_port_regs(data, REG_INPUT_PORT0, &buf) < 0) {
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return -1;
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}
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*value = buf.all;
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return 0;
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}
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int
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gpio_pcal9535a_config_port(struct gpio_pcal9535a_data *data, uint32_t pin, int flags)
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{
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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if(setup_port_dir(data, pin, flags) < 0) {
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return -1;
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}
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if(setup_port_polarity(data, pin, flags) < 0) {
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return -1;
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}
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if(setup_port_pullupdown(data, pin, flags) < 0) {
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return -1;
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}
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return 0;
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}
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int
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gpio_pcal9535a_init(struct gpio_pcal9535a_data *data, uint16_t i2c_slave_addr)
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{
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/* has to init after I2C master */
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if(!quarkX1000_i2c_is_available()) {
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return -1;
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}
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data->i2c_slave_addr = i2c_slave_addr;
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/* default for registers according to datasheet */
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data->reg_cache.output.all = 0xFFFF;
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data->reg_cache.pol_inv.all = 0x0;
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data->reg_cache.dir.all = 0xFFFF;
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data->reg_cache.pud_en.all = 0x0;
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data->reg_cache.pud_sel.all = 0xFFFF;
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return 0;
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}
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