c796e270bf
PCI Interrupt Routing is mapped using Interrupt Queue Agents IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each PCI-mapped device in the SoC. PCI based interrupts PIRQ[A:H] are then available for consumption by either the 8259 PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control Registers PIRQ[A:H]. More information about can be find in Intel Quark X1000 datasheet[1] section 21.11. [1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
213 lines
6.6 KiB
C
213 lines
6.6 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "pci.h"
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#include "helpers.h"
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/* I/O port for PCI configuration address */
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#define PCI_CONFIG_ADDR_PORT 0xCF8
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/* I/O port for PCI configuration data */
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#define PCI_CONFIG_DATA_PORT 0xCFC
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/*---------------------------------------------------------------------------*/
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/* Initialize PCI configuration register address in preparation for accessing
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* the specified register.
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*/
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static void
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set_addr(pci_config_addr_t addr)
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{
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addr.en_mapping = 1;
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outl(PCI_CONFIG_ADDR_PORT, addr.raw);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Read from the specified PCI configuration register.
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* \param addr Address of PCI configuration register.
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* \return Value read from PCI configuration register.
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*/
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uint32_t
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pci_config_read(pci_config_addr_t addr)
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{
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set_addr(addr);
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return inl(PCI_CONFIG_DATA_PORT);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set current PIRQ to interrupt queue agent. PCI based interrupts
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* PIRQ[A:H] are then available for consumption by either the 8259
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* PICs or the IO-APIC depending on configuration of the 8 PIRQx
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* Routing Control Registers PIRQ[A:H]. See also pci_pirq_set_irq().
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* \param agent Interrupt Queue Agent to be used, IRQAGENT[0:3].
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* \param pin Interrupt Pin Route to be used, INT[A:D].
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* \param pirq PIRQ to be used, PIRQ[A:H].
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* \return Returns 0 on success and a negative number otherwise.
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*/
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int
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pci_irq_agent_set_pirq(IRQAGENT agent, INTR_PIN pin, PIRQ pirq)
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{
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pci_config_addr_t pci;
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uint16_t value;
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uint32_t rcba_addr, offset = 0;
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assert(agent >= IRQAGENT0 && agent <= IRQAGENT3);
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assert(pin >= INTA && pin <= INTD);
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assert(pirq >= PIRQA && pirq <= PIRQH);
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pci.raw = 0;
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pci.bus = 0;
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pci.dev = 31;
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pci.func = 0;
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pci.reg_off = 0xF0; /* Root Complex Base Address Register */
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/* masked to clear non-address bits. */
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rcba_addr = pci_config_read(pci) & ~0x3FFF;
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switch(agent) {
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case IRQAGENT0:
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if (pin != INTA)
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return -1;
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offset = 0x3140;
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break;
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case IRQAGENT1:
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offset = 0x3142;
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break;
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case IRQAGENT2:
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if (pin != INTA)
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return -1;
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offset = 0x3144;
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break;
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case IRQAGENT3:
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offset = 0x3146;
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}
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value = *(uint16_t*)(rcba_addr + offset);
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/* clear interrupt pin route and set corresponding pirq. */
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switch(pin) {
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case INTA:
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value &= ~0xF;
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value |= pirq;
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break;
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case INTB:
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value &= ~0xF0;
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value |= (pirq << 4);
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break;
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case INTC:
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value &= ~0xF00;
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value |= (pirq << 8);
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break;
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case INTD:
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value &= ~0xF000;
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value |= (pirq << 12);
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}
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*(uint16_t*)(rcba_addr + offset) = value;
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set current IRQ to PIRQ. The interrupt router can be
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* programmed to allow PIRQ[A:H] to be routed internally
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* to the 8259 as ISA compatible interrupts. See also
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* pci_irq_agent_set_pirq().
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* \param pirq PIRQ to be used, PIRQ[A:H].
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* \param pin IRQ to be used, IRQ[0:15].
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* \param route_to_legacy Whether or not the interrupt should be routed to PIC 8259.
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*/
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void
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pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy)
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{
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pci_config_addr_t pci;
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uint32_t value;
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assert(pirq >= PIRQA && pirq <= PIRQH);
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assert(irq >= 0 && irq <= 0xF);
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assert(route_to_legacy == 0 || route_to_legacy == 1);
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pci.raw = 0;
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pci.bus = 0;
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pci.dev = 31;
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pci.func = 0;
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pci.reg_off = (pirq <= PIRQD) ? 0x60 : 0x64; /* PABCDRC and PEFGHRC Registers */
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value = pci_config_read(pci);
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switch(pirq) {
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case PIRQA:
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case PIRQE:
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value &= ~0x8F;
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value |= irq;
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value |= (!route_to_legacy << 7);
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break;
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case PIRQB:
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case PIRQF:
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value &= ~0x8F00;
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value |= (irq << 8);
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value |= (!route_to_legacy << 15);
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break;
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case PIRQC:
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case PIRQG:
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value &= ~0x8F0000;
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value |= (irq << 16);
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value |= (!route_to_legacy << 23);
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break;
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case PIRQD:
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case PIRQH:
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value &= ~0x8F000000;
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value |= (irq << 24);
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value |= (!route_to_legacy << 31);
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}
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set_addr(pci);
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outl(PCI_CONFIG_DATA_PORT, value);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Initialize a structure for a PCI device driver that performs
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* MMIO to address range 0. Assumes that device has already
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* been configured with an MMIO address range 0, e.g. by
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* firmware.
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* \param c_this Structure that will be initialized to represent the driver.
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* \param pci_addr PCI base address of device.
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*/
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void
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pci_init_bar0(pci_driver_t *c_this, pci_config_addr_t pci_addr)
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{
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pci_addr.reg_off = PCI_CONFIG_REG_BAR0;
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/* The BAR0 value is masked to clear non-address bits. */
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c_this->mmio = pci_config_read(pci_addr) & ~0xFFF;
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}
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/*---------------------------------------------------------------------------*/
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