220 lines
6.3 KiB
C
220 lines
6.3 KiB
C
/*
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* Copyright (c) 2011, George Oikonomou - <oikonomou@users.sourceforge.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*/
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/**
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* \file
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* Header file with definitions of bit masks for some cc2530 SFRs
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*
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* \author
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* George Oikonomou - <oikonomou@users.sourceforge.net>
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*/
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#ifndef SFR_BITS_H_
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#define SFR_BITS_H_
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/* CLKCON */
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#define CLKCONCMD_OSC32K 0x80
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#define CLKCONCMD_OSC 0x40
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#define CLKCONCMD_TICKSPD2 0x20
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#define CLKCONCMD_TICKSPD1 0x10
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#define CLKCONCMD_TICKSPD0 0x08
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#define CLKCONCMD_CLKSPD2 0x04
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#define CLKCONCMD_CLKSPD1 0x02
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#define CLKCONCMD_CLKSPD0 0x01
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/* SLEEPCMD and SLEEPSTA */
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#define SLEEP_OSC32K_CALDIS 0x80
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#define SLEEP_XOSC_STB 0x40
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#define SLEEP_HFRC_STB 0x20
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#define SLEEP_RST1 0x10 /* SLEEPSTA only */
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#define SLEEP_RST0 0x08 /* SLEEPSTA only */
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#define SLEEP_OSC_PD 0x04
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#define SLEEP_MODE1 0x02
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#define SLEEP_MODE0 0x01
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/* PCON */
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#define PCON_IDLE 0x01
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/* T1CTL */
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#define T1CTL_DIV1 0x08
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#define T1CTL_DIV0 0x04
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#define T1CTL_MODE1 0x02
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#define T1CTL_MODE0 0x01
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/* T1CCTLx */
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#define T1CCTL_RFIRQ 0x80
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#define T1CCTL_IM 0x40
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#define T1CCTL_CMP2 0x20
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#define T1CCTL_CMP1 0x10
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#define T1CCTL_CMP0 0x08
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#define T1CCTL_MODE 0x04
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#define T1CCTL_CAP1 0x02
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#define T1CCTL_CAP0 0x01
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/* T1STAT */
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#define T1STAT_OVFIF 0x20
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#define T1STAT_CH4IF 0x10
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#define T1STAT_CH3IF 0x08
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#define T1STAT_CH2IF 0x04
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#define T1STAT_CH1IF 0x02
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#define T1STAT_CH0IF 0x01
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/* WDCTL */
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#define WDCTL_CLR3 0x80
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#define WDCTL_CLR2 0x40
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#define WDCTL_CLR1 0x20
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#define WDCTL_CLR0 0x10
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#define WDCTL_MODE1 0x08
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#define WDCTL_MODE0 0x04
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#define WDCTL_INT1 0x02
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#define WDCTL_INT0 0x01
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/* ADCCON1 */
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#define ADCCON1_EOC 0x80
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#define ADCCON1_ST 0x40
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#define ADCCON1_STSEL1 0x20
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#define ADCCON1_STSEL0 0x10
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/* ADCCON1 - RNG bits */
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#define ADCCON1_RCTRL1 0x08
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#define ADCCON1_RCTRL0 0x04
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/* ADCCON3 */
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#define ADCCON3_EREF1 0x80
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#define ADCCON3_EREF0 0x40
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#define ADCCON3_EDIV1 0x20
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#define ADCCON3_EDIV0 0x10
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#define ADCCON3_ECH3 0x08
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#define ADCCON3_ECH2 0x04
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#define ADCCON3_ECH1 0x02
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#define ADCCON3_ECH0 0x01
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/* PERCFG */
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#define PERCFG_T1CFG 0x40
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#define PERCFG_T3CFG 0x20
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#define PERCFG_T4CFG 0x10
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#define PERCFG_U1CFG 0x02
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#define PERCFG_U0CFG 0x01
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/* UxCSR */
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#define UCSR_MODE 0x80
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#define UCSR_RE 0x40
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#define UCSR_SLAVE 0x20
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#define UCSR_FE 0x10
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#define UCSR_ERR 0x08
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#define UCSR_RX_BYTE 0x04
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#define UCSR_TX_BYTE 0x02
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#define UCSR_ACTIVE 0x01
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/* IEN2 */
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#define IEN2_WDTIE 0x20
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#define IEN2_P1IE 0x10
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#define IEN2_UTX1IE 0x08
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#define IEN2_UTX0IE 0x04
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#define IEN2_P2IE 0x02
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#define IEN2_RFIE 0x01
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/* PICTL */
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#define PICTL_PADSC 0x40
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#define PICTL_P2ICON 0x08
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#define PICTL_P1ICONH 0x04
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#define PICTL_P1ICONL 0x02
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#define PICTL_P0ICON 0x01
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/* DMAARM */
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#define DMAARM_ABORT 0x80
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#define DMAARM_DMAARM4 0x10
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#define DMAARM_DMAARM3 0x08
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#define DMAARM_DMAARM2 0x04
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#define DMAARM_DMAARM1 0x02
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#define DMAARM_DMAARM0 0x01
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/* DMAREQ */
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#define DMAREQ_DMAREQ4 0x10
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#define DMAREQ_DMAREQ3 0x08
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#define DMAREQ_DMAREQ2 0x04
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#define DMAREQ_DMAREQ1 0x02
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#define DMAREQ_DMAREQ0 0x01
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/* DMAIRQ */
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#define DMAIRQ_DMAIF4 0x10
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#define DMAIRQ_DMAIF3 0x08
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#define DMAIRQ_DMAIF2 0x04
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#define DMAIRQ_DMAIF1 0x02
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#define DMAIRQ_DMAIF0 0x01
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/*---------------------------------------------------------------------------
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* XREG bits, excluding RF and USB
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*---------------------------------------------------------------------------*/
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/* FCTL */
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#define FCTL_BUSY 0x80
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#define FCTL_FULL 0x40
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#define FCTL_ABORT 0x20
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#define FCTL_CM1 0x08
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#define FCTL_CM0 0x04
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#define FCTL_WRITE 0x02
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#define FCTL_ERASE 0x01
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/*---------------------------------------------------------------------------
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* Radio Register Bits
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*---------------------------------------------------------------------------*/
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/* FRMFILT0 */
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#define FRMFILT0_FRAME_FILTER_EN 0x01
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/* FRMCTRL0 */
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#define FRMCTRL0_APPEND_DATA_MODE 0x80
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#define FRMCTRL0_AUTOCRC 0x40
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#define FRMCTRL0_AUTOACK 0x20
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#define FRMCTRL0_ENERGY_SCAN 0x10
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#define FRMCTRL0_RX_MODE1 0x08
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#define FRMCTRL0_RX_MODE0 0x04
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#define FRMCTRL0_TX_MODE1 0x02
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#define FRMCTRL0_TX_MODE0 0x01
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/* FRMCTRL1 */
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#define FRMCTRL1_PENDING_OR 0x04
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#define FRMCTRL1_IGNORE_TX_UNDERF 0x02
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#define FRMCTRL1_SET_RXENMASK_ON_TX 0x01
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/* FSMSTAT1 */
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#define FSMSTAT1_FIFO 0x80
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#define FSMSTAT1_FIFOP 0x40
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#define FSMSTAT1_SFD 0x20
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#define FSMSTAT1_CCA 0x10
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#define FSMSTAT1_TX_ACTIVE 0x02
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#define FSMSTAT1_RX_ACTIVE 0x01
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/* RSSISTAT */
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#define RSSISTAT_RSSI_VALID 0x01
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/* RFRND */
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#define RFRND_QRND 0x02
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#define RFRND_IRND 0x01
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#endif /* SFR_BITS_H_ */
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