b92a5afcc4
Using the AES interrupt allows the user process not to waste time polling for the completion of the operation. This time can be used by the user process to do something else, or to let the system enter PM0. Since the system is now free to perform various operations during a crypto operation, a protection of the crypto resource is added, and PM1+ is prohibited in order not to stall crypto operations. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
127 lines
4.6 KiB
C
127 lines
4.6 KiB
C
/*
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* Original file:
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Port to Contiki:
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* Copyright (c) 2013, ADVANSEE - http://www.advansee.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-aes
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* @{
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*
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* \file
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* Implementation of the cc2538 AES driver
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*/
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#include "contiki.h"
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#include "dev/rom-util.h"
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#include "dev/aes.h"
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#include "reg.h"
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_load_key(const void *key, uint8_t key_area)
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{
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uint32_t aligned_key[4];
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* The key address needs to be 4-byte aligned */
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rom_util_memcpy(aligned_key, key, sizeof(aligned_key));
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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/* Configure master control module */
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_KEYSTORE;
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/* Clear any outstanding events */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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/* Configure key store module (area, size): 128-bit key size */
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REG(AES_KEY_STORE_SIZE) = (REG(AES_KEY_STORE_SIZE) &
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~AES_KEY_STORE_SIZE_KEY_SIZE_M) |
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AES_KEY_STORE_SIZE_KEY_SIZE_128;
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/* Enable keys to write (e.g. Key 0) */
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REG(AES_KEY_STORE_WRITE_AREA) = 0x00000001 << key_area;
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/* Configure DMAC
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the key in ext. memory */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)aligned_key;
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/* Total key length in bytes (e.g. 16 for 1 x 128-bit key) */
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REG(AES_DMAC_CH0_DMALENGTH) = (REG(AES_DMAC_CH0_DMALENGTH) &
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~AES_DMAC_CH_DMALENGTH_DMALEN_M) |
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(0x10 << AES_DMAC_CH_DMALENGTH_DMALEN_S);
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/* Wait for operation to complete */
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while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_RESULT_AV));
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/* Check for absence of errors in DMA and key store */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
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/* Disable master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return CRYPTO_DMA_BUS_ERROR;
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}
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_WR_ERR;
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/* Disable master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_WRITE_ERROR;
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}
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/* Acknowledge the interrupt */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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/* Disable master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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/* Check status, if error return error code */
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if(!(REG(AES_KEY_STORE_WRITTEN_AREA) & (0x00000001 << key_area))) {
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return AES_KEYSTORE_WRITE_ERROR;
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}
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return CRYPTO_SUCCESS;
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}
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/** @} */
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