129 lines
5.1 KiB
C
129 lines
5.1 KiB
C
/*
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* Contiki SeedEye Platform project
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*
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* Copyright (c) 2012,
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* Scuola Superiore Sant'Anna (http://www.sssup.it) and
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* Consorzio Nazionale Interuniversitario per le Telecomunicazioni
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* (http://www.cnit.it).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/**
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* \addtogroup mrf24j40 MRF24J40 Driver
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*
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* @{
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*/
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/**
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* \file mrf24j40_arch.h
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* \brief MRF24J40 Specific Arch Conf
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* \author Giovanni Pellerano <giovanni.pellerano@evilaliv3.org>
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* \date 2012-03-21
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*/
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#ifndef MRF24J40_ARCH_H_
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#define MRF24J40_ARCH_H_
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#include "p32xxxx.h"
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#include <stdint.h>
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#include "dev/radio.h"
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/* Pin Mapping */
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#define MRF24J40_RESETn PORTGbits.RG15
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#define MRF24J40_INT PORTAbits.RA15
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#define MRF24J40_CSn PORTFbits.RF12
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#define MRF24J40_WAKE PORTGbits.RG12
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/* Pin Tri-States */
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#define MRF24J40_TRIS_RESETn TRISGbits.TRISG1
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#define MRF24J40_TRIS_INT TRISAbits.TRISA15
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#define MRF24J40_TRIS_CSn TRISFbits.TRISF12
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#define MRF24J40_TRIS_WAKE TRISGbits.TRISG12
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/* RESET low/high */
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#define MRF24J40_HARDRESET_LOW() MRF24J40_RESETn = 0
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#define MRF24J40_HARDRESET_HIGH() MRF24J40_RESETn = 1
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#define MRF24J40_CSn_LOW() MRF24J40_CSn = 0
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#define MRF24J40_CSn_HIGH() MRF24J40_CSn = 1
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/* Spi port Mapping */
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#ifdef __USE_MRF24J40_SPI_PORT_1__
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#define MRF24J40_SPI_PORT_INIT pic32_spi1_init
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#define MRF24J40_SPI_PORT_WRITE pic32_spi1_write
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#define MRF24J40_SPI_PORT_READ pic32_spi1_read
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#elif defined __USE_MRF24J40_SPI_PORT_1A__
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#define MRF24J40_SPI_PORT_INIT pic32_spi1A_init
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#define MRF24J40_SPI_PORT_WRITE pic32_spi1A_write
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#define MRF24J40_SPI_PORT_READ pic32_spi1A_read
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#elif defined __USE_MRF24J40_SPI_PORT_2A__
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#define MRF24J40_SPI_PORT_INIT pic32_spi2A_init
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#define MRF24J40_SPI_PORT_WRITE pic32_spi2A_write
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#define MRF24J40_SPI_PORT_READ pic32_spi2A_read
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#elif defined __USE_MRF24J40_SPI_PORT_3A__
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#define MRF24J40_SPI_PORT_INIT pic32_spi3A_init
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#define MRF24J40_SPI_PORT_WRITE pic32_spi3A_write
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#define MRF24J40_SPI_PORT_READ pic32_spi3A_read
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#else
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#define MRF24J40_SPI_PORT_INIT pic32_spi3A_init
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#define MRF24J40_SPI_PORT_WRITE pic32_spi3A_write
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#define MRF24J40_SPI_PORT_READ pic32_spi3A_read
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#endif
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/* IRC Configuration */
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#define MRF24J40_ISR() ISR(_EXTERNAL_4_VECTOR)
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#define MRF24J40_INTERRUPT_FLAG_SET() IFS0SET = _IFS0_INT4IF_MASK
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#define MRF24J40_INTERRUPT_FLAG_CLR() IFS0CLR = _IFS0_INT4IF_MASK
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#define MRF24J40_INTERRUPT_ENABLE_SET() IEC0SET = _IEC0_INT4IE_MASK
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#define MRF24J40_INTERRUPT_ENABLE_CLR() IEC0CLR = _IEC0_INT4IE_MASK
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#define MRF24J40_INTERRUPT_ENABLE_STAT() IEC0bits.INT4IE
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#define MRF24J40_PINDIRECTION_INIT() \
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do { \
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MRF24J40_TRIS_RESETn = 0; \
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MRF24J40_TRIS_INT = 1; \
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MRF24J40_TRIS_CSn = 0; \
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MRF24J40_TRIS_WAKE = 0; \
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} while(0)
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#define MRF24J40_INTERRUPT_INIT(p, s) \
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do { \
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MRF24J40_INTERRUPT_ENABLE_CLR(); \
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MRF24J40_INTERRUPT_FLAG_CLR(); \
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INTCONCLR = _INTCON_INT4EP_MASK; \
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IPC4CLR = _IPC4_INT4IP_MASK | _IPC4_INT4IS_MASK; \
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IPC4SET = (p << _IPC4_INT4IP_POSITION) | (s << _IPC4_INT4IS_POSITION); \
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MRF24J40_INTERRUPT_ENABLE_SET(); \
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} while(0)
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#endif /* MRF24J40_ARCH_H_ */
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/** @} */
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