e0aefd11d9
This patch extends the protection domain framework with a third plugin that is a hybrid of the previous two. The hardware task switching mechanism has a strictly-defined format for TSS data structures that causes more space to be consumed than would otherwise be required. This patch defines a smaller data structure that is allocated for each protection domain, only requiring 32 bytes instead of 128 bytes. It uses the same multi-segment memory layout as the TSS-based plugin and leaves paging disabled. However, it uses a similar mechanism as the paging plugin to perform system call dispatches and returns. For additional information, please refer to cpu/x86/mm/README.md.
71 lines
2.7 KiB
C
71 lines
2.7 KiB
C
/*
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* Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gdt.h"
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#include "gdt-layout.h"
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#include "prot-domains.h"
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#include "segmentation.h"
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#include "stacks.h"
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#include "tss.h"
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/* System-wide TSS */
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tss_t ATTR_BSS_KERN sys_tss;
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static segment_desc_t ATTR_BSS_GDT sys_tss_desc;
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Initialize system-wide TSS.
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*/
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void
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tss_init(void)
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{
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segment_desc_t seg_desc;
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/* Initialize TSS */
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KERN_WRITEW(sys_tss.iomap_base, sizeof(sys_tss));
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KERN_WRITEL(sys_tss.esp2, ((uint32_t)stacks_int) + STACKS_SIZE_INT);
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KERN_WRITEL(sys_tss.ss2, GDT_SEL_STK_INT);
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KERN_WRITEL(sys_tss.esp0, ((uint32_t)stacks_exc) + STACKS_SIZE_EXC);
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KERN_WRITEL(sys_tss.ss0, GDT_SEL_STK_EXC);
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segment_desc_init(&seg_desc,
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KERN_DATA_OFF_TO_PHYS_ADDR(&sys_tss), sizeof(sys_tss),
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SEG_FLAG(DPL, PRIV_LVL_EXC) |
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SEG_DESCTYPE_SYS | SEG_TYPE_TSS32_AVAIL);
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gdt_insert(GDT_IDX_OF_DESC(&sys_tss_desc), seg_desc);
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__asm__ __volatile__ (
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"ltr %0"
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:
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: "r" ((uint16_t)GDT_SEL_OF_DESC(&sys_tss_desc, 0)));
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}
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/*---------------------------------------------------------------------------*/
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