945 lines
24 KiB
C
945 lines
24 KiB
C
/*
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* Contiki SeedEye Platform project
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*
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* Copyright (c) 2012,
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* Scuola Superiore Sant'Anna (http://www.sssup.it) and
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* Consorzio Nazionale Interuniversitario per le Telecomunicazioni
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* (http://www.cnit.it).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/**
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* \addtogroup mrf24j40 MRF24J40 Driver
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*
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* @{
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*/
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/**
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* \file mrf24j40.c
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*
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* \brief MRF24J40 Driver
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* \author Giovanni Pellerano <giovanni.pellerano@evilaliv3.org>
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* \date 2012-03-21
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*/
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#include "contiki.h"
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#include "mrf24j40.h"
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#include "mrf24j40_arch.h"
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#include <pic32_spi.h>
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#include <pic32_irq.h>
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#include "net/packetbuf.h"
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#include "net/netstack.h"
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#define DEBUG 0
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#if DEBUG
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#include <stdio.h>
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#define PRINTF(...) printf(__VA_ARGS__)
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#else
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#define PRINTF(...)
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#endif
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/*---------------------------------------------------------------------------*/
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PROCESS(mrf24j40_process, "MRF24J40 driver");
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/*---------------------------------------------------------------------------*/
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static volatile uint8_t mrf24j40_last_lqi;
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static volatile uint8_t mrf24j40_last_rssi;
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static volatile uint8_t status_tx;
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static volatile uint8_t pending;
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static volatile uint8_t receive_on;
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/*---------------------------------------------------------------------------*/
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static void
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set_short_add_mem(uint8_t addr, uint8_t val)
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{
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const uint8_t tmp = MRF24J40_INTERRUPT_ENABLE_STAT();
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uint8_t msg[2];
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msg[0] = (addr << 1) | 0x01;
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msg[1] = val;
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_CLR();
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}
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MRF24J40_CSn_LOW();
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MRF24J40_SPI_PORT_WRITE(msg, 2);
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MRF24J40_CSn_HIGH();
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_SET();
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}
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}
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/*---------------------------------------------------------------------------*/
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static void
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set_long_add_mem(uint16_t addr, uint8_t val)
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{
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const uint8_t tmp = MRF24J40_INTERRUPT_ENABLE_STAT();
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uint8_t msg[3];
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msg[0] = (((uint8_t)(addr >> 3)) & 0x7F) | 0x80;
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msg[1] = (((uint8_t)(addr << 5)) & 0xE0) | 0x10;
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msg[2] = val;
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_CLR();
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}
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MRF24J40_CSn_LOW();
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MRF24J40_SPI_PORT_WRITE(msg, 3);
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MRF24J40_CSn_HIGH();
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_SET();
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}
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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get_short_add_mem(uint8_t addr)
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{
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const uint8_t tmp = MRF24J40_INTERRUPT_ENABLE_STAT();
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uint8_t ret_val;
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addr <<= 1;
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_CLR();
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}
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MRF24J40_CSn_LOW();
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MRF24J40_SPI_PORT_WRITE(&addr, 1);
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MRF24J40_SPI_PORT_READ(&ret_val, 1);
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MRF24J40_CSn_HIGH();
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_SET();
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}
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return ret_val;
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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get_long_add_mem(uint16_t addr)
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{
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const uint8_t tmp = MRF24J40_INTERRUPT_ENABLE_STAT();
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uint8_t ret_val;
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uint8_t msg[2];
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msg[0] = (((uint8_t)(addr >> 3)) & 0x7F) | 0x80;
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msg[1] = ((uint8_t)(addr << 5)) & 0xE0;
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_CLR();
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}
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MRF24J40_CSn_LOW();
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MRF24J40_SPI_PORT_WRITE(msg, 2);
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MRF24J40_SPI_PORT_READ(&ret_val, 1);
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MRF24J40_CSn_HIGH();
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if(tmp) {
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MRF24J40_INTERRUPT_ENABLE_SET();
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}
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return ret_val;
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}
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/*---------------------------------------------------------------------------*/
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static void
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reset_rf_state_machine(void)
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{
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/*
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* Reset RF state machine
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*/
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const uint8_t rfctl = get_short_add_mem(MRF24J40_RFCTL);
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set_short_add_mem(MRF24J40_RFCTL, rfctl | 0b00000100);
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set_short_add_mem(MRF24J40_RFCTL, rfctl & 0b11111011);
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clock_delay_usec(2500);
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}
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/*---------------------------------------------------------------------------*/
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void
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flush_rx_fifo(void)
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{
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set_short_add_mem(MRF24J40_RXFLUSH, get_short_add_mem(MRF24J40_RXFLUSH) | 0b00000001);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set the channel
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*
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* This routine sets the rx/tx channel
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*/
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void
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mrf24j40_set_channel(uint16_t ch)
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{
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set_long_add_mem(MRF24J40_RFCON0, ((ch - 11) << 4) | 0b00000011);
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reset_rf_state_machine();
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Store MAC PAN ID
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*
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* This routine sets the MAC PAN ID in the MRF24J40.
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*/
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void
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mrf24j40_set_panid(uint16_t id)
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{
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set_short_add_mem(MRF24J40_PANIDL, (uint8_t)id);
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set_short_add_mem(MRF24J40_PANIDH, (uint8_t)(id >> 8));
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Store short MAC address
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*
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* This routine sets the short MAC address in the MRF24J40.
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*/
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void
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mrf24j40_set_short_mac_addr(uint16_t addr)
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{
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set_short_add_mem(MRF24J40_SADRL, (uint8_t)addr);
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set_short_add_mem(MRF24J40_SADRH, (uint8_t)(addr >> 8));
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Store extended MAC address
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*
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* This routine sets the extended MAC address in the MRF24J40.
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*/
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void
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mrf24j40_set_extended_mac_addr(uint64_t addr)
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{
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set_short_add_mem(MRF24J40_EADR7, (uint8_t)addr);
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set_short_add_mem(MRF24J40_EADR6, (uint8_t)(addr >> 8));
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set_short_add_mem(MRF24J40_EADR5, (uint8_t)(addr >> 16));
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set_short_add_mem(MRF24J40_EADR4, (uint8_t)(addr >> 24));
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set_short_add_mem(MRF24J40_EADR3, (uint8_t)(addr >> 32));
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set_short_add_mem(MRF24J40_EADR2, (uint8_t)(addr >> 40));
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set_short_add_mem(MRF24J40_EADR1, (uint8_t)(addr >> 48));
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set_short_add_mem(MRF24J40_EADR0, (uint8_t)(addr >> 56));
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Get short MAC address
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*
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* This routine gets the short MAC address stored in the MRF24J40.
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*/
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void
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mrf24j40_get_short_mac_addr(uint16_t *addr)
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{
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*(((uint8_t *)& addr)) = get_short_add_mem(MRF24J40_SADRH);
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*(((uint8_t *)& addr) + 1) = get_short_add_mem(MRF24J40_SADRL);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Gets extended MAC address
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*
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* This routine gets the extended MAC address stored in the MRF24J40.
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*/
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void
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mrf24j40_get_extended_mac_addr(uint64_t *addr)
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{
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*(((uint8_t *)& addr)) = get_short_add_mem(MRF24J40_EADR7);
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*(((uint8_t *)& addr) + 1) = get_short_add_mem(MRF24J40_EADR6);
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*(((uint8_t *)& addr) + 2) = get_short_add_mem(MRF24J40_EADR5);
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*(((uint8_t *)& addr) + 3) = get_short_add_mem(MRF24J40_EADR4);
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*(((uint8_t *)& addr) + 4) = get_short_add_mem(MRF24J40_EADR3);
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*(((uint8_t *)& addr) + 5) = get_short_add_mem(MRF24J40_EADR2);
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*(((uint8_t *)& addr) + 6) = get_short_add_mem(MRF24J40_EADR1);
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*(((uint8_t *)& addr) + 7) = get_short_add_mem(MRF24J40_EADR0);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set TX power
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*
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* This routine sets the transmission power of the MRF24J40.
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*/
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void
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mrf24j40_set_tx_power(uint8_t pwr)
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{
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set_long_add_mem(MRF24J40_RFCON3, pwr);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Get radio status
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*
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* This routine returns the MRF24J40 status.
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*/
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uint8_t
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mrf24j40_get_status(void)
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{
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return get_long_add_mem(MRF24J40_RFSTATE);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Get the RSSI
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*
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* This routine returns the rssi value mesured in dbm
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* Note: to convert the returned value to dBm, use the table 3-8 available
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* in the MRF24J40 datasheet.
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*/
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uint8_t
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mrf24j40_get_rssi(void)
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{
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/*
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* 3.6.1 RSSI FIRMWARE REQUEST (RSSI MODE1)
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* In this mode, the host microcontroller sends a request
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* to calculate RSSI, then waits until it is done and then
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* reads the RSSI value. The steps are:
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*
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* 1.
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* Set RSSIMODE1 0x3E<7> – Initiate RSSI
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* calculation.
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*
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* 2.
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* Wait until RSSIRDY 0x3E<0> is set to ‘1’ – RSSI
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* calculation is complete.
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*
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* 3.
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* Read RSSI 0x210<7:0> – The RSSI register
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* contains the averaged RSSI received power
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* level for 8 symbol periods.
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*/
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/* Initiate RSSI calculation */
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set_short_add_mem(MRF24J40_BBREG6, get_short_add_mem(MRF24J40_BBREG6) | 0b10000000);
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/* Wait until RSSI calculation is done */
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while(!(get_short_add_mem(MRF24J40_BBREG6) & 0b00000001)) {
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;
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}
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mrf24j40_last_rssi = get_long_add_mem(MRF24J40_RSSI);
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return mrf24j40_last_rssi;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Get the last read RSSI
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*
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* This routine returns the last rssi value mesured in dbm
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* Note: to convert the returned value to dBm, use the table 3-8 available
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* in the MRF24J40 datasheet.
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*/
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uint8_t
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mrf24j40_get_last_rssi(void)
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{
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return mrf24j40_last_rssi;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Get the last read LQI
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*
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* This routine returns the last lqi
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*/
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uint8_t
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mrf24j40_get_last_lqi(void)
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{
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return mrf24j40_last_lqi;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Store message
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*
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* This routine stores a buffer of buf_len bytes in the TX_FIFO
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* buffer of the MRF24J40.
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||
*/
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int32_t
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mrf24j40_set_txfifo(const uint8_t *buf, uint8_t buf_len)
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{
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uint8_t i;
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if((buf_len == 0) || (buf_len > 128)) {
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return -1;
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}
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set_long_add_mem(MRF24J40_NORMAL_TX_FIFO, 0);
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set_long_add_mem(MRF24J40_NORMAL_TX_FIFO + 1, buf_len);
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for(i = 0; i < buf_len; ++i) {
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set_long_add_mem(MRF24J40_NORMAL_TX_FIFO + 2 + i, buf[i]);
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}
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return 0;
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}
|
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/*---------------------------------------------------------------------------*/
|
||
/**
|
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* \brief Get message
|
||
*
|
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* This routine is used to retrieve a message stored in the RX_FIFO
|
||
*/
|
||
int32_t
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mrf24j40_get_rxfifo(uint8_t *buf, uint8_t buf_len)
|
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{
|
||
uint8_t i, len;
|
||
|
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MRF24J40_INTERRUPT_ENABLE_CLR();
|
||
|
||
/* Disable packet reception */
|
||
set_short_add_mem(MRF24J40_BBREG1, 0b00000100);
|
||
|
||
/* Get packet length discarding 2 bytes (LQI, RSSI) */
|
||
len = get_long_add_mem(MRF24J40_RX_FIFO) - 2;
|
||
|
||
if(len <= buf_len) {
|
||
/* Get the packet */
|
||
for(i = 0; i < len; ++i) {
|
||
buf[i] = get_long_add_mem(MRF24J40_RX_FIFO + i + 1);
|
||
}
|
||
|
||
/*
|
||
* packet len includes = header + paylod + LQI + RSSI
|
||
*/
|
||
#ifdef ADD_RSSI_AND_LQI_TO_PACKET
|
||
mrf24j40_last_lqi = get_long_add_mem(MRF24J40_RX_FIFO + len + 3);
|
||
mrf24j40_last_rssi = get_long_add_mem(MRF24J40_RX_FIFO + len + 4);
|
||
#endif
|
||
} else {
|
||
len = 0;
|
||
}
|
||
|
||
/* Enable packet reception */
|
||
set_short_add_mem(MRF24J40_BBREG1, 0b00000000);
|
||
|
||
pending = 0;
|
||
|
||
#ifdef MRF24J40_PROMISCUOUS_MODE
|
||
/*
|
||
* Flush RX FIFO as suggested by the work around 1 in
|
||
* MRF24J40 Silicon Errata.
|
||
*/
|
||
flush_rx_fifo();
|
||
#endif
|
||
|
||
MRF24J40_INTERRUPT_ENABLE_SET();
|
||
|
||
return len == 0 ? -1 : len;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
/**
|
||
* \brief Start sleep
|
||
*
|
||
* This routine puts the radio in sleep mode.
|
||
*/
|
||
static void
|
||
put_to_sleep(void)
|
||
{
|
||
/* Prepare WAKE pin: */
|
||
MRF24J40_WAKE = 0;
|
||
|
||
/* Enable Immediate Wake-up mode */
|
||
set_short_add_mem(MRF24J40_WAKECON, 0b10000000);
|
||
|
||
set_short_add_mem(MRF24J40_SOFTRST, 0b00000100);
|
||
|
||
set_short_add_mem(MRF24J40_RXFLUSH, 0b01100000);
|
||
|
||
/* Put to sleep */
|
||
set_short_add_mem(MRF24J40_SLPACK, 0b10000000);
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
/**
|
||
* \brief Awake the radio
|
||
*
|
||
* This routine turns on and sets the radio on receiving mode.
|
||
* Note: After performing this routine the radio is in the receiving state.
|
||
*/
|
||
static void
|
||
wake(void)
|
||
{
|
||
/* Wake-up */
|
||
MRF24J40_WAKE = 1;
|
||
|
||
/* RF State Machine reset */
|
||
set_short_add_mem(MRF24J40_RFCTL, 0b00000100);
|
||
set_short_add_mem(MRF24J40_RFCTL, 0b00000000);
|
||
|
||
clock_delay_usec(2500);
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_on(void)
|
||
{
|
||
if(!receive_on) {
|
||
wake();
|
||
|
||
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
|
||
receive_on = 1;
|
||
}
|
||
|
||
return 1;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_off(void)
|
||
{
|
||
if(receive_on) {
|
||
ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
|
||
receive_on = 0;
|
||
|
||
put_to_sleep();
|
||
}
|
||
|
||
return 1;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
/**
|
||
* \brief Init transceiver
|
||
*
|
||
* This routine initializes the radio transceiver
|
||
*/
|
||
int
|
||
mrf24j40_init(void)
|
||
{
|
||
uint8_t i;
|
||
|
||
/* Set the IO pins direction */
|
||
MRF24J40_PINDIRECTION_INIT();
|
||
|
||
/* Set interrupt registers and reset flags */
|
||
MRF24J40_INTERRUPT_INIT(6, 3);
|
||
|
||
if(MRF24J40_SPI_PORT_INIT(10000000, SPI_DEFAULT) < 0)
|
||
return -1;
|
||
|
||
PRINTF("MRF24J40 Initialization started\n");
|
||
|
||
MRF24J40_HARDRESET_LOW();
|
||
|
||
clock_delay_usec(2500);
|
||
|
||
MRF24J40_HARDRESET_HIGH();
|
||
|
||
clock_delay_usec(2500);
|
||
|
||
/*
|
||
* bit 7:3 reserved: Maintain as ‘0’
|
||
* bit 2 RSTPWR: Power Management Reset bit
|
||
* 1 = Reset power management circuitry (bit is automatically cleared to ‘0’ by hardware)
|
||
* bit 1 RSTBB: Baseband Reset bit
|
||
* 1 = Reset baseband circuitry (bit is automatically cleared to ‘0’ by hardware)
|
||
* bit 0 RSTMAC: MAC Reset bit
|
||
* 1 = Reset MAC circuitry (bit is automatically cleared to ‘0’ by hardware)
|
||
*/
|
||
set_short_add_mem(MRF24J40_SOFTRST, 0b00000111);
|
||
|
||
/*
|
||
* wait until the radio reset is completed
|
||
*/
|
||
do {
|
||
i = get_short_add_mem(MRF24J40_SOFTRST);
|
||
} while((i & 0b0000111) != 0);
|
||
|
||
clock_delay_usec(2500);
|
||
|
||
|
||
/*
|
||
* bit 7 FIFOEN: FIFO Enable bit 1 = Enabled (default). Always maintain this bit as a ‘1’.
|
||
* bit 6 reserved: Maintain as ‘0’
|
||
* bit 5:2 TXONTS<3:0>: Transmitter Enable On Time Symbol bits(1)
|
||
* Transmitter on time before beginning of packet. Units: symbol period (16 μs).
|
||
* Minimum value: 0x1. Default value: 0x2 (2 * 16 μs = 32 μs). Recommended value: 0x6 (6 * 16 μs = 96 μs).
|
||
* bit 1:0 TXONT<8:7>: Transmitter Enable On Time Tick bits(1)
|
||
* Transmitter on time before beginning of packet. TXONT is a 9-bit value. TXONT<6:0> bits are located
|
||
* in SYMTICKH<7:1>. Units: tick (50 ns). Default value = 0x028 (40 * 50 ns = 2 μs).
|
||
*/
|
||
set_short_add_mem(MRF24J40_PACON2, 0b10011000);
|
||
|
||
mrf24j40_set_channel(MRF24J40_DEFAULT_CHANNEL);
|
||
|
||
set_long_add_mem(MRF24J40_RFCON1, 0b00000010); /* program the RF and Baseband Register */
|
||
/* as suggested by the datasheet */
|
||
|
||
set_long_add_mem(MRF24J40_RFCON2, 0b10000000); /* enable PLL */
|
||
|
||
mrf24j40_set_tx_power(0b00000000); /* set power 0dBm (plus 20db power amplifier 20dBm)*/
|
||
|
||
/*
|
||
* Set up
|
||
*
|
||
* bit 7 '1' as suggested by the datasheet
|
||
* bit 6:5 '00' reserved
|
||
* bit 4 '1' recovery from sleep 1 usec
|
||
* bit 3 '0' battery monitor disabled
|
||
* bit 2:0 '000' reserved
|
||
*/
|
||
set_long_add_mem(MRF24J40_RFCON6, 0b10010000);
|
||
|
||
set_long_add_mem(MRF24J40_RFCON7, 0b10000000); /* Sleep clock = 100kHz */
|
||
set_long_add_mem(MRF24J40_RFCON8, 0b00000010); /* as suggested by the datasheet */
|
||
|
||
set_long_add_mem(MRF24J40_SLPCON1, 0b00100001); /* as suggested by the datasheet */
|
||
|
||
/* Program CCA, RSSI threshold values */
|
||
set_short_add_mem(MRF24J40_BBREG2, 0b01111000); /* Recommended value by the datashet */
|
||
set_short_add_mem(MRF24J40_CCAEDTH, 0b01100000); /* Recommended value by the datashet */
|
||
|
||
#ifdef MRF24J40MB
|
||
/* Activate the external amplifier needed by the MRF24J40MB */
|
||
set_long_add_mem(MRF24J40_TESTMODE, 0b0001111);
|
||
PRINTF("MRF24J40 Init Amplifier activated \n");
|
||
#endif
|
||
|
||
#ifdef ADD_RSSI_AND_LQI_TO_PACKET
|
||
/* Enable the packet RSSI */
|
||
set_short_add_mem(MRF24J40_BBREG6, 0b01000000);
|
||
PRINTF("MRF24J40 Init append RSSI and LQI to packet\n");
|
||
#endif
|
||
|
||
/*
|
||
* Wait until the radio state machine is not on rx mode
|
||
*/
|
||
do {
|
||
i = get_long_add_mem(MRF24J40_RFSTATE);
|
||
} while((i & 0xA0) != 0xA0);
|
||
|
||
i = 0;
|
||
|
||
#ifdef MRF24J40_DISABLE_AUTOMATIC_ACK
|
||
i = i | 0b00100000;
|
||
PRINTF("MRF24J40 Init NO_AUTO_ACK\n");
|
||
#endif
|
||
|
||
#ifdef MRF24J40_PAN_COORDINATOR
|
||
i = i | 0b00001000;
|
||
PRINTF("MRF24J40 Init PAN COORD\n");
|
||
set_short_add_mem(MRF24J40_ORDER, 0b11111111);
|
||
#endif
|
||
|
||
#ifdef MRF24J40_COORDINATOR
|
||
i = i | 0b00000100;
|
||
PRINTF("MRF24J40 Init COORD\n");
|
||
#endif
|
||
|
||
#ifdef MRF24J40_ACCEPT_WRONG_CRC_PKT
|
||
i = i | 0b00000010;
|
||
PRINTF("MRF24J40 Init Accept Wrong CRC\n");
|
||
#endif
|
||
|
||
#ifdef MRF24J40_PROMISCUOUS_MODE
|
||
i = i | 0b00000001;
|
||
PRINTF("MRF24J40 Init PROMISCUOUS MODE\n");
|
||
#endif
|
||
|
||
/*
|
||
* Set the RXMCR register.
|
||
* Default setting i = 0x00, which means:
|
||
* - Automatic ACK;
|
||
* - Device is not a PAN coordinator;
|
||
* - Device is not a coordinator;
|
||
* - Accept only packets with good CRC
|
||
* - Discard packet when there is a MAC address mismatch,
|
||
* illegal frame type, dPAN/sPAN or MAC short address mismatch.
|
||
*/
|
||
set_short_add_mem(MRF24J40_RXMCR, i);
|
||
PRINTF("RXMCR 0x%X\n", i);
|
||
|
||
/*
|
||
* Set the TXMCR register.
|
||
* bit 7 '0' Enable No Carrier Sense Multiple Access (CSMA) Algorithm.
|
||
* bit 6 '0' Disable Battery Life Extension Mode bit.
|
||
* bit 5 '0' Disable Slotted CSMA-CA Mode bit.
|
||
* bit 4:3 '11' MAC Minimum Backoff Exponent bits (macMinBE).
|
||
* bit 2:0 '100' CSMA Backoff bits (macMaxCSMABackoff)
|
||
*/
|
||
set_short_add_mem(MRF24J40_TXMCR, 0b00011100);
|
||
|
||
i = get_short_add_mem(MRF24J40_TXMCR);
|
||
PRINTF("TXMCR 0x%X\n", i);
|
||
|
||
/*
|
||
* Set TX turn around time as defined by IEEE802.15.4 standard
|
||
*/
|
||
set_short_add_mem(MRF24J40_TXSTBL, 0b10010101);
|
||
set_short_add_mem(MRF24J40_TXTIME, 0b00110000);
|
||
|
||
#ifdef INT_POLARITY_HIGH
|
||
/* Set interrupt edge polarity high */
|
||
set_long_add_mem(MRF24J40_SLPCON0, 0b00000011);
|
||
PRINTF("MRF24J40 Init INT Polarity High\n");
|
||
#else
|
||
set_long_add_mem(MRF24J40_SLPCON0, 0b00000001);
|
||
PRINTF("MRF24J40 Init INT Polarity Low\n");
|
||
#endif
|
||
|
||
PRINTF("MRF24J40 Inititialization completed\n");
|
||
|
||
mrf24j40_last_lqi = 0;
|
||
mrf24j40_last_rssi = 0;
|
||
status_tx = MRF24J40_TX_ERR_NONE;
|
||
pending = 0;
|
||
|
||
receive_on = 1;
|
||
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
|
||
|
||
reset_rf_state_machine();
|
||
|
||
/* Flush RX FIFO */
|
||
flush_rx_fifo();
|
||
|
||
process_start(&mrf24j40_process, NULL);
|
||
|
||
/*
|
||
*
|
||
* Setup interrupts.
|
||
*
|
||
* set INTCON
|
||
* bit 7 '1' Disables the sleep alert interrupt
|
||
* bit 6 '1' Disables the wake-up alert interrupt
|
||
* bit 5 '1' Disables the half symbol timer interrupt
|
||
* bit 4 '1' Disables the security key request interrupt
|
||
* bit 3 '0' Enables the RX FIFO reception interrupt
|
||
* bit 2 '1' Disables the TX GTS2 FIFO transmission interrupt
|
||
* bit 1 '1' Disables the TX GTS1 FIFO transmission interrupt
|
||
* bit 0 '0' Enables the TX Normal FIFO transmission interrupt
|
||
*/
|
||
set_short_add_mem(MRF24J40_INTCON, 0b11110110);
|
||
|
||
return 0;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_prepare(const void *data, unsigned short len)
|
||
{
|
||
PRINTF("PREPARE %u bytes\n", len);
|
||
|
||
uint8_t receive_was_on = receive_on;
|
||
|
||
mrf24j40_on();
|
||
|
||
ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
|
||
|
||
ENERGEST_ON(ENERGEST_TYPE_TRANSMIT);
|
||
|
||
mrf24j40_set_txfifo(data, len);
|
||
|
||
ENERGEST_OFF(ENERGEST_TYPE_TRANSMIT);
|
||
|
||
if(!receive_was_on) {
|
||
mrf24j40_off();
|
||
} else {
|
||
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_transmit(unsigned short len)
|
||
{
|
||
PRINTF("TRANSMIT %u bytes\n", len);
|
||
|
||
uint8_t receive_was_on = receive_on;
|
||
|
||
mrf24j40_on();
|
||
|
||
ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
|
||
|
||
ENERGEST_ON(ENERGEST_TYPE_TRANSMIT);
|
||
|
||
status_tx = MRF24J40_TX_WAIT;
|
||
|
||
set_short_add_mem(MRF24J40_TXNCON, 0b00000001);
|
||
|
||
/* Wait until the transmission has finished. */
|
||
while(status_tx == MRF24J40_TX_WAIT) {
|
||
;
|
||
}
|
||
|
||
ENERGEST_OFF(ENERGEST_TYPE_TRANSMIT);
|
||
|
||
if(!receive_was_on) {
|
||
mrf24j40_off();
|
||
} else {
|
||
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
|
||
}
|
||
|
||
switch(status_tx) {
|
||
case MRF24J40_TX_ERR_NONE:
|
||
return RADIO_TX_OK;
|
||
case MRF24J40_TX_ERR_COLLISION:
|
||
return RADIO_TX_COLLISION;
|
||
case MRF24J40_TX_ERR_MAXRETRY:
|
||
return RADIO_TX_NOACK;
|
||
default:
|
||
return RADIO_TX_ERR;
|
||
}
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_write(const void *data, uint16_t len)
|
||
{
|
||
int ret = -1;
|
||
|
||
PRINTF("PREPARE & TRANSMIT %u bytes\n", len);
|
||
|
||
if(mrf24j40_prepare(data, len))
|
||
return ret;
|
||
|
||
ret = mrf24j40_transmit(len);
|
||
|
||
return ret;
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_read(void *data, uint16_t len)
|
||
{
|
||
return mrf24j40_get_rxfifo(data, len);
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_cca(void)
|
||
{
|
||
uint8_t ret;
|
||
|
||
uint8_t receive_was_on = receive_on;
|
||
|
||
mrf24j40_on();
|
||
|
||
ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
|
||
|
||
ENERGEST_ON(ENERGEST_TYPE_TRANSMIT);
|
||
|
||
ret = mrf24j40_get_rssi() <= 95; /* -69dbm */
|
||
|
||
if(!receive_was_on) {
|
||
mrf24j40_off();
|
||
} else {
|
||
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
|
||
}
|
||
|
||
return ret;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_receiving_packet(void)
|
||
{
|
||
return 0;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
int
|
||
mrf24j40_pending_packet(void)
|
||
{
|
||
return pending;
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
MRF24J40_ISR()
|
||
{
|
||
INT_status int_status;
|
||
TX_status tx_status;
|
||
|
||
ENERGEST_ON(ENERGEST_TYPE_IRQ);
|
||
|
||
int_status.val = get_short_add_mem(MRF24J40_INTSTAT);
|
||
|
||
if(!int_status.val) {
|
||
return;
|
||
}
|
||
|
||
if(int_status.bits.RXIF) {
|
||
|
||
pending = 1;
|
||
|
||
process_poll(&mrf24j40_process);
|
||
|
||
}
|
||
|
||
if(int_status.bits.TXNIF) {
|
||
|
||
tx_status.val = get_short_add_mem(MRF24J40_TXSTAT);
|
||
|
||
if(tx_status.bits.TXNSTAT) {
|
||
if(tx_status.bits.CCAFAIL) {
|
||
status_tx = MRF24J40_TX_ERR_COLLISION;
|
||
} else {
|
||
status_tx = MRF24J40_TX_ERR_MAXRETRY;
|
||
}
|
||
} else {
|
||
status_tx = MRF24J40_TX_ERR_NONE;
|
||
}
|
||
}
|
||
|
||
MRF24J40_INTERRUPT_FLAG_CLR();
|
||
|
||
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
|
||
}
|
||
/*---------------------------------------------------------------------------*/
|
||
PROCESS_THREAD(mrf24j40_process, ev, data)
|
||
{
|
||
PROCESS_BEGIN();
|
||
|
||
uint8_t ret;
|
||
|
||
while(1) {
|
||
PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL);
|
||
|
||
if(!pending) {
|
||
continue;
|
||
}
|
||
|
||
packetbuf_clear();
|
||
|
||
ret = mrf24j40_read(packetbuf_dataptr(), PACKETBUF_SIZE);
|
||
|
||
packetbuf_set_datalen(ret);
|
||
|
||
#ifdef ADD_RSSI_AND_LQI_TO_PACKET
|
||
packetbuf_set_attr(PACKETBUF_ATTR_RSSI, mrf24j40_last_rssi);
|
||
packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, mrf24j40_last_lqi);
|
||
#endif
|
||
|
||
NETSTACK_RDC.input();
|
||
}
|
||
|
||
PROCESS_END();
|
||
}
|
||
|
||
/*---------------------------------------------------------------------------*/
|
||
const struct radio_driver mrf24j40_driver = {
|
||
mrf24j40_init,
|
||
mrf24j40_prepare,
|
||
mrf24j40_transmit,
|
||
mrf24j40_write,
|
||
mrf24j40_read,
|
||
mrf24j40_cca,
|
||
mrf24j40_receiving_packet,
|
||
mrf24j40_pending_packet,
|
||
mrf24j40_on,
|
||
mrf24j40_off
|
||
};
|
||
/*---------------------------------------------------------------------------*/
|
||
|
||
/** @} */
|