135 lines
4.7 KiB
C
135 lines
4.7 KiB
C
/*
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* Copyright (c) 2010, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/**
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* \file
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* A brief description of what this file is
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* \author
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* Niclas Finne <nfi@sics.se>
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* Joakim Eriksson <joakime@sics.se>
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*/
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#ifndef PLATFORM_CONF_H_
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#define PLATFORM_CONF_H_
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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/* Platform name, type, and MCU clock rate */
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#define PLATFORM_NAME "Iris"
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#define PLATFORM_TYPE IRIS
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#ifndef F_CPU
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#define F_CPU 8000000UL
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#endif
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/* The AVR tick interrupt usually is done with an 8 bit counter around 128 Hz.
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* 125 Hz needs slightly more overhead during the interrupt, as does a 32 bit
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* clock_time_t.
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*/
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/* Clock ticks per second */
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#define CLOCK_CONF_SECOND 128
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#if 1
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/* 16 bit counter overflows every ~10 minutes */
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typedef unsigned short clock_time_t;
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#define CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0)
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#define INFINITE_TIME 0xffff
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#define RIME_CONF_BROADCAST_ANNOUNCEMENT_MAX_TIME INFINITE_TIME/CLOCK_CONF_SECOND /* Default uses 600 */
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#define COLLECT_CONF_BROADCAST_ANNOUNCEMENT_MAX_TIME INFINITE_TIME/CLOCK_CONF_SECOND /* Default uses 600 */
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#else
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typedef unsigned long clock_time_t;
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#define CLOCK_LT(a,b) ((signed long)((a)-(b)) < 0)
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#define INFINITE_TIME 0xffffffff
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#endif
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/* These routines are not part of the contiki core but can be enabled in cpu/avr/clock.c */
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void clock_delay_msec(uint16_t howlong);
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void clock_adjust_ticks(clock_time_t howmany);
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/* LED ports */
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#define LEDS_PxDIR DDRA // port direction register
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#define LEDS_PxOUT PORTA // port register
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#define LEDS_CONF_RED 0x04 //red led
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#define LEDS_CONF_GREEN 0x02 // green led
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#define LEDS_CONF_YELLOW 0x01 // yellow led
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/* COM port to be used for SLIP connection */
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#define SLIP_PORT RS232_PORT_0
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/* Pre-allocated memory for loadable modules heap space (in bytes)*/
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#define MMEM_CONF_SIZE 256
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/* Use the following address for code received via the codeprop
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* facility
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*/
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#define EEPROMFS_ADDR_CODEPROP 0x8000
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#define EEPROM_NODE_ID_START 0x00
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#define NETSTACK_CONF_RADIO rf230_driver
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/*
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* SPI bus configuration for the TMote Sky.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF SPDR
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#define SPI_RXBUF SPDR
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#define BV(bitno) _BV(bitno)
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#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
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#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
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#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
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/*
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* SPI bus - M25P80 external flash configuration.
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*/
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#define FLASH_PWR 3 /* P4.3 Output */
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#define FLASH_CS 4 /* P4.4 Output */
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#define FLASH_HOLD 7 /* P4.7 Output */
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/* Enable/disable flash access to the SPI bus (active low). */
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#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
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#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
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#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
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#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
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#define CSN 0
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#endif /* PLATFORM_CONF_H_ */
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