a5046e83c7
This is a general cleanup of things like code style issues and code structure of the STM32w port to make it more like the rest of Contiki is structured.
474 lines
15 KiB
C
474 lines
15 KiB
C
/*
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* File: clocks.c
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* Description: STM32W108 internal, clock specific HAL functions
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* This file is provided for completeness and it should not be modified
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* by customers as it comtains code very tightly linked to undocumented
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* device features
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*
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* <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
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*/
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#include PLATFORM_HEADER
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#include "error.h"
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#include "hal/hal.h"
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#include "hal/micro/cortexm3/mpu.h"
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#include "hal/micro/cortexm3/mfg-token.h"
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//Provide a simple means for enabling calibration debug output
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#define CALDBG(x)
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//#define CALDBG(x) x
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//The slowest frequency for the 10kHz RC source is 8kHz (125us). The PERIOD
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//register updates every 16 cycles, so to be safe 17 cycles = 2125us. But,
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//we need twice this maximum time because the period measurement runs
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//asynchronously, and the value of CLKRC_TUNE is changed immediately before
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//the delay.
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#define SLOWRC_PERIOD_SETTLE_TIME 4250
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//The CLK_PERIOD register measures the number of 12MHz clock cycles that
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//occur in 16 cycles of the SlowRC clock. This is meant to smooth out the the
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//noise inherently present in the analog RC source. While these 16 cycles
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//smooths out most noise, there is still some jitter in the bottom bits of
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//CLK_PERIOD. To further smooth out the noise, we take several readings of
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//CLK_PERIOD and average them out. Testing has shown that the bottom 3 and 4
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//bits of CLK_PERIOD contain most of the jitter. Averaging 8 samples will
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//smooth out 3 bits of jitter and provide a realiable and stable reading useful
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//in the calculations, while taking much less time than 16 or 32 samples.
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#define SLOWRC_PERIOD_SAMPLES 8
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//The register CLK1K_CAL is a fractional divider that divides the 10kHz analog
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//source with the goal of generating a 1024Hz, clk1k output.
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// 10000Hz / CLK1K_CAL = 1024Hz.
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//Since the CLK_PERIOD register measures the number of 12MHz cycles in 16
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//cycles of the RC:
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// 16 * 12000000
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// ------------- = ~10kHz
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// CLK_PERIOD
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//and
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// ~10kHz / 1024 = X
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//where X is the fractional number that belongs in CLK1K_CAL. Since the
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//integer portion of CLK1K_CAL is bits 15:11 and the fractional is 10:0,
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//multiplying X by 2048 (bit shift left by 11) generates the proper CLK1K_CAL
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//register value.
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//
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//Putting this all together:
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// 16 * 12000000 * 2048 384000000
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// -------------------- = ------------ = CLK1K_CAL
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// CLK_PERIOD * 1024 CLK_PERIOD
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//
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#define CLK1K_NUMERATOR 384000000
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void halInternalCalibrateSlowRc( void )
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{
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uint8_t i;
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uint32_t average=0;
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int16_t delta;
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uint32_t period;
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "halInternalCalibrateSlowRc:\r\n");
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)
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////---- STEP 1: coarsely tune SlowRC in analog section to ~10kHz ----////
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//To operate properly across the full temperature and voltage range,
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//the RC source in the analog section needs to be first coarsely tuned
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//to 10kHz. The CLKRC_TUNE register, which is 2's compliment, provides 16
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//steps at ~400Hz per step yielding approximate frequences of 8kHz at 7
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//and 15kHz at -8.
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//Start with our reset values for TUNE and CAL
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CLK_PERIODMODE = 0; //measure SlowRC
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CLKRC_TUNE = CLKRC_TUNE_RESET;
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CLK1K_CAL = CLK1K_CAL_RESET;
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//wait for the PERIOD register to properly update
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halCommonDelayMicroseconds(SLOWRC_PERIOD_SETTLE_TIME);
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//Measure the current CLK_PERIOD to obtain a baseline
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT,
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"period: %u, ", CLK_PERIOD);
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u Hz\r\n",
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((uint16_t)(((uint32_t)192000000)/((uint32_t)CLK_PERIOD))));
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)
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//For 10kHz, the ideal CLK_PERIOD is 19200. Calculate the PERIOD delta.
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//It's possible for a chip's 10kHz source RC to be too far out of range
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//for the CLKRC_TUNE to bring it back to 10kHz. Therefore, we have to
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//ensure that our delta correction does not exceed the tune range so
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//tune has to be capped to the end of the vailable range so it does not
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//wrap. Even if we cannot achieve 10kHz, the 1kHz calibration can still
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//properly correct to 1kHz.
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//Each CLKRC_TUNE step yields a CLK_PERIOD delta of *approximately* 800.
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//Calculate how many steps we are off. While dividing by 800 may seem
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//like an ugly calculation, the precision of the result is worth the small
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//bit of code and time needed to do a divide.
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period = CLK_PERIOD;
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//Round to the nearest integer
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delta = (19200+400) - period;
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delta /= 800;
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//CLKRC_TUNE is a 4 bit signed number. cap the delta to 7/-8
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if(delta > 7) {
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delta = 7;
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}
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if(delta < -8) {
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delta = -8;
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}
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "TUNE steps delta: %d\r\n",
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delta);
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)
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CLKRC_TUNE = delta;
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//wait for PERIOD to update before taking another sample
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halCommonDelayMicroseconds(SLOWRC_PERIOD_SETTLE_TIME);
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT,
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"period: %u, ", CLK_PERIOD);
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u Hz\r\n",
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((uint16_t)(((uint32_t)192000000)/((uint32_t)CLK_PERIOD))));
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)
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//The analog section should now be producing an output of ~10kHz
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////---- STEP 2: fine tune the SlowRC to 1024Hz ----////
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//Our goal is to generate a 1024Hz source. The register CLK1K_CAL is a
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//fractional divider that divides the 10kHz analog source and generates
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//the clk1k output. At reset, the default value is 0x5000 which yields a
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//division of 10.000. By averaging several samples of CLK_PERIOD, we
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//can then calculate the proper divisor need for CLK1K_CAL to make 1024Hz.
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for(i=0;i<SLOWRC_PERIOD_SAMPLES;i++) {
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halCommonDelayMicroseconds(SLOWRC_PERIOD_SETTLE_TIME);
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average += CLK_PERIOD;
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}
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//calculate the average, with proper rounding
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average = (average+(SLOWRC_PERIOD_SAMPLES/2))/SLOWRC_PERIOD_SAMPLES;
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "average: %u, %u Hz\r\n",
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((uint16_t)average), ((uint16_t)(((uint32_t)192000000)/((uint32_t)average))));
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)
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//using an average period sample, calculate the clk1k divisor
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CLK1K_CAL = (uint16_t)(CLK1K_NUMERATOR/average);
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT,"CLK1K_CAL=%2X\r\n",CLK1K_CAL);
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)
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//The SlowRC timer is now producing a 1024Hz tick (+/-2Hz).
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "DONE\r\n");
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)
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}
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//The slowest frequency for the FastRC source is 4MHz (250ns). The PERIOD
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//register updates every 256 cycles, so to be safe 257 cycles = 64us. But,
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//we need twice this maximum time because the period measurement runs
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//asynchronously, and the value of OSCHF_TUNE is changed immediately before
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//the delay.
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#define FASTRC_PERIOD_SETTLE_TIME 128
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//The CLK_PERIOD register measures the number of 12MHz cycles in 256
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//cycles of OSCHF:
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// 256 * 12000000
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// ------------- = ~12MHz
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// CLK_PERIOD
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void halInternalCalibrateFastRc(void)
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{
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int32_t newTune = -16;
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CALDBG(
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "halInternalCalibrateFastRc:\r\n");
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)
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////---- coarsely tune FastRC in analog section to ~12MHz ----////
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//The RC source in the analog section needs to be coarsely tuned
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//to 12MHz. The OSCHF_TUNE register, which is 2's compliment, provides 32
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//steps at ~0.5MHz per step yielding approximate frequences of 4MHz at 15
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//and 20MHz at -16.
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CLK_PERIODMODE = 1; //measure FastRC
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CALDBG(
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//start at the fastest possible frequency
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OSCHF_TUNE = newTune;
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//wait for the PERIOD register to properly update
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halCommonDelayMicroseconds(FASTRC_PERIOD_SETTLE_TIME);
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//Measure the current CLK_PERIOD to obtain a baseline
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stSerialPrintf(ST_ASSERT_SERIAL_PORT,
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"period: %u, ", CLK_PERIOD);
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u kHz\r\n",
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((uint16_t)((((uint32_t)3072000000)/((uint32_t)CLK_PERIOD))/1000)));
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)
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//For 12MHz, the ideal CLK_PERIOD is 256. Tune the frequency down until
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//the period is <= 256, which says the frequency is as close to 12MHz as
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//possible (without going over 12MHz)
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//Start at the fastest possible frequency (-16) and increase to the slowest
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//possible (15). When CLK_PERIOD is <=256 or we run out of tune values,
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//we're done.
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for(;newTune<16;newTune++) {
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//decrease frequency by one step (by increasing tune value)
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OSCHF_TUNE = newTune;
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//wait for the PERIOD register to properly update
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halCommonDelayMicroseconds(FASTRC_PERIOD_SETTLE_TIME);
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//kickout if we're tuned
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if(CLK_PERIOD>=256) {
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break;
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}
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}
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CALDBG(
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//Measure the current CLK_PERIOD to show the final result
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stSerialPrintf(ST_ASSERT_SERIAL_PORT,
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"period: %u, ", CLK_PERIOD);
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stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u kHz\r\n",
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((uint16_t)((((uint32_t)3072000000)/((uint32_t)CLK_PERIOD))/1000)));
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)
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//The analog section should now be producing an output of 11.5MHz - 12.0MHz
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}
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#define OSC24M_BIASTRIM_OFFSET (0x2)
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#define OSC24M_BIASTRIM_MIN (0+OSC24M_BIASTRIM_OFFSET)
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#define OSC24M_BIASTRIM_MAX OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK
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#define OSC24M_BIASTRIM_MSB (1 << (OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS-1))
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#define OSC24M_BIASTRIM_UNINIT (0xFFFF)
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tokTypeMfgOsc24mBiasTrim biasTrim=OSC24M_BIASTRIM_UNINIT;
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//This function is intended to be called periodically, from the stack and
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//application, to check the XTAL bias trim is within appropriate levels
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//and adjust if not. This function is *not* designed to be used before
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//halInternalSwitchToXtal has been called.
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void halCommonCheckXtalBiasTrim(void)
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{
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//HI is set indicating the trim value is too high. Decrement the trim.
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if((OSC24M_COMP & OSC24M_HI) == OSC24M_HI) {
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biasTrim--;
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}
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//LO is cleared indicating the trim value is too low. Inrement the trim.
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if((OSC24M_COMP & OSC24M_LO) != OSC24M_LO) {
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biasTrim++;
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//Add an offset to the bias trim as a factor of safety.
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if(biasTrim < (OSC24M_BIASTRIM_MAX - OSC24M_BIASTRIM_OFFSET)) {
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biasTrim += OSC24M_BIASTRIM_OFFSET;
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} else {
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biasTrim = OSC24M_BIASTRIM_MAX;
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}
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}
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//Don't allow bias trim to dip below the offset regardless of LO.
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if(biasTrim<OSC24M_BIASTRIM_OFFSET) {
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biasTrim = OSC24M_BIASTRIM_OFFSET;
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}
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OSC24M_BIASTRIM = biasTrim;
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}
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static boolean setBiasCheckLow(void)
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{
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OSC24M_BIASTRIM = biasTrim;
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halCommonDelayMicroseconds(1500);
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return ((OSC24M_COMP & OSC24M_LO) == OSC24M_LO);
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}
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void halInternalSearchForBiasTrim(void)
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{
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uint8_t bit;
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//Enable the XTAL so we can search for the proper bias trim (NOTE: This
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//will also forcefully ensure we're on the OSCHF so that we don't
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//accidentally trip the NMI while searching.)
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OSC24M_CTRL = OSC24M_CTRL_OSC24M_EN;
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//Do a binary search of the 4-bit bias trim values to find
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//smallest bias trim value for which LO = 1.
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biasTrim = 0;
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bit = (OSC24M_BIASTRIM_MSB << 1);
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do {
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bit >>= 1;
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biasTrim += bit;
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//Set trim and wait for 1.5ms to allow the oscillator to stabilize.
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if(setBiasCheckLow()) {
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biasTrim -= bit;
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}
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} while(bit);
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//If the last bias value went too low, increment it.
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if((OSC24M_COMP & OSC24M_LO) != OSC24M_LO) {
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biasTrim++;
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}
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//Add an offset to the bias trim as a factor of safety.
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if(biasTrim < (OSC24M_BIASTRIM_MAX - OSC24M_BIASTRIM_OFFSET)) {
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biasTrim += OSC24M_BIASTRIM_OFFSET;
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} else {
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biasTrim = OSC24M_BIASTRIM_MAX;
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}
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//Using the shadow variable, the clock switch logic will take over from here,
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//enabling, verifying, and tweaking as needed.
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}
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//This function configures the flash access controller for optimal
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//current consumption when FCLK is operating at 24MHz. By providing
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//this function the calling code does not have to be aware of the
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//details of setting FLASH_ACCESS.
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static void halInternalConfigXtal24MhzFlashAccess(void)
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{
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ATOMIC(
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BYPASS_MPU(
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#if defined(CORTEXM3_STM32W108)
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FLASH_ACCESS = (FLASH_ACCESS_PREFETCH_EN |
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(1<<FLASH_ACCESS_CODE_LATENCY_BIT));
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#endif
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)
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)
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}
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//NOTE: The global "shadow" variable biasTrim will be set by either:
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// A) TOKEN_MFG_OSC24M_BIAS_TRIM when booting fresh
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// B) searchForBiasTrim() when booting fresh and the token is not valid
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// C) halInternalSwitchToXtal() if halInternalSwitchToXtal() already ran
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void halInternalSwitchToXtal(void)
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{
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boolean loSet;
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boolean hiSet;
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boolean setTrimOneLastTime = FALSE;
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//If it hasn't yet been initialized,
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//preload our biasTrim shadow variable from the token. If the token is
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//not set, then run a search to find an initial value. The bias trim
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//algorithm/clock switch logic will always use the biasTrim shadow
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//variable as the starting point for finding the bias, and then
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//save that new bias to the shadow variable.
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if(biasTrim == OSC24M_BIASTRIM_UNINIT) {
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halCommonGetMfgToken(&biasTrim, TOKEN_MFG_OSC24M_BIAS_TRIM);
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if(biasTrim == 0xFFFF) {
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halInternalSearchForBiasTrim();
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}
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}
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//Ensure the XTAL is enabled (with the side effect of ensuring we're
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//still on OSCHF).
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OSC24M_CTRL = OSC24M_CTRL_OSC24M_EN;
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do {
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//Set trim to our shadow variable and wait for 1.5ms to allow the
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//oscillator to stabilize.
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loSet = setBiasCheckLow();
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hiSet = (OSC24M_COMP & OSC24M_HI) == OSC24M_HI;
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//The bias is too low, so we need to increment the bias trim.
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if(!loSet) {
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biasTrim++;
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}
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//The bias is too high, so we need to decrement the bias trim.
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if(hiSet) {
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//but don't trim below our min value
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if(biasTrim>OSC24M_BIASTRIM_MIN) {
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biasTrim--;
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setTrimOneLastTime = TRUE;
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}
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}
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//Kickout when HI=0 and LO=1 or we've hit the MAX or the MIN
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} while( (hiSet || !loSet) &&
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(biasTrim<OSC24M_BIASTRIM_MAX) &&
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(biasTrim>OSC24M_BIASTRIM_MIN) );
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//The LO bit being cleared means we've corrected up from the bottom and
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//therefore need to apply the offset. Additionally, if our trim value
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//is below the offset, we still need to apply the offset. And, when
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//applying the offset respect the max possible value of the trim.
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if(!loSet || (biasTrim<OSC24M_BIASTRIM_OFFSET)){
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if(biasTrim < (OSC24M_BIASTRIM_MAX - OSC24M_BIASTRIM_OFFSET)) {
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biasTrim += OSC24M_BIASTRIM_OFFSET;
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} else {
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biasTrim = OSC24M_BIASTRIM_MAX;
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}
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setTrimOneLastTime = TRUE;
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}
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if(setTrimOneLastTime) {
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setBiasCheckLow();
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}
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//We've found a valid trim value and we've waited for the oscillator
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//to stabalize, it's now safe to select the XTAL
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OSC24M_CTRL |= OSC24M_CTRL_OSC24M_SEL;
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//If the XTAL switch failed, the NMI ISR will trigger, creeping the bias
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//trim up higher, and if max bias is reached the ISR will trigger a reset.
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//Our standard mode of operation is 24MHz (CPU/FCLK is sourced from SYSCLK)
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CPU_CLKSEL = CPU_CLKSEL_FIELD;
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//Configure flash access for optimal current consumption at 24MHz
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halInternalConfigXtal24MhzFlashAccess();
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}
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