0f137e4bdd
This function is only supposed to be used by uart.c, so it should be static. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
401 lines
13 KiB
C
401 lines
13 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-uart
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* @{
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*
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* \file
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* Implementation of the cc2538 UART driver
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*/
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#include "contiki.h"
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#include "sys/energest.h"
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#include "dev/sys-ctrl.h"
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#include "dev/ioc.h"
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#include "dev/gpio.h"
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#include "dev/uart.h"
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#include "lpm.h"
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#include "reg.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#ifndef UART0_RX_PORT
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#define UART0_RX_PORT (-1)
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#endif
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#ifndef UART0_RX_PIN
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#define UART0_RX_PIN (-1)
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#endif
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#if UART0_RX_PORT >= 0 && UART0_RX_PIN < 0 || \
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UART0_RX_PORT < 0 && UART0_RX_PIN >= 0
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#error Both UART0_RX_PORT and UART0_RX_PIN must be valid or invalid
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#endif
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#ifndef UART0_TX_PORT
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#define UART0_TX_PORT (-1)
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#endif
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#ifndef UART0_TX_PIN
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#define UART0_TX_PIN (-1)
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#endif
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#if UART0_TX_PORT >= 0 && UART0_TX_PIN < 0 || \
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UART0_TX_PORT < 0 && UART0_TX_PIN >= 0
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#error Both UART0_TX_PORT and UART0_TX_PIN must be valid or invalid
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#endif
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#if UART0_RX_PORT >= 0 && UART0_TX_PORT < 0 || \
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UART0_RX_PORT < 0 && UART0_TX_PORT >= 0
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#error Both UART0_RX and UART0_TX pads must be valid or invalid
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#endif
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#if UART_IN_USE(0) && UART0_RX_PORT < 0
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#error Contiki is configured to use UART0, but its pads are not valid
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#endif
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#ifndef UART1_RX_PORT
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#define UART1_RX_PORT (-1)
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#endif
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#ifndef UART1_RX_PIN
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#define UART1_RX_PIN (-1)
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#endif
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#if UART1_RX_PORT >= 0 && UART1_RX_PIN < 0 || \
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UART1_RX_PORT < 0 && UART1_RX_PIN >= 0
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#error Both UART1_RX_PORT and UART1_RX_PIN must be valid or invalid
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#endif
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#ifndef UART1_TX_PORT
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#define UART1_TX_PORT (-1)
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#endif
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#ifndef UART1_TX_PIN
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#define UART1_TX_PIN (-1)
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#endif
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#if UART1_TX_PORT >= 0 && UART1_TX_PIN < 0 || \
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UART1_TX_PORT < 0 && UART1_TX_PIN >= 0
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#error Both UART1_TX_PORT and UART1_TX_PIN must be valid or invalid
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#endif
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#if UART1_RX_PORT >= 0 && UART1_TX_PORT < 0 || \
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UART1_RX_PORT < 0 && UART1_TX_PORT >= 0
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#error Both UART1_RX and UART1_TX pads must be valid or invalid
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#endif
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#if UART_IN_USE(1) && UART1_RX_PORT < 0
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#error Contiki is configured to use UART1, but its pads are not valid
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#endif
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#ifndef UART1_CTS_PORT
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#define UART1_CTS_PORT (-1)
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#endif
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#ifndef UART1_CTS_PIN
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#define UART1_CTS_PIN (-1)
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#endif
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#if UART1_CTS_PORT >= 0 && UART1_CTS_PIN < 0 || \
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UART1_CTS_PORT < 0 && UART1_CTS_PIN >= 0
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#error Both UART1_CTS_PORT and UART1_CTS_PIN must be valid or invalid
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#endif
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#ifndef UART1_RTS_PORT
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#define UART1_RTS_PORT (-1)
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#endif
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#ifndef UART1_RTS_PIN
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#define UART1_RTS_PIN (-1)
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#endif
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#if UART1_RTS_PORT >= 0 && UART1_RTS_PIN < 0 || \
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UART1_RTS_PORT < 0 && UART1_RTS_PIN >= 0
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#error Both UART1_RTS_PORT and UART1_RTS_PIN must be valid or invalid
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#endif
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/*---------------------------------------------------------------------------*/
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/*
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* Baud rate defines used in uart_init() to set the values of UART_IBRD and
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* UART_FBRD in order to achieve the configured baud rates.
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*/
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#define UART_CLOCK_RATE SYS_CTRL_SYS_CLOCK
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#define UART_CTL_HSE_VALUE 0
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#define UART_CTL_VALUE (UART_CTL_RXE | UART_CTL_TXE | (UART_CTL_HSE_VALUE << 5))
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/* DIV_ROUND() divides integers while avoiding a rounding error: */
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#define DIV_ROUND(num, denom) (((num) + (denom) / 2) / (denom))
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#define BAUD2BRD(baud) DIV_ROUND(UART_CLOCK_RATE << (UART_CTL_HSE_VALUE + 2), (baud))
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#define BAUD2IBRD(baud) (BAUD2BRD(baud) >> 6)
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#define BAUD2FBRD(baud) (BAUD2BRD(baud) & 0x3f)
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/*---------------------------------------------------------------------------*/
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typedef struct {
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int8_t port;
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int8_t pin;
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} uart_pad_t;
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typedef struct {
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uint32_t sys_ctrl_rcgcuart_uart;
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uint32_t sys_ctrl_scgcuart_uart;
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uint32_t sys_ctrl_dcgcuart_uart;
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uint32_t base;
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uint32_t ioc_uartrxd_uart;
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uint32_t ioc_pxx_sel_uart_txd;
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uint32_t ibrd;
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uint32_t fbrd;
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uart_pad_t rx;
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uart_pad_t tx;
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uart_pad_t cts;
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uart_pad_t rts;
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uint8_t nvic_int;
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} uart_regs_t;
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/*---------------------------------------------------------------------------*/
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static const uart_regs_t uart_regs[UART_INSTANCE_COUNT] = {
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{
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.sys_ctrl_rcgcuart_uart = SYS_CTRL_RCGCUART_UART0,
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.sys_ctrl_scgcuart_uart = SYS_CTRL_SCGCUART_UART0,
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.sys_ctrl_dcgcuart_uart = SYS_CTRL_DCGCUART_UART0,
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.base = UART_0_BASE,
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.ioc_uartrxd_uart = IOC_UARTRXD_UART0,
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.ioc_pxx_sel_uart_txd = IOC_PXX_SEL_UART0_TXD,
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.ibrd = BAUD2IBRD(UART0_CONF_BAUD_RATE),
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.fbrd = BAUD2FBRD(UART0_CONF_BAUD_RATE),
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.rx = {UART0_RX_PORT, UART0_RX_PIN},
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.tx = {UART0_TX_PORT, UART0_TX_PIN},
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.cts = {-1, -1},
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.rts = {-1, -1},
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.nvic_int = NVIC_INT_UART0
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}, {
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.sys_ctrl_rcgcuart_uart = SYS_CTRL_RCGCUART_UART1,
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.sys_ctrl_scgcuart_uart = SYS_CTRL_SCGCUART_UART1,
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.sys_ctrl_dcgcuart_uart = SYS_CTRL_DCGCUART_UART1,
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.base = UART_1_BASE,
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.ioc_uartrxd_uart = IOC_UARTRXD_UART1,
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.ioc_pxx_sel_uart_txd = IOC_PXX_SEL_UART1_TXD,
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.ibrd = BAUD2IBRD(UART1_CONF_BAUD_RATE),
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.fbrd = BAUD2FBRD(UART1_CONF_BAUD_RATE),
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.rx = {UART1_RX_PORT, UART1_RX_PIN},
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.tx = {UART1_TX_PORT, UART1_TX_PIN},
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.cts = {UART1_CTS_PORT, UART1_CTS_PIN},
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.rts = {UART1_RTS_PORT, UART1_RTS_PIN},
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.nvic_int = NVIC_INT_UART1
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}
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};
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static int (* input_handler[UART_INSTANCE_COUNT])(unsigned char c);
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/*---------------------------------------------------------------------------*/
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static void
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reset(uint32_t uart_base)
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{
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uint32_t lchr;
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/* Make sure the UART is disabled before trying to configure it */
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REG(uart_base + UART_CTL) = UART_CTL_VALUE;
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/* Clear error status */
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REG(uart_base + UART_ECR) = 0xFF;
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/* Store LCHR configuration */
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lchr = REG(uart_base + UART_LCRH);
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/* Flush FIFOs by clearing LCHR.FEN */
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REG(uart_base + UART_LCRH) = 0;
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/* Restore LCHR configuration */
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REG(uart_base + UART_LCRH) = lchr;
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/* UART Enable */
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REG(uart_base + UART_CTL) |= UART_CTL_UARTEN;
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}
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/*---------------------------------------------------------------------------*/
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static bool
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permit_pm1(void)
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{
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const uart_regs_t *regs;
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for(regs = &uart_regs[0]; regs < &uart_regs[UART_INSTANCE_COUNT]; regs++) {
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/* Note: UART_FR.TXFE reads 0 if the UART clock is gated. */
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if((REG(SYS_CTRL_RCGCUART) & regs->sys_ctrl_rcgcuart_uart) != 0 &&
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(REG(regs->base + UART_FR) & UART_FR_TXFE) == 0) {
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return false;
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}
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}
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return true;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_init(uint8_t uart)
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{
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const uart_regs_t *regs;
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if(uart >= UART_INSTANCE_COUNT) {
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return;
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}
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regs = &uart_regs[uart];
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if(regs->rx.port < 0 || regs->tx.port < 0) {
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return;
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}
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lpm_register_peripheral(permit_pm1);
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/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
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REG(SYS_CTRL_RCGCUART) |= regs->sys_ctrl_rcgcuart_uart;
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REG(SYS_CTRL_SCGCUART) |= regs->sys_ctrl_scgcuart_uart;
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REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
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/* Run on SYS_DIV */
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REG(regs->base + UART_CC) = 0;
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/*
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* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
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*
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* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
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* ioc.h. The value can also be calculated as:
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*
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* (port << 3) + pin
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*/
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REG(regs->ioc_uartrxd_uart) = (regs->rx.port << 3) + regs->rx.pin;
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/*
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* Pad Control for the TX pin:
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* - Set function to UARTn TX
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* - Output Enable
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*/
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ioc_set_sel(regs->tx.port, regs->tx.pin, regs->ioc_pxx_sel_uart_txd);
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ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_OE);
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/* Set RX and TX pins to peripheral mode */
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
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GPIO_PIN_MASK(regs->tx.pin));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
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GPIO_PIN_MASK(regs->rx.pin));
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/*
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* UART Interrupt Masks:
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* Acknowledge RX and RX Timeout
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* Acknowledge Framing, Overrun and Break Errors
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*/
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REG(regs->base + UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(regs->base + UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(regs->base + UART_IFLS) =
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UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
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/* Make sure the UART is disabled before trying to configure it */
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REG(regs->base + UART_CTL) = UART_CTL_VALUE;
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/* Baud Rate Generation */
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REG(regs->base + UART_IBRD) = regs->ibrd;
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REG(regs->base + UART_FBRD) = regs->fbrd;
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/* UART Control: 8N1 with FIFOs */
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REG(regs->base + UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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/*
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* Enable hardware flow control (RTS/CTS) if requested.
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* Note that hardware flow control is available only on UART1.
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*/
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if(regs->cts.port >= 0) {
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REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
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ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
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REG(UART_1_BASE + UART_CTL) |= UART_CTL_CTSEN;
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}
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if(regs->rts.port >= 0) {
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ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
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ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
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REG(UART_1_BASE + UART_CTL) |= UART_CTL_RTSEN;
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}
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/* UART Enable */
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REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
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/* Enable UART0 Interrupts */
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nvic_interrupt_enable(regs->nvic_int);
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_set_input(uint8_t uart, int (* input)(unsigned char c))
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{
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if(uart >= UART_INSTANCE_COUNT) {
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return;
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}
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input_handler[uart] = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_write_byte(uint8_t uart, uint8_t b)
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{
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uint32_t uart_base;
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if(uart >= UART_INSTANCE_COUNT) {
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return;
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}
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uart_base = uart_regs[uart].base;
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/* Block if the TX FIFO is full */
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while(REG(uart_base + UART_FR) & UART_FR_TXFF);
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REG(uart_base + UART_DR) = b;
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}
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/*---------------------------------------------------------------------------*/
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static void
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uart_isr(uint8_t uart)
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{
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uint32_t uart_base;
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uint16_t mis;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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uart_base = uart_regs[uart].base;
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/* Store the current MIS and clear all flags early, except the RTM flag.
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* This will clear itself when we read out the entire FIFO contents */
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mis = REG(uart_base + UART_MIS) & 0x0000FFFF;
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REG(uart_base + UART_ICR) = 0x0000FFBF;
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if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
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while(!(REG(uart_base + UART_FR) & UART_FR_RXFE)) {
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if(input_handler[uart] != NULL) {
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input_handler[uart]((unsigned char)(REG(uart_base + UART_DR) & 0xFF));
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} else {
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/* To prevent an Overrun Error, we need to flush the FIFO even if we
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* don't have an input_handler. Use mis as a data trash can */
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mis = REG(uart_base + UART_DR);
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}
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}
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} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {
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/* ISR triggered due to some error condition */
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reset(uart_base);
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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/*---------------------------------------------------------------------------*/
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#define UART_ISR(u) void uart##u##_isr(void) { uart_isr(u); }
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UART_ISR(0)
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UART_ISR(1)
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/** @} */
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