e0aefd11d9
This patch extends the protection domain framework with a third plugin that is a hybrid of the previous two. The hardware task switching mechanism has a strictly-defined format for TSS data structures that causes more space to be consumed than would otherwise be required. This patch defines a smaller data structure that is allocated for each protection domain, only requiring 32 bytes instead of 128 bytes. It uses the same multi-segment memory layout as the TSS-based plugin and leaves paging disabled. However, it uses a similar mechanism as the paging plugin to perform system call dispatches and returns. For additional information, please refer to cpu/x86/mm/README.md.
86 lines
3.8 KiB
C
86 lines
3.8 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_MM_SWSEG_PROT_DOMAINS_H_
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#define CPU_X86_MM_SWSEG_PROT_DOMAINS_H_
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "ldt-layout.h"
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#include "paging.h"
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#include "segmentation.h"
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#include "syscalls-int.h"
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struct dom_kern_data {
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/** Local Descriptor Table with per-domain descriptors */
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segment_desc_t ldt[LDT_NUM_DESC];
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/** Flags are defined with the prefix PROT_DOMAINS_FLAG in prot-domains.h */
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uint32_t flags;
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/**
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* Original return address from call stack when this protection domain
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* invoked some other protection domain. This serves to control the return
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* entrypoint. The callee is not permitted to modify this value (unless the
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* callee is the kernel protection domain).
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*/
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uintptr_t orig_ret_addr;
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/* This structure is precisely 32 bytes in length, a power of 2. If its size
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* changes, add an alignment attribute to keep it aligned at a power of 2 so
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* that dereferencing arrays of these structures uses shift instructions
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* instead of multiplication. Shifting is faster than multiplication.
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*/
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};
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/* relies on dom_kern_data: */
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#include "multi-segment.h"
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#define PROT_DOMAINS_ENTER_ISR(exc) \
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MULTI_SEGMENT_ENTER_ISR(exc) \
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PROT_DOMAINS_ENTER_ISR_COMMON(exc)
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#define PROT_DOMAINS_LEAVE_ISR(exc) \
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PROT_DOMAINS_LEAVE_ISR_COMMON(exc) \
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MULTI_SEGMENT_LEAVE_ISR(exc)
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#define prot_domains_impl_init syscalls_int_init
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#define prot_domains_set_wp(en)
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/* Allocate one additional GDT entry for each protection domain. Note that
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* the particular storage allocated by this statement may actually be used for
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* some other protection domain, depending on how the linker happens to arrange
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* all of the GDT storage. The GDT_IDX_LDT macro in gdt-layout.h determine
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* which storage is used for each protection domain. Thus, this storage should
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* not be referenced directly by its variable name.
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*/
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#define PROT_DOMAINS_ALLOC_IMPL(nm) \
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static segment_desc_t ATTR_BSS_GDT_MID _gdt_storage_##nm
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#endif /* CPU_X86_MM_SWSEG_PROT_DOMAINS_H_ */
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