5261bb861d
When returning from PM1/2, the sleep timer value (used by RTIMER_NOW()) is not up-to-date until a positive edge on the 32-kHz clock has been detected after the system clock restarted. To ensure an updated value is read, wait for a positive transition on the 32-kHz clock by polling the SYS_CTRL_CLOCK_STA.SYNC_32K bit, before reading the sleep timer value. Because of this RTIMER_NOW() fixup, lpm_exit() has to be called at the very beginning of ISRs waking up the SoC. This also ensures that all clocks and timers are enabled at the correct frequency and updated before using them following wake-up. Without this fix, etimers could sometimes (randomly, depending on timings) become ultra slow (observed from 10x to 40x slower than normal) if the system exited PM1/2 very often. This issue occurred more often with PM1. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
158 lines
5 KiB
C
158 lines
5 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-rtimer
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* @{
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*
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* \file
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* Implementation of the arch-specific rtimer functions for the cc2538
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*
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*/
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#include "contiki.h"
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#include "sys/energest.h"
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#include "sys/rtimer.h"
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#include "dev/nvic.h"
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#include "dev/smwdthrosc.h"
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#include "cpu.h"
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#include "lpm.h"
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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static volatile rtimer_clock_t next_trigger;
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/*---------------------------------------------------------------------------*/
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/**
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* \brief We don't need to explicitly initialise anything but this
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* routine is required by the API.
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*
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* The Sleep Timer starts ticking automatically as soon as the device
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* turns on. We don't need to turn on interrupts before the first call
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* to rtimer_arch_schedule()
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*/
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void
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rtimer_arch_init(void)
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{
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return;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Schedules an rtimer task to be triggered at time t
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* \param t The time when the task will need executed. This is an absolute
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* time, in other words the task will be executed AT time \e t,
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* not IN \e t ticks
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*/
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void
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rtimer_arch_schedule(rtimer_clock_t t)
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{
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rtimer_clock_t now;
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/* STLOAD must be 1 */
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while((REG(SMWDTHROSC_STLOAD) & SMWDTHROSC_STLOAD_STLOAD) != 1);
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INTERRUPTS_DISABLE();
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now = RTIMER_NOW();
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/*
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* New value must be 5 ticks in the future. The ST may tick once while we're
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* writing the registers. We play it safe here and we add a bit of leeway
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*/
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if((int32_t)(t - now) < 7) {
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t = now + 7;
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}
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/* ST0 latches ST[1:3] and must be written last */
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REG(SMWDTHROSC_ST3) = (t >> 24) & 0x000000FF;
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REG(SMWDTHROSC_ST2) = (t >> 16) & 0x000000FF;
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REG(SMWDTHROSC_ST1) = (t >> 8) & 0x000000FF;
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REG(SMWDTHROSC_ST0) = t & 0x000000FF;
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INTERRUPTS_ENABLE();
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/* Store the value. The LPM module will query us for it */
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next_trigger = t;
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nvic_interrupt_enable(NVIC_INT_SM_TIMER);
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}
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/*---------------------------------------------------------------------------*/
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rtimer_clock_t
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rtimer_arch_next_trigger()
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{
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return next_trigger;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Returns the current real-time clock time
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* \return The current rtimer time in ticks
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*/
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rtimer_clock_t
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rtimer_arch_now()
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{
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rtimer_clock_t rv;
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/* SMWDTHROSC_ST0 latches ST[1:3] and must be read first */
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rv = REG(SMWDTHROSC_ST0);
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rv |= (REG(SMWDTHROSC_ST1) << 8);
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rv |= (REG(SMWDTHROSC_ST2) << 16);
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rv |= (REG(SMWDTHROSC_ST3) << 24);
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return rv;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief The rtimer ISR
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*
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* Interrupts are only turned on when we have an rtimer task to schedule
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* Once the interrupt fires, the task is called and then interrupts no
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* longer get acknowledged until the next task needs scheduled.
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*/
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void
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rtimer_isr()
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{
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/*
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* If we were in PM1+, call the wake-up sequence first. This will make sure
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* that the 32MHz OSC is selected as the clock source. We need to do this
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* before calling the next rtimer_task, since the task may need the RF.
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*/
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lpm_exit();
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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next_trigger = 0;
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nvic_interrupt_unpend(NVIC_INT_SM_TIMER);
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nvic_interrupt_disable(NVIC_INT_SM_TIMER);
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rtimer_run_next();
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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/*---------------------------------------------------------------------------*/
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/** @} */
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