289 lines
8.2 KiB
C
289 lines
8.2 KiB
C
#define GPIO_FUNC_SEL0 0x80000018 /* GPIO 15 - 0; 2 bit blocks */
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#define BASE_UART1 0x80005000
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#define UART1_CON 0x80005000
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#define UART1_STAT 0x80005004
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#define UART1_DATA 0x80005008
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#define UR1CON 0x8000500c
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#define UT1CON 0x80005010
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#define UART1_CTS 0x80005014
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#define UART1_BR 0x80005018
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#include "maca.h"
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#include "embedded_types.h"
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#define reg(x) (*(volatile uint32_t *)(x))
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#define DELAY 400000
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#define DATA 0x00401000;
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#define NL "\033[K\r\n"
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void putc(uint8_t c);
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void puts(uint8_t *s);
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void put_hex(uint8_t x);
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void put_hex16(uint16_t x);
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void put_hex32(uint32_t x);
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const uint8_t hex[16]={'0','1','2','3','4','5','6','7',
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'8','9','a','b','c','d','e','f'};
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void magic(void) {
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#define X 0x80009a000
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#define Y 0x80009a008
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#define VAL 0x0000f7df
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volatile uint32_t x,y;
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x = reg(X); /* get X */
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x &= 0xfffeffff; /* clear bit 16 */
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reg(X) = x; /* put it back */
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y = reg(Y); /* get Y */
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y |= VAL; /* or with the VAL */
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x = reg(X); /* get X again */
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x |= 16; /* or with 16 */
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reg(X) = x; /* put X back */
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reg(Y) = y; /* put Y back */
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}
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uint32_t ackBox[10];
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#define command_xcvr_rx() \
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do { \
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maca_txlen = (uint32_t)1<<16; \
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maca_dmatx = (uint32_t)&ackBox; \
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maca_dmarx = DATA; \
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maca_tmren = (maca_cpl_clk | maca_soft_clk); \
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maca_control = (control_prm | control_asap | control_seq_rx); \
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}while(FALSE)
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void dump_regs(uint32_t base, uint32_t len) {
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volatile uint32_t i;
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puts("base +0 +4 +8 +c +10 +14 +18 +1c \n\r");
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for (i = 0; i < len; i ++) {
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if ((i & 7) == 0) {
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put_hex16(4 * i);
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}
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puts(" ");
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put_hex32(reg(base+(4*i)));
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if ((i & 7) == 7)
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puts(NL);
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}
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puts(NL);
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}
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__attribute__ ((section ("startup")))
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void main(void) {
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uint8_t c;
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volatile uint32_t i;
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uint32_t tmp;
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volatile uint32_t *data;
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uint16_t status;
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/* Restore UART regs. to default */
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/* in case there is still bootloader state leftover */
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reg(UART1_CON) = 0x0000c800; /* mask interrupts, 16 bit sample --- helps explain the baud rate */
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/* INC = 767; MOD = 9999 works: 115200 @ 24 MHz 16 bit sample */
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#define INC 767
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#define MOD 9999
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reg(UART1_BR) = INC<<16 | MOD;
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/* see Section 11.5.1.2 Alternate Modes */
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/* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */
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/* From the datasheet: "The peripheral function will control operation of the pad IF */
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/* THE PERIPHERAL IS ENABLED. */
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reg(UART1_CON) = 0x00000003; /* enable receive and transmit */
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reg(GPIO_FUNC_SEL0) = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
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/* turn on the voltage regulators for the radio */
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/* you clod! */
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for(i=0; i<DELAY; i++) { continue; }
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reg(0x80003048) = 0x00000ff8;
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/* use the 24MHz clock for the modem */
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reg(0x80009000) = 0x80050100;
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reg(MACA_RESET) = 0x3; /* reset, turn on the clock */
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for(i=0; i<DELAY; i++) { continue; }
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reg(MACA_RESET) = 0x2; /* unreset, turn on the clock */
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for(i=0; i<DELAY; i++) { continue; }
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reset_maca();
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radio_init();
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init_phy();
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/* some kind of sequence in init phy from MACPHY.a dissassmbly */
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// magic();
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reg(MACA_CONTROL) = SMAC_MACA_CNTL_INIT_STATE;
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for(i=0; i<DELAY; i++) { continue; }
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data = (void *)DATA;
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data[0] = 0xdeadbeef;
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reg(MACA_DMARX) = DATA; /* put data somewhere */
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// reg(MACA_PREAMBLE) = 0xface0fff;
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reg(MACA_PREAMBLE) = 0;
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puts("maca_base\n\r");
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dump_regs(MACA_BASE, 96);
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puts("modem write base\n\r");
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dump_regs(0x80009000, 96);
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puts("modem read base\n\r");
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dump_regs(0x800091c0, 96);
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puts("CRM\n\r");
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dump_regs(0x80003000, 96);
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puts("reserved modem_base\n\r");
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dump_regs(0x80009200, 192);
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// while(1);
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command_xcvr_rx();
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puts("\033[H\033[2J");
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while(1) {
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uint32_t TsmRxSteps, LastWarmupStep, LastWarmupData, LastWarmdownStep, LastWarmdownData;
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puts("\033[Hrftest-rx --- " );
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puts(" maca_getrxlvl: 0x");
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put_hex(reg(MACA_GETRXLVL));
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puts(" data[0]: 0x");
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put_hex32(data[0]);
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puts(" status: 0x");
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put_hex32(reg(MACA_STATUS));
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puts(" random: 0x");
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put_hex32(reg(MACA_RANDOM));
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puts(NL);
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puts("Maca_base");
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puts(NL);
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dump_regs(MACA_BASE,96);
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puts("0x80009000");
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puts(NL);
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dump_regs(0x80009000,192);
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/* /\* start rx sequence *\/ */
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/* reg(MACA_CONTROL) = 0x00031a01; /\* abort *\/ */
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/* while (((tmp = reg(MACA_STATUS)) & 15) == 14) */
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/* puts("."); */
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/* puts("abort status is "); put_hex32(tmp); puts(NL); */
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/* puts("1 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("2 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("3 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* read TSM_RX_STEPS */
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TsmRxSteps = (*((volatile uint32_t *)(0x80009204)));
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puts("TsmRxSteps: ");
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put_hex32(TsmRxSteps);
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puts(NL);
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/* isolate the RX_WU_STEPS */
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/* shift left to align with 32-bit addressing */
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LastWarmupStep = (TsmRxSteps & 0x1f) << 2;
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/* Read "current" TSM step and save this value for later */
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LastWarmupData = (*((volatile uint32_t *)(0x80009300 + LastWarmupStep)));
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puts("LastWarmupData: ");
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put_hex32(LastWarmupData);
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puts(NL);
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/* isolate the RX_WD_STEPS */
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/* right-shift bits down to bit 0 position */
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/* left-shift to align with 32-bit addressing */
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LastWarmdownStep = ((TsmRxSteps & 0x1f00) >> 8) << 2;
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/* write "last warmdown data" to current TSM step to shutdown rx */
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LastWarmdownData = (*((volatile uint32_t *)(0x80009300 + LastWarmdownStep)));
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puts("LastWarmdownData: ");
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put_hex32(LastWarmdownData);
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puts(NL);
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status = reg(MACA_STATUS) & 0x0000ffff;
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switch(status)
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{
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case(cc_aborted):
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{
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puts("aborted\n\r");
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ResumeMACASync();
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command_xcvr_rx();
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break;
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}
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case(cc_not_completed):
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{
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puts("not completed\n\r");
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ResumeMACASync();
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break;
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}
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case(cc_success):
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{
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puts("success\n\r");
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break;
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}
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default:
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{
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puts("status: ");
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put_hex16(status);
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ResumeMACASync();
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command_xcvr_rx();
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}
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}
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/* reg(MACA_CONTROL) = 0x00031a04; /\* receive *\/ */
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/* while (((tmp = reg(MACA_STATUS)) & 15) == 14) */
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/* puts("."); */
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/* puts("complete status is "); put_hex32(tmp); puts(NL); */
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/* puts("1 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("2 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("3 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts(NL); */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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};
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}
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void putc(uint8_t c) {
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while(reg(UT1CON)==31); /* wait for there to be room in the buffer */
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reg(UART1_DATA) = c;
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}
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void puts(uint8_t *s) {
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while(s && *s!=0) {
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putc(*s++);
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}
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}
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void put_hex(uint8_t x)
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{
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putc(hex[x >> 4]);
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putc(hex[x & 15]);
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}
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void put_hex16(uint16_t x)
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{
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put_hex((x >> 8) & 0xFF);
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put_hex((x) & 0xFF);
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}
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void put_hex32(uint32_t x)
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{
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put_hex((x >> 24) & 0xFF);
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put_hex((x >> 16) & 0xFF);
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put_hex((x >> 8) & 0xFF);
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put_hex((x) & 0xFF);
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}
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