4cdb7ba9b6
This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
170 lines
6.2 KiB
C
170 lines
6.2 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdlib.h>
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#include "helpers.h"
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#include "paging.h"
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#include "prot-domains.h"
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#include "syscalls.h"
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#include "uart-16x50.h"
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/* Refer to Intel Quark SoC X1000 Datasheet, Chapter 18 for more details on
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* UART operation.
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*/
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/* Divisor Latch Access Bit (DLAB) mask for Line Control Register (LCR).
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*
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* When bit is set, enables access to divisor registers to set baud rate. When
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* clear, enables access to other registers mapped to the same addresses as the
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* divisor registers.
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*/
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#define UART_LCR_7_DLAB BIT(7)
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/* Setting for LCR that configures the UART to operate with no parity, 1 stop
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* bit, and eight bits per character.
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*/
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#define UART_LCR_8BITS 0x03
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/* FIFO Control Register (FCR) bitmasks */
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#define UART_FCR_0_FIFOE BIT(0) /*< enable FIFOs */
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#define UART_FCR_1_RFIFOR BIT(1) /*< reset RX FIFO */
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#define UART_FCR_2_XFIFOR BIT(2) /*< reset TX FIFO */
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/* Line Status Register (LSR) Transmit Holding Register Empty bitmask to check
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* whether the Transmit Holding Register (THR) or TX FIFO is empty.
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*/
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#define UART_LSR_5_THRE BIT(5)
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/* MMIO registers for UART */
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typedef struct uart_16x50_regs {
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volatile uint32_t rbr_thr_dll, ier_dlh, iir_fcr, lcr;
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volatile uint32_t mcr, lsr, msr, scr, usr, htx, dmasa;
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} uart_16x50_regs_t;
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#if X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__PAGING
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/* When paging-based protection domains are in use, at least one page of memory
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* must be reserved to facilitate access to the MMIO region, since that is the
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* smallest unit of memory that can be managed with paging:
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*/
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#define UART_MMIO_SZ MIN_PAGE_SIZE
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#else
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/* Multi-segment protection domain implementations can control memory with
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* byte granularity. Thus, only the registers defined in the uart_16x50_regs
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* structure are included in the MMIO region allocated for this protection
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* domain:
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*/
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#define UART_MMIO_SZ sizeof(uart_16x50_regs_t)
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#endif
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void uart_16x50_setup(uart_16x50_driver_t c_this, uint16_t dl);
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/*---------------------------------------------------------------------------*/
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SYSCALLS_DEFINE(uart_16x50_setup, uart_16x50_driver_t c_this, uint16_t dl)
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{
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uart_16x50_regs_t ATTR_MMIO_ADDR_SPACE *regs =
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(uart_16x50_regs_t ATTR_MMIO_ADDR_SPACE *)PROT_DOMAINS_MMIO(c_this);
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prot_domains_enable_mmio();
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/* Set the DLAB bit to enable access to divisor settings. */
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MMIO_WRITEL(regs->lcr, UART_LCR_7_DLAB);
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/* The divisor settings configure the baud rate, and may need to be defined
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* on a per-device basis.
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*/
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MMIO_WRITEL(regs->rbr_thr_dll, dl & UINT8_MAX);
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MMIO_WRITEL(regs->ier_dlh, dl >> 8);
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/* Clear the DLAB bit to enable access to other settings and configure other
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* UART parameters.
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*/
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MMIO_WRITEL(regs->lcr, UART_LCR_8BITS);
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/* Enable the FIFOs. */
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MMIO_WRITEL(regs->iir_fcr,
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UART_FCR_0_FIFOE | UART_FCR_1_RFIFOR | UART_FCR_2_XFIFOR);
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prot_domains_disable_mmio();
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Transmit a character through a UART.
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* \param c_this Initialized structure representing the device.
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* \param c Character to be transmitted.
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*
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* This procedure will block indefinitely until the UART is ready
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* to accept the character to be transmitted.
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*/
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SYSCALLS_DEFINE(uart_16x50_tx, uart_16x50_driver_t c_this, uint8_t c)
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{
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uint32_t ready;
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uart_16x50_regs_t ATTR_MMIO_ADDR_SPACE *regs =
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(uart_16x50_regs_t ATTR_MMIO_ADDR_SPACE *)PROT_DOMAINS_MMIO(c_this);
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prot_domains_enable_mmio();
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/* Wait for space in TX FIFO. */
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do {
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MMIO_READL(ready, regs->lsr);
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} while((ready & UART_LSR_5_THRE) == 0);
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/* Add character to TX FIFO. */
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MMIO_WRITEL(regs->rbr_thr_dll, c);
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prot_domains_disable_mmio();
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Initialize an MMIO-programmable 16X50 UART.
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* \param c_this Structure that will be initialized to represent the device.
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* \param pci_addr PCI address of device.
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* \param dl Divisor setting to configure the baud rate.
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*/
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void
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uart_16x50_init(uart_16x50_driver_t ATTR_KERN_ADDR_SPACE *c_this,
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pci_config_addr_t pci_addr,
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uint16_t dl)
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{
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uart_16x50_driver_t loc_c_this;
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/* This assumes that the UART had an MMIO range assigned to it by the
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* firmware during boot.
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*/
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pci_init(c_this, pci_addr, UART_MMIO_SZ, 0, 0);
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SYSCALLS_INIT(uart_16x50_setup);
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SYSCALLS_AUTHZ(uart_16x50_setup, *c_this);
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SYSCALLS_INIT(uart_16x50_tx);
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SYSCALLS_AUTHZ(uart_16x50_tx, *c_this);
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prot_domains_copy_dcd(&loc_c_this, c_this);
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uart_16x50_setup(loc_c_this, dl);
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}
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/*---------------------------------------------------------------------------*/
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