40f49948e6
This commit adds cpu, platform and example files, providing support for running Contiki on TI's cc2538 DK
112 lines
4.8 KiB
C
112 lines
4.8 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-soc-adc cc2538 ADC and RNG
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*
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* Register declarations for the cc2538 ADC and H/W RNG
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* @{
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*
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* \file
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* Header file with register declarations for the cc2538 ADC and H/W RNG
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*/
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#ifndef SOC_ADC_H_
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#define SOC_ADC_H_
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/*---------------------------------------------------------------------------*/
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/** \name ADC and RNG Register offset declarations
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* @{
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*/
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#define SOC_ADC_ADCCON1 0x400D7000 /**< ADC Control 1 */
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#define SOC_ADC_ADCCON2 0x400D7004 /**< ADC Control 2 */
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#define SOC_ADC_ADCCON3 0x400D7008 /**< ADC Control 3 */
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#define SOC_ADC_ADCL 0x400D700C /**< ADC Result, least significant part */
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#define SOC_ADC_ADCH 0x400D7010 /**< ADC Result, most significant part */
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#define SOC_ADC_RNDL 0x400D7014 /**< RNG low byte */
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#define SOC_ADC_RNDH 0x400D7018 /**< RNG high byte */
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#define SOC_ADC_CMPCTL 0x400D7024 /**< Analog comparator control and status */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SOC_ADC_ADCCON1 register bit masks
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* @{
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*/
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#define SOC_ADC_ADCCON1_EOC 0x00000080 /**< End of conversion */
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#define SOC_ADC_ADCCON1_ST 0x00000040 /**< Start conversion */
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#define SOC_ADC_ADCCON1_STSEL 0x00000030 /**< Start select */
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#define SOC_ADC_ADCCON1_RCTRL 0x0000000C /**< Controls the 16-bit RNG */
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#define SOC_ADC_ADCCON1_RCTRL1 0x00000008 /**< RCTRL high bit */
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#define SOC_ADC_ADCCON1_RCTRL0 0x00000004 /**< RCTRL low bit */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SOC_ADC_ADCCON2 register bit masks
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* @{
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*/
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#define SOC_ADC_ADCCON2_SREF 0x000000C0 /**< Reference voltage for sequence */
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#define SOC_ADC_ADCCON2_SDIV 0x00000030 /**< Decimation rate for sequence */
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#define SOC_ADC_ADCCON2_SCH 0x0000000F /**< Sequence channel select */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SOC_ADC_ADCCON3 register bit masks
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* @{
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*/
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#define SOC_ADC_ADCCON3_EREF 0x000000C0 /**< Reference voltage for extra */
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#define SOC_ADC_ADCCON3_EDIV 0x00000030 /**< Decimation rate for extra */
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#define SOC_ADC_ADCCON3_ECH 0x0000000F /**< Single channel select */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SOC_ADC_ADC[L:H] register bit masks
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* @{
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*/
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#define SOC_ADC_ADCL_ADC 0x000000FC /**< ADC Result, least significant part */
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#define SOC_ADC_ADCH_ADC 0x000000FF /**< ADC Result, most significant part */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SOC_ADC_RND[L:H] register bit masks
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* @{
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*/
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#define SOC_ADC_RNDL_RNDL 0x000000FF /**< Random value/seed or CRC result low byte */
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#define SOC_ADC_RNDH_RNDH 0x000000FF /**< Random value or CRC result/input data, high byte */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SOC_ADC_CMPCTL register bit masks
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* @{
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*/
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#define SOC_ADC_CMPCTL_EN 0x00000002 /**< Comparator enable */
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#define SOC_ADC_CMPCTL_OUTPUT 0x00000001 /**< Comparator output */
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/** @} */
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#endif /* SOC_ADC_H_ */
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/**
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* @}
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* @}
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*/
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