169 lines
4.8 KiB
C
169 lines
4.8 KiB
C
/* -*- C -*- */
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/* @(#)$Id: contiki-conf.h,v 1.2 2007/04/11 15:24:39 bg- Exp $ */
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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/* #define CB_GATEWAY */
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#include <avr/interrupt.h>
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#define CCIF
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#define CLIF
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#define AODV_NUM_RT_ENTRIES 32
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/* Helper prototypes that should go somewhere. */
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void *sbrk(int);
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typedef unsigned char spl_t;
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static inline void splx_(spl_t s) { SREG = s; }
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static inline spl_t splhigh_(void) { spl_t s = SREG; cli(); return s; }
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void cpu_init(void);
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#define splhigh() splhigh_()
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#define splx(s) splx_((spl_t)s)
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void clock_delay(unsigned int us2);
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void clock_wait(int ms10);
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void clock_set_seconds(unsigned long s);
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unsigned long clock_seconds(void);
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#define WITH_UIP 1
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#define WITH_ASCII 1
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#define PROCESS_CONF_FASTPOLL 4
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/* Our clock resolution, this is the same as Unix HZ. */
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/* Fix clock.c XXX/bg */
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#define CLOCK_CONF_SECOND 62
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/* CPU target speed in Hz */
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#define F_CPU 8000000L
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/* The +1 and divide by 2 is to achieve rounding. */
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#define BAUD2UBR(baud) ((u16_t)((F_CPU/baud/8uL + 1)/2 - 1))
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/* UART configs */
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//#define MCU_MHZ 8
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//#define MCU atmega128
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//#define SLIP_PORT RS232_PORT_1
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#define UIP_CONF_DHCP_LIGHT
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#define UIP_CONF_LLH_LEN 0
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#define UIP_CONF_BUFFER_SIZE 116
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#define UIP_CONF_RECEIVE_WINDOW (UIP_CONF_BUFFER_SIZE - 40)
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#define UIP_CONF_MAX_CONNECTIONS 4
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#define UIP_CONF_MAX_LISTENPORTS 8
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#define UIP_CONF_UDP_CONNS 12
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#define UIP_CONF_FWCACHE_SIZE 30
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#define UIP_CONF_BROADCAST 1
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//#define UIP_ARCH_IPCHKSUM 1
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#define UIP_CONF_UDP_CHECKSUMS 1
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#define UIP_CONF_PINGADDRCONF 0
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#define UIP_CONF_LOGGING 0
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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#ifdef CB_GATEWAY
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/* LED port E */
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#define LEDS_CONF_GREEN _BV(2) /* PE.2 - Output */
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#define LEDS_CONF_YELLOW _BV(3) /* PE.3 - Output */
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#else
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#define LEDS_ORANGE 8
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/* LED port B */
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#define LEDS_CONF_ORANGE _BV(4) /* PB.4 - Output */
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#define LEDS_CONF_GREEN _BV(7) /* PB.7 - Output */
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/* LED port E */
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#define LEDS_CONF_RED _BV(3) /* PE.3 - Output */
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#define LEDS_CONF_YELLOW _BV(4) /* PE.4 - Output */
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#endif
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typedef unsigned char u8_t;
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typedef unsigned short u16_t;
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typedef unsigned long u32_t;
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typedef u16_t uip_stats_t;
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typedef u16_t clock_time_t;
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typedef u32_t off_t;
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#define ROM_ERASE_UNIT_SIZE SPM_PAGESIZE
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#define XMEM_ERASE_UNIT_SIZE 8
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/* Use the first 64k of external flash for codeprop. */
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#define EEPROMFS_ADDR_CODEPROP (128 * XMEM_ERASE_UNIT_SIZE)
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#define CC2420_RADIO
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/*
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* SPI bus configuration for the CC2420DBK.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF SPDR
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#define SPI_RXBUF SPDR
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#define BV(bitno) _BV(bitno)
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#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SCK 1 /* - Output: SPI Serial Clock (SCLK) */
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#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) */
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#define MISO 3 /* - Input: SPI Master in - slave out (MISO) */
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define FIFO_P 0 /* - Input: FIFOP from CC2420 */
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#define FIFO 1 /* - Input: FIFO from CC2420 */
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#define CCA 6 /* - Input: CCA from CC2420 */
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#define SFD 4 /* - Input: SFD from CC2420 */
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#define CSN 0 /* - Output: SPI Chip Select (CS_N) */
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#define VREG_EN 5 /* - Output: VREG_EN to CC2420 */
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#define RESET_N 6 /* - Output: RESET_N to CC2420 */
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/* Pin status. */
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#define FIFO_IS_1 (!!(PIND & BV(FIFO)))
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#define CCA_IS_1 (!!(PIND & BV(CCA) ))
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#define RESET_IS_1 (!!(PINB & BV(RESET_N)))
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#define VREG_IS_1 (!!(PINB & BV(VREG_EN)))
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#define FIFOP_IS_1 (!!(PIND & BV(FIFO_P)))
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#define SFD_IS_1 (!!(PIND & BV(SFD)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() ( PORTB |= BV(RESET_N) )
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#define SET_RESET_ACTIVE() ( PORTB &= ~BV(RESET_N) )
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() ( PORTB |= BV(VREG_EN) )
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#define SET_VREG_INACTIVE() ( PORTB &= ~BV(VREG_EN) )
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/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
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#define FIFOP_INT_INIT() do {\
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EICRA |= 0x03; \
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CLEAR_FIFOP_INT(); \
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} while (0)
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/* FIFOP on external interrupt 0. */
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#define ENABLE_FIFOP_INT() do { EIMSK |= 0x01; } while (0)
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#define DISABLE_FIFOP_INT() do { EIMSK &= ~0x01; } while (0)
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#define CLEAR_FIFOP_INT() do { EIFR = 0x01; } while (0)
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/* Enables/disables CC2420 access to the SPI bus (not the bus).
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*
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* These guys should really be renamed but are compatible with the
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* original Chipcon naming.
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*
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* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
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* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
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*/
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#define SPI_ENABLE() ( PORTB &= ~BV(CSN) ) /* ENABLE CSn (active low) */
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#define SPI_DISABLE() ( PORTB |= BV(CSN) ) /* DISABLE CSn (active low) */
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#endif /* CONTIKI_CONF_H */
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