afd9b5b0b7
This commit implements pic_eoi(int irq) and a helper macro PIC_INT(irq). This first checks which PICs should be 'acked' given an IRQ number, while the macro returns the actual system interrupt number for the IRQ according to the offset used on the PIC initialization.
81 lines
3.1 KiB
C
81 lines
3.1 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <math.h>
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#include "drivers/pic.h"
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#include "pit.h"
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#include "helpers.h"
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#include "interrupt.h"
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/* PCs usually provide an 8254 PIT chip with maximum clock of 1.193182 MHz. */
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#define PIT_CONTROL_PORT 0x43
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#define PIT_COUNTER0_PORT 0x40
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#define PIT_CLOCK_FREQUENCY 1193182
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#define PIT_IRQ 0
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#define PIT_INT PIC_INT(PIT_IRQ)
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static pit_int_callback interrupt_cb;
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static void
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pit_int_handler(void)
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{
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interrupt_cb();
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pic_eoi(PIT_IRQ);
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}
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/*---------------------------------------------------------------------------*/
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void
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pit_init(uint32_t ticks_rate, pit_int_callback cb)
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{
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SET_INTERRUPT_HANDLER(PIT_INT, 0, pit_int_handler);
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interrupt_cb = cb;
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/* Calculate the 16bit divisor that can provide the chosen clock tick rate
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* (CLOCK_CONF_SECOND in contiki-conf.h). For reference --> tick rate = clock frequency / divisor.
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* If we provide an odd divisor to the Square Wave generator (Mode 3) of
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* the Counter0, the duty cycle won't be exactly 50%, so we always round
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* it to nearest even integer.
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*/
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uint16_t divisor = rint(PIT_CLOCK_FREQUENCY / ticks_rate);
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/* Setup Control register flags in a didactic way. */
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uint8_t flags = 0x30; /* Set bits 7:6 to select Counter0 and 5:4 to select "write 7:0 bits first". */
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flags |= 0x6; /* Set bits 3:1 to Mode 3 and bit 0 to BCD off. */
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outb(PIT_CONTROL_PORT, flags);
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outb(PIT_COUNTER0_PORT, divisor & 0xFF); /* Write least significant bytes first. */
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outb(PIT_COUNTER0_PORT, (divisor >> 8) & 0xFF);
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pic_unmask_irq(PIT_IRQ);
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}
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