2c9a538582
bump libmc1322x to 7bee48243c
Conflicts:
cpu/mc1322x/board/Makefile.board
cpu/mc1322x/lib/include/uart.h
cpu/mc1322x/lib/uart1.c
cpu/mc1322x/lib/uart2.c
cpu/mc1322x/src/default_lowlevel.c
201 lines
6.1 KiB
C
201 lines
6.1 KiB
C
/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of libmc1322x: see http://mc1322x.devl.org
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* for details.
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*
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*
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*/
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#ifndef UART_H
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#define UART_H
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#include <stdint.h>
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/* Timer registers are all 16-bit wide with 16-bit access only */
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#define UART1_BASE (0x80005000)
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#define UART2_BASE (0x8000B000)
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struct UART_struct {
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union {
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uint32_t CON;
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struct UART_CON {
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uint32_t TXE:1;
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uint32_t RXE:1;
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uint32_t PEN:1;
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uint32_t EP:1;
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uint32_t ST2:1;
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uint32_t SB:1;
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uint32_t CONTX:1;
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uint32_t TXOENB:1;
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uint32_t :2;
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uint32_t XTIM:1;
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uint32_t FCP:1;
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uint32_t FCE:1;
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uint32_t MTXR:1;
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uint32_t MRXR:1;
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uint32_t TST:1;
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uint32_t :16;
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} CONbits;
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};
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union {
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uint32_t STAT;
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struct UART_STAT {
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uint32_t SE:1;
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uint32_t PE:1;
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uint32_t FE:1;
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uint32_t TOE:1;
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uint32_t ROE:1;
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uint32_t RUE:1;
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uint32_t RXRDY:1;
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uint32_t TXRDY:1;
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uint32_t :24;
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} USTATbits;
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};
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union {
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uint32_t DATA;
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struct UART_DATA {
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uint32_t DATA:8;
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uint32_t :24;
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} DATAbits;
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};
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union {
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uint32_t RXCON;
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struct UART_URXCON {
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uint32_t LVL:6;
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uint32_t :26;
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} RXCONbits;
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};
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union {
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uint32_t TXCON;
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struct UART_TXCON {
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uint32_t LVL:6;
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uint32_t :26;
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} TXCONbits;
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};
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union {
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uint32_t CTS;
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struct UART_CTS {
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uint32_t LVL:5;
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uint32_t :27;
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} CTSbits;
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};
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union {
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uint32_t BR;
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struct UART_BR {
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uint32_t MOD:16;
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uint32_t INC:16;
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} BRbits;
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};
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};
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static volatile struct UART_struct * const UART1 = (void *) (UART1_BASE);
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static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE);
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/* Old uart definitions, for compatibility */
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#ifndef REG_NO_COMPAT
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#define UCON (0)
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/* UCON bits */
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#define UCON_SAMP 10
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#define UCON_SAMP_8X 0
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#define UCON_SAMP_16X 1
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#define USTAT (0x04)
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#define UDATA (0x08)
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#define URXCON (0x0c)
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#define UTXCON (0x10)
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#define UCTS (0x14)
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#define UBRCNT (0x18)
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#define UART1_UCON ((volatile uint32_t *) ( UART1_BASE + UCON ))
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#define UART1_USTAT ((volatile uint32_t *) ( UART1_BASE + USTAT ))
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#define UART1_UDATA ((volatile uint32_t *) ( UART1_BASE + UDATA ))
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#define UART1_URXCON ((volatile uint32_t *) ( UART1_BASE + URXCON ))
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#define UART1_UTXCON ((volatile uint32_t *) ( UART1_BASE + UTXCON ))
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#define UART1_UCTS ((volatile uint32_t *) ( UART1_BASE + UCTS ))
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#define UART1_UBRCNT ((volatile uint32_t *) ( UART1_BASE + UBRCNT ))
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#define UART2_UCON ((volatile uint32_t *) ( UART2_BASE + UCON ))
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#define UART2_USTAT ((volatile uint32_t *) ( UART2_BASE + USTAT ))
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#define UART2_UDATA ((volatile uint32_t *) ( UART2_BASE + UDATA ))
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#define UART2_URXCON ((volatile uint32_t *) ( UART2_BASE + URXCON ))
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#define UART2_UTXCON ((volatile uint32_t *) ( UART2_BASE + UTXCON ))
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#define UART2_UCTS ((volatile uint32_t *) ( UART2_BASE + UCTS ))
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#define UART2_UBRCNT ((volatile uint32_t *) ( UART2_BASE + UBRCNT ))
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#endif /* REG_NO_COMPAT */
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void uart_init(volatile struct UART_struct * uart, uint32_t baud);
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void uart_setbaud(volatile struct UART_struct * uart, uint32_t baud);
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void uart_flowctl(volatile struct UART_struct * uart, uint8_t on);
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/* The mc1322x has a 32 byte hardware FIFO for transmitted characters.
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* Currently it is always filled from a larger RAM buffer. It would be
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* possible to eliminate that overhead by filling directly from a chain
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* of data buffer pointers, but printf's would be not so easy.
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*/
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#define UART1_TX_BUFFERSIZE 1024
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extern volatile uint32_t u1_tx_head, u1_tx_tail;
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void uart1_putc(char c);
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/* The mc1322x has a 32 byte hardware FIFO for received characters.
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* If a larger rx buffersize is specified the FIFO will be extended into RAM.
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* RAM transfers will occur on interrupt when the FIFO is nearly full.
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* If a smaller buffersize is specified hardware flow control will be
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* initiated at that FIFO level.
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* Set to 32 for no flow control or RAM buffer.
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*/
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#define UART1_RX_BUFFERSIZE 128
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#if UART1_RX_BUFFERSIZE > 32
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extern volatile uint32_t u1_rx_head, u1_rx_tail;
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#define uart1_can_get() ((u1_rx_head!=u1_rx_tail) || (*UART1_URXCON > 0))
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#else
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#define uart1_can_get() (*UART1_URXCON > 0)
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#endif
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uint8_t uart1_getc(void);
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#define UART2_TX_BUFFERSIZE 1024
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extern volatile uint32_t u2_tx_head, u2_tx_tail;
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void uart2_putc(char c);
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#define UART2_RX_BUFFERSIZE 128
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#if UART2_RX_BUFFERSIZE > 32
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extern volatile uint32_t u2_rx_head, u2_rx_tail;
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#define uart2_can_get() ((u2_rx_head!=u2_rx_tail) || (*UART2_URXCON > 0))
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#else
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#define uart2_can_get() (*UART2_URXCON > 0)
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#endif
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uint8_t uart2_getc(void);
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#endif
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