95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/**
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* \file
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* Driver for the cc2530 DMA controller. Derived from the cc2430
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* equivalent
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*
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* \author
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* Original: Martti Huttunen <martti@sensinode.com>
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* Port: Zach Shelby <zach@sensinode.com>
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* Further Modifications:
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* George Oikonomou <oikonomou@users.sourceforge.net>
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*
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*/
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#include "contiki.h"
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#include "dev/dma.h"
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#include "cc253x.h"
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#if DMA_ON
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struct dma_config dma_conf[DMA_CHANNEL_COUNT]; /* DMA Descriptors */
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struct process * dma_callback[DMA_CHANNEL_COUNT];
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/*---------------------------------------------------------------------------*/
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void
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dma_init(void)
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{
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uint16_t tmp_ptr;
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memset(dma_conf, 0, 4 * sizeof(dma_config_t));
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for(tmp_ptr = 0; tmp_ptr < DMA_CHANNEL_COUNT; tmp_ptr++) {
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dma_callback[tmp_ptr] = 0;
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}
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/* The address of the descriptor for Channel 0 is configured separately */
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tmp_ptr = (uint16_t) &(dma_conf[0]);
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DMA0CFGH = tmp_ptr >> 8;
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DMA0CFGL = tmp_ptr;
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/*
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* Descriptors for Channels 1-4 must be consecutive in RAM.
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* We write the address of the 1st one to the register and the rest are
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* derived by the SoC
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*/
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#if (DMA_CHANNEL_COUNT > 1)
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tmp_ptr = (uint16_t) &(dma_conf[1]);
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DMA1CFGH = tmp_ptr >> 8;
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DMA1CFGL = tmp_ptr;
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#endif
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DMAIE = 1; /* Enable DMA interrupts */
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Associate process p with DMA channel c. When a transfer on that channel
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* completes, the ISR will poll this process.
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*/
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void
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dma_associate_process(struct process * p, uint8_t c)
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{
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if((!c) || (c >= DMA_CHANNEL_COUNT)) {
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return;
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}
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if(p) {
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dma_conf[c].inc_prio |= 8; /* Enable interrupt generation */
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DMAIE = 1; /* Make sure DMA interrupts are acknowledged */
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}
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dma_callback[c] = p;
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Reset a channel to idle state. As per cc253x datasheet section 8.1,
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* we must reconfigure the channel to trigger source 0 between each
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* reconfiguration.
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*/
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void
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dma_reset(uint8_t c)
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{
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static __xdata uint8_t dummy;
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if(c >= DMA_CHANNEL_COUNT) {
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return;
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}
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DMA_ABORT(c);
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dma_conf[c].src_h = (uint16_t) &dummy >> 8;
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dma_conf[c].src_l = (uint16_t) &dummy;
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dma_conf[c].dst_h = (uint16_t) &dummy >> 8;
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dma_conf[c].dst_l = (uint16_t) &dummy;
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dma_conf[c].len_h = 0;
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dma_conf[c].len_l = 1;
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dma_conf[c].wtt = DMA_BLOCK;
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dma_conf[c].inc_prio = DMA_PRIO_GUARANTEED;
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DMA_TRIGGER(c); // The operation order is important
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DMA_ARM(c);
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while(DMAARM & (1 << c));
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}
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#endif
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