402 lines
13 KiB
C
402 lines
13 KiB
C
/** @file hal/micro/cortexm3/nvm.c
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* @brief Cortex-M3 Non-Volatile Memory data storage system.
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*
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* This file implements the NVM data storage system. Refer to nvm.h for
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* full documentation of how the NVM data storage system works, is configured,
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* and is accessed.
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*
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* <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
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*/
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#include PLATFORM_HEADER
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#include "error.h"
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#ifdef NVM_RAM_EMULATION
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static int16u calibrationData[32+2]={
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0xFFFF, 0xFFFF,
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0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
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0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
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0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
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0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
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};
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int8u halCommonReadFromNvm(void *data, int32u offset, int16u length)
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{
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halCommonMemCopy(data, ((int8u *) calibrationData) + offset, length);
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return ST_SUCCESS;
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}
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int8u halCommonWriteToNvm(const void *data, int32u offset, int16u length)
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{
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halCommonMemCopy(((int8u *) calibrationData) + offset, data, length);
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return ST_SUCCESS;
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}
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#else
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//flash.h gives access to halInternalFlashErase and halInternalFlashWrite.
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#include "hal/micro/cortexm3/flash.h"
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//nvm.h includes memmap.h. These two headers define the key parameters:
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// MFB_PAGE_SIZE_B
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// MFB_TOP
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// NVM_LEFT_PAGE
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// NVM_RIGHT_PAGE
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// NVM_DATA_SIZE_B
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// NVM_FLASH_PAGE_COUNT
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// NVM_MGMT_SIZE_B
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#include "hal/micro/cortexm3/nvm.h"
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//Define two variables that hold the actual NVM data storage. LEFT and RIGHT
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//are not required to be continuous memory blocks so they can be define
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//separately. The linker is responsible for placing these storage containers
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//on flash page boundaries.
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NO_STRIPPING __no_init VAR_AT_SEGMENT (const int8u nvmStorageLeft[NVM_DATA_SIZE_B], __NVM__);
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NO_STRIPPING __no_init VAR_AT_SEGMENT (const int8u nvmStorageRight[NVM_DATA_SIZE_B], __NVM__);
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static int8u determineState(void)
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{
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int32u leftMgmt = *(int32u *)NVM_LEFT_PAGE;
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int32u rightMgmt = *(int32u *)NVM_RIGHT_PAGE;
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int8u state=0;
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if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFFFF)) {
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//State 1 and state 4 use identical mgmt words. The function
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//determineState() is only called at the start of a NVM read
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//or write. During a read, state 1 and 4 both read from the
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//LEFT so there is no reason to make a distinction. During
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//a write, the system will see the current page as LEFT and
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//therefore be transitioning from LEFT to RIGHT so state 4 is
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//correct. State 1 is only required to transition from 0 to 2.
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state = 4;
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} else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFF00FFFF)) {
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state = 2;
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} else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFF000000)) {
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state = 3;
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} else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFFFF)) {
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state = 4;
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} else if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFF00)) {
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state = 5;
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} else if((leftMgmt==0xFF000000) && (rightMgmt==0xFFFFFF00)) {
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state = 6;
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} else if((leftMgmt==0xFF000000) && (rightMgmt==0xFFFF0000)) {
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state = 7;
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} else if((leftMgmt==0xFFFFFFFF) && (rightMgmt==0xFFFF0000)) {
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state = 8;
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} else if((leftMgmt==0xFFFFFF00) && (rightMgmt==0xFFFF0000)) {
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state = 9;
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} else if((leftMgmt==0xFFFFFF00) && (rightMgmt==0xFF000000)) {
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state = 10;
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} else {
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//State 0 is used to indicate erased or invalid.
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state = 0;
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}
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return state;
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}
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int8u halCommonReadFromNvm(void *data, int32u offset, int16u length)
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{
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int16u i;
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int16u *flash;
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//Remember: all flash writes are 16bits.
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int16u *ram = (int16u*)data;
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//The NVM data storage system cannot function if the LEFT and RIGHT
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//storage are not aligned to physical flash pages.
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assert((NVM_LEFT_PAGE%MFB_PAGE_SIZE_B)==0);
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assert((NVM_RIGHT_PAGE%MFB_PAGE_SIZE_B)==0);
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//The offset of the NVM data must be 16bit aligned.
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assert((offset&0x1)==0);
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//The length of the NVM data must be 16bit aligned.
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assert((length&0x1)==0);
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assert(offset+length<NVM_DATA_SIZE_B);
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//Obtain the data from NVM storage.
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switch(determineState()) {
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case 1:
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case 2:
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case 3:
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case 4:
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case 9:
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case 10:
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flash = (int16u *)(NVM_LEFT_PAGE+offset);
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for(i=0;i<(length/2);i++) {
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ram[i] = flash[i];
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}
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break;
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case 5:
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case 6:
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case 7:
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case 8:
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flash = (int16u *)(NVM_RIGHT_PAGE+offset);
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for(i=0;i<(length/2);i++) {
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ram[i] = flash[i];
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}
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break;
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case 0:
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default:
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//Reading from NVM while the mgmt bytes are in an invalid state
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//should not return any bytes actually found in flash. Instead,
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//return nothing but 0xFF. This is legitimate because the next
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//call to the write function will also find invalid mgmt bytes
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//and trigger an erasure of NVM, after which the NVM really will
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//contain just 0xFF for data (plus the new data supplied during
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//the write call).
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for(i=0;i<(length/2);i++) {
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ram[i] = 0xFFFF;
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}
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//Inform the calling code. using ST_ERR_FATAL, that there were
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//invalid mgmt bytes and 0xFF was forcefully returned.
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return ST_ERR_FATAL;
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}
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return ST_SUCCESS;
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}
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int16u *halCommonGetAddressFromNvm(int32u offset)
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{
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int16u *flash;
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//The NVM data storage system cannot function if the LEFT and RIGHT
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//storage are not aligned to physical flash pages.
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assert((NVM_LEFT_PAGE%MFB_PAGE_SIZE_B)==0);
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assert((NVM_RIGHT_PAGE%MFB_PAGE_SIZE_B)==0);
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//The offset of the NVM data must be 16bit aligned.
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assert((offset&0x1)==0);
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//Obtain the data from NVM storage.
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switch(determineState()) {
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case 1:
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case 2:
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case 3:
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case 4:
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case 9:
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case 10:
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flash = (int16u *)(NVM_LEFT_PAGE+offset);
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break;
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case 5:
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case 6:
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case 7:
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case 8:
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flash = (int16u *)(NVM_RIGHT_PAGE+offset);
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break;
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case 0:
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default:
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// Flash is in an invalid state
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// Fix it with a dummy write and then return the flash page left
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{
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int16u dummy = 0xFFFF;
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halCommonWriteToNvm(&dummy, 0, 2);
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flash = (int16u *)(NVM_LEFT_PAGE+offset);
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}
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}
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return flash;
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}
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static int8u erasePage(int32u page)
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{
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StStatus status;
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int32u i, k;
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int32u address;
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int8u *flash;
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//Erasing a LEFT or RIGHT page requires erasing all of the flash pages.
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//Since the mgmt bytes are stored at the bottom of a page, the flash pages
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//are erased from the top down ensuring that that mgmt words are the last
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//data to be erased. This way, if a reset occurs while erasing, the mgmt
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//words are still valid the next time determineState() is called.
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for(i=NVM_FLASH_PAGE_COUNT;i>0;i--) {
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address = (page+((i-1)*MFB_PAGE_SIZE_B));
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flash = (int8u *)address;
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//Scan the page to determine if it is fully erased already.
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//If the flash is not erased, erase it. The purpose of scanning
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//first is to save a little time if erasing is not required.
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for(k=0;k<MFB_PAGE_SIZE_B;k++,flash++) {
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if(*flash != 0xFF) {
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status = halInternalFlashErase(MFB_PAGE_ERASE, address);
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if(status != ST_SUCCESS) {
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return status;
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}
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//Don't bother looking at the rest of this flash page and just
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//move to the next.
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k=MFB_PAGE_SIZE_B;
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}
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}
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}
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return ST_SUCCESS;
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}
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//This macro is responsible for erasing an NVM page (LEFT or RIGHT).
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#define ERASE_PAGE(page) \
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do { \
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status = erasePage(page); \
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if(status != ST_SUCCESS) { \
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return status; \
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} \
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} while(0)
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//This macro is responsible for writing the new data into the destination
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//page and copying existing data from the source page to the
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//destination page.
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#define WRITE_DATA(destPage, srcPage, offset, length) \
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do { \
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/*Copy all data below the new data from the srcPage to the destPage*/ \
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status = halInternalFlashWrite(destPage+NVM_MGMT_SIZE_B, \
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(int16u *)(srcPage+NVM_MGMT_SIZE_B), \
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(offset-NVM_MGMT_SIZE_B)/2); \
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if(status != ST_SUCCESS) { return status; } \
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/*Write the new data*/ \
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status = halInternalFlashWrite(destPage+offset, \
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ram, \
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(length)/2); \
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if(status != ST_SUCCESS) { return status; } \
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/*Copy all data above the new data from the srcPage to the destPage*/ \
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status = halInternalFlashWrite(destPage+offset+length, \
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(int16u *)(srcPage+offset+length), \
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(NVM_DATA_SIZE_B- \
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length-offset- \
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NVM_MGMT_SIZE_B)/2); \
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if(status != ST_SUCCESS) { return status; } \
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} while(0)
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//This macro is responsible for writing 16bits of management data to
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//the proper management address.
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#define WRITE_MGMT_16BITS(address, data) \
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do{ \
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int16u value = data; \
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status = halInternalFlashWrite((address), &value, 1); \
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if(status != ST_SUCCESS) { \
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return status; \
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} \
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} while(0)
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int8u halCommonWriteToNvm(const void *data, int32u offset, int16u length)
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{
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StStatus status;
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int8u state, exitState;
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int32u srcPage;
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int32u destPage;
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//Remember: NVM data storage works on 16bit quantities.
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int16u *ram = (int16u*)data;
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//The NVM data storage system cannot function if the LEFT and RIGHT
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//storage are not aligned to physical flash pages.
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assert((NVM_LEFT_PAGE%MFB_PAGE_SIZE_B)==0);
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assert((NVM_RIGHT_PAGE%MFB_PAGE_SIZE_B)==0);
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//The offset of the NVM data must be 16bit aligned.
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assert((offset&0x1)==0);
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//The length of the NVM data must be 16bit aligned.
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assert((length&0x1)==0);
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//It is illegal to write to an offset outside of NVM storage.
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assert(offset+length<NVM_DATA_SIZE_B);
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state = determineState();
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switch(state) {
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case 1:
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case 2:
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case 3:
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case 4:
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case 9:
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case 10:
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srcPage = NVM_LEFT_PAGE;
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destPage = NVM_RIGHT_PAGE;
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exitState = 7;
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break;
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case 5:
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case 6:
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case 7:
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case 8:
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srcPage = NVM_RIGHT_PAGE;
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destPage = NVM_LEFT_PAGE;
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exitState = 3;
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break;
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case 0:
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default:
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//Invalid state. Default to writing to the LEFT page. Defaulting to
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//using RIGHT as the source page is valid since the RIGHT page
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//will also be erased and therefore produce 0xFF for data values.
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state = 0;
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srcPage = NVM_RIGHT_PAGE;
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destPage = NVM_LEFT_PAGE;
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exitState = 3;
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break;
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}
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//Advance the state machine. Starting on state 3 requires state 7 to
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//exit and starting on state 7 requires state 3 to exit. Starting on
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//any other state requires either 3 or 7 to exit.
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//NOTE: Refer to nvm.h for a description of the states and how the
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// state transitions correspond to erasing, writing data, and
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// writing mgmt values.
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while(TRUE) {
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switch(state) {
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case 0:
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//State 0 is the only state where the source page needs to be erased.
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ERASE_PAGE(srcPage);
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ERASE_PAGE(destPage);
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WRITE_DATA(destPage, srcPage, offset, length);
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WRITE_MGMT_16BITS(NVM_LEFT_PAGE+0, 0x0000);
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state=1;
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break;
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case 1:
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WRITE_MGMT_16BITS(NVM_RIGHT_PAGE+2, 0xFF00);
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state=2;
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break;
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case 2:
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WRITE_MGMT_16BITS(NVM_RIGHT_PAGE+0, 0x0000);
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state=3;
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break;
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case 3:
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if(exitState==3) {
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return ST_SUCCESS;
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}
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ERASE_PAGE(destPage);
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state=4;
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break;
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case 4:
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WRITE_DATA(destPage, srcPage, offset, length);
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WRITE_MGMT_16BITS(NVM_RIGHT_PAGE+0, 0xFF00);
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state=5;
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break;
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case 5:
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WRITE_MGMT_16BITS(NVM_LEFT_PAGE+2, 0xFF00);
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state=6;
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break;
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case 6:
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WRITE_MGMT_16BITS(NVM_RIGHT_PAGE+0, 0x0000);
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state=7;
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break;
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case 7:
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if(exitState==7) {
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return ST_SUCCESS;
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}
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ERASE_PAGE(destPage);
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state=8;
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break;
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case 8:
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WRITE_DATA(destPage, srcPage, offset, length);
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WRITE_MGMT_16BITS(NVM_LEFT_PAGE+0, 0xFF00);
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state=9;
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break;
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case 9:
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WRITE_MGMT_16BITS(NVM_RIGHT_PAGE+2, 0xFF00);
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state=10;
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break;
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case 10:
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WRITE_MGMT_16BITS(NVM_LEFT_PAGE+0, 0x0000);
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state=3;
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break;
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}
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}
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}
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#endif // NVM_RAM_EMULATION
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