3908253038
This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
115 lines
4.4 KiB
C
115 lines
4.4 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_MM_PAGING_PROT_DOMAINS_H_
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#define CPU_X86_MM_PAGING_PROT_DOMAINS_H_
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "dma.h"
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#include "helpers.h"
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#include "paging.h"
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#include "syscalls-int.h"
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struct dom_kern_data {
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/** Base physical address of optional MMIO region */
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uintptr_t mmio;
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/** Number of (contiguous) pages in MMIO region */
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size_t mmio_sz;
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/** Base physical address of optional metadata region */
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uintptr_t meta;
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/** Number of (contiguous) pages in metadata region */
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size_t meta_sz;
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/** Flags are defined with the prefix PROT_DOMAINS_FLAG in prot-domains.h */
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uint32_t flags;
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/**
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* Original return address from call stack when this protection domain
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* invoked some other protection domain. This serves to control the return
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* entrypoint. The callee is not permitted to modify this value (unless the
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* callee is the kernel protection domain).
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*/
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uintptr_t orig_ret_addr;
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/* align to next-larger power of 2 to enable usage of shifting instead of
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* multiplication to index an array of these structures.
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*/
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} __attribute__((aligned(32)));
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/** Linear base address at which to map the MMIO region. */
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#define PROT_DOMAINS_MMIO_LINEAR_BASE (MIN_PAGE_SIZE + (uintptr_t)&_ebss_kern_addr)
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/** Maximum supported size of MMIO region */
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#define PROT_DOMAINS_MAX_MMIO_SZ 0x4000
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/** Linear base address at which to map the metadata region */
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#define PROT_DOMAINS_META_LINEAR_BASE \
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(MIN_PAGE_SIZE + (PROT_DOMAINS_MMIO_LINEAR_BASE + PROT_DOMAINS_MAX_MMIO_SZ))
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#define PROT_DOMAINS_META_OFF_TO_PHYS(off, meta_phys_base) \
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((meta_phys_base) + ((off) - PROT_DOMAINS_META_LINEAR_BASE))
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/** Any MMIO region mapping always starts at a particular linear address. */
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#define PROT_DOMAINS_MMIO(dcd) PROT_DOMAINS_MMIO_LINEAR_BASE
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/**
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* Any metadata region mapping always starts at a particular linear address.
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*/
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#define PROT_DOMAINS_META(dcd) PROT_DOMAINS_META_LINEAR_BASE
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#define PROT_DOMAINS_ENTER_ISR(exc) \
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PROT_DOMAINS_ENTER_ISR_COMMON(exc)
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#define PROT_DOMAINS_LEAVE_ISR(exc) PROT_DOMAINS_LEAVE_ISR_COMMON(exc)
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/* Enable paging */
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#define CR0_PG BIT(31)
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/* Enable write protection in supervisor mode */
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#define CR0_WP BIT(16)
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/* Enable protected mode */
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#define CR0_PE BIT(0)
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/**
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* \brief Enable or disable write protection enforcement in supervisor mode.
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* When disabled, supervisory code (i.e. code running at ring levels
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* 0-2) is permitted to write to pages that are marked read-only in
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* page tables.
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*
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* \param en Set to true to enable write protection enforcement.
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*/
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static inline void prot_domains_set_wp(bool en)
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{
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uint32_t cr0_val = CR0_PG | CR0_PE;
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if(en) {
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cr0_val |= CR0_WP;
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}
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__asm__ __volatile__ ("mov %0, %%cr0" :: "r"(cr0_val));
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}
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#endif /* CPU_X86_MM_PAGING_PROT_DOMAINS_H_ */
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