150 lines
5.8 KiB
C
150 lines
5.8 KiB
C
/**
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* \file
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* Header file for the cc2430 DMA controller
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*
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* \author
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* Original: Martti Huttunen <martti@sensinode.com>
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* Port: Zach Shelby <zach@sensinode.com>
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* Further Modifications:
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* George Oikonomou <oikonomou@users.sourceforge.net>
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*/
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#ifndef __DMA_H
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#define __DMA_H
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#include "cc253x.h"
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#include "sfr-bits.h"
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/* DMA triggers */
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#define DMA_T_NONE 0 /* None, DMAREQ.DMAREQx bits start transfer */
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#define DMA_T_PREV 1 /* completion of previous channel */
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#define DMA_T_T1_CH0 2 /* Timer 1, compare, channel 0 */
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#define DMA_T_T1_CH1 3 /* Timer 1, compare, channel 1 */
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#define DMA_T_T1_CH2 4 /* Timer 1, compare, channel 2 */
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#define DMA_T_T2_COMP 5 /* Timer 2, compare */
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#define DMA_T_T2_OVFL 6 /* Timer 2, overflow */
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#define DMA_T_T3_CH0 7 /* Timer 3, compare, channel 0 */
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#define DMA_T_T3_CH1 8 /* Timer 3, compare, channel 1 */
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#define DMA_T_T4_CH0 9 /* Timer 4, compare, channel 0 */
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#define DMA_T_T4_CH1 10 /* Timer 4, compare, channel 1 */
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#define DMA_T_ST 11 /* Sleep Timer compare */
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#define DMA_T_IOC_0 12 /* Port 0 I/O pin input transition */
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#define DMA_T_IOC_1 13 /* Port 1 I/O pin input transition */
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#define DMA_T_URX0 14 /* USART0 RX complete */
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#define DMA_T_UTX0 15 /* USART0 TX complete */
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#define DMA_T_URX1 16 /* USART1 RX complete */
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#define DMA_T_UTX1 17 /* USART1 TX complete */
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#define DMA_T_FLASH 18 /* Flash data write complete */
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#define DMA_T_RADIO 19 /* RF packet byte received/transmit */
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#define DMA_T_ADC_CHALL 20 /* ADC end of a conversion in a sequence */
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#define DMA_T_ADC_CH11 21 /* ADC end of conversion channel 0 in sequence */
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#define DMA_T_ADC_CH21 22 /* ADC end of conversion channel 1 in sequence */
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#define DMA_T_ADC_CH32 23 /* ADC end of conversion channel 2 in sequence */
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#define DMA_T_ADC_CH42 24 /* ADC end of conversion channel 3 in sequence */
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#define DMA_T_ADC_CH53 25 /* ADC end of conversion channel 4 in sequence */
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#define DMA_T_ADC_CH63 26 /* ADC end of conversion channel 5 in sequence */
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#define DMA_T_ADC_CH74 27 /* ADC end of conversion channel 6 in sequence */
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#define DMA_T_ADC_CH84 28 /* ADC end of conversion channel 7 in sequence */
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#define DMA_T_ENC_DW 29 /* AES processor requests download input data */
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#define DMA_T_ENC_UP 30 /* AES processor requests upload output data */
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/* variable DMA length modes (VLEN) */
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#define DMA_VLEN_LEN (0 << 5) /* Use LEN for transfer count*/
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/*
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* Transfer the number of bytes/words specified by first byte/word + 1
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* (up to a maximum specified by LEN).
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* Thus transfer count excludes length byte/word.
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*/
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#define DMA_VLEN_N1 (1 << 5)
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/*
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* Transfer the number of bytes/words specified by first byte/word
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* (up to a maximum specified by LEN).
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* Thus transfer count includes length byte/word.
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*/
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#define DMA_VLEN_N (2 << 5)
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/*
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* Transfer the number of bytes/words specified by first byte/word + 2
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* (up to a maximum specified by LEN).
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*/
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#define DMA_VLEN_N2 (3 << 5)
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/*
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* Transfer the number of bytes/words specified by first byte/word + 3
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* (up to a maximum specified by LEN).
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*/
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#define DMA_VLEN_N3 (4 << 5)
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#define DMA_VLEN_RES1 (5 << 5) /* reserved */
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#define DMA_VLEN_RES2 (6 << 5) /* reserved */
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#define DMA_VLEN_LEN2 (7 << 5) /* Use LEN for transfer count */
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/* Transfer Types (Byte 6 [6:5]) */
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#define DMA_SINGLE 0x00 /* Single */
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#define DMA_BLOCK 0x20 /* Block */
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#define DMA_RPT_SINGLE 0x40 /* Repeated single */
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#define DMA_RPT_BLOCK 0x60 /* Repeated block */
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/* Source Increment Modes (Byte 7 [7:6])*/
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#define DMA_SRC_INC_NO 0x00 /* Source No increment */
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#define DMA_SRC_INC_1 0x40 /* Source Increment 1 */
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#define DMA_SRC_INC_2 0x80 /* Source Increment 2 */
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#define DMA_SRC_DEC 0xC0 /* Source Decrement 1 */
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/* Source Increment Modes (Byte 7 [5:4])*/
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#define DMA_DST_INC_NO 0x00 /* DestinationNo increment */
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#define DMA_DST_INC_1 0x10 /* Destination Increment 1 */
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#define DMA_DST_INC_2 0x20 /* Destination Increment 2 */
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#define DMA_DST_DEC 0x30 /* Destination Decrement 1 */
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/* Descriptor Byte 7, Bits[3:0] */
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#define DMA_IRQ_MASK_ENABLE 0x08
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#define DMA_MODE_7_BIT 0x04
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#define DMA_PRIO_HIGH 0x02
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#define DMA_PRIO_ASSURED 0x01
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#define DMA_PRIO_LOW 0x00
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/** DMA configuration structure */
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typedef struct dma_config {
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uint8_t src_h; /* source address high byte*/
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uint8_t src_l; /* source address low byte*/
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uint8_t dst_h; /* dest. address high byte*/
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uint8_t dst_l; /* dest. address low byte*/
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uint8_t len_h; /* [7:5] VLEN, [4:0] length high byte, 5 lowest bits*/
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uint8_t len_l; /* length low byte*/
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uint8_t wtt; /* 7: wordsize, [6:5] transfer mode, [4:0] trigger */
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/* [7:6] src inc, [5:4] dst_inc, 3: IRQ, 2: M8(vlen), [1-0] prio */
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uint8_t inc_prio;
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} dma_config_t;
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#ifdef DMA_CONF_ON
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#define DMA_ON DMA_CONF_ON
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#else
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#define DMA_ON 0
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#endif
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/* Number of DMA Channels and their Descriptors */
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#if DMA_ON
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#define DMA_CHANNEL_COUNT 2
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extern dma_config_t dma_conf[DMA_CHANNEL_COUNT];
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#endif
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/* DMA-Related Macros */
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#define DMA_ARM(c) (DMAARM |= (1 << c)) /* Arm DMA Channel C */
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#define DMA_TRIGGER(c) (DMAREQ |= (1 << c)) /* Trigger DMA Channel C */
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/*
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* Check Channel C for Transfer Status
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* 1: Complete, Pending Interrupt, 0: Incomplete
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*/
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#define DMA_STATUS(c) (DMAIRQ &(1 << c))
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/* Abort Ongoing DMA Transfers on Channel C */
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#define DMA_ABORT(c) (DMAARM = DMAARM_ABORT | (1 << c))
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#define DMA_ABORT_ALL() (DMAARM = 0x9F) /* Abort ALL Ongoing DMA Transfers */
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/* Functions Declarations */
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void dma_init(void);
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void dma_associate_process(struct process *p, uint8_t c);
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void dma_reset(uint8_t c);
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/* Only link the ISR when DMA_ON is .... on */
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#if DMA_ON
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void dma_isr(void) __interrupt(DMA_VECTOR);
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#endif
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#endif /*__DMA_H*/
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