495 lines
25 KiB
C
495 lines
25 KiB
C
/*
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* Original file:
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Port to Contiki:
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* Copyright (c) 2013, ADVANSEE - http://www.advansee.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-crypto
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* @{
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*
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* \defgroup cc2538-aes cc2538 AES
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*
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* Driver for the cc2538 AES modes of the security core
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* @{
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*
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* \file
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* Header file for the cc2538 AES driver
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*/
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#ifndef AES_H_
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#define AES_H_
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#include "contiki.h"
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#include "dev/crypto.h"
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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/** \name AES register offsets
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* @{
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*/
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#define AES_DMAC_CH0_CTRL 0x4008B000 /**< Channel 0 control */
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#define AES_DMAC_CH0_EXTADDR 0x4008B004 /**< Channel 0 external address */
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#define AES_DMAC_CH0_DMALENGTH 0x4008B00C /**< Channel 0 DMA length */
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#define AES_DMAC_STATUS 0x4008B018 /**< DMAC status */
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#define AES_DMAC_SWRES 0x4008B01C /**< DMAC software reset */
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#define AES_DMAC_CH1_CTRL 0x4008B020 /**< Channel 1 control */
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#define AES_DMAC_CH1_EXTADDR 0x4008B024 /**< Channel 1 external address */
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#define AES_DMAC_CH1_DMALENGTH 0x4008B02C /**< Channel 1 DMA length */
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#define AES_DMAC_MST_RUNPARAMS 0x4008B078 /**< DMAC master run-time parameters */
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#define AES_DMAC_PERSR 0x4008B07C /**< DMAC port error raw status */
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#define AES_DMAC_OPTIONS 0x4008B0F8 /**< DMAC options */
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#define AES_DMAC_VERSION 0x4008B0FC /**< DMAC version */
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#define AES_KEY_STORE_WRITE_AREA \
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0x4008B400 /**< Key store write area */
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#define AES_KEY_STORE_WRITTEN_AREA \
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0x4008B404 /**< Key store written area */
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#define AES_KEY_STORE_SIZE 0x4008B408 /**< Key store size */
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#define AES_KEY_STORE_READ_AREA 0x4008B40C /**< Key store read area */
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#define AES_AES_KEY2_0 0x4008B500 /**< AES_KEY2_0 / AES_GHASH_H_IN_0 */
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#define AES_AES_KEY2_1 0x4008B504 /**< AES_KEY2_1 / AES_GHASH_H_IN_1 */
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#define AES_AES_KEY2_2 0x4008B508 /**< AES_KEY2_2 / AES_GHASH_H_IN_2 */
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#define AES_AES_KEY2_3 0x4008B50C /**< AES_KEY2_3 / AES_GHASH_H_IN_3 */
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#define AES_AES_KEY3_0 0x4008B510 /**< AES_KEY3_0 / AES_KEY2_4 */
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#define AES_AES_KEY3_1 0x4008B514 /**< AES_KEY3_1 / AES_KEY2_5 */
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#define AES_AES_KEY3_2 0x4008B518 /**< AES_KEY3_2 / AES_KEY2_6 */
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#define AES_AES_KEY3_3 0x4008B51C /**< AES_KEY3_3 / AES_KEY2_7 */
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#define AES_AES_IV_0 0x4008B540 /**< AES initialization vector */
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#define AES_AES_IV_1 0x4008B544 /**< AES initialization vector */
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#define AES_AES_IV_2 0x4008B548 /**< AES initialization vector */
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#define AES_AES_IV_3 0x4008B54C /**< AES initialization vector */
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#define AES_AES_CTRL 0x4008B550 /**< AES input/output buffer control and mode */
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#define AES_AES_C_LENGTH_0 0x4008B554 /**< AES crypto length (LSW) */
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#define AES_AES_C_LENGTH_1 0x4008B558 /**< AES crypto length (MSW) */
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#define AES_AES_AUTH_LENGTH 0x4008B55C /**< Authentication length */
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#define AES_AES_DATA_IN_OUT_0 0x4008B560 /**< Data input/output */
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#define AES_AES_DATA_IN_OUT_1 0x4008B564 /**< Data Input/Output */
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#define AES_AES_DATA_IN_OUT_2 0x4008B568 /**< Data Input/Output */
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#define AES_AES_DATA_IN_OUT_3 0x4008B56C /**< Data Input/Output */
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#define AES_AES_TAG_OUT_0 0x4008B570 /**< TAG */
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#define AES_AES_TAG_OUT_1 0x4008B574 /**< TAG */
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#define AES_AES_TAG_OUT_2 0x4008B578 /**< TAG */
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#define AES_AES_TAG_OUT_3 0x4008B57C /**< TAG */
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#define AES_HASH_DATA_IN_0 0x4008B600 /**< HASH data input */
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#define AES_HASH_DATA_IN_1 0x4008B604 /**< HASH data input */
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#define AES_HASH_DATA_IN_2 0x4008B608 /**< HASH data input */
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#define AES_HASH_DATA_IN_3 0x4008B60C /**< HASH data input */
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#define AES_HASH_DATA_IN_4 0x4008B610 /**< HASH data input */
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#define AES_HASH_DATA_IN_5 0x4008B614 /**< HASH data input */
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#define AES_HASH_DATA_IN_6 0x4008B618 /**< HASH data input */
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#define AES_HASH_DATA_IN_7 0x4008B61C /**< HASH data input */
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#define AES_HASH_DATA_IN_8 0x4008B620 /**< HASH data input */
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#define AES_HASH_DATA_IN_9 0x4008B624 /**< HASH data input */
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#define AES_HASH_DATA_IN_10 0x4008B628 /**< HASH data input */
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#define AES_HASH_DATA_IN_11 0x4008B62C /**< HASH data input */
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#define AES_HASH_DATA_IN_12 0x4008B630 /**< HASH data input */
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#define AES_HASH_DATA_IN_13 0x4008B634 /**< HASH data input */
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#define AES_HASH_DATA_IN_14 0x4008B638 /**< HASH data input */
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#define AES_HASH_DATA_IN_15 0x4008B63C /**< HASH data input */
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#define AES_HASH_IO_BUF_CTRL 0x4008B640 /**< Input/output buffer control and status */
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#define AES_HASH_MODE_IN 0x4008B644 /**< Hash mode */
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#define AES_HASH_LENGTH_IN_L 0x4008B648 /**< Hash length */
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#define AES_HASH_LENGTH_IN_H 0x4008B64C /**< Hash length */
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#define AES_HASH_DIGEST_A 0x4008B650 /**< Hash digest */
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#define AES_HASH_DIGEST_B 0x4008B654 /**< Hash digest */
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#define AES_HASH_DIGEST_C 0x4008B658 /**< Hash digest */
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#define AES_HASH_DIGEST_D 0x4008B65C /**< Hash digest */
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#define AES_HASH_DIGEST_E 0x4008B660 /**< Hash digest */
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#define AES_HASH_DIGEST_F 0x4008B664 /**< Hash digest */
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#define AES_HASH_DIGEST_G 0x4008B668 /**< Hash digest */
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#define AES_HASH_DIGEST_H 0x4008B66C /**< Hash digest */
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#define AES_CTRL_ALG_SEL 0x4008B700 /**< Algorithm select */
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#define AES_CTRL_PROT_EN 0x4008B704 /**< Master PROT privileged access enable */
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#define AES_CTRL_SW_RESET 0x4008B740 /**< Software reset */
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#define AES_CTRL_INT_CFG 0x4008B780 /**< Interrupt configuration */
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#define AES_CTRL_INT_EN 0x4008B784 /**< Interrupt enable */
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#define AES_CTRL_INT_CLR 0x4008B788 /**< Interrupt clear */
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#define AES_CTRL_INT_SET 0x4008B78C /**< Interrupt set */
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#define AES_CTRL_INT_STAT 0x4008B790 /**< Interrupt status */
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#define AES_CTRL_OPTIONS 0x4008B7F8 /**< Options */
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#define AES_CTRL_VERSION 0x4008B7FC /**< Version */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_CHx_CTRL registers bit fields
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* @{
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*/
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#define AES_DMAC_CH_CTRL_PRIO 0x00000002 /**< Channel priority 0: Low 1: High */
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#define AES_DMAC_CH_CTRL_EN 0x00000001 /**< Channel enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_CHx_DMALENGTH registers bit fields
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* @{
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*/
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#define AES_DMAC_CH_DMALENGTH_DMALEN_M \
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0x0000FFFF /**< Channel DMA length in bytes mask */
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#define AES_DMAC_CH_DMALENGTH_DMALEN_S 0 /**< Channel DMA length in bytes shift */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_STATUS register bit fields
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* @{
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*/
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#define AES_DMAC_STATUS_PORT_ERR \
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0x00020000 /**< AHB port transfer errors */
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#define AES_DMAC_STATUS_CH1_ACT 0x00000002 /**< Channel 1 active (DMA transfer on-going) */
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#define AES_DMAC_STATUS_CH0_ACT 0x00000001 /**< Channel 0 active (DMA transfer on-going) */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_SWRES register bit fields
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* @{
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*/
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#define AES_DMAC_SWRES_SWRES 0x00000001 /**< Software reset enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_MST_RUNPARAMS register bit fields
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* @{
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*/
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_4 \
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(2 << 12) /**< Maximum burst size: 4 bytes */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_8 \
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(3 << 12) /**< Maximum burst size: 8 bytes */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_16 \
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(4 << 12) /**< Maximum burst size: 16 bytes */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_32 \
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(5 << 12) /**< Maximum burst size: 32 bytes */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_64 \
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(6 << 12) /**< Maximum burst size: 64 bytes */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_M \
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0x0000F000 /**< Maximum burst size mask */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_S \
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12 /**< Maximum burst size shift */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_IDLE_EN \
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0x00000800 /**< Idle insertion between bursts */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_INCR_EN \
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0x00000400 /**< Fixed-length burst or single transfers */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_LOCK_EN \
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0x00000200 /**< Locked transfers */
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#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BIGEND \
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0x00000100 /**< Big endian AHB master */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_PERSR register bit fields
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* @{
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*/
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#define AES_DMAC_PERSR_PORT1_AHB_ERROR \
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0x00001000 /**< AHB bus error */
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#define AES_DMAC_PERSR_PORT1_CHANNEL \
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0x00000200 /**< Last serviced channel (0 or 1) */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_OPTIONS register bit fields
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* @{
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*/
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#define AES_DMAC_OPTIONS_NR_OF_CHANNELS_M \
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0x00000F00 /**< Number of channels implemented mask */
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#define AES_DMAC_OPTIONS_NR_OF_CHANNELS_S \
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8 /**< Number of channels implemented shift */
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#define AES_DMAC_OPTIONS_NR_OF_PORTS_M \
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0x00000007 /**< Number of ports implemented mask */
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#define AES_DMAC_OPTIONS_NR_OF_PORTS_S 0 /**< Number of ports implemented shift */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_DMAC_VERSION register bit fields
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* @{
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*/
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#define AES_DMAC_VERSION_HW_MAJOR_VERSION_M \
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0x0F000000 /**< Major version number mask */
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#define AES_DMAC_VERSION_HW_MAJOR_VERSION_S \
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24 /**< Major version number shift */
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#define AES_DMAC_VERSION_HW_MINOR_VERSION_M \
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0x00F00000 /**< Minor version number mask */
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#define AES_DMAC_VERSION_HW_MINOR_VERSION_S \
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20 /**< Minor version number shift */
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#define AES_DMAC_VERSION_HW_PATCH_LEVEL_M \
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0x000F0000 /**< Patch level mask */
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#define AES_DMAC_VERSION_HW_PATCH_LEVEL_S \
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16 /**< Patch level shift */
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#define AES_DMAC_VERSION_EIP_NUMBER_COMPL_M \
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0x0000FF00 /**< EIP_NUMBER 1's complement mask */
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#define AES_DMAC_VERSION_EIP_NUMBER_COMPL_S \
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8 /**< EIP_NUMBER 1's complement shift */
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#define AES_DMAC_VERSION_EIP_NUMBER_M \
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0x000000FF /**< DMAC EIP-number mask */
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#define AES_DMAC_VERSION_EIP_NUMBER_S 0 /**< DMAC EIP-number shift */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_KEY_STORE_SIZE register bit fields
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* @{
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*/
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#define AES_KEY_STORE_SIZE_KEY_SIZE_128 1 /**< Key size: 128 bits */
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#define AES_KEY_STORE_SIZE_KEY_SIZE_192 2 /**< Key size: 192 bits */
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#define AES_KEY_STORE_SIZE_KEY_SIZE_256 3 /**< Key size: 256 bits */
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#define AES_KEY_STORE_SIZE_KEY_SIZE_M \
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0x00000003 /**< Key size mask */
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#define AES_KEY_STORE_SIZE_KEY_SIZE_S 0 /**< Key size shift */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_KEY_STORE_READ_AREA register bit fields
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* @{
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*/
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#define AES_KEY_STORE_READ_AREA_BUSY \
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0x80000000 /**< Key store operation busy */
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#define AES_KEY_STORE_READ_AREA_RAM_AREA_M \
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0x0000000F /**< Key store RAM area select mask */
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#define AES_KEY_STORE_READ_AREA_RAM_AREA_S \
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0 /**< Key store RAM area select shift */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_AES_CTRL register bit fields
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* @{
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*/
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#define AES_AES_CTRL_CONTEXT_READY \
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0x80000000 /**< Context data registers can be overwritten */
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#define AES_AES_CTRL_SAVED_CONTEXT_READY \
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0x40000000 /**< AES auth. TAG and/or IV block(s) available */
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#define AES_AES_CTRL_SAVE_CONTEXT \
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0x20000000 /**< Auth. TAG or result IV needs to be stored */
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#define AES_AES_CTRL_CCM_M_M 0x01C00000 /**< CCM auth. field length mask */
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#define AES_AES_CTRL_CCM_M_S 22 /**< CCM auth. field length shift */
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#define AES_AES_CTRL_CCM_L_M 0x00380000 /**< CCM length field width mask */
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#define AES_AES_CTRL_CCM_L_S 19 /**< CCM length field width shift */
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#define AES_AES_CTRL_CCM 0x00040000 /**< AES-CCM mode */
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#define AES_AES_CTRL_GCM 0x00030000 /**< AES-GCM mode */
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#define AES_AES_CTRL_CBC_MAC 0x00008000 /**< AES-CBC MAC mode */
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#define AES_AES_CTRL_CTR_WIDTH_32 (0 << 7) /**< CTR counter width: 32 bits */
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#define AES_AES_CTRL_CTR_WIDTH_64 (1 << 7) /**< CTR counter width: 64 bits */
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#define AES_AES_CTRL_CTR_WIDTH_96 (2 << 7) /**< CTR counter width: 96 bits */
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#define AES_AES_CTRL_CTR_WIDTH_128 \
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(3 << 7) /**< CTR counter width: 128 bits */
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#define AES_AES_CTRL_CTR_WIDTH_M \
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0x00000180 /**< CTR counter width mask */
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#define AES_AES_CTRL_CTR_WIDTH_S 7 /**< CTR counter width shift */
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#define AES_AES_CTRL_CTR 0x00000040 /**< AES-CTR mode */
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#define AES_AES_CTRL_CBC 0x00000020 /**< AES-CBC mode */
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#define AES_AES_CTRL_KEY_SIZE_128 (1 << 3) /**< Key size: 128 bits */
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#define AES_AES_CTRL_KEY_SIZE_192 (2 << 3) /**< Key size: 192 bits */
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#define AES_AES_CTRL_KEY_SIZE_256 (3 << 3) /**< Key size: 256 bits */
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#define AES_AES_CTRL_KEY_SIZE_M 0x00000018 /**< Key size mask */
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#define AES_AES_CTRL_KEY_SIZE_S 3 /**< Key size shift */
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#define AES_AES_CTRL_DIRECTION_ENCRYPT \
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0x00000004 /**< Encrypt */
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#define AES_AES_CTRL_INPUT_READY \
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0x00000002 /**< AES input buffer empty */
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#define AES_AES_CTRL_OUTPUT_READY \
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0x00000001 /**< AES output block available */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_AES_C_LENGTH_1 register bit fields
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* @{
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*/
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#define AES_AES_C_LENGTH_1_C_LENGTH_M \
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0x1FFFFFFF /**< Crypto length bits [60:32] mask */
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#define AES_AES_C_LENGTH_1_C_LENGTH_S 0 /**< Crypto length bits [60:32] shift */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_HASH_IO_BUF_CTRL register bit fields
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* @{
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*/
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#define AES_HASH_IO_BUF_CTRL_PAD_DMA_MESSAGE \
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0x00000080 /**< Hash engine message padding required */
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#define AES_HASH_IO_BUF_CTRL_GET_DIGEST \
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0x00000040 /**< Hash engine digest requested */
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#define AES_HASH_IO_BUF_CTRL_PAD_MESSAGE \
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0x00000020 /**< Last message data in HASH_DATA_IN, apply hash padding */
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#define AES_HASH_IO_BUF_CTRL_RFD_IN \
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0x00000004 /**< Hash engine input buffer can accept new data */
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#define AES_HASH_IO_BUF_CTRL_DATA_IN_AV \
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0x00000002 /**< Start processing HASH_DATA_IN data */
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#define AES_HASH_IO_BUF_CTRL_OUTPUT_FULL \
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0x00000001 /**< Output buffer registers available */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_HASH_MODE_IN register bit fields
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* @{
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*/
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#define AES_HASH_MODE_IN_SHA256_MODE \
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0x00000008 /**< Hash mode */
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#define AES_HASH_MODE_IN_NEW_HASH \
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0x00000001 /**< New hash session */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_ALG_SEL register bit fields
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* @{
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*/
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#define AES_CTRL_ALG_SEL_TAG 0x80000000 /**< DMA operation includes TAG */
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#define AES_CTRL_ALG_SEL_HASH 0x00000004 /**< Select hash engine as DMA destination */
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#define AES_CTRL_ALG_SEL_AES 0x00000002 /**< Select AES engine as DMA source/destination */
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#define AES_CTRL_ALG_SEL_KEYSTORE \
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0x00000001 /**< Select Key Store as DMA destination */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_PROT_EN register bit fields
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* @{
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*/
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#define AES_CTRL_PROT_EN_PROT_EN \
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0x00000001 /**< m_h_prot[1] asserted for DMA reads towards key store */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_SW_RESET register bit fields
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* @{
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*/
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#define AES_CTRL_SW_RESET_SW_RESET \
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0x00000001 /**< Reset master control and key store */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_INT_CFG register bit fields
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* @{
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*/
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#define AES_CTRL_INT_CFG_LEVEL 0x00000001 /**< Level interrupt type */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_INT_EN register bit fields
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* @{
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*/
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#define AES_CTRL_INT_EN_DMA_IN_DONE \
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0x00000002 /**< DMA input done interrupt enabled */
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#define AES_CTRL_INT_EN_RESULT_AV \
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0x00000001 /**< Result available interrupt enabled */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_INT_CLR register bit fields
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* @{
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*/
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#define AES_CTRL_INT_CLR_DMA_BUS_ERR \
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0x80000000 /**< Clear DMA bus error status */
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#define AES_CTRL_INT_CLR_KEY_ST_WR_ERR \
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0x40000000 /**< Clear key store write error status */
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#define AES_CTRL_INT_CLR_KEY_ST_RD_ERR \
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0x20000000 /**< Clear key store read error status */
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#define AES_CTRL_INT_CLR_DMA_IN_DONE \
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0x00000002 /**< Clear DMA in done interrupt */
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#define AES_CTRL_INT_CLR_RESULT_AV \
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0x00000001 /**< Clear result available interrupt */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_INT_SET register bit fields
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* @{
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*/
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#define AES_CTRL_INT_SET_DMA_IN_DONE \
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0x00000002 /**< Set DMA data in done interrupt */
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#define AES_CTRL_INT_SET_RESULT_AV \
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0x00000001 /**< Set result available interrupt */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_INT_STAT register bit fields
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* @{
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*/
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#define AES_CTRL_INT_STAT_DMA_BUS_ERR \
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0x80000000 /**< DMA bus error detected */
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#define AES_CTRL_INT_STAT_KEY_ST_WR_ERR \
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0x40000000 /**< Write error detected */
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#define AES_CTRL_INT_STAT_KEY_ST_RD_ERR \
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0x20000000 /**< Read error detected */
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#define AES_CTRL_INT_STAT_DMA_IN_DONE \
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0x00000002 /**< DMA data in done interrupt status */
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#define AES_CTRL_INT_STAT_RESULT_AV \
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0x00000001 /**< Result available interrupt status */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_OPTIONS register bit fields
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* @{
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*/
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#define AES_CTRL_OPTIONS_TYPE_M 0xFF000000 /**< Device type mask */
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#define AES_CTRL_OPTIONS_TYPE_S 24 /**< Device type shift */
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#define AES_CTRL_OPTIONS_AHBINTERFACE \
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0x00010000 /**< AHB interface available */
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#define AES_CTRL_OPTIONS_SHA_256 \
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0x00000100 /**< The HASH core supports SHA-256 */
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#define AES_CTRL_OPTIONS_AES_CCM \
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0x00000080 /**< AES-CCM available as single operation */
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#define AES_CTRL_OPTIONS_AES_GCM \
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0x00000040 /**< AES-GCM available as single operation */
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#define AES_CTRL_OPTIONS_AES_256 \
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0x00000020 /**< AES core supports 256-bit keys */
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#define AES_CTRL_OPTIONS_AES_128 \
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0x00000010 /**< AES core supports 128-bit keys */
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#define AES_CTRL_OPTIONS_HASH 0x00000004 /**< HASH Core available */
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#define AES_CTRL_OPTIONS_AES 0x00000002 /**< AES core available */
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#define AES_CTRL_OPTIONS_KEYSTORE \
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0x00000001 /**< KEY STORE available */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES_CTRL_VERSION register bit fields
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|
* @{
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|
*/
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#define AES_CTRL_VERSION_MAJOR_VERSION_M \
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0x0F000000 /**< Major version number mask */
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#define AES_CTRL_VERSION_MAJOR_VERSION_S \
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24 /**< Major version number shift */
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#define AES_CTRL_VERSION_MINOR_VERSION_M \
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0x00F00000 /**< Minor version number mask */
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#define AES_CTRL_VERSION_MINOR_VERSION_S \
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20 /**< Minor version number shift */
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#define AES_CTRL_VERSION_PATCH_LEVEL_M \
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0x000F0000 /**< Patch level mask */
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#define AES_CTRL_VERSION_PATCH_LEVEL_S 16 /**< Patch level shift */
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#define AES_CTRL_VERSION_EIP_NUMBER_COMPL_M \
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|
0x0000FF00 /**< EIP_NUMBER 1's complement mask */
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|
#define AES_CTRL_VERSION_EIP_NUMBER_COMPL_S \
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|
8 /**< EIP_NUMBER 1's complement shift */
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|
#define AES_CTRL_VERSION_EIP_NUMBER_M \
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|
0x000000FF /**< EIP-120t EIP-number mask */
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#define AES_CTRL_VERSION_EIP_NUMBER_S 0 /**< EIP-120t EIP-number shift */
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/** @} */
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|
/*---------------------------------------------------------------------------*/
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|
/** \name AES drivers return codes
|
|
* @{
|
|
*/
|
|
#define AES_KEYSTORE_READ_ERROR 5
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|
#define AES_KEYSTORE_WRITE_ERROR 6
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|
/** @} */
|
|
/*---------------------------------------------------------------------------*/
|
|
/** \name AES functions
|
|
* @{
|
|
*/
|
|
|
|
/** \brief Writes keys into the Key RAM
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|
* \param keys Pointer to AES Keys
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|
* \param key_size Key size: \c AES_KEY_STORE_SIZE_KEY_SIZE_x
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|
* \param count Number of keys (1 to 8 - \p start_area for 128-bit keys, 1 to
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|
* (8 - \p start_area) / 2 for 192- and 256-bit keys)
|
|
* \param start_area Start area in Key RAM where to store the key (0 to 7, must
|
|
* be even for 192- and 256-bit keys)
|
|
* \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
|
|
* \note Calling this function with a value of \p key_size different from the
|
|
* one passed for the previous calls causes the deletion of all previously
|
|
* stored keys.
|
|
*/
|
|
uint8_t aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
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|
uint8_t start_area);
|
|
|
|
/** @} */
|
|
|
|
#endif /* AES_H_ */
|
|
|
|
/**
|
|
* @}
|
|
* @}
|
|
*/
|